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schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3mp/testbench.vhd | 1 | 19,866 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| gpl-2.0 | 4e2017d77b31b2add2c5457720d341db | 0.575254 | 3.041801 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd | 1 | 20,639 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | f75cd203cb31bf3511db65cdfd3077bd | 0.538156 | 3.758012 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2c2ahb_apb.vhd | 1 | 7,346 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
| gpl-2.0 | 979e4d9146b86dcd07625b69190431e4 | 0.548189 | 3.536832 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/bc3bf9cf92381990/ip_design_xbar_0_sim_netlist.vhdl | 1 | 218,650 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:50:58 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_sim_netlist.vhdl
-- Design : ip_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd is
port (
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_ready_d0_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_2\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_atarget_enc_reg[1]_2\ : in STD_LOGIC;
\gen_axilite.s_axi_arready_i_reg\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_3\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_grant_any : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_1\ : STD_LOGIC;
signal \^gen_axilite.s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[5]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_10_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_11_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_12_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_5_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_6_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_7_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_8_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_9_n_0\ : STD_LOGIC;
signal \^m_axi_arprot[2]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_12\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_9\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_bready[4]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair16";
begin
SR(0) <= \^sr\(0);
aa_grant_rnw <= \^aa_grant_rnw\;
\gen_axilite.s_axi_bvalid_i_reg\ <= \^gen_axilite.s_axi_bvalid_i_reg\;
\gen_axilite.s_axi_bvalid_i_reg_0\ <= \^gen_axilite.s_axi_bvalid_i_reg_0\;
\gen_axilite.s_axi_bvalid_i_reg_1\ <= \^gen_axilite.s_axi_bvalid_i_reg_1\;
\gen_axilite.s_axi_rvalid_i_reg\ <= \^gen_axilite.s_axi_rvalid_i_reg\;
\m_axi_arprot[2]\(34 downto 0) <= \^m_axi_arprot[2]\(34 downto 0);
m_ready_d0(0) <= \^m_ready_d0\(0);
m_valid_i <= \^m_valid_i\;
\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5C505050F0F0F0F0"
)
port map (
I0 => \^gen_axilite.s_axi_bvalid_i_reg\,
I1 => mi_wready(0),
I2 => mi_bvalid(0),
I3 => \^gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \^gen_axilite.s_axi_bvalid_i_reg_1\,
I5 => Q(6),
O => \gen_axilite.s_axi_bvalid_i_reg_2\
);
\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => m_ready_d(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_bvalid_i_reg_1\
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d_1(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_rvalid_i_reg\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF5300000050"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aa_grant_any,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^m_axi_arprot[2]\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^m_axi_arprot[2]\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^m_axi_arprot[2]\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^m_axi_arprot[2]\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^m_axi_arprot[2]\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^m_axi_arprot[2]\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^m_axi_arprot[2]\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^m_axi_arprot[2]\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^m_axi_arprot[2]\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^m_axi_arprot[2]\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^m_axi_arprot[2]\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^m_axi_arprot[2]\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^m_axi_arprot[2]\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^m_axi_arprot[2]\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^m_axi_arprot[2]\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^m_axi_arprot[2]\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^m_axi_arprot[2]\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^m_axi_arprot[2]\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^m_axi_arprot[2]\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^m_axi_arprot[2]\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^m_axi_arprot[2]\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^m_axi_arprot[2]\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^m_axi_arprot[2]\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^m_axi_arprot[2]\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^m_axi_arprot[2]\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^m_axi_arprot[2]\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^m_axi_arprot[2]\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^m_axi_arprot[2]\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^m_axi_arprot[2]\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^m_axi_arprot[2]\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^m_axi_arprot[2]\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^m_axi_arprot[2]\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^m_axi_arprot[2]\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^m_axi_arprot[2]\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^m_axi_arprot[2]\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AAA800000000"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => aresetn_d,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00EFFFFFFFEFFFFF"
)
port map (
I0 => \m_ready_d_reg[0]_1\,
I1 => \m_ready_d_reg[1]\,
I2 => \^m_ready_d0\(0),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => \m_ready_d[0]_i_4_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30020002"
)
port map (
I0 => m_axi_wready(0),
I1 => \m_atarget_enc_reg[2]_3\(2),
I2 => \m_atarget_enc_reg[2]_3\(1),
I3 => \m_atarget_enc_reg[2]_3\(0),
I4 => m_axi_wready(1),
O => \gen_no_arbiter.m_valid_i_reg_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => aa_grant_any,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8AAA"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_3_n_0\,
I2 => \m_atarget_hot[6]_i_5_n_0\,
I3 => \m_atarget_hot[5]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(0)
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_4_n_0\,
I2 => \m_atarget_hot[6]_i_3_n_0\,
I3 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(1)
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000020AAAAAAAA"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_6_n_0\,
I2 => \m_atarget_hot[6]_i_5_n_0\,
I3 => \m_atarget_hot[6]_i_4_n_0\,
I4 => \m_atarget_hot[6]_i_3_n_0\,
I5 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(2)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_4_n_0\,
I1 => aa_grant_any,
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_3_n_0\,
I1 => aa_grant_any,
O => D(1)
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_6_n_0\,
I1 => aa_grant_any,
O => D(2)
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \m_atarget_hot[6]_i_5_n_0\,
O => D(3)
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[4]_i_2_n_0\,
I1 => aa_grant_any,
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arprot[2]\(17),
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \^m_axi_arprot[2]\(16),
I3 => \^m_axi_arprot[2]\(19),
I4 => \^m_axi_arprot[2]\(18),
I5 => \m_atarget_hot[6]_i_7_n_0\,
O => \m_atarget_hot[4]_i_2_n_0\
);
\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \m_atarget_hot[5]_i_2_n_0\,
O => D(5)
);
\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \m_atarget_hot[6]_i_7_n_0\,
I1 => \^m_axi_arprot[2]\(17),
I2 => \m_atarget_hot[6]_i_8_n_0\,
I3 => \^m_axi_arprot[2]\(19),
I4 => \^m_axi_arprot[2]\(18),
I5 => \^m_axi_arprot[2]\(16),
O => \m_atarget_hot[5]_i_2_n_0\
);
\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000020000000000"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[6]_i_3_n_0\,
I2 => \m_atarget_hot[6]_i_4_n_0\,
I3 => \m_atarget_hot[6]_i_5_n_0\,
I4 => \m_atarget_hot[6]_i_6_n_0\,
I5 => aa_grant_any,
O => D(6)
);
\m_atarget_hot[6]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \^m_axi_arprot[2]\(24),
I1 => \^m_axi_arprot[2]\(20),
I2 => \^m_axi_arprot[2]\(21),
I3 => \^m_axi_arprot[2]\(23),
I4 => \^m_axi_arprot[2]\(22),
I5 => \^m_axi_arprot[2]\(25),
O => \m_atarget_hot[6]_i_10_n_0\
);
\m_atarget_hot[6]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^m_axi_arprot[2]\(18),
I1 => \^m_axi_arprot[2]\(19),
I2 => \^m_axi_arprot[2]\(16),
I3 => \^m_axi_arprot[2]\(13),
I4 => \^m_axi_arprot[2]\(12),
O => \m_atarget_hot[6]_i_11_n_0\
);
\m_atarget_hot[6]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^m_axi_arprot[2]\(19),
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(16),
O => \m_atarget_hot[6]_i_12_n_0\
);
\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \m_atarget_hot[6]_i_7_n_0\,
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(19),
I3 => \m_atarget_hot[6]_i_8_n_0\,
I4 => \^m_axi_arprot[2]\(17),
O => \m_atarget_hot[6]_i_2_n_0\
);
\m_atarget_hot[6]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \m_atarget_hot[6]_i_9_n_0\,
I1 => \m_atarget_hot[6]_i_10_n_0\,
I2 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_3_n_0\
);
\m_atarget_hot[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \m_atarget_hot[6]_i_11_n_0\,
I3 => \^m_axi_arprot[2]\(14),
I4 => \^m_axi_arprot[2]\(17),
I5 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_4_n_0\
);
\m_atarget_hot[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \m_atarget_hot[6]_i_12_n_0\,
I3 => \^m_axi_arprot[2]\(14),
I4 => \^m_axi_arprot[2]\(17),
I5 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_5_n_0\
);
\m_atarget_hot[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \^m_axi_arprot[2]\(17),
I2 => \m_atarget_hot[6]_i_8_n_0\,
I3 => \^m_axi_arprot[2]\(16),
I4 => \^m_axi_arprot[2]\(19),
I5 => \^m_axi_arprot[2]\(18),
O => \m_atarget_hot[6]_i_6_n_0\
);
\m_atarget_hot[6]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFDFF"
)
port map (
I0 => \^m_axi_arprot[2]\(24),
I1 => \^m_axi_arprot[2]\(20),
I2 => \^m_axi_arprot[2]\(25),
I3 => \^m_axi_arprot[2]\(21),
I4 => \^m_axi_arprot[2]\(23),
I5 => \^m_axi_arprot[2]\(22),
O => \m_atarget_hot[6]_i_7_n_0\
);
\m_atarget_hot[6]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \^m_axi_arprot[2]\(26),
I1 => \^m_axi_arprot[2]\(29),
I2 => \^m_axi_arprot[2]\(27),
I3 => \^m_axi_arprot[2]\(30),
I4 => \^m_axi_arprot[2]\(31),
I5 => \^m_axi_arprot[2]\(28),
O => \m_atarget_hot[6]_i_8_n_0\
);
\m_atarget_hot[6]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^m_axi_arprot[2]\(16),
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(19),
I3 => \m_atarget_hot[6]_i_8_n_0\,
I4 => \^m_axi_arprot[2]\(17),
O => \m_atarget_hot[6]_i_9_n_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(3)
);
\m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(4)
);
\m_axi_arvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(5)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(3)
);
\m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(4)
);
\m_axi_awvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(5)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(0),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(1),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(2),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(3),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(4),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(4)
);
\m_axi_bready[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(5),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(5)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(0),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(1),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(2),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(3),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(3)
);
\m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(4),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(4)
);
\m_axi_wvalid[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(5),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(5)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(0),
I4 => sr_rvalid,
O => E(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(0),
O => \^gen_axilite.s_axi_bvalid_i_reg\
);
\m_ready_d[0]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \m_ready_d_reg[0]_0\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFA8AA"
)
port map (
I0 => \^gen_axilite.s_axi_rvalid_i_reg\,
I1 => \m_atarget_enc_reg[1]_2\,
I2 => \gen_axilite.s_axi_arready_i_reg\,
I3 => \m_atarget_enc_reg[1]_3\,
I4 => m_ready_d_1(1),
I5 => m_valid_i_reg_0,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(1),
O => \^gen_axilite.s_axi_bvalid_i_reg_0\
);
\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFDFF00FF00FF00"
)
port map (
I0 => \m_atarget_enc_reg[1]_3\,
I1 => \gen_axilite.s_axi_arready_i_reg\,
I2 => \m_atarget_enc_reg[1]_2\,
I3 => m_ready_d_1(1),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => m_ready_d0_0(0)
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FFFDFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \m_atarget_enc_reg[2]_2\,
I2 => \m_atarget_enc_reg[1]_0\,
I3 => m_ready_d(2),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \^m_ready_d0\(0)
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(1),
I1 => m_valid_i_i_2_n_0,
I2 => m_valid_i_i_3_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => sr_rvalid,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_rready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAA8AAA8AAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => \m_atarget_enc_reg[0]\,
I5 => \m_atarget_enc_reg[1]_1\,
O => m_valid_i_i_3_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \m_atarget_enc_reg[1]\,
O => s_axi_bvalid(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_grant_any,
I1 => sr_rvalid,
O => s_axi_rvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \m_atarget_enc_reg[2]_0\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(0),
I1 => m_valid_i_i_3_n_0,
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\m_ready_d_reg[2]_0\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal m_valid_i_i_6_n_0 : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F07F0000"
)
port map (
I0 => Q(0),
I1 => \m_ready_d_reg[1]_2\,
I2 => mi_arready(6),
I3 => mi_rvalid(6),
I4 => aresetn_d,
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
Q => mi_arready(6),
R => '0'
);
\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => \m_ready_d_reg[2]_0\,
I3 => Q(0),
I4 => \^mi_wready\(0),
O => \gen_axilite.s_axi_awready_i_i_1_n_0\
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_i_1_n_0\,
Q => \^mi_wready\(0),
R => SR(0)
);
\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_reg_0\,
Q => \^mi_bvalid\(0),
R => SR(0)
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF8800"
)
port map (
I0 => mi_arready(6),
I1 => \m_ready_d_reg[1]_2\,
I2 => aa_rready,
I3 => Q(0),
I4 => mi_rvalid(6),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
Q => mi_rvalid(6),
R => SR(0)
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"08300800"
)
port map (
I0 => mi_arready(6),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_arready(0),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F3F5FFFFF3F5F"
)
port map (
I0 => m_axi_awready(0),
I1 => m_axi_awready(1),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => \^mi_wready\(0),
O => \m_ready_d_reg[2]\
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF08030800"
)
port map (
I0 => m_axi_rvalid(2),
I1 => \m_atarget_enc_reg[2]\(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rvalid(0),
I5 => m_valid_i_i_6_n_0,
O => m_valid_i_reg
);
m_valid_i_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"08300800"
)
port map (
I0 => mi_rvalid(6),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rvalid(1),
O => m_valid_i_i_6_n_0
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A008A8A"
)
port map (
I0 => \m_atarget_enc_reg[1]_0\,
I1 => \m_atarget_enc_reg[1]_1\,
I2 => m_axi_bvalid(1),
I3 => \m_atarget_enc_reg[2]_2\,
I4 => m_axi_bvalid(2),
I5 => \^m_ready_d_reg[0]_0\,
O => \m_ready_d_reg[0]\
);
\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00830080"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => m_axi_bvalid(0),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A008A8A"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[1]\,
I2 => m_axi_wready(0),
I3 => \m_atarget_enc_reg[2]_1\,
I4 => m_axi_wready(2),
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d_reg[1]\
);
\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B000800"
)
port map (
I0 => \^mi_wready\(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter is
port (
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_2\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[0]_3\ : out STD_LOGIC;
\m_ready_d_reg[1]_2\ : out STD_LOGIC;
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\gen_axilite.s_axi_awready_i_reg\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
aresetn_d : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_3_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_8_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_ready_d[2]_i_5\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_6\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_8\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_3\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_4\ : label is "soft_lutpair27";
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[0]_1\ <= \^m_ready_d_reg[0]_1\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \^m_ready_d_reg[1]_0\,
I2 => \m_atarget_enc_reg[2]_0\,
I3 => \gen_axilite.s_axi_awready_i_reg\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_atarget_enc_reg[1]\,
I2 => \gen_no_arbiter.grant_rnw_reg_0\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_atarget_enc_reg[2]\,
I2 => \gen_no_arbiter.grant_rnw_reg\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_ready_d0(0),
I1 => \m_ready_d[2]_i_3_n_0\,
I2 => aresetn_d,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABBFFFF"
)
port map (
I0 => \^m_ready_d_reg[0]_0\,
I1 => \^m_ready_d\(1),
I2 => \m_atarget_enc_reg[2]\,
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => m_ready_d0(0),
O => \m_ready_d[2]_i_3_n_0\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"23002000"
)
port map (
I0 => m_axi_awready(3),
I1 => Q(2),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_awready(2),
O => \m_ready_d_reg[2]_1\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00320002"
)
port map (
I0 => m_axi_awready(0),
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => m_axi_awready(1),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \^m_ready_d_reg[0]_1\,
I2 => \m_ready_d[2]_i_8_n_0\,
I3 => \gen_axilite.s_axi_bvalid_i_reg\,
I4 => \gen_no_arbiter.grant_rnw_reg_0\,
O => \^m_ready_d_reg[0]_0\
);
\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C080008"
)
port map (
I0 => m_axi_bvalid(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_bvalid(4),
O => \m_ready_d[2]_i_8_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF053FFFFFF53F"
)
port map (
I0 => m_axi_bvalid(0),
I1 => m_axi_bvalid(1),
I2 => Q(1),
I3 => Q(0),
I4 => Q(2),
I5 => m_axi_bvalid(2),
O => \^m_ready_d_reg[0]_1\
);
\s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
O => \m_ready_d_reg[0]_2\
);
\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => \m_ready_d_reg[0]_3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF530FFFFF53FF"
)
port map (
I0 => m_axi_wready(2),
I1 => m_axi_wready(0),
I2 => Q(2),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
O => \m_ready_d_reg[1]_1\
);
\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => \m_ready_d_reg[1]_2\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
sr_rvalid : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_15_splitter";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0080"
)
port map (
I0 => sr_rvalid,
I1 => \m_payload_i_reg[0]\(0),
I2 => s_axi_rready(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^m_ready_d\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => m_valid_i_reg,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FF5F3FFFFF5F3F"
)
port map (
I0 => m_axi_arready(2),
I1 => m_axi_arready(1),
I2 => Q(1),
I3 => Q(0),
I4 => Q(2),
I5 => m_axi_arready(4),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d[1]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => m_axi_arready(3),
I1 => Q(1),
I2 => Q(2),
I3 => Q(0),
I4 => m_axi_arready(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
m_valid_i_reg_0 : out STD_LOGIC;
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_hot_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[10]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_3_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair21";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_rready <= \^aa_rready\;
m_valid_i_reg_1(1 downto 0) <= \^m_valid_i_reg_1\(1 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_1\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_1\(0),
Q => \^m_valid_i_reg_1\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(3),
O => m_axi_rready(3)
);
\m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(4),
O => m_axi_rready(4)
);
\m_axi_rready[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(5),
O => m_axi_rready(5)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CA000F00CA0000"
)
port map (
I0 => m_axi_rdata(135),
I1 => m_axi_rdata(167),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(7),
O => \m_payload_i[10]_i_2_n_0\
);
\m_payload_i[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(71),
I1 => m_axi_rdata(103),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(39),
O => \m_payload_i[10]_i_3_n_0\
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(8),
I1 => m_axi_rdata(168),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(136),
O => \m_payload_i[11]_i_2_n_0\
);
\m_payload_i[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_axi_rdata(40),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(104),
O => \m_payload_i[11]_i_3_n_0\
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(9),
I1 => m_axi_rdata(137),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(169),
O => \m_payload_i[12]_i_2_n_0\
);
\m_payload_i[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_axi_rdata(41),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(105),
O => \m_payload_i[12]_i_3_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(10),
I1 => m_axi_rdata(138),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(170),
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_axi_rdata(42),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(106),
O => \m_payload_i[13]_i_3_n_0\
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(11),
I1 => m_axi_rdata(139),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(171),
O => \m_payload_i[14]_i_2_n_0\
);
\m_payload_i[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0F0A000C000A00"
)
port map (
I0 => m_axi_rdata(43),
I1 => m_axi_rdata(107),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(75),
O => \m_payload_i[14]_i_3_n_0\
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(76),
I1 => m_axi_rdata(44),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(108),
O => \m_payload_i[15]_i_2_n_0\
);
\m_payload_i[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_axi_rdata(140),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(172),
O => \m_payload_i[15]_i_3_n_0\
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(13),
I1 => m_axi_rdata(141),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(173),
O => \m_payload_i[16]_i_2_n_0\
);
\m_payload_i[16]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(77),
I1 => m_axi_rdata(45),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(109),
O => \m_payload_i[16]_i_3_n_0\
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(14),
I1 => m_axi_rdata(142),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(174),
O => \m_payload_i[17]_i_2_n_0\
);
\m_payload_i[17]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(78),
I1 => m_axi_rdata(46),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(110),
O => \m_payload_i[17]_i_3_n_0\
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(15),
I1 => m_axi_rdata(175),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(143),
O => \m_payload_i[18]_i_2_n_0\
);
\m_payload_i[18]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(79),
I1 => m_axi_rdata(47),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(111),
O => \m_payload_i[18]_i_3_n_0\
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(16),
I1 => m_axi_rdata(176),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(144),
O => \m_payload_i[19]_i_2_n_0\
);
\m_payload_i[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_axi_rdata(112),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(48),
O => \m_payload_i[19]_i_3_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[1]_i_2_n_0\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_rresp(8),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(2),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rresp(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rresp(4),
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00A2AAAA0AA2AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(6),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(10),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(17),
I1 => m_axi_rdata(177),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(145),
O => \m_payload_i[20]_i_2_n_0\
);
\m_payload_i[20]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(113),
I1 => m_axi_rdata(49),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(81),
O => \m_payload_i[20]_i_3_n_0\
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(18),
I1 => m_axi_rdata(146),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(178),
O => \m_payload_i[21]_i_2_n_0\
);
\m_payload_i[21]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(82),
I1 => m_axi_rdata(50),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(114),
O => \m_payload_i[21]_i_3_n_0\
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(19),
I1 => m_axi_rdata(179),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(147),
O => \m_payload_i[22]_i_2_n_0\
);
\m_payload_i[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(83),
I1 => m_axi_rdata(51),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(115),
O => \m_payload_i[22]_i_3_n_0\
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(20),
I1 => m_axi_rdata(180),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(148),
O => \m_payload_i[23]_i_2_n_0\
);
\m_payload_i[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(84),
I1 => m_axi_rdata(52),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(116),
O => \m_payload_i[23]_i_3_n_0\
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(21),
I1 => m_axi_rdata(149),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(181),
O => \m_payload_i[24]_i_2_n_0\
);
\m_payload_i[24]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_axi_rdata(53),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(117),
O => \m_payload_i[24]_i_3_n_0\
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(22),
I1 => m_axi_rdata(150),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(182),
O => \m_payload_i[25]_i_2_n_0\
);
\m_payload_i[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(86),
I1 => m_axi_rdata(54),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(118),
O => \m_payload_i[25]_i_3_n_0\
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_axi_rdata(183),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(151),
O => \m_payload_i[26]_i_2_n_0\
);
\m_payload_i[26]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(87),
I1 => m_axi_rdata(55),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(119),
O => \m_payload_i[26]_i_3_n_0\
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(24),
I1 => m_axi_rdata(184),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(152),
O => \m_payload_i[27]_i_2_n_0\
);
\m_payload_i[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(120),
I1 => m_axi_rdata(56),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(88),
O => \m_payload_i[27]_i_3_n_0\
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(121),
I1 => m_axi_rdata(57),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(89),
O => \m_payload_i[28]_i_2_n_0\
);
\m_payload_i[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_axi_rdata(153),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(185),
O => \m_payload_i[28]_i_3_n_0\
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(122),
I1 => m_axi_rdata(58),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(90),
O => \m_payload_i[29]_i_2_n_0\
);
\m_payload_i[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(26),
I1 => m_axi_rdata(154),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(186),
O => \m_payload_i[29]_i_3_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
I4 => \m_payload_i[2]_i_4_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_rresp(9),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(3),
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rresp(1),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rresp(5),
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00A2AAAA0AA2AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(7),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(11),
O => \m_payload_i[2]_i_4_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(27),
I1 => m_axi_rdata(155),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(187),
O => \m_payload_i[30]_i_2_n_0\
);
\m_payload_i[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_axi_rdata(123),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(59),
O => \m_payload_i[30]_i_3_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(92),
I1 => m_axi_rdata(60),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(124),
O => \m_payload_i[31]_i_2_n_0\
);
\m_payload_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_axi_rdata(156),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(188),
O => \m_payload_i[31]_i_3_n_0\
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[32]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(125),
I1 => m_axi_rdata(61),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(93),
O => \m_payload_i[32]_i_2_n_0\
);
\m_payload_i[32]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(29),
I1 => m_axi_rdata(157),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(189),
O => \m_payload_i[32]_i_3_n_0\
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(30),
I1 => m_axi_rdata(158),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(190),
O => \m_payload_i[33]_i_2_n_0\
);
\m_payload_i[33]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(94),
I1 => m_axi_rdata(62),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(126),
O => \m_payload_i[33]_i_3_n_0\
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(31),
I1 => m_axi_rdata(159),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(191),
O => \m_payload_i[34]_i_3_n_0\
);
\m_payload_i[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_axi_rdata(63),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(127),
O => \m_payload_i[34]_i_4_n_0\
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(0),
I1 => m_axi_rdata(128),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(160),
O => \m_payload_i[3]_i_2_n_0\
);
\m_payload_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_axi_rdata(96),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(32),
O => \m_payload_i[3]_i_3_n_0\
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(1),
I1 => m_axi_rdata(161),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(129),
O => \m_payload_i[4]_i_2_n_0\
);
\m_payload_i[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(65),
I1 => m_axi_rdata(33),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(97),
O => \m_payload_i[4]_i_3_n_0\
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(2),
I1 => m_axi_rdata(130),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(162),
O => \m_payload_i[5]_i_2_n_0\
);
\m_payload_i[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(66),
I1 => m_axi_rdata(34),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(98),
O => \m_payload_i[5]_i_3_n_0\
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_axi_rdata(163),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(131),
O => \m_payload_i[6]_i_2_n_0\
);
\m_payload_i[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_axi_rdata(99),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(35),
O => \m_payload_i[6]_i_3_n_0\
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(4),
I1 => m_axi_rdata(164),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(132),
O => \m_payload_i[7]_i_2_n_0\
);
\m_payload_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(68),
I1 => m_axi_rdata(36),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(100),
O => \m_payload_i[7]_i_3_n_0\
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(5),
I1 => m_axi_rdata(133),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(165),
O => \m_payload_i[8]_i_2_n_0\
);
\m_payload_i[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_axi_rdata(37),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(101),
O => \m_payload_i[8]_i_3_n_0\
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(6),
I1 => m_axi_rdata(134),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(166),
O => \m_payload_i[9]_i_2_n_0\
);
\m_payload_i[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(70),
I1 => m_axi_rdata(38),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(102),
O => \m_payload_i[9]_i_3_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => \^sr_rvalid\,
I1 => \^q\(0),
I2 => s_axi_rready(0),
I3 => aa_grant_rnw,
I4 => m_valid_i,
I5 => m_ready_d(0),
O => \m_ready_d_reg[1]\
);
m_valid_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF05F3FFFFF5F3F"
)
port map (
I0 => m_axi_rvalid(1),
I1 => m_axi_rvalid(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rvalid(2),
O => m_valid_i_reg_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7FFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]\(2),
I1 => \m_atarget_enc_reg[2]\(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \skid_buffer_reg_n_0_[0]\,
I4 => \^aa_rready\,
O => skid_buffer(0)
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd is
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_10 : STD_LOGIC;
signal addr_arbiter_inst_n_19 : STD_LOGIC;
signal addr_arbiter_inst_n_27 : STD_LOGIC;
signal addr_arbiter_inst_n_3 : STD_LOGIC;
signal addr_arbiter_inst_n_34 : STD_LOGIC;
signal addr_arbiter_inst_n_35 : STD_LOGIC;
signal addr_arbiter_inst_n_36 : STD_LOGIC;
signal addr_arbiter_inst_n_38 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_46 : STD_LOGIC;
signal addr_arbiter_inst_n_47 : STD_LOGIC;
signal addr_arbiter_inst_n_51 : STD_LOGIC;
signal addr_arbiter_inst_n_52 : STD_LOGIC;
signal addr_arbiter_inst_n_53 : STD_LOGIC;
signal addr_arbiter_inst_n_6 : STD_LOGIC;
signal addr_arbiter_inst_n_8 : STD_LOGIC;
signal addr_arbiter_inst_n_89 : STD_LOGIC;
signal addr_arbiter_inst_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_atarget_hot : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 5 downto 3 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 2 to 2 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_bvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal mi_wready : STD_LOGIC_VECTOR ( 6 to 6 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_37 : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
signal splitter_ar_n_1 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_10 : STD_LOGIC;
signal splitter_aw_n_11 : STD_LOGIC;
signal splitter_aw_n_12 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal splitter_aw_n_7 : STD_LOGIC;
signal splitter_aw_n_8 : STD_LOGIC;
signal splitter_aw_n_9 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
begin
addr_arbiter_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd
port map (
D(6) => addr_arbiter_inst_n_4,
D(5) => m_atarget_hot0(5),
D(4) => addr_arbiter_inst_n_6,
D(3) => m_atarget_hot0(3),
D(2) => addr_arbiter_inst_n_8,
D(1) => addr_arbiter_inst_n_9,
D(0) => addr_arbiter_inst_n_10,
E(0) => p_1_in,
Q(6 downto 0) => m_atarget_hot(6 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\aresetn_d_reg[1]\(1) => reg_slice_r_n_45,
\aresetn_d_reg[1]\(0) => reg_slice_r_n_46,
\gen_axilite.s_axi_arready_i_reg\ => \gen_decerr.decerr_slave_inst_n_7\,
\gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_19,
\gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_27,
\gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_34,
\gen_axilite.s_axi_bvalid_i_reg_2\ => addr_arbiter_inst_n_89,
\gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_38,
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_47,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_2\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_7,
\m_atarget_enc_reg[1]_1\ => reg_slice_r_n_38,
\m_atarget_enc_reg[1]_2\ => splitter_ar_n_0,
\m_atarget_enc_reg[1]_3\ => splitter_ar_n_1,
\m_atarget_enc_reg[2]\(2) => addr_arbiter_inst_n_51,
\m_atarget_enc_reg[2]\(1) => addr_arbiter_inst_n_52,
\m_atarget_enc_reg[2]\(0) => addr_arbiter_inst_n_53,
\m_atarget_enc_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_9,
\m_atarget_enc_reg[2]_3\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_axi_arprot[2]\(34 downto 0) => Q(34 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_wready(1) => m_axi_wready(3),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
m_ready_d0_0(0) => m_ready_d0(1),
m_ready_d_1(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_3,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_46,
\m_ready_d_reg[0]_1\ => splitter_aw_n_0,
\m_ready_d_reg[1]\ => splitter_aw_n_5,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_36,
m_valid_i_reg_0 => reg_slice_r_n_2,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_35,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave
port map (
Q(0) => m_atarget_hot(6),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_89,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_27,
\m_atarget_enc_reg[1]\ => splitter_aw_n_10,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_4,
\m_atarget_enc_reg[1]_1\ => splitter_aw_n_8,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[2]_0\ => splitter_aw_n_6,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_12,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_11,
m_axi_arready(0) => m_axi_arready(1),
m_axi_awready(1 downto 0) => m_axi_awready(5 downto 4),
m_axi_bvalid(2 downto 1) => m_axi_bvalid(5 downto 4),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rvalid(2) => m_axi_rvalid(5),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(2 downto 1) => m_axi_wready(3 downto 2),
m_axi_wready(0) => m_axi_wready(0),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_4\,
\m_ready_d_reg[1]_1\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[1]_2\ => addr_arbiter_inst_n_38,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_34,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_2\,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6)
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_53,
Q => m_atarget_enc(0),
R => '0'
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_52,
Q => m_atarget_enc(1),
R => '0'
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_51,
Q => m_atarget_enc(2),
R => '0'
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_10,
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_9,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_8,
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(3),
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_6,
Q => m_atarget_hot(4),
R => reset
);
\m_atarget_hot_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(5),
Q => m_atarget_hot(5),
R => reset
);
\m_atarget_hot_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_4,
Q => m_atarget_hot(6),
R => reset
);
reg_slice_r: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
port map (
E(0) => p_1_in,
Q(34 downto 1) => \s_axi_rdata[31]\(33 downto 0),
Q(0) => reg_slice_r_n_37,
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_35,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_36,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_hot_reg[5]\(5 downto 0) => m_atarget_hot(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(2 downto 0) => m_axi_rvalid(4 downto 2),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_38,
m_valid_i_reg_1(1) => reg_slice_r_n_45,
m_valid_i_reg_1(0) => reg_slice_r_n_46,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[0]_INST_0_i_2_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(0),
I1 => m_axi_bresp(8),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(10),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(4),
I1 => m_axi_bresp(2),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(6),
O => \s_axi_bresp[0]_INST_0_i_2_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[1]_INST_0_i_2_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(1),
I1 => m_axi_bresp(9),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(11),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(5),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(7),
O => \s_axi_bresp[1]_INST_0_i_2_n_0\
);
splitter_ar: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_3,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_46,
m_axi_arready(4 downto 1) => m_axi_arready(5 downto 2),
m_axi_arready(0) => m_axi_arready(0),
\m_payload_i_reg[0]\(0) => reg_slice_r_n_37,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0(1),
\m_ready_d_reg[1]_0\ => splitter_ar_n_0,
\m_ready_d_reg[1]_1\ => splitter_ar_n_1,
m_valid_i_reg => reg_slice_r_n_2,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg\ => \gen_decerr.decerr_slave_inst_n_4\,
\gen_axilite.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_6\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_27,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_19,
\gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_5,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_0\ => addr_arbiter_inst_n_47,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_bvalid(4 downto 0) => m_axi_bvalid(5 downto 1),
m_axi_wready(2 downto 1) => m_axi_wready(5 downto 4),
m_axi_wready(0) => m_axi_wready(1),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
\m_ready_d_reg[0]_0\ => splitter_aw_n_0,
\m_ready_d_reg[0]_1\ => splitter_aw_n_4,
\m_ready_d_reg[0]_2\ => splitter_aw_n_8,
\m_ready_d_reg[0]_3\ => splitter_aw_n_11,
\m_ready_d_reg[1]_0\ => splitter_aw_n_6,
\m_ready_d_reg[1]_1\ => splitter_aw_n_10,
\m_ready_d_reg[1]_2\ => splitter_aw_n_12,
\m_ready_d_reg[2]_0\ => splitter_aw_n_7,
\m_ready_d_reg[2]_1\ => splitter_aw_n_9
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 191 downto 172 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_arburst(11) <= \<const0>\;
m_axi_arburst(10) <= \<const0>\;
m_axi_arburst(9) <= \<const0>\;
m_axi_arburst(8) <= \<const0>\;
m_axi_arburst(7) <= \<const0>\;
m_axi_arburst(6) <= \<const0>\;
m_axi_arburst(5) <= \<const0>\;
m_axi_arburst(4) <= \<const0>\;
m_axi_arburst(3) <= \<const0>\;
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(23) <= \<const0>\;
m_axi_arcache(22) <= \<const0>\;
m_axi_arcache(21) <= \<const0>\;
m_axi_arcache(20) <= \<const0>\;
m_axi_arcache(19) <= \<const0>\;
m_axi_arcache(18) <= \<const0>\;
m_axi_arcache(17) <= \<const0>\;
m_axi_arcache(16) <= \<const0>\;
m_axi_arcache(15) <= \<const0>\;
m_axi_arcache(14) <= \<const0>\;
m_axi_arcache(13) <= \<const0>\;
m_axi_arcache(12) <= \<const0>\;
m_axi_arcache(11) <= \<const0>\;
m_axi_arcache(10) <= \<const0>\;
m_axi_arcache(9) <= \<const0>\;
m_axi_arcache(8) <= \<const0>\;
m_axi_arcache(7) <= \<const0>\;
m_axi_arcache(6) <= \<const0>\;
m_axi_arcache(5) <= \<const0>\;
m_axi_arcache(4) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(47) <= \<const0>\;
m_axi_arlen(46) <= \<const0>\;
m_axi_arlen(45) <= \<const0>\;
m_axi_arlen(44) <= \<const0>\;
m_axi_arlen(43) <= \<const0>\;
m_axi_arlen(42) <= \<const0>\;
m_axi_arlen(41) <= \<const0>\;
m_axi_arlen(40) <= \<const0>\;
m_axi_arlen(39) <= \<const0>\;
m_axi_arlen(38) <= \<const0>\;
m_axi_arlen(37) <= \<const0>\;
m_axi_arlen(36) <= \<const0>\;
m_axi_arlen(35) <= \<const0>\;
m_axi_arlen(34) <= \<const0>\;
m_axi_arlen(33) <= \<const0>\;
m_axi_arlen(32) <= \<const0>\;
m_axi_arlen(31) <= \<const0>\;
m_axi_arlen(30) <= \<const0>\;
m_axi_arlen(29) <= \<const0>\;
m_axi_arlen(28) <= \<const0>\;
m_axi_arlen(27) <= \<const0>\;
m_axi_arlen(26) <= \<const0>\;
m_axi_arlen(25) <= \<const0>\;
m_axi_arlen(24) <= \<const0>\;
m_axi_arlen(23) <= \<const0>\;
m_axi_arlen(22) <= \<const0>\;
m_axi_arlen(21) <= \<const0>\;
m_axi_arlen(20) <= \<const0>\;
m_axi_arlen(19) <= \<const0>\;
m_axi_arlen(18) <= \<const0>\;
m_axi_arlen(17) <= \<const0>\;
m_axi_arlen(16) <= \<const0>\;
m_axi_arlen(15) <= \<const0>\;
m_axi_arlen(14) <= \<const0>\;
m_axi_arlen(13) <= \<const0>\;
m_axi_arlen(12) <= \<const0>\;
m_axi_arlen(11) <= \<const0>\;
m_axi_arlen(10) <= \<const0>\;
m_axi_arlen(9) <= \<const0>\;
m_axi_arlen(8) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(5) <= \<const0>\;
m_axi_arlock(4) <= \<const0>\;
m_axi_arlock(3) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(23) <= \<const0>\;
m_axi_arqos(22) <= \<const0>\;
m_axi_arqos(21) <= \<const0>\;
m_axi_arqos(20) <= \<const0>\;
m_axi_arqos(19) <= \<const0>\;
m_axi_arqos(18) <= \<const0>\;
m_axi_arqos(17) <= \<const0>\;
m_axi_arqos(16) <= \<const0>\;
m_axi_arqos(15) <= \<const0>\;
m_axi_arqos(14) <= \<const0>\;
m_axi_arqos(13) <= \<const0>\;
m_axi_arqos(12) <= \<const0>\;
m_axi_arqos(11) <= \<const0>\;
m_axi_arqos(10) <= \<const0>\;
m_axi_arqos(9) <= \<const0>\;
m_axi_arqos(8) <= \<const0>\;
m_axi_arqos(7) <= \<const0>\;
m_axi_arqos(6) <= \<const0>\;
m_axi_arqos(5) <= \<const0>\;
m_axi_arqos(4) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(23) <= \<const0>\;
m_axi_arregion(22) <= \<const0>\;
m_axi_arregion(21) <= \<const0>\;
m_axi_arregion(20) <= \<const0>\;
m_axi_arregion(19) <= \<const0>\;
m_axi_arregion(18) <= \<const0>\;
m_axi_arregion(17) <= \<const0>\;
m_axi_arregion(16) <= \<const0>\;
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(17) <= \<const0>\;
m_axi_arsize(16) <= \<const0>\;
m_axi_arsize(15) <= \<const0>\;
m_axi_arsize(14) <= \<const0>\;
m_axi_arsize(13) <= \<const0>\;
m_axi_arsize(12) <= \<const0>\;
m_axi_arsize(11) <= \<const0>\;
m_axi_arsize(10) <= \<const0>\;
m_axi_arsize(9) <= \<const0>\;
m_axi_arsize(8) <= \<const0>\;
m_axi_arsize(7) <= \<const0>\;
m_axi_arsize(6) <= \<const0>\;
m_axi_arsize(5) <= \<const0>\;
m_axi_arsize(4) <= \<const0>\;
m_axi_arsize(3) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(5) <= \<const0>\;
m_axi_aruser(4) <= \<const0>\;
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_awburst(11) <= \<const0>\;
m_axi_awburst(10) <= \<const0>\;
m_axi_awburst(9) <= \<const0>\;
m_axi_awburst(8) <= \<const0>\;
m_axi_awburst(7) <= \<const0>\;
m_axi_awburst(6) <= \<const0>\;
m_axi_awburst(5) <= \<const0>\;
m_axi_awburst(4) <= \<const0>\;
m_axi_awburst(3) <= \<const0>\;
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(23) <= \<const0>\;
m_axi_awcache(22) <= \<const0>\;
m_axi_awcache(21) <= \<const0>\;
m_axi_awcache(20) <= \<const0>\;
m_axi_awcache(19) <= \<const0>\;
m_axi_awcache(18) <= \<const0>\;
m_axi_awcache(17) <= \<const0>\;
m_axi_awcache(16) <= \<const0>\;
m_axi_awcache(15) <= \<const0>\;
m_axi_awcache(14) <= \<const0>\;
m_axi_awcache(13) <= \<const0>\;
m_axi_awcache(12) <= \<const0>\;
m_axi_awcache(11) <= \<const0>\;
m_axi_awcache(10) <= \<const0>\;
m_axi_awcache(9) <= \<const0>\;
m_axi_awcache(8) <= \<const0>\;
m_axi_awcache(7) <= \<const0>\;
m_axi_awcache(6) <= \<const0>\;
m_axi_awcache(5) <= \<const0>\;
m_axi_awcache(4) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(47) <= \<const0>\;
m_axi_awlen(46) <= \<const0>\;
m_axi_awlen(45) <= \<const0>\;
m_axi_awlen(44) <= \<const0>\;
m_axi_awlen(43) <= \<const0>\;
m_axi_awlen(42) <= \<const0>\;
m_axi_awlen(41) <= \<const0>\;
m_axi_awlen(40) <= \<const0>\;
m_axi_awlen(39) <= \<const0>\;
m_axi_awlen(38) <= \<const0>\;
m_axi_awlen(37) <= \<const0>\;
m_axi_awlen(36) <= \<const0>\;
m_axi_awlen(35) <= \<const0>\;
m_axi_awlen(34) <= \<const0>\;
m_axi_awlen(33) <= \<const0>\;
m_axi_awlen(32) <= \<const0>\;
m_axi_awlen(31) <= \<const0>\;
m_axi_awlen(30) <= \<const0>\;
m_axi_awlen(29) <= \<const0>\;
m_axi_awlen(28) <= \<const0>\;
m_axi_awlen(27) <= \<const0>\;
m_axi_awlen(26) <= \<const0>\;
m_axi_awlen(25) <= \<const0>\;
m_axi_awlen(24) <= \<const0>\;
m_axi_awlen(23) <= \<const0>\;
m_axi_awlen(22) <= \<const0>\;
m_axi_awlen(21) <= \<const0>\;
m_axi_awlen(20) <= \<const0>\;
m_axi_awlen(19) <= \<const0>\;
m_axi_awlen(18) <= \<const0>\;
m_axi_awlen(17) <= \<const0>\;
m_axi_awlen(16) <= \<const0>\;
m_axi_awlen(15) <= \<const0>\;
m_axi_awlen(14) <= \<const0>\;
m_axi_awlen(13) <= \<const0>\;
m_axi_awlen(12) <= \<const0>\;
m_axi_awlen(11) <= \<const0>\;
m_axi_awlen(10) <= \<const0>\;
m_axi_awlen(9) <= \<const0>\;
m_axi_awlen(8) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(5) <= \<const0>\;
m_axi_awlock(4) <= \<const0>\;
m_axi_awlock(3) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(23) <= \<const0>\;
m_axi_awqos(22) <= \<const0>\;
m_axi_awqos(21) <= \<const0>\;
m_axi_awqos(20) <= \<const0>\;
m_axi_awqos(19) <= \<const0>\;
m_axi_awqos(18) <= \<const0>\;
m_axi_awqos(17) <= \<const0>\;
m_axi_awqos(16) <= \<const0>\;
m_axi_awqos(15) <= \<const0>\;
m_axi_awqos(14) <= \<const0>\;
m_axi_awqos(13) <= \<const0>\;
m_axi_awqos(12) <= \<const0>\;
m_axi_awqos(11) <= \<const0>\;
m_axi_awqos(10) <= \<const0>\;
m_axi_awqos(9) <= \<const0>\;
m_axi_awqos(8) <= \<const0>\;
m_axi_awqos(7) <= \<const0>\;
m_axi_awqos(6) <= \<const0>\;
m_axi_awqos(5) <= \<const0>\;
m_axi_awqos(4) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(23) <= \<const0>\;
m_axi_awregion(22) <= \<const0>\;
m_axi_awregion(21) <= \<const0>\;
m_axi_awregion(20) <= \<const0>\;
m_axi_awregion(19) <= \<const0>\;
m_axi_awregion(18) <= \<const0>\;
m_axi_awregion(17) <= \<const0>\;
m_axi_awregion(16) <= \<const0>\;
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(17) <= \<const0>\;
m_axi_awsize(16) <= \<const0>\;
m_axi_awsize(15) <= \<const0>\;
m_axi_awsize(14) <= \<const0>\;
m_axi_awsize(13) <= \<const0>\;
m_axi_awsize(12) <= \<const0>\;
m_axi_awsize(11) <= \<const0>\;
m_axi_awsize(10) <= \<const0>\;
m_axi_awsize(9) <= \<const0>\;
m_axi_awsize(8) <= \<const0>\;
m_axi_awsize(7) <= \<const0>\;
m_axi_awsize(6) <= \<const0>\;
m_axi_awsize(5) <= \<const0>\;
m_axi_awsize(4) <= \<const0>\;
m_axi_awsize(3) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(5) <= \<const0>\;
m_axi_awuser(4) <= \<const0>\;
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(191 downto 160) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(159 downto 128) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(5) <= \<const0>\;
m_axi_wlast(4) <= \<const0>\;
m_axi_wlast(3) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
m_axi_wstrb(23 downto 20) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(19 downto 16) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(5) <= \<const0>\;
m_axi_wuser(4) <= \<const0>\;
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
Q(31 downto 12) => \^m_axi_awaddr\(191 downto 172),
Q(11 downto 0) => \^m_axi_araddr\(11 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(33 downto 2) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5]";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20]";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(191 downto 0) => m_axi_araddr(191 downto 0),
m_axi_arburst(11 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(11 downto 0),
m_axi_arcache(23 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(23 downto 0),
m_axi_arid(5 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(5 downto 0),
m_axi_arlen(47 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(47 downto 0),
m_axi_arlock(5 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(5 downto 0),
m_axi_arprot(17 downto 0) => m_axi_arprot(17 downto 0),
m_axi_arqos(23 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(23 downto 0),
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arregion(23 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(23 downto 0),
m_axi_arsize(17 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(17 downto 0),
m_axi_aruser(5 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awaddr(191 downto 0) => m_axi_awaddr(191 downto 0),
m_axi_awburst(11 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(11 downto 0),
m_axi_awcache(23 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(23 downto 0),
m_axi_awid(5 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(5 downto 0),
m_axi_awlen(47 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(47 downto 0),
m_axi_awlock(5 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(5 downto 0),
m_axi_awprot(17 downto 0) => m_axi_awprot(17 downto 0),
m_axi_awqos(23 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(23 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awregion(23 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(23 downto 0),
m_axi_awsize(17 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(17 downto 0),
m_axi_awuser(5 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bid(5 downto 0) => B"000000",
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_buser(5 downto 0) => B"000000",
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rid(5 downto 0) => B"000000",
m_axi_rlast(5 downto 0) => B"111111",
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_ruser(5 downto 0) => B"000000",
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wdata(191 downto 0) => m_axi_wdata(191 downto 0),
m_axi_wid(5 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(5 downto 0),
m_axi_wlast(5 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wstrb(23 downto 0) => m_axi_wstrb(23 downto 0),
m_axi_wuser(5 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast(0) => '1',
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 37983de296f99f2fa402447dfdbccc6f | 0.558139 | 2.632942 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/DPATH.vhd | 1 | 5,751 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity DPATH is
port(
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- operation type
OT: in operation;
-- operand
OP: in operand;
-- result
RES: out operand;
-- zero flag
ZF: out std_logic;
-- stop - the processing is finished
Stop: out std_logic
);
end DPATH;
architecture Beh_Stack of DPATH is
component LIFO
generic(
-- address bus
m: integer := 2;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- write/read operation type
WR: in std_logic;
-- read data bus
RB: out std_logic_vector(n-1 downto 0);
-- write data bus
WB: in std_logic_vector(n-1 downto 0)
);
end component;
type states is (I, IPOP1, IPOP2, A, SB, SH, IPUSH, MOVERES, MOVERESOP, H);
-- I - Idle - the initial state for operations
-- IPOP1 - POP 1 - pop the value and put it into the first internal operand i_op1
-- IPOP2 - POP 2 - pop the value and put it into the second internal operand i_op2
-- A - res_op = i_op1 + i_op2
-- SB - res_op = i_op1 - i_op2
-- IPUSH - PUSH - push the value of res_op to the stack
-- MOVERES - i_res = i_op1 - used in external POP operation
-- MOVERESOP - res_op = i_op - used in external push operation
-- H - Halt - indicates that the processing has been completed
signal nxt_state, cur_state: states;
-- operation result
signal res_op: operand;
-- internal input operand value
signal i_op: operand;
-- internal first operand value
signal i_op1: operand;
-- internal second operand value
signal i_op2: operand;
-- the result of the data path
signal i_res: operand;
signal s_en: std_logic;
signal s_wr: std_logic;
signal s_res: operand;
signal s_data: operand;
signal t_zf: std_logic;
Begin
USTACK: LIFO
generic map(
m => 5,
n => 16
)
port map(
CLK => CLK,
EN => s_en,
WR => s_wr,
RB => s_res,
WB => s_data
);
i_op <= OP;
FSM: process(CLK, nxt_state)
begin
if rising_edge(CLK) then
cur_state <= nxt_state;
end if;
end process;
-- Next state
COMB: process(cur_state, EN, OT)
begin
case cur_state is
when I =>
if (EN = '1') then
case OT is
when ADD | SUBT | SHIFT | POP | POPIN => nxt_state <= IPOP1;
when others => nxt_state <= MOVERESOP;
end case;
else
nxt_state <= I;
end if;
when IPOP1 =>
if (OT = POP or OT = POPIN) then
nxt_state <= MOVERES;
elsif (OT = SHIFT) then
nxt_state <= SH;
else
nxt_state <= IPOP2;
end if;
when IPOP2 =>
if (OT = ADD) then
nxt_state <= A;
else
nxt_state <= SB;
end if;
when A | SB | SH | MOVERESOP => nxt_state <= IPUSH;
when MOVERES => nxt_state <= H;
when IPUSH => nxt_state <= H;
when H => nxt_state <= I;
when others => nxt_state <= I;
end case;
end process;
-- stop signal handler
PSTOP: process (cur_state)
begin
if (cur_state = H) then
stop <= '1';
else
stop <= '0';
end if;
end process;
STACKCTRL: process (cur_state, nxt_state)
begin
if (nxt_state = IPOP1 or nxt_state = IPOP2) then
s_wr <= '1';
s_en <= '1';
elsif (cur_state = IPUSH) then
s_wr <= '0';
s_en <= '1';
else
s_wr <= '1';
s_en <= '0';
end if;
end process;
OP1CTRL: process (cur_state, s_res)
begin
if (cur_state = IPOP1) then
i_op1 <= s_res;
end if;
end process;
OP2CTRL: process (cur_state, s_res)
begin
if (cur_state = IPOP2) then
i_op2 <= s_res;
end if;
end process;
OPRESULTCTRL: process (cur_state, i_op1, i_op2, i_op)
begin
if (cur_state = A) then
res_op <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_op1) + CONV_INTEGER(i_op2), 16);
elsif (cur_state = SB) then
res_op <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_op1) - CONV_INTEGER(i_op2), 16);
elsif (cur_state = SH) then
for i in 0 to 14 loop
res_op(i) <= i_op1(i) xor i_op1(i+1);
end loop;
res_op(15) <= i_op1(15);
elsif (cur_state = MOVERESOP) then
res_op <= i_op;
end if;
end process;
IRESCTRL: process (cur_state, i_op1)
begin
if (cur_state = MOVERES) then
i_res <= i_op1;
end if;
end process;
FLAGS: process(res_op)
begin
if res_op = (res_op'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
s_data <= res_op;
RES <= i_res;
ZF <= t_zf;
End Beh_Stack; | mit | 64c1671c922e663ac18229d43b23351c | 0.469136 | 3.712718 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/fmsp430.vhd | 1 | 28,121 | ------------------------------------------------------------------------------
-- Copyright (C) 2009 , Olivier Girard
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp430.vhd
--!
--! @brief fpgaMSP430 Top level file
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_core_package.all;
use work.fmsp_per_package.all;
use work.fmsp_dbg_package.all;
use work.fmsp_functions.all;
entity fmsp430 is
generic (
INST_NR : integer := 0; -- Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; -- Program Memory Size
DMEM_SIZE : integer := 16384; -- Data Memory Size
PER_SIZE : integer := 16384; -- Peripheral Memory Size
MULTIPLIER : boolean := false; -- Include/Exclude Hardware Multiplier
USER_VERSION : integer := 0; -- Custom user version number
DEBUG_EN : boolean := false; -- Include/Exclude Serial Debug interface
WATCHDOG : boolean := false; -- Include/Exclude Watchdog timer
DMA_IF_EN : boolean := false; -- Include/Exclude DMA interface support
NMI_EN : boolean := false; -- Include/Exclude Non-Maskable-Interrupt support
IRQ_NR : integer := 16; -- Number of IRQs
SYNC_NMI_EN : boolean := true; --
SYNC_CPU_EN : boolean := true; --
SYNC_DBG_EN : boolean := true; --
SYNC_DBG_UART_RXD : boolean := true; -- Synchronize RXD inputs
DBG_UART : boolean := false; -- Enable UART (8N1) debug interface
DBG_I2C : boolean := true; -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN : boolean := false; -- Enable the I2C broadcast address
DBG_RST_BRK_EN : boolean := false; -- CPU break on PUC reset
DBG_HWBRK_0_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_1_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_2_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_3_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_RANGE : boolean := true; -- Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC : boolean := true; -- Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; -- Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000
);
port (
mclk : in std_logic; -- Main system clock
-- Inputs
lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
reset_n : in std_logic; -- Reset Pin (active low, asynchronous and non-glitchy)
cpu_en : in std_logic; -- Enable CPU code execution (asynchronous and non-glitchy)
nmi : in std_logic; -- Non-maskable interrupt (asynchronous and non-glitchy)
-- Debug interface
dbg_en : in std_logic; -- Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_addr : in std_logic_vector(6 downto 0); -- Debug interface: I2C Address
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); -- Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; -- Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; -- Debug interface: I2C SDA IN
dbg_i2c_sda_out : out std_logic := '1'; -- Debug interface: I2C SDA OUT
dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD (asynchronous)
dbg_uart_txd : out std_logic := '1'; -- Debug interface: UART TXD
-- DMA access
dma_addr : in std_logic_vector(15 downto 1); -- Direct Memory Access address
dma_dout : out std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_din : in std_logic_vector(15 downto 0); -- Direct Memory Access data input
dma_en : in std_logic; -- Direct Memory Access enable (high active)
dma_we : in std_logic_vector(1 downto 0); -- Direct Memory Access write byte enable (high active)
dma_priority : in std_logic; -- Direct Memory Access priority (0:low / 1:high)
dma_ready : out std_logic; -- Direct Memory Access is complete
dma_resp : out std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
-- Data memory
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); -- Data Memory address
dmem_dout : in std_logic_vector(15 downto 0); -- Data Memory data output
dmem_din : out std_logic_vector(15 downto 0); -- Data Memory data input
dmem_wen : out std_logic_vector(1 downto 0); -- Data Memory write byte enable (low active)
dmem_cen : out std_logic; -- Data Memory chip enable (low active)
-- Program memory
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); -- Program Memory address
pmem_dout : in std_logic_vector(15 downto 0); -- Program Memory data output
pmem_din : out std_logic_vector(15 downto 0); -- Program Memory data input (optional)
pmem_wen : out std_logic_vector(1 downto 0); -- Program Memory write enable (low active) (optional)
pmem_cen : out std_logic; -- Program Memory chip enable (low active)
-- Peripheral interface
per_irq : in std_logic_vector(IRQ_NR-3 downto 0); -- Maskable interrupts (14, 30 or 62)
per_irq_acc : out std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
per_rst : out std_logic; -- Main system reset
per_freeze : out std_logic; -- Freeze peripherals
per_aclk_en : out std_logic; -- FPGA ONLY: ACLK enable
per_smclk_en : out std_logic; -- FPGA ONLY: SMCLK enable
-- Peripheral memory
per_addr : out std_logic_vector(13 downto 0); -- Peripheral address
per_dout : in std_logic_vector(15 downto 0); -- Peripheral data output
per_din : out std_logic_vector(15 downto 0); -- Peripheral data input
per_we : out std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
per_en : out std_logic -- Peripheral enable (high active)
);
end entity fmsp430;
architecture RTL of fmsp430 is
constant C_INST_NR : std_logic_vector(7 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(INST_NR,8));--x"00";
constant C_TOTAL_NR : std_logic_vector(7 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(TOTAL_NR,8));--x"00";
--=============================================================================
-- 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
--=============================================================================
type core_wires_type is record
cpu_en : std_logic;
lfxt_clk : std_logic;
cpuoff : std_logic;
oscoff : std_logic;
scg1 : std_logic;
por : std_logic;
gie : std_logic;
cpu_id : std_logic_vector(31 downto 0);
nmi : std_logic;
nmi_acc : std_logic;
nmi_pnd : std_logic;
nmi_wkup : std_logic;
irq_acc : std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
dma_dout : std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_ready : std_logic; -- Direct Memory Access is complete
dma_resp : std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
mrst : std_logic; -- Main system reset
end record;
type peripheral_wires_type is record
addr : std_logic_vector(13 downto 0); -- Peripheral address
din : std_logic_vector(15 downto 0); -- Peripheral data input
en : std_logic; -- Peripheral enable (high active)
we : std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
aclk_en : std_logic; -- FPGA ONLY: ACLK enable
smclk_en : std_logic; -- FPGA ONLY: SMCLK enable
end record;
type dbg_wires_type is record
en : std_logic;
rst : std_logic;
puc_pnd_set : std_logic;
decode_noirq : std_logic;
pc : std_logic_vector(15 downto 0);
halt_cmd : std_logic;
halt_st : std_logic;
irq : std_logic;
wkup : std_logic;
cpu_reset : std_logic;
freeze : std_logic;
mem_addr : std_logic_vector(15 downto 0);
mem_dout : std_logic_vector(15 downto 0);
mem_din : std_logic_vector(15 downto 0);
mem_wr : std_logic_vector(1 downto 0);
mem_en : std_logic;
reg_din : std_logic_vector(15 downto 0);
reg_wr : std_logic;
eu_mab : std_logic_vector(15 downto 0);
eu_mdb_in : std_logic_vector(15 downto 0);
eu_mdb_out : std_logic_vector(15 downto 0);
eu_mb_wr : std_logic_vector(1 downto 0);
eu_mb_en : std_logic;
fe_mab : std_logic_vector(15 downto 0);
fe_mdb_in : std_logic_vector(15 downto 0);
fe_mb_en : std_logic;
fe_pmem_wait : std_logic;
end record;
type wdt_wires_type is record
ie : std_logic;
nmies : std_logic;
ifg : std_logic;
irq : std_logic;
wkup : std_logic;
cpu_reset : std_logic;
ifg_sw_clr : std_logic;
ifg_sw_set : std_logic;
end record;
signal wires : core_wires_type;
signal dbg_w : dbg_wires_type := ( en => '0',
rst => '0',
puc_pnd_set => '0',
decode_noirq => '0',
pc => x"0000",
halt_cmd => '0',
halt_st => '0',
irq => '0',
wkup => '0',
cpu_reset => '0',
freeze => '0',
mem_addr => x"0000",
mem_dout => x"0000",
mem_din => x"0000",
mem_wr => "00",
mem_en => '0',
reg_din => x"0000",
reg_wr => '0',
eu_mab => x"0000",
eu_mdb_in => x"0000",
eu_mdb_out => x"0000",
eu_mb_wr => "00",
eu_mb_en => '0',
fe_mab => x"0000",
fe_mdb_in => x"0000",
fe_mb_en => '0',
fe_pmem_wait => '0'
);
signal wdt_w : wdt_wires_type;
signal per_w : peripheral_wires_type;
signal per_dout_sfr : std_logic_vector(15 downto 0);
signal per_dout_clk : std_logic_vector(15 downto 0);
signal per_dout_wdt : std_logic_vector(15 downto 0) := x"0000";
signal per_dout_mpy : std_logic_vector(15 downto 0) := x"0000";
signal per_dout_or : std_logic_vector(15 downto 0);
begin
--=============================================================================
-- 1) CORE (<=> FETCH & DECODE & EXECUTE & MEMORY BACKBONE)
--=============================================================================
--! Synchronization
sync_cell_dbg_en : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_DBG_EN
)
port map(
rst => wires.por,
clk => mclk,
data_in => dbg_en,
data_out => dbg_w.en
);
sync_cell_lfxt_clk : fmsp_sync_cell
generic map(
SYNC_EN => false
)
port map(
clk => mclk,
rst => wires.por,
data_in => lfxt_clk,
data_out => wires.lfxt_clk
);
sync_cell_cpu_en : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_CPU_EN
)
port map(
clk => mclk,
rst => wires.por,
data_in => cpu_en,
data_out => wires.cpu_en
);
sync_cell_nmi : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_NMI_EN
)
port map(
clk => mclk,
rst => wires.mrst,
data_in => nmi,
data_out => wires.nmi
);
--=============================================================================
-- 1) CORE (<=> FETCH & DECODE & EXECUTE & MEMORY BACKBONE)
--=============================================================================
core_unit : fmsp_core
generic map(
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE,
DMA_IF_EN => DMA_IF_EN, -- Wakeup condition from DMA interface
IRQ_NR => IRQ_NR -- Number of IRQs
)
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
-- Debug Interface
dbg_halt_cmd => dbg_w.halt_cmd, -- Debug interface Halt CPU command
dbg_halt_st => dbg_w.halt_st, -- Halt/Run status from CPU
dbg_reg_din => dbg_w.reg_din, -- Debug unit CPU register data input
dbg_reg_wr => dbg_w.reg_wr, -- Debug unit CPU register write
dbg_mem_addr => dbg_w.mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_w.mem_dout, -- Debug unit data output
dbg_mem_din => dbg_w.mem_din, -- Debug unit Memory data input
dbg_mem_en => dbg_w.mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_w.mem_wr, -- Debug unit memory write
eu_mem_addr => dbg_w.eu_mab, -- Execution-Unit Memory address bus
eu_mem_en => dbg_w.eu_mb_en, -- Execution-Unit Memory bus enable
eu_mem_wr => dbg_w.eu_mb_wr, -- Execution-Unit Memory bus write transfer
fe_mem_din => dbg_w.fe_mdb_in, -- Frontend Memory data bus input
decode_noirq => dbg_w.decode_noirq, -- Frontend decode instruction
pc => dbg_w.pc, -- Program counter
-- DMA access
dma_addr => dma_addr, -- Direct Memory Access address
dma_dout => dma_dout, -- Direct Memory Access data output
dma_din => dma_din, -- Direct Memory Access data input
dma_we => dma_we, -- Direct Memory Access write byte enable (high active)
dma_en => dma_en, -- Direct Memory Access enable (high active)
dma_priority => dma_priority, -- Direct Memory Access priority (0:low / 1:high)
dma_ready => dma_ready, -- Direct Memory Access is complete
dma_resp => dma_resp, -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr => per_w.addr, -- Peripheral address
per_dout => per_dout_or, -- Peripheral data output
per_din => per_w.din, -- Peripheral data input
per_we => per_w.we, -- Peripheral write enable (high active)
per_en => per_w.en, -- Peripheral enable (high active)
-- Data memory
dmem_addr => dmem_addr, -- Data Memory address
dmem_dout => dmem_dout, -- Data Memory data output
dmem_din => dmem_din, -- Data Memory data input
dmem_wen => dmem_wen, -- Data Memory write enable (low active)
dmem_cen => dmem_cen, -- Data Memory chip enable (low active)
-- Program memory
pmem_addr => pmem_addr, -- Program Memory address
pmem_dout => pmem_dout, -- Program Memory data output
pmem_din => pmem_din, -- Program Memory data input (optional)
pmem_wen => pmem_wen, -- Program Memory write enable (low active) (optional)
pmem_cen => pmem_cen, -- Program Memory chip enable (low active)
-- Non Maskable Interrupt
nmi_pnd => wires.nmi_pnd, -- Non-maskable interrupt pending
nmi_wkup => wires.nmi_wkup, -- NMI Wakeup
nmi_acc => wires.nmi_acc, -- Non-Maskable interrupt request accepted
-- Watchdog Interrupt
wdt_irq => wdt_w.irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_w.wkup, -- Watchdog Wakeup
-- Maskable Interrupt
irq => per_irq, -- Maskable interrupts
irq_acc => wires.irq_acc, -- Interrupt request accepted
--============
cpu_en_s => wires.cpu_en, -- Enable CPU code execution (synchronous)
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1 -- System clock generator 1. Turns off the SMCLK
);
--=============================================================================
-- 2) GLOBAL CLOCK & RESET MANAGEMENT
--=============================================================================
clock_module_0 : fmsp_clock_module
generic map(
INST_NR => INST_NR, -- Current fmsp instance number (for multicore systems)
TOTAL_NR => TOTAL_NR, -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
DEBUG_EN => DEBUG_EN, -- Include/Exclude Serial Debug interface
WATCHDOG => WATCHDOG, -- Include/Exclude Watchdog timer
DMA_IF_EN => DMA_IF_EN, -- Include/Exclude DMA interface support
NMI_EN => NMI_EN -- Include/Exclude Non-Maskable-Interrupt support
)
port map(
mclk => mclk, -- Main system clock
-- INPUTs
reset_n => reset_n, -- Reset Pin (low active, asynchronous)
lfxt_clk => wires.lfxt_clk, -- Low frequency oscillator (typ 32kHz)
cpu_en => wires.cpu_en, -- Enable CPU code execution (synchronous)
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1, -- System clock generator 1. Turns off the SMCLK
wdt_reset => wdt_w.cpu_reset, -- Watchdog-timer reset
-- OUTPUTs
por => wires.por, -- Power-on reset
puc_rst => wires.mrst, -- Main system reset
-- Debug Interface
dbg_rst => dbg_w.rst, -- Debug unit reset
dbg_en => dbg_w.en, -- Debug interface enable (synchronous)
puc_pnd_set => dbg_w.puc_pnd_set, -- PUC pending set for the serial debug interface
dbg_cpu_reset => dbg_w.cpu_reset, -- Reset CPU from debug interface
-- Peripheral interface
smclk_en => per_w.smclk_en, -- SMCLK enable
aclk_en => per_w.aclk_en, -- ACLK enable
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_clk -- Peripheral data output
);
--=============================================================================
-- 3) SPECIAL FUNCTION REGISTERS
--=============================================================================
sfr_0 : fmsp_sfr
generic map(
INST_NR => INST_NR, -- Current fmsp instance number (for multicore systems)
TOTAL_NR => TOTAL_NR, -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
MULTIPLIER => MULTIPLIER, -- Include/Exclude Hardware Multiplier
USER_VERSION => USER_VERSION, -- Custom user version number
WATCHDOG => WATCHDOG, -- Include/Exclude Watchdog timer
NMI_EN => NMI_EN -- Include/Exclude Non-Maskable-Interrupt support
)
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
cpu_id => wires.cpu_id, -- CPU ID
-- Non Maskable Interrupt
nmi => wires.nmi, -- Non-maskable interrupt (asynchronous)
nmi_acc => wires.nmi_acc, -- Non-Maskable interrupt request accepted
nmi_pnd => wires.nmi_pnd, -- NMI Pending
nmi_wkup => wires.nmi_wkup, -- NMI Wakeup
-- Watchdog Interface
wdtie => wdt_w.ie, -- Watchdog-timer interrupt enable
wdtifg => wdt_w.ifg, -- Watchdog-timer interrupt flag
wdtifg_sw_clr => wdt_w.ifg_sw_clr, -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set => wdt_w.ifg_sw_set, -- Watchdog-timer interrupt flag software set
wdtnmies => wdt_w.nmies, -- Watchdog-timer NMI edge selection
-- Peripheral interface
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_sfr -- Peripheral data output
);
--=============================================================================
-- 4) WATCHDOG TIMER
--=============================================================================
ADD_WATCHDOG : if WATCHDOG generate
watchdog : fmsp_watchdog
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
por => wires.por, -- Power-on reset
-- INPUTs
dbg_freeze => dbg_w.freeze, -- Freeze Watchdog counter
wdtie => wdt_w.ie, -- Watchdog-timer interrupt enable
wdtifg_irq_clr => wires.irq_acc(IRQ_NR-6), -- Clear Watchdog-timer interrupt flag
wdtifg_sw_clr => wdt_w.ifg_sw_clr, -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set => wdt_w.ifg_sw_set, -- Watchdog-timer interrupt flag software set
-- OUTPUTs
wdt_reset => wdt_w.cpu_reset, -- Watchdog-timer reset
wdt_irq => wdt_w.irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_w.wkup, -- Watchdog Wakeup
wdtifg => wdt_w.ifg, -- Watchdog-timer interrupt flag
wdtnmies => wdt_w.nmies, -- Watchdog-timer NMI edge selection
-- Peripheral interface
aclk_en => per_w.aclk_en, -- ACLK enable
smclk_en => per_w.smclk_en, -- SMCLK enable
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_wdt -- Peripheral data output
);
end generate ADD_WATCHDOG;
--=============================================================================
-- 5) HARDWARE MULTIPLIER
--=============================================================================
ADD_MULTIPLIER : if MULTIPLIER generate
multiplier : fmsp_multiplier
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
-- Peripheral interface
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_mpy -- Peripheral data output
);
end generate ADD_MULTIPLIER;
--=============================================================================
-- 6) PERIPHERALS' OUTPUT BUS
--=============================================================================
per_dout_or <= per_dout
or per_dout_clk
or per_dout_sfr
or per_dout_wdt
or per_dout_mpy;
--=============================================================================
-- 7) DEBUG INTERFACE
--=============================================================================
dbg : fmsp_dbg
generic map(
DBG_DCO_FREQ => DBG_DCO_FREQ, -- Debug mclk frequency
DBG_UART => DBG_UART, -- Enable UART (8N1) debug interface
DBG_UART_AUTO_SYNC => DBG_UART_AUTO_SYNC, -- Debug UART interface auto data synchronization
DBG_UART_BAUD => DBG_UART_BAUD, -- Debug UART interface data rate
DBG_I2C => DBG_I2C, -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN => DBG_I2C_BROADCAST_EN, -- Enable the I2C broadcast address
DBG_RST_BRK_EN => DBG_RST_BRK_EN, -- CPU break on PUC reset
DBG_HWBRK_0_EN => DBG_HWBRK_0_EN, -- Include hardware breakpoints unit
DBG_HWBRK_1_EN => DBG_HWBRK_1_EN, -- Include hardware breakpoints unit
DBG_HWBRK_2_EN => DBG_HWBRK_2_EN, -- Include hardware breakpoints unit
DBG_HWBRK_3_EN => DBG_HWBRK_3_EN, -- Include hardware breakpoints unit
DBG_HWBRK_RANGE => DBG_HWBRK_RANGE, -- Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD => SYNC_DBG_UART_RXD -- Synchronize RXD inputs
)
port map(
dbg_clk => mclk, -- Debug unit clock
dbg_rst => dbg_w.rst, -- Debug unit reset
-- INPUTs
cpu_nr_inst => C_INST_NR, -- Current fmsp instance number
cpu_nr_total => C_TOTAL_NR, -- Total number of fmsp instances-1
cpu_id => wires.cpu_id, -- CPU ID
cpu_en_s => wires.cpu_en, -- Enable CPU code execution (synchronous)
dbg_en_s => dbg_w.en, -- Debug interface enable (synchronous)
dbg_halt_st => dbg_w.halt_st, -- Halt/Run status from CPU
-- I2C Interface
dbg_i2c_addr => dbg_i2c_addr, -- Debug interface: I2C Address
dbg_i2c_broadcast => dbg_i2c_broadcast, -- Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl => dbg_i2c_scl, -- Debug interface: I2C SCL
dbg_i2c_sda_in => dbg_i2c_sda_in, -- Debug interface: I2C SDA IN
dbg_i2c_sda_out => dbg_i2c_sda_out, -- Debug interface: I2C SDA OUT
-- UART Interface
dbg_uart_rxd => dbg_uart_rxd, -- Debug interface: UART RXD (asynchronous)
dbg_uart_txd => dbg_uart_txd, -- Debug interface: UART TXD
-- Core interface
dbg_mem_din => dbg_w.mem_din, -- Debug unit Memory data input
dbg_mem_addr => dbg_w.mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_w.mem_dout, -- Debug unit data output
dbg_mem_en => dbg_w.mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_w.mem_wr, -- Debug unit memory write
dbg_reg_din => dbg_w.reg_din, -- Debug unit CPU register data input
decode_noirq => dbg_w.decode_noirq, -- Frontend decode instruction
eu_mab => dbg_w.eu_mab, -- Execution-Unit Memory address bus
eu_mb_en => dbg_w.eu_mb_en, -- Execution-Unit Memory bus enable
eu_mb_wr => dbg_w.eu_mb_wr, -- Execution-Unit Memory bus write transfer
fe_mdb_in => dbg_w.fe_mdb_in, -- Frontend Memory data bus input
pc => dbg_w.pc, -- Program counter
puc_pnd_set => dbg_w.puc_pnd_set, -- PUC pending set for the serial debug interface
-- OUTPUTs
dbg_cpu_reset => dbg_w.cpu_reset, -- Reset CPU from debug interface
dbg_freeze => dbg_w.freeze, -- Freeze peripherals
dbg_halt_cmd => dbg_w.halt_cmd, -- Halt CPU command
dbg_reg_wr => dbg_w.reg_wr -- Debug unit CPU register write
);
-- Peripheral interface
per_irq_acc <= wires.irq_acc; -- Interrupt request accepted (one-hot signal)
per_rst <= wires.mrst; -- Main system reset
per_freeze <= dbg_w.freeze; -- Freeze peripherals
per_aclk_en <= per_w.aclk_en; -- ACLK enable
per_smclk_en <= per_w.smclk_en; -- FPGA ONLY: SMCLK enable
per_addr <= per_w.addr; -- Peripheral address
per_din <= per_w.din; -- Peripheral data input
per_en <= per_w.en; -- Peripheral enable (high active)
per_we <= per_w.we; -- Peripheral write enable (high active)
end RTL; -- fmsp430
| bsd-3-clause | 3fbc9b23d405f13c7229a2c6f2f74e7f | 0.591586 | 2.984927 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/07e9351aee22473d/ip_design_axi_gpio_1_0_sim_netlist.vhdl | 1 | 130,243 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_sim_netlist.vhdl
-- Design : ip_design_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_3_n_0\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[5]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dual.gpio2_OE[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio_OE[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[27]_i_3\ : label is "soft_lutpair2";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
\ip2bus_data_i_D1_reg[0]\(8 downto 0) <= \^ip2bus_data_i_d1_reg[0]\(8 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(1),
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_Data_Out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(2),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(2)
);
\Dual.gpio2_Data_Out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(1),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(1)
);
\Dual.gpio2_Data_Out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(0)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => \Dual.gpio2_OE_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => E(0)
);
\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(7),
O => D(7)
);
\Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(6),
O => D(6)
);
\Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(5),
O => D(5)
);
\Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(4),
O => D(4)
);
\Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(3),
O => D(3)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => \Dual.gpio_OE_reg[0]\(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040400"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(7)
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(6)
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(5)
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(4),
I3 => reg3(4),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(4)
);
\ip2bus_data_i_D1[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \ip2bus_data_i_D1[27]_i_2_n_0\
);
\ip2bus_data_i_D1[27]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \ip2bus_data_i_D1[27]_i_3_n_0\
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(3),
I3 => reg3(3),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(2),
I3 => reg3(2),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(1),
I3 => reg3(1),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(0),
I3 => reg3(0),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
reg3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[7]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[6]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[5]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[4]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[3]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[2]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[1]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]_0\ : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 4 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair13";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => reg1(4),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => reg1(3),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => reg1(2),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => reg1(1),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(4),
Q => reg1(0),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[0]_0\,
Q => reg3(7),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[1]_0\,
Q => reg3(6),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[2]_0\,
Q => reg3(5),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[3]_0\,
Q => reg3(4),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[4]_0\,
Q => reg3(3),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[5]_0\,
Q => reg3(2),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[6]_0\,
Q => reg3(1),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[7]_0\,
Q => reg3(0),
R => bus2ip_rnw_i_reg
);
\Dual.INPUT_DOUBLE_REGS4\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio2_io_i_d2(0),
scndry_vect_out(6) => gpio2_io_i_d2(1),
scndry_vect_out(5) => gpio2_io_i_d2(2),
scndry_vect_out(4) => gpio2_io_i_d2(3),
scndry_vect_out(3) => gpio2_io_i_d2(4),
scndry_vect_out(2) => gpio2_io_i_d2(5),
scndry_vect_out(1) => gpio2_io_i_d2(6),
scndry_vect_out(0) => gpio2_io_i_d2(7)
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => Q(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => Q(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => Q(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => Q(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => Q(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => Q(2),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => Q(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => Q(0),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(7),
Q => gpio2_io_o(7),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(6),
Q => gpio2_io_o(6),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(5),
Q => gpio2_io_o(5),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(4),
Q => gpio2_io_o(4),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(3),
Q => gpio2_io_o(3),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(2),
Q => gpio2_io_o(2),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(1),
Q => gpio2_io_o(1),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(0),
Q => gpio2_io_o(0),
R => SS(0)
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(7),
Q => gpio2_io_t(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(6),
Q => gpio2_io_t(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(5),
Q => gpio2_io_t(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(4),
Q => gpio2_io_t(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(3),
Q => gpio2_io_t(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(2),
Q => gpio2_io_t(2),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(1),
Q => gpio2_io_t(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(0),
Q => gpio2_io_t(0),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(4),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(4),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(7),
Q => gpio_io_t(4),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(6),
Q => gpio_io_t(3),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(5),
Q => gpio_io_t(2),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(4),
Q => gpio_io_t(1),
S => SS(0)
);
\Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(3),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 4 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 7 downto 0 );
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair9";
begin
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ <= \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(4),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(4),
O => Read_Reg_In(0)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(3),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(3),
O => Read_Reg_In(1)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(2),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(2),
O => Read_Reg_In(2)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(1),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(1),
O => Read_Reg_In(3)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(0),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(0),
O => Read_Reg_In(4)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(7),
I1 => gpio2_io_t(7),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(6),
I1 => gpio2_io_t(6),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(5),
I1 => gpio2_io_t(5),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(4),
I1 => gpio2_io_t(4),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(3),
I1 => gpio2_io_t(3),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(2),
I1 => gpio2_io_t(2),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(1),
I1 => gpio2_io_t(1),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(0),
I1 => gpio2_io_t(0),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\,
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q => start2,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8 downto 0) => \ip2bus_data_i_D1_reg[0]\(8 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
reg1(4 downto 0) => reg1(4 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(8),
Q => s_axi_rdata(8),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 4 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 7 downto 0 );
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => bus2ip_rnw,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\,
\Dual.gpio2_Data_In_reg[0]\(7 downto 0) => \Dual.gpio2_Data_In_reg[0]\(7 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
Q(4 downto 0) => Q(4 downto 0),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
SR => bus2ip_reset,
gpio2_io_t(7 downto 0) => gpio2_io_t(7 downto 0),
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8 downto 0) => \ip2bus_data_i_D1_reg[0]\(8 downto 0),
\ip2bus_data_i_D1_reg[0]_0\(8 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(8 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(4 downto 0) => reg1(4 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(8 downto 0) => s_axi_rdata(8 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_core_1_n_16 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal reg1 : STD_LOGIC_VECTOR ( 27 to 31 );
signal reg3 : STD_LOGIC_VECTOR ( 24 to 31 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute max_fanout : string;
attribute max_fanout of s_axi_aclk : signal is "10000";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute max_fanout of s_axi_aresetn : signal is "10000";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_t(7 downto 0) <= \^gpio2_io_t\(7 downto 0);
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(7 downto 3) => p_0_out(4 downto 0),
D(2) => AXI_LITE_IPIF_I_n_12,
D(1) => AXI_LITE_IPIF_I_n_13,
D(0) => AXI_LITE_IPIF_I_n_14,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => AXI_LITE_IPIF_I_n_24,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ => AXI_LITE_IPIF_I_n_32,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ => AXI_LITE_IPIF_I_n_31,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ => AXI_LITE_IPIF_I_n_30,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ => AXI_LITE_IPIF_I_n_29,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ => AXI_LITE_IPIF_I_n_28,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ => AXI_LITE_IPIF_I_n_27,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ => AXI_LITE_IPIF_I_n_26,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ => AXI_LITE_IPIF_I_n_25,
\Dual.gpio2_Data_In_reg[0]\(7) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]\(6) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]\(5) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]\(4) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]\(3) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]\(2) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]\(1) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]\(0) => gpio2_Data_In(7),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_17,
\Dual.gpio2_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_18,
\Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_16,
E(0) => AXI_LITE_IPIF_I_n_15,
GPIO_xferAck_i => GPIO_xferAck_i,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(7 downto 0) => \^gpio2_io_t\(7 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\(7) => ip2bus_data(24),
\ip2bus_data_i_D1_reg[0]\(6) => ip2bus_data(25),
\ip2bus_data_i_D1_reg[0]\(5) => ip2bus_data(26),
\ip2bus_data_i_D1_reg[0]\(4) => ip2bus_data(27),
\ip2bus_data_i_D1_reg[0]\(3) => ip2bus_data(28),
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data(29),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(8) => \^s_axi_rdata\(30),
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(7 downto 3) => p_0_out(4 downto 0),
D(2) => AXI_LITE_IPIF_I_n_12,
D(1) => AXI_LITE_IPIF_I_n_13,
D(0) => AXI_LITE_IPIF_I_n_14,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(4) => gpio_Data_In(0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(3) => gpio_Data_In(1),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(2) => gpio_Data_In(2),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(1) => gpio_Data_In(3),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(0) => gpio_Data_In(4),
\Dual.gpio2_Data_In_reg[0]_0\ => AXI_LITE_IPIF_I_n_32,
\Dual.gpio2_Data_In_reg[1]_0\ => AXI_LITE_IPIF_I_n_31,
\Dual.gpio2_Data_In_reg[2]_0\ => AXI_LITE_IPIF_I_n_30,
\Dual.gpio2_Data_In_reg[3]_0\ => AXI_LITE_IPIF_I_n_29,
\Dual.gpio2_Data_In_reg[4]_0\ => AXI_LITE_IPIF_I_n_28,
\Dual.gpio2_Data_In_reg[5]_0\ => AXI_LITE_IPIF_I_n_27,
\Dual.gpio2_Data_In_reg[6]_0\ => AXI_LITE_IPIF_I_n_26,
\Dual.gpio2_Data_In_reg[7]_0\ => AXI_LITE_IPIF_I_n_25,
E(0) => AXI_LITE_IPIF_I_n_15,
GPIO_xferAck_i => GPIO_xferAck_i,
Q(7) => gpio2_Data_In(0),
Q(6) => gpio2_Data_In(1),
Q(5) => gpio2_Data_In(2),
Q(4) => gpio2_Data_In(3),
Q(3) => gpio2_Data_In(4),
Q(2) => gpio2_Data_In(5),
Q(1) => gpio2_Data_In(6),
Q(0) => gpio2_Data_In(7),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_24,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_16,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_17,
bus2ip_rnw_i_reg_2(0) => AXI_LITE_IPIF_I_n_18,
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => gpio2_io_o(7 downto 0),
gpio2_io_t(7 downto 0) => \^gpio2_io_t\(7 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_16,
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_16,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio2_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
attribute x_interface_parameter of gpio2_io_i : signal is "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(7 downto 0),
gpio2_io_t(7 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(7 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 152de9b38b8a2cd30695977c69b331f5 | 0.598865 | 2.552783 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spi.vhd | 1 | 8,094 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Pacakge: spi
-- File: spi.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SPI interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package spi is
type spi_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
astart : std_ulogic;
cstart : std_ulogic;
ignore : std_ulogic;
end record;
type spi_in_vector is array (natural range <>) of spi_in_type;
constant spi_in_none : spi_in_type := ('0', '0', '0', '0', '0', '0', '0');
type spi_out_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
ssn : std_logic_vector(7 downto 0); -- used by GE/OC SPI core
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
type spi_out_vector is array (natural range <>) of spi_out_type;
constant spi_out_none : spi_out_type := ('0', '0', '0', '0', '0', '0',
(others => '0'), '0', '0', '0');
-- SPI master/slave controller
component spictrl
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
netlist : integer := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end component;
-- SPI to AHB bridge
type spi2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
en : std_ulogic;
end record;
type spi2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component spi2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahbx
generic (
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end component;
type spimctrl_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
cd : std_ulogic;
end record;
type spimctrl_out_type is record
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
csn : std_ulogic;
cdcsnoen : std_ulogic;
errorn : std_ulogic;
ready : std_ulogic;
initialized : std_ulogic;
end record;
constant spimctrl_out_none : spimctrl_out_type :=
('0', '1', '0', '1', '1', '1', '0', '0');
component spimctrl
generic (
hindex : integer := 0;
hirq : integer := 0;
faddr : integer := 16#000#;
fmask : integer := 16#fff#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
spliten : integer := 0;
oepol : integer := 0;
sdcard : integer range 0 to 1 := 0;
readcmd : integer range 0 to 255 := 16#0B#;
dummybyte : integer range 0 to 1 := 1;
dualoutput : integer range 0 to 1 := 0;
scaler : integer range 1 to 512 := 1;
altscaler : integer range 1 to 512 := 1;
pwrupcnt : integer := 0;
maxahbaccsz : integer range 0 to 256 := AHBDW;
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end component;
end;
| gpl-2.0 | 53d901d2903218dfd4afc8215b531534 | 0.507536 | 3.748958 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/TestBench/signature_t.vhd | 1 | 1,340 | library ieee;
use ieee.std_logic_1164.all;
entity signature_T is
end signature_T;
architecture Beh of signature_T is
component Signature
port (
CLK: in std_logic;
RST: in std_logic;
Pin: in std_logic;
Pout: out std_logic_vector(0 to 15)
);
end component;
signal CLK: std_logic := '0';
signal RST: std_logic := '0';
signal Pin: std_logic := '0';
signal Pout: std_logic_vector(0 to 15);
constant CLK_Period: time := 10 ns;
begin
uut: Signature port map (
CLK => CLK,
RST => RST,
PIn => Pin,
Pout => Pout
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
stim_proc: process
begin
wait for CLK_Period;
RST <= '0'; wait for CLK_Period;
RST <= '1'; wait for 2*CLK_Period;
PIn <= '1'; wait for CLK_Period;
RST <= '0'; wait for CLK_Period;
PIn <= '1'; wait for CLK_Period;
PIn <= '0'; wait for CLK_Period;
PIn <= '0'; wait for CLK_Period;
PIn <= '0'; wait for CLK_Period;
PIn <= '0'; wait for CLK_Period;
PIn <= '1'; wait for CLK_Period;
PIn <= '1'; wait for CLK_Period;
wait for 8*CLK_period;
end process;
end Beh;
configuration TESTBENCH_FOR_signature of signature_T is
for Beh
for UUT : Signature
use entity work.signature(behavior);
end for;
end for;
end TESTBENCH_FOR_signature; | mit | d3659dc75bb0355c6a5642db146da22c | 0.633582 | 2.803347 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/charrom.vhd | 1 | 119,223 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: charrom
-- File: charrom.vhd
-- Author: Marcus Hellqvist
-- Description: Character ROM for video controller
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity charrom is
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of charrom is
signal romdata : std_logic_vector(7 downto 0);
signal romaddr : std_logic_vector(11 downto 0);
begin
data <= romdata;
p0: process(clk)
begin
if rising_edge(clk) then
romaddr <= addr;
end if;
end process;
p1: process(romaddr)
begin
case conv_integer(romaddr) is
when 16#000# => romdata <= X"00"; --
when 16#100# => romdata <= X"00"; --
when 16#200# => romdata <= X"00"; --
when 16#300# => romdata <= X"00"; --
when 16#400# => romdata <= X"00"; --
when 16#500# => romdata <= X"00"; --
when 16#600# => romdata <= X"00"; --
when 16#700# => romdata <= X"00"; --
when 16#800# => romdata <= X"00"; --
when 16#900# => romdata <= X"00"; --
when 16#a00# => romdata <= X"00"; --
when 16#b00# => romdata <= X"00"; --
when 16#c00# => romdata <= X"00"; --
when 16#020# => romdata <= X"00"; --
when 16#120# => romdata <= X"00"; --
when 16#220# => romdata <= X"00"; --
when 16#320# => romdata <= X"00"; --
when 16#420# => romdata <= X"00"; --
when 16#520# => romdata <= X"00"; --
when 16#620# => romdata <= X"00"; --
when 16#720# => romdata <= X"00"; --
when 16#820# => romdata <= X"00"; --
when 16#920# => romdata <= X"00"; --
when 16#a20# => romdata <= X"00"; --
when 16#b20# => romdata <= X"00"; --
when 16#c20# => romdata <= X"00"; --
when 16#021# => romdata <= X"00"; -- !
when 16#121# => romdata <= X"00"; -- !
when 16#221# => romdata <= X"10"; -- !
when 16#321# => romdata <= X"10"; -- !
when 16#421# => romdata <= X"10"; -- !
when 16#521# => romdata <= X"10"; -- !
when 16#621# => romdata <= X"10"; -- !
when 16#721# => romdata <= X"10"; -- !
when 16#821# => romdata <= X"10"; -- !
when 16#921# => romdata <= X"00"; -- !
when 16#a21# => romdata <= X"10"; -- !
when 16#b21# => romdata <= X"00"; -- !
when 16#c21# => romdata <= X"00"; -- !
when 16#022# => romdata <= X"00"; -- "
when 16#122# => romdata <= X"00"; -- "
when 16#222# => romdata <= X"24"; -- "
when 16#322# => romdata <= X"24"; -- "
when 16#422# => romdata <= X"24"; -- "
when 16#522# => romdata <= X"00"; -- "
when 16#622# => romdata <= X"00"; -- "
when 16#722# => romdata <= X"00"; -- "
when 16#822# => romdata <= X"00"; -- "
when 16#922# => romdata <= X"00"; -- "
when 16#a22# => romdata <= X"00"; -- "
when 16#b22# => romdata <= X"00"; -- "
when 16#c22# => romdata <= X"00"; -- "
when 16#023# => romdata <= X"00"; -- #
when 16#123# => romdata <= X"00"; -- #
when 16#223# => romdata <= X"00"; -- #
when 16#323# => romdata <= X"24"; -- #
when 16#423# => romdata <= X"24"; -- #
when 16#523# => romdata <= X"7e"; -- #
when 16#623# => romdata <= X"24"; -- #
when 16#723# => romdata <= X"7e"; -- #
when 16#823# => romdata <= X"24"; -- #
when 16#923# => romdata <= X"24"; -- #
when 16#a23# => romdata <= X"00"; -- #
when 16#b23# => romdata <= X"00"; -- #
when 16#c23# => romdata <= X"00"; -- #
when 16#024# => romdata <= X"00"; -- $
when 16#124# => romdata <= X"00"; -- $
when 16#224# => romdata <= X"10"; -- $
when 16#324# => romdata <= X"3c"; -- $
when 16#424# => romdata <= X"50"; -- $
when 16#524# => romdata <= X"50"; -- $
when 16#624# => romdata <= X"38"; -- $
when 16#724# => romdata <= X"14"; -- $
when 16#824# => romdata <= X"14"; -- $
when 16#924# => romdata <= X"78"; -- $
when 16#a24# => romdata <= X"10"; -- $
when 16#b24# => romdata <= X"00"; -- $
when 16#c24# => romdata <= X"00"; -- $
when 16#025# => romdata <= X"00"; -- %
when 16#125# => romdata <= X"00"; -- %
when 16#225# => romdata <= X"22"; -- %
when 16#325# => romdata <= X"52"; -- %
when 16#425# => romdata <= X"24"; -- %
when 16#525# => romdata <= X"08"; -- %
when 16#625# => romdata <= X"08"; -- %
when 16#725# => romdata <= X"10"; -- %
when 16#825# => romdata <= X"24"; -- %
when 16#925# => romdata <= X"2a"; -- %
when 16#a25# => romdata <= X"44"; -- %
when 16#b25# => romdata <= X"00"; -- %
when 16#c25# => romdata <= X"00"; -- %
when 16#026# => romdata <= X"00"; -- &
when 16#126# => romdata <= X"00"; -- &
when 16#226# => romdata <= X"00"; -- &
when 16#326# => romdata <= X"00"; -- &
when 16#426# => romdata <= X"30"; -- &
when 16#526# => romdata <= X"48"; -- &
when 16#626# => romdata <= X"48"; -- &
when 16#726# => romdata <= X"30"; -- &
when 16#826# => romdata <= X"4a"; -- &
when 16#926# => romdata <= X"44"; -- &
when 16#a26# => romdata <= X"3a"; -- &
when 16#b26# => romdata <= X"00"; -- &
when 16#c26# => romdata <= X"00"; -- &
when 16#027# => romdata <= X"00"; -- '
when 16#127# => romdata <= X"00"; -- '
when 16#227# => romdata <= X"10"; -- '
when 16#327# => romdata <= X"10"; -- '
when 16#427# => romdata <= X"10"; -- '
when 16#527# => romdata <= X"00"; -- '
when 16#627# => romdata <= X"00"; -- '
when 16#727# => romdata <= X"00"; -- '
when 16#827# => romdata <= X"00"; -- '
when 16#927# => romdata <= X"00"; -- '
when 16#a27# => romdata <= X"00"; -- '
when 16#b27# => romdata <= X"00"; -- '
when 16#c27# => romdata <= X"00"; -- '
when 16#028# => romdata <= X"00"; -- (
when 16#128# => romdata <= X"00"; -- (
when 16#228# => romdata <= X"04"; -- (
when 16#328# => romdata <= X"08"; -- (
when 16#428# => romdata <= X"08"; -- (
when 16#528# => romdata <= X"10"; -- (
when 16#628# => romdata <= X"10"; -- (
when 16#728# => romdata <= X"10"; -- (
when 16#828# => romdata <= X"08"; -- (
when 16#928# => romdata <= X"08"; -- (
when 16#a28# => romdata <= X"04"; -- (
when 16#b28# => romdata <= X"00"; -- (
when 16#c28# => romdata <= X"00"; -- (
when 16#029# => romdata <= X"00"; -- )
when 16#129# => romdata <= X"00"; -- )
when 16#229# => romdata <= X"20"; -- )
when 16#329# => romdata <= X"10"; -- )
when 16#429# => romdata <= X"10"; -- )
when 16#529# => romdata <= X"08"; -- )
when 16#629# => romdata <= X"08"; -- )
when 16#729# => romdata <= X"08"; -- )
when 16#829# => romdata <= X"10"; -- )
when 16#929# => romdata <= X"10"; -- )
when 16#a29# => romdata <= X"20"; -- )
when 16#b29# => romdata <= X"00"; -- )
when 16#c29# => romdata <= X"00"; -- )
when 16#02a# => romdata <= X"00"; -- *
when 16#12a# => romdata <= X"00"; -- *
when 16#22a# => romdata <= X"24"; -- *
when 16#32a# => romdata <= X"18"; -- *
when 16#42a# => romdata <= X"7e"; -- *
when 16#52a# => romdata <= X"18"; -- *
when 16#62a# => romdata <= X"24"; -- *
when 16#72a# => romdata <= X"00"; -- *
when 16#82a# => romdata <= X"00"; -- *
when 16#92a# => romdata <= X"00"; -- *
when 16#a2a# => romdata <= X"00"; -- *
when 16#b2a# => romdata <= X"00"; -- *
when 16#c2a# => romdata <= X"00"; -- *
when 16#02b# => romdata <= X"00"; -- +
when 16#12b# => romdata <= X"00"; -- +
when 16#22b# => romdata <= X"00"; -- +
when 16#32b# => romdata <= X"00"; -- +
when 16#42b# => romdata <= X"10"; -- +
when 16#52b# => romdata <= X"10"; -- +
when 16#62b# => romdata <= X"7c"; -- +
when 16#72b# => romdata <= X"10"; -- +
when 16#82b# => romdata <= X"10"; -- +
when 16#92b# => romdata <= X"00"; -- +
when 16#a2b# => romdata <= X"00"; -- +
when 16#b2b# => romdata <= X"00"; -- +
when 16#c2b# => romdata <= X"00"; -- +
when 16#02c# => romdata <= X"00"; -- ,
when 16#12c# => romdata <= X"00"; -- ,
when 16#22c# => romdata <= X"00"; -- ,
when 16#32c# => romdata <= X"00"; -- ,
when 16#42c# => romdata <= X"00"; -- ,
when 16#52c# => romdata <= X"00"; -- ,
when 16#62c# => romdata <= X"00"; -- ,
when 16#72c# => romdata <= X"00"; -- ,
when 16#82c# => romdata <= X"00"; -- ,
when 16#92c# => romdata <= X"38"; -- ,
when 16#a2c# => romdata <= X"30"; -- ,
when 16#b2c# => romdata <= X"40"; -- ,
when 16#c2c# => romdata <= X"00"; -- ,
when 16#02d# => romdata <= X"00"; -- -
when 16#12d# => romdata <= X"00"; -- -
when 16#22d# => romdata <= X"00"; -- -
when 16#32d# => romdata <= X"00"; -- -
when 16#42d# => romdata <= X"00"; -- -
when 16#52d# => romdata <= X"00"; -- -
when 16#62d# => romdata <= X"7c"; -- -
when 16#72d# => romdata <= X"00"; -- -
when 16#82d# => romdata <= X"00"; -- -
when 16#92d# => romdata <= X"00"; -- -
when 16#a2d# => romdata <= X"00"; -- -
when 16#b2d# => romdata <= X"00"; -- -
when 16#c2d# => romdata <= X"00"; -- -
when 16#02e# => romdata <= X"00"; -- .
when 16#12e# => romdata <= X"00"; -- .
when 16#22e# => romdata <= X"00"; -- .
when 16#32e# => romdata <= X"00"; -- .
when 16#42e# => romdata <= X"00"; -- .
when 16#52e# => romdata <= X"00"; -- .
when 16#62e# => romdata <= X"00"; -- .
when 16#72e# => romdata <= X"00"; -- .
when 16#82e# => romdata <= X"00"; -- .
when 16#92e# => romdata <= X"10"; -- .
when 16#a2e# => romdata <= X"38"; -- .
when 16#b2e# => romdata <= X"10"; -- .
when 16#c2e# => romdata <= X"00"; -- .
when 16#02f# => romdata <= X"00"; -- /
when 16#12f# => romdata <= X"00"; -- /
when 16#22f# => romdata <= X"02"; -- /
when 16#32f# => romdata <= X"02"; -- /
when 16#42f# => romdata <= X"04"; -- /
when 16#52f# => romdata <= X"08"; -- /
when 16#62f# => romdata <= X"10"; -- /
when 16#72f# => romdata <= X"20"; -- /
when 16#82f# => romdata <= X"40"; -- /
when 16#92f# => romdata <= X"80"; -- /
when 16#a2f# => romdata <= X"80"; -- /
when 16#b2f# => romdata <= X"00"; -- /
when 16#c2f# => romdata <= X"00"; -- /
when 16#030# => romdata <= X"00"; -- 0
when 16#130# => romdata <= X"00"; -- 0
when 16#230# => romdata <= X"18"; -- 0
when 16#330# => romdata <= X"24"; -- 0
when 16#430# => romdata <= X"42"; -- 0
when 16#530# => romdata <= X"42"; -- 0
when 16#630# => romdata <= X"42"; -- 0
when 16#730# => romdata <= X"42"; -- 0
when 16#830# => romdata <= X"42"; -- 0
when 16#930# => romdata <= X"24"; -- 0
when 16#a30# => romdata <= X"18"; -- 0
when 16#b30# => romdata <= X"00"; -- 0
when 16#c30# => romdata <= X"00"; -- 0
when 16#031# => romdata <= X"00"; -- 1
when 16#131# => romdata <= X"00"; -- 1
when 16#231# => romdata <= X"10"; -- 1
when 16#331# => romdata <= X"30"; -- 1
when 16#431# => romdata <= X"50"; -- 1
when 16#531# => romdata <= X"10"; -- 1
when 16#631# => romdata <= X"10"; -- 1
when 16#731# => romdata <= X"10"; -- 1
when 16#831# => romdata <= X"10"; -- 1
when 16#931# => romdata <= X"10"; -- 1
when 16#a31# => romdata <= X"7c"; -- 1
when 16#b31# => romdata <= X"00"; -- 1
when 16#c31# => romdata <= X"00"; -- 1
when 16#032# => romdata <= X"00"; -- 2
when 16#132# => romdata <= X"00"; -- 2
when 16#232# => romdata <= X"3c"; -- 2
when 16#332# => romdata <= X"42"; -- 2
when 16#432# => romdata <= X"42"; -- 2
when 16#532# => romdata <= X"02"; -- 2
when 16#632# => romdata <= X"04"; -- 2
when 16#732# => romdata <= X"18"; -- 2
when 16#832# => romdata <= X"20"; -- 2
when 16#932# => romdata <= X"40"; -- 2
when 16#a32# => romdata <= X"7e"; -- 2
when 16#b32# => romdata <= X"00"; -- 2
when 16#c32# => romdata <= X"00"; -- 2
when 16#033# => romdata <= X"00"; -- 3
when 16#133# => romdata <= X"00"; -- 3
when 16#233# => romdata <= X"7e"; -- 3
when 16#333# => romdata <= X"02"; -- 3
when 16#433# => romdata <= X"04"; -- 3
when 16#533# => romdata <= X"08"; -- 3
when 16#633# => romdata <= X"1c"; -- 3
when 16#733# => romdata <= X"02"; -- 3
when 16#833# => romdata <= X"02"; -- 3
when 16#933# => romdata <= X"42"; -- 3
when 16#a33# => romdata <= X"3c"; -- 3
when 16#b33# => romdata <= X"00"; -- 3
when 16#c33# => romdata <= X"00"; -- 3
when 16#034# => romdata <= X"00"; -- 4
when 16#134# => romdata <= X"00"; -- 4
when 16#234# => romdata <= X"04"; -- 4
when 16#334# => romdata <= X"0c"; -- 4
when 16#434# => romdata <= X"14"; -- 4
when 16#534# => romdata <= X"24"; -- 4
when 16#634# => romdata <= X"44"; -- 4
when 16#734# => romdata <= X"44"; -- 4
when 16#834# => romdata <= X"7e"; -- 4
when 16#934# => romdata <= X"04"; -- 4
when 16#a34# => romdata <= X"04"; -- 4
when 16#b34# => romdata <= X"00"; -- 4
when 16#c34# => romdata <= X"00"; -- 4
when 16#035# => romdata <= X"00"; -- 5
when 16#135# => romdata <= X"00"; -- 5
when 16#235# => romdata <= X"7e"; -- 5
when 16#335# => romdata <= X"40"; -- 5
when 16#435# => romdata <= X"40"; -- 5
when 16#535# => romdata <= X"5c"; -- 5
when 16#635# => romdata <= X"62"; -- 5
when 16#735# => romdata <= X"02"; -- 5
when 16#835# => romdata <= X"02"; -- 5
when 16#935# => romdata <= X"42"; -- 5
when 16#a35# => romdata <= X"3c"; -- 5
when 16#b35# => romdata <= X"00"; -- 5
when 16#c35# => romdata <= X"00"; -- 5
when 16#036# => romdata <= X"00"; -- 6
when 16#136# => romdata <= X"00"; -- 6
when 16#236# => romdata <= X"1c"; -- 6
when 16#336# => romdata <= X"20"; -- 6
when 16#436# => romdata <= X"40"; -- 6
when 16#536# => romdata <= X"40"; -- 6
when 16#636# => romdata <= X"5c"; -- 6
when 16#736# => romdata <= X"62"; -- 6
when 16#836# => romdata <= X"42"; -- 6
when 16#936# => romdata <= X"42"; -- 6
when 16#a36# => romdata <= X"3c"; -- 6
when 16#b36# => romdata <= X"00"; -- 6
when 16#c36# => romdata <= X"00"; -- 6
when 16#037# => romdata <= X"00"; -- 7
when 16#137# => romdata <= X"00"; -- 7
when 16#237# => romdata <= X"7e"; -- 7
when 16#337# => romdata <= X"02"; -- 7
when 16#437# => romdata <= X"04"; -- 7
when 16#537# => romdata <= X"08"; -- 7
when 16#637# => romdata <= X"08"; -- 7
when 16#737# => romdata <= X"10"; -- 7
when 16#837# => romdata <= X"10"; -- 7
when 16#937# => romdata <= X"20"; -- 7
when 16#a37# => romdata <= X"20"; -- 7
when 16#b37# => romdata <= X"00"; -- 7
when 16#c37# => romdata <= X"00"; -- 7
when 16#038# => romdata <= X"00"; -- 8
when 16#138# => romdata <= X"00"; -- 8
when 16#238# => romdata <= X"3c"; -- 8
when 16#338# => romdata <= X"42"; -- 8
when 16#438# => romdata <= X"42"; -- 8
when 16#538# => romdata <= X"42"; -- 8
when 16#638# => romdata <= X"3c"; -- 8
when 16#738# => romdata <= X"42"; -- 8
when 16#838# => romdata <= X"42"; -- 8
when 16#938# => romdata <= X"42"; -- 8
when 16#a38# => romdata <= X"3c"; -- 8
when 16#b38# => romdata <= X"00"; -- 8
when 16#c38# => romdata <= X"00"; -- 8
when 16#039# => romdata <= X"00"; -- 9
when 16#139# => romdata <= X"00"; -- 9
when 16#239# => romdata <= X"3c"; -- 9
when 16#339# => romdata <= X"42"; -- 9
when 16#439# => romdata <= X"42"; -- 9
when 16#539# => romdata <= X"46"; -- 9
when 16#639# => romdata <= X"3a"; -- 9
when 16#739# => romdata <= X"02"; -- 9
when 16#839# => romdata <= X"02"; -- 9
when 16#939# => romdata <= X"04"; -- 9
when 16#a39# => romdata <= X"38"; -- 9
when 16#b39# => romdata <= X"00"; -- 9
when 16#c39# => romdata <= X"00"; -- 9
when 16#03a# => romdata <= X"00"; -- :
when 16#13a# => romdata <= X"00"; -- :
when 16#23a# => romdata <= X"00"; -- :
when 16#33a# => romdata <= X"00"; -- :
when 16#43a# => romdata <= X"10"; -- :
when 16#53a# => romdata <= X"38"; -- :
when 16#63a# => romdata <= X"10"; -- :
when 16#73a# => romdata <= X"00"; -- :
when 16#83a# => romdata <= X"00"; -- :
when 16#93a# => romdata <= X"10"; -- :
when 16#a3a# => romdata <= X"38"; -- :
when 16#b3a# => romdata <= X"10"; -- :
when 16#c3a# => romdata <= X"00"; -- :
when 16#03b# => romdata <= X"00"; -- ;
when 16#13b# => romdata <= X"00"; -- ;
when 16#23b# => romdata <= X"00"; -- ;
when 16#33b# => romdata <= X"00"; -- ;
when 16#43b# => romdata <= X"10"; -- ;
when 16#53b# => romdata <= X"38"; -- ;
when 16#63b# => romdata <= X"10"; -- ;
when 16#73b# => romdata <= X"00"; -- ;
when 16#83b# => romdata <= X"00"; -- ;
when 16#93b# => romdata <= X"38"; -- ;
when 16#a3b# => romdata <= X"30"; -- ;
when 16#b3b# => romdata <= X"40"; -- ;
when 16#c3b# => romdata <= X"00"; -- ;
when 16#03c# => romdata <= X"00"; -- <
when 16#13c# => romdata <= X"00"; -- <
when 16#23c# => romdata <= X"02"; -- <
when 16#33c# => romdata <= X"04"; -- <
when 16#43c# => romdata <= X"08"; -- <
when 16#53c# => romdata <= X"10"; -- <
when 16#63c# => romdata <= X"20"; -- <
when 16#73c# => romdata <= X"10"; -- <
when 16#83c# => romdata <= X"08"; -- <
when 16#93c# => romdata <= X"04"; -- <
when 16#a3c# => romdata <= X"02"; -- <
when 16#b3c# => romdata <= X"00"; -- <
when 16#c3c# => romdata <= X"00"; -- <
when 16#03d# => romdata <= X"00"; -- =
when 16#13d# => romdata <= X"00"; -- =
when 16#23d# => romdata <= X"00"; -- =
when 16#33d# => romdata <= X"00"; -- =
when 16#43d# => romdata <= X"00"; -- =
when 16#53d# => romdata <= X"7e"; -- =
when 16#63d# => romdata <= X"00"; -- =
when 16#73d# => romdata <= X"00"; -- =
when 16#83d# => romdata <= X"7e"; -- =
when 16#93d# => romdata <= X"00"; -- =
when 16#a3d# => romdata <= X"00"; -- =
when 16#b3d# => romdata <= X"00"; -- =
when 16#c3d# => romdata <= X"00"; -- =
when 16#03e# => romdata <= X"00"; -- >
when 16#13e# => romdata <= X"00"; -- >
when 16#23e# => romdata <= X"40"; -- >
when 16#33e# => romdata <= X"20"; -- >
when 16#43e# => romdata <= X"10"; -- >
when 16#53e# => romdata <= X"08"; -- >
when 16#63e# => romdata <= X"04"; -- >
when 16#73e# => romdata <= X"08"; -- >
when 16#83e# => romdata <= X"10"; -- >
when 16#93e# => romdata <= X"20"; -- >
when 16#a3e# => romdata <= X"40"; -- >
when 16#b3e# => romdata <= X"00"; -- >
when 16#c3e# => romdata <= X"00"; -- >
when 16#03f# => romdata <= X"00"; -- ?
when 16#13f# => romdata <= X"00"; -- ?
when 16#23f# => romdata <= X"3c"; -- ?
when 16#33f# => romdata <= X"42"; -- ?
when 16#43f# => romdata <= X"42"; -- ?
when 16#53f# => romdata <= X"02"; -- ?
when 16#63f# => romdata <= X"04"; -- ?
when 16#73f# => romdata <= X"08"; -- ?
when 16#83f# => romdata <= X"08"; -- ?
when 16#93f# => romdata <= X"00"; -- ?
when 16#a3f# => romdata <= X"08"; -- ?
when 16#b3f# => romdata <= X"00"; -- ?
when 16#c3f# => romdata <= X"00"; -- ?
when 16#040# => romdata <= X"00"; -- @
when 16#140# => romdata <= X"00"; -- @
when 16#240# => romdata <= X"3c"; -- @
when 16#340# => romdata <= X"42"; -- @
when 16#440# => romdata <= X"42"; -- @
when 16#540# => romdata <= X"4e"; -- @
when 16#640# => romdata <= X"52"; -- @
when 16#740# => romdata <= X"56"; -- @
when 16#840# => romdata <= X"4a"; -- @
when 16#940# => romdata <= X"40"; -- @
when 16#a40# => romdata <= X"3c"; -- @
when 16#b40# => romdata <= X"00"; -- @
when 16#c40# => romdata <= X"00"; -- @
when 16#041# => romdata <= X"00"; -- A
when 16#141# => romdata <= X"00"; -- A
when 16#241# => romdata <= X"18"; -- A
when 16#341# => romdata <= X"24"; -- A
when 16#441# => romdata <= X"42"; -- A
when 16#541# => romdata <= X"42"; -- A
when 16#641# => romdata <= X"42"; -- A
when 16#741# => romdata <= X"7e"; -- A
when 16#841# => romdata <= X"42"; -- A
when 16#941# => romdata <= X"42"; -- A
when 16#a41# => romdata <= X"42"; -- A
when 16#b41# => romdata <= X"00"; -- A
when 16#c41# => romdata <= X"00"; -- A
when 16#042# => romdata <= X"00"; -- B
when 16#142# => romdata <= X"00"; -- B
when 16#242# => romdata <= X"78"; -- B
when 16#342# => romdata <= X"44"; -- B
when 16#442# => romdata <= X"42"; -- B
when 16#542# => romdata <= X"44"; -- B
when 16#642# => romdata <= X"78"; -- B
when 16#742# => romdata <= X"44"; -- B
when 16#842# => romdata <= X"42"; -- B
when 16#942# => romdata <= X"44"; -- B
when 16#a42# => romdata <= X"78"; -- B
when 16#b42# => romdata <= X"00"; -- B
when 16#c42# => romdata <= X"00"; -- B
when 16#043# => romdata <= X"00"; -- C
when 16#143# => romdata <= X"00"; -- C
when 16#243# => romdata <= X"3c"; -- C
when 16#343# => romdata <= X"42"; -- C
when 16#443# => romdata <= X"40"; -- C
when 16#543# => romdata <= X"40"; -- C
when 16#643# => romdata <= X"40"; -- C
when 16#743# => romdata <= X"40"; -- C
when 16#843# => romdata <= X"40"; -- C
when 16#943# => romdata <= X"42"; -- C
when 16#a43# => romdata <= X"3c"; -- C
when 16#b43# => romdata <= X"00"; -- C
when 16#c43# => romdata <= X"00"; -- C
when 16#044# => romdata <= X"00"; -- D
when 16#144# => romdata <= X"00"; -- D
when 16#244# => romdata <= X"78"; -- D
when 16#344# => romdata <= X"44"; -- D
when 16#444# => romdata <= X"42"; -- D
when 16#544# => romdata <= X"42"; -- D
when 16#644# => romdata <= X"42"; -- D
when 16#744# => romdata <= X"42"; -- D
when 16#844# => romdata <= X"42"; -- D
when 16#944# => romdata <= X"44"; -- D
when 16#a44# => romdata <= X"78"; -- D
when 16#b44# => romdata <= X"00"; -- D
when 16#c44# => romdata <= X"00"; -- D
when 16#045# => romdata <= X"00"; -- E
when 16#145# => romdata <= X"00"; -- E
when 16#245# => romdata <= X"7e"; -- E
when 16#345# => romdata <= X"40"; -- E
when 16#445# => romdata <= X"40"; -- E
when 16#545# => romdata <= X"40"; -- E
when 16#645# => romdata <= X"78"; -- E
when 16#745# => romdata <= X"40"; -- E
when 16#845# => romdata <= X"40"; -- E
when 16#945# => romdata <= X"40"; -- E
when 16#a45# => romdata <= X"7e"; -- E
when 16#b45# => romdata <= X"00"; -- E
when 16#c45# => romdata <= X"00"; -- E
when 16#046# => romdata <= X"00"; -- F
when 16#146# => romdata <= X"00"; -- F
when 16#246# => romdata <= X"7e"; -- F
when 16#346# => romdata <= X"40"; -- F
when 16#446# => romdata <= X"40"; -- F
when 16#546# => romdata <= X"40"; -- F
when 16#646# => romdata <= X"78"; -- F
when 16#746# => romdata <= X"40"; -- F
when 16#846# => romdata <= X"40"; -- F
when 16#946# => romdata <= X"40"; -- F
when 16#a46# => romdata <= X"40"; -- F
when 16#b46# => romdata <= X"00"; -- F
when 16#c46# => romdata <= X"00"; -- F
when 16#047# => romdata <= X"00"; -- G
when 16#147# => romdata <= X"00"; -- G
when 16#247# => romdata <= X"3c"; -- G
when 16#347# => romdata <= X"42"; -- G
when 16#447# => romdata <= X"40"; -- G
when 16#547# => romdata <= X"40"; -- G
when 16#647# => romdata <= X"40"; -- G
when 16#747# => romdata <= X"4e"; -- G
when 16#847# => romdata <= X"42"; -- G
when 16#947# => romdata <= X"46"; -- G
when 16#a47# => romdata <= X"3a"; -- G
when 16#b47# => romdata <= X"00"; -- G
when 16#c47# => romdata <= X"00"; -- G
when 16#048# => romdata <= X"00"; -- H
when 16#148# => romdata <= X"00"; -- H
when 16#248# => romdata <= X"42"; -- H
when 16#348# => romdata <= X"42"; -- H
when 16#448# => romdata <= X"42"; -- H
when 16#548# => romdata <= X"42"; -- H
when 16#648# => romdata <= X"7e"; -- H
when 16#748# => romdata <= X"42"; -- H
when 16#848# => romdata <= X"42"; -- H
when 16#948# => romdata <= X"42"; -- H
when 16#a48# => romdata <= X"42"; -- H
when 16#b48# => romdata <= X"00"; -- H
when 16#c48# => romdata <= X"00"; -- H
when 16#049# => romdata <= X"00"; -- I
when 16#149# => romdata <= X"00"; -- I
when 16#249# => romdata <= X"7c"; -- I
when 16#349# => romdata <= X"10"; -- I
when 16#449# => romdata <= X"10"; -- I
when 16#549# => romdata <= X"10"; -- I
when 16#649# => romdata <= X"10"; -- I
when 16#749# => romdata <= X"10"; -- I
when 16#849# => romdata <= X"10"; -- I
when 16#949# => romdata <= X"10"; -- I
when 16#a49# => romdata <= X"7c"; -- I
when 16#b49# => romdata <= X"00"; -- I
when 16#c49# => romdata <= X"00"; -- I
when 16#04a# => romdata <= X"00"; -- J
when 16#14a# => romdata <= X"00"; -- J
when 16#24a# => romdata <= X"1f"; -- J
when 16#34a# => romdata <= X"04"; -- J
when 16#44a# => romdata <= X"04"; -- J
when 16#54a# => romdata <= X"04"; -- J
when 16#64a# => romdata <= X"04"; -- J
when 16#74a# => romdata <= X"04"; -- J
when 16#84a# => romdata <= X"04"; -- J
when 16#94a# => romdata <= X"44"; -- J
when 16#a4a# => romdata <= X"38"; -- J
when 16#b4a# => romdata <= X"00"; -- J
when 16#c4a# => romdata <= X"00"; -- J
when 16#04b# => romdata <= X"00"; -- K
when 16#14b# => romdata <= X"00"; -- K
when 16#24b# => romdata <= X"42"; -- K
when 16#34b# => romdata <= X"44"; -- K
when 16#44b# => romdata <= X"48"; -- K
when 16#54b# => romdata <= X"50"; -- K
when 16#64b# => romdata <= X"60"; -- K
when 16#74b# => romdata <= X"50"; -- K
when 16#84b# => romdata <= X"48"; -- K
when 16#94b# => romdata <= X"44"; -- K
when 16#a4b# => romdata <= X"42"; -- K
when 16#b4b# => romdata <= X"00"; -- K
when 16#c4b# => romdata <= X"00"; -- K
when 16#04c# => romdata <= X"00"; -- L
when 16#14c# => romdata <= X"00"; -- L
when 16#24c# => romdata <= X"40"; -- L
when 16#34c# => romdata <= X"40"; -- L
when 16#44c# => romdata <= X"40"; -- L
when 16#54c# => romdata <= X"40"; -- L
when 16#64c# => romdata <= X"40"; -- L
when 16#74c# => romdata <= X"40"; -- L
when 16#84c# => romdata <= X"40"; -- L
when 16#94c# => romdata <= X"40"; -- L
when 16#a4c# => romdata <= X"7e"; -- L
when 16#b4c# => romdata <= X"00"; -- L
when 16#c4c# => romdata <= X"00"; -- L
when 16#04d# => romdata <= X"00"; -- M
when 16#14d# => romdata <= X"00"; -- M
when 16#24d# => romdata <= X"82"; -- M
when 16#34d# => romdata <= X"82"; -- M
when 16#44d# => romdata <= X"c6"; -- M
when 16#54d# => romdata <= X"aa"; -- M
when 16#64d# => romdata <= X"92"; -- M
when 16#74d# => romdata <= X"92"; -- M
when 16#84d# => romdata <= X"82"; -- M
when 16#94d# => romdata <= X"82"; -- M
when 16#a4d# => romdata <= X"82"; -- M
when 16#b4d# => romdata <= X"00"; -- M
when 16#c4d# => romdata <= X"00"; -- M
when 16#04e# => romdata <= X"00"; -- N
when 16#14e# => romdata <= X"00"; -- N
when 16#24e# => romdata <= X"42"; -- N
when 16#34e# => romdata <= X"42"; -- N
when 16#44e# => romdata <= X"62"; -- N
when 16#54e# => romdata <= X"52"; -- N
when 16#64e# => romdata <= X"4a"; -- N
when 16#74e# => romdata <= X"46"; -- N
when 16#84e# => romdata <= X"42"; -- N
when 16#94e# => romdata <= X"42"; -- N
when 16#a4e# => romdata <= X"42"; -- N
when 16#b4e# => romdata <= X"00"; -- N
when 16#c4e# => romdata <= X"00"; -- N
when 16#04f# => romdata <= X"00"; -- O
when 16#14f# => romdata <= X"00"; -- O
when 16#24f# => romdata <= X"3c"; -- O
when 16#34f# => romdata <= X"42"; -- O
when 16#44f# => romdata <= X"42"; -- O
when 16#54f# => romdata <= X"42"; -- O
when 16#64f# => romdata <= X"42"; -- O
when 16#74f# => romdata <= X"42"; -- O
when 16#84f# => romdata <= X"42"; -- O
when 16#94f# => romdata <= X"42"; -- O
when 16#a4f# => romdata <= X"3c"; -- O
when 16#b4f# => romdata <= X"00"; -- O
when 16#c4f# => romdata <= X"00"; -- O
when 16#050# => romdata <= X"00"; -- P
when 16#150# => romdata <= X"00"; -- P
when 16#250# => romdata <= X"7c"; -- P
when 16#350# => romdata <= X"42"; -- P
when 16#450# => romdata <= X"42"; -- P
when 16#550# => romdata <= X"42"; -- P
when 16#650# => romdata <= X"7c"; -- P
when 16#750# => romdata <= X"40"; -- P
when 16#850# => romdata <= X"40"; -- P
when 16#950# => romdata <= X"40"; -- P
when 16#a50# => romdata <= X"40"; -- P
when 16#b50# => romdata <= X"00"; -- P
when 16#c50# => romdata <= X"00"; -- P
when 16#051# => romdata <= X"00"; -- Q
when 16#151# => romdata <= X"00"; -- Q
when 16#251# => romdata <= X"3c"; -- Q
when 16#351# => romdata <= X"42"; -- Q
when 16#451# => romdata <= X"42"; -- Q
when 16#551# => romdata <= X"42"; -- Q
when 16#651# => romdata <= X"42"; -- Q
when 16#751# => romdata <= X"42"; -- Q
when 16#851# => romdata <= X"52"; -- Q
when 16#951# => romdata <= X"4a"; -- Q
when 16#a51# => romdata <= X"3c"; -- Q
when 16#b51# => romdata <= X"02"; -- Q
when 16#c51# => romdata <= X"00"; -- Q
when 16#052# => romdata <= X"00"; -- R
when 16#152# => romdata <= X"00"; -- R
when 16#252# => romdata <= X"7c"; -- R
when 16#352# => romdata <= X"42"; -- R
when 16#452# => romdata <= X"42"; -- R
when 16#552# => romdata <= X"42"; -- R
when 16#652# => romdata <= X"7c"; -- R
when 16#752# => romdata <= X"50"; -- R
when 16#852# => romdata <= X"48"; -- R
when 16#952# => romdata <= X"44"; -- R
when 16#a52# => romdata <= X"42"; -- R
when 16#b52# => romdata <= X"00"; -- R
when 16#c52# => romdata <= X"00"; -- R
when 16#053# => romdata <= X"00"; -- S
when 16#153# => romdata <= X"00"; -- S
when 16#253# => romdata <= X"3c"; -- S
when 16#353# => romdata <= X"42"; -- S
when 16#453# => romdata <= X"40"; -- S
when 16#553# => romdata <= X"40"; -- S
when 16#653# => romdata <= X"3c"; -- S
when 16#753# => romdata <= X"02"; -- S
when 16#853# => romdata <= X"02"; -- S
when 16#953# => romdata <= X"42"; -- S
when 16#a53# => romdata <= X"3c"; -- S
when 16#b53# => romdata <= X"00"; -- S
when 16#c53# => romdata <= X"00"; -- S
when 16#054# => romdata <= X"00"; -- T
when 16#154# => romdata <= X"00"; -- T
when 16#254# => romdata <= X"fe"; -- T
when 16#354# => romdata <= X"10"; -- T
when 16#454# => romdata <= X"10"; -- T
when 16#554# => romdata <= X"10"; -- T
when 16#654# => romdata <= X"10"; -- T
when 16#754# => romdata <= X"10"; -- T
when 16#854# => romdata <= X"10"; -- T
when 16#954# => romdata <= X"10"; -- T
when 16#a54# => romdata <= X"10"; -- T
when 16#b54# => romdata <= X"00"; -- T
when 16#c54# => romdata <= X"00"; -- T
when 16#055# => romdata <= X"00"; -- U
when 16#155# => romdata <= X"00"; -- U
when 16#255# => romdata <= X"42"; -- U
when 16#355# => romdata <= X"42"; -- U
when 16#455# => romdata <= X"42"; -- U
when 16#555# => romdata <= X"42"; -- U
when 16#655# => romdata <= X"42"; -- U
when 16#755# => romdata <= X"42"; -- U
when 16#855# => romdata <= X"42"; -- U
when 16#955# => romdata <= X"42"; -- U
when 16#a55# => romdata <= X"3c"; -- U
when 16#b55# => romdata <= X"00"; -- U
when 16#c55# => romdata <= X"00"; -- U
when 16#056# => romdata <= X"00"; -- V
when 16#156# => romdata <= X"00"; -- V
when 16#256# => romdata <= X"82"; -- V
when 16#356# => romdata <= X"82"; -- V
when 16#456# => romdata <= X"44"; -- V
when 16#556# => romdata <= X"44"; -- V
when 16#656# => romdata <= X"44"; -- V
when 16#756# => romdata <= X"28"; -- V
when 16#856# => romdata <= X"28"; -- V
when 16#956# => romdata <= X"28"; -- V
when 16#a56# => romdata <= X"10"; -- V
when 16#b56# => romdata <= X"00"; -- V
when 16#c56# => romdata <= X"00"; -- V
when 16#057# => romdata <= X"00"; -- W
when 16#157# => romdata <= X"00"; -- W
when 16#257# => romdata <= X"82"; -- W
when 16#357# => romdata <= X"82"; -- W
when 16#457# => romdata <= X"82"; -- W
when 16#557# => romdata <= X"82"; -- W
when 16#657# => romdata <= X"92"; -- W
when 16#757# => romdata <= X"92"; -- W
when 16#857# => romdata <= X"92"; -- W
when 16#957# => romdata <= X"aa"; -- W
when 16#a57# => romdata <= X"44"; -- W
when 16#b57# => romdata <= X"00"; -- W
when 16#c57# => romdata <= X"00"; -- W
when 16#058# => romdata <= X"00"; -- X
when 16#158# => romdata <= X"00"; -- X
when 16#258# => romdata <= X"82"; -- X
when 16#358# => romdata <= X"82"; -- X
when 16#458# => romdata <= X"44"; -- X
when 16#558# => romdata <= X"28"; -- X
when 16#658# => romdata <= X"10"; -- X
when 16#758# => romdata <= X"28"; -- X
when 16#858# => romdata <= X"44"; -- X
when 16#958# => romdata <= X"82"; -- X
when 16#a58# => romdata <= X"82"; -- X
when 16#b58# => romdata <= X"00"; -- X
when 16#c58# => romdata <= X"00"; -- X
when 16#059# => romdata <= X"00"; -- Y
when 16#159# => romdata <= X"00"; -- Y
when 16#259# => romdata <= X"82"; -- Y
when 16#359# => romdata <= X"82"; -- Y
when 16#459# => romdata <= X"44"; -- Y
when 16#559# => romdata <= X"28"; -- Y
when 16#659# => romdata <= X"10"; -- Y
when 16#759# => romdata <= X"10"; -- Y
when 16#859# => romdata <= X"10"; -- Y
when 16#959# => romdata <= X"10"; -- Y
when 16#a59# => romdata <= X"10"; -- Y
when 16#b59# => romdata <= X"00"; -- Y
when 16#c59# => romdata <= X"00"; -- Y
when 16#05a# => romdata <= X"00"; -- Z
when 16#15a# => romdata <= X"00"; -- Z
when 16#25a# => romdata <= X"7e"; -- Z
when 16#35a# => romdata <= X"02"; -- Z
when 16#45a# => romdata <= X"04"; -- Z
when 16#55a# => romdata <= X"08"; -- Z
when 16#65a# => romdata <= X"10"; -- Z
when 16#75a# => romdata <= X"20"; -- Z
when 16#85a# => romdata <= X"40"; -- Z
when 16#95a# => romdata <= X"40"; -- Z
when 16#a5a# => romdata <= X"7e"; -- Z
when 16#b5a# => romdata <= X"00"; -- Z
when 16#c5a# => romdata <= X"00"; -- Z
when 16#05b# => romdata <= X"00"; -- [
when 16#15b# => romdata <= X"00"; -- [
when 16#25b# => romdata <= X"3c"; -- [
when 16#35b# => romdata <= X"20"; -- [
when 16#45b# => romdata <= X"20"; -- [
when 16#55b# => romdata <= X"20"; -- [
when 16#65b# => romdata <= X"20"; -- [
when 16#75b# => romdata <= X"20"; -- [
when 16#85b# => romdata <= X"20"; -- [
when 16#95b# => romdata <= X"20"; -- [
when 16#a5b# => romdata <= X"3c"; -- [
when 16#b5b# => romdata <= X"00"; -- [
when 16#c5b# => romdata <= X"00"; -- [
when 16#05c# => romdata <= X"00"; -- \
when 16#15c# => romdata <= X"00"; -- \
when 16#25c# => romdata <= X"80"; -- \
when 16#35c# => romdata <= X"80"; -- \
when 16#45c# => romdata <= X"40"; -- \
when 16#55c# => romdata <= X"20"; -- \
when 16#65c# => romdata <= X"10"; -- \
when 16#75c# => romdata <= X"08"; -- \
when 16#85c# => romdata <= X"04"; -- \
when 16#95c# => romdata <= X"02"; -- \
when 16#a5c# => romdata <= X"02"; -- \
when 16#b5c# => romdata <= X"00"; -- \
when 16#c5c# => romdata <= X"00"; -- \
when 16#05d# => romdata <= X"00"; -- ]
when 16#15d# => romdata <= X"00"; -- ]
when 16#25d# => romdata <= X"78"; -- ]
when 16#35d# => romdata <= X"08"; -- ]
when 16#45d# => romdata <= X"08"; -- ]
when 16#55d# => romdata <= X"08"; -- ]
when 16#65d# => romdata <= X"08"; -- ]
when 16#75d# => romdata <= X"08"; -- ]
when 16#85d# => romdata <= X"08"; -- ]
when 16#95d# => romdata <= X"08"; -- ]
when 16#a5d# => romdata <= X"78"; -- ]
when 16#b5d# => romdata <= X"00"; -- ]
when 16#c5d# => romdata <= X"00"; -- ]
when 16#05e# => romdata <= X"00"; -- ^
when 16#15e# => romdata <= X"00"; -- ^
when 16#25e# => romdata <= X"10"; -- ^
when 16#35e# => romdata <= X"28"; -- ^
when 16#45e# => romdata <= X"44"; -- ^
when 16#55e# => romdata <= X"00"; -- ^
when 16#65e# => romdata <= X"00"; -- ^
when 16#75e# => romdata <= X"00"; -- ^
when 16#85e# => romdata <= X"00"; -- ^
when 16#95e# => romdata <= X"00"; -- ^
when 16#a5e# => romdata <= X"00"; -- ^
when 16#b5e# => romdata <= X"00"; -- ^
when 16#c5e# => romdata <= X"00"; -- ^
when 16#05f# => romdata <= X"00"; -- _
when 16#15f# => romdata <= X"00"; -- _
when 16#25f# => romdata <= X"00"; -- _
when 16#35f# => romdata <= X"00"; -- _
when 16#45f# => romdata <= X"00"; -- _
when 16#55f# => romdata <= X"00"; -- _
when 16#65f# => romdata <= X"00"; -- _
when 16#75f# => romdata <= X"00"; -- _
when 16#85f# => romdata <= X"00"; -- _
when 16#95f# => romdata <= X"00"; -- _
when 16#a5f# => romdata <= X"00"; -- _
when 16#b5f# => romdata <= X"fe"; -- _
when 16#c5f# => romdata <= X"00"; -- _
when 16#060# => romdata <= X"00"; -- `
when 16#160# => romdata <= X"10"; -- `
when 16#260# => romdata <= X"08"; -- `
when 16#360# => romdata <= X"00"; -- `
when 16#460# => romdata <= X"00"; -- `
when 16#560# => romdata <= X"00"; -- `
when 16#660# => romdata <= X"00"; -- `
when 16#760# => romdata <= X"00"; -- `
when 16#860# => romdata <= X"00"; -- `
when 16#960# => romdata <= X"00"; -- `
when 16#a60# => romdata <= X"00"; -- `
when 16#b60# => romdata <= X"00"; -- `
when 16#c60# => romdata <= X"00"; -- `
when 16#061# => romdata <= X"00"; -- a
when 16#161# => romdata <= X"00"; -- a
when 16#261# => romdata <= X"00"; -- a
when 16#361# => romdata <= X"00"; -- a
when 16#461# => romdata <= X"00"; -- a
when 16#561# => romdata <= X"3c"; -- a
when 16#661# => romdata <= X"02"; -- a
when 16#761# => romdata <= X"3e"; -- a
when 16#861# => romdata <= X"42"; -- a
when 16#961# => romdata <= X"46"; -- a
when 16#a61# => romdata <= X"3a"; -- a
when 16#b61# => romdata <= X"00"; -- a
when 16#c61# => romdata <= X"00"; -- a
when 16#062# => romdata <= X"00"; -- b
when 16#162# => romdata <= X"00"; -- b
when 16#262# => romdata <= X"40"; -- b
when 16#362# => romdata <= X"40"; -- b
when 16#462# => romdata <= X"40"; -- b
when 16#562# => romdata <= X"5c"; -- b
when 16#662# => romdata <= X"62"; -- b
when 16#762# => romdata <= X"42"; -- b
when 16#862# => romdata <= X"42"; -- b
when 16#962# => romdata <= X"62"; -- b
when 16#a62# => romdata <= X"5c"; -- b
when 16#b62# => romdata <= X"00"; -- b
when 16#c62# => romdata <= X"00"; -- b
when 16#063# => romdata <= X"00"; -- c
when 16#163# => romdata <= X"00"; -- c
when 16#263# => romdata <= X"00"; -- c
when 16#363# => romdata <= X"00"; -- c
when 16#463# => romdata <= X"00"; -- c
when 16#563# => romdata <= X"3c"; -- c
when 16#663# => romdata <= X"42"; -- c
when 16#763# => romdata <= X"40"; -- c
when 16#863# => romdata <= X"40"; -- c
when 16#963# => romdata <= X"42"; -- c
when 16#a63# => romdata <= X"3c"; -- c
when 16#b63# => romdata <= X"00"; -- c
when 16#c63# => romdata <= X"00"; -- c
when 16#064# => romdata <= X"00"; -- d
when 16#164# => romdata <= X"00"; -- d
when 16#264# => romdata <= X"02"; -- d
when 16#364# => romdata <= X"02"; -- d
when 16#464# => romdata <= X"02"; -- d
when 16#564# => romdata <= X"3a"; -- d
when 16#664# => romdata <= X"46"; -- d
when 16#764# => romdata <= X"42"; -- d
when 16#864# => romdata <= X"42"; -- d
when 16#964# => romdata <= X"46"; -- d
when 16#a64# => romdata <= X"3a"; -- d
when 16#b64# => romdata <= X"00"; -- d
when 16#c64# => romdata <= X"00"; -- d
when 16#065# => romdata <= X"00"; -- e
when 16#165# => romdata <= X"00"; -- e
when 16#265# => romdata <= X"00"; -- e
when 16#365# => romdata <= X"00"; -- e
when 16#465# => romdata <= X"00"; -- e
when 16#565# => romdata <= X"3c"; -- e
when 16#665# => romdata <= X"42"; -- e
when 16#765# => romdata <= X"7e"; -- e
when 16#865# => romdata <= X"40"; -- e
when 16#965# => romdata <= X"42"; -- e
when 16#a65# => romdata <= X"3c"; -- e
when 16#b65# => romdata <= X"00"; -- e
when 16#c65# => romdata <= X"00"; -- e
when 16#066# => romdata <= X"00"; -- f
when 16#166# => romdata <= X"00"; -- f
when 16#266# => romdata <= X"1c"; -- f
when 16#366# => romdata <= X"22"; -- f
when 16#466# => romdata <= X"20"; -- f
when 16#566# => romdata <= X"20"; -- f
when 16#666# => romdata <= X"7c"; -- f
when 16#766# => romdata <= X"20"; -- f
when 16#866# => romdata <= X"20"; -- f
when 16#966# => romdata <= X"20"; -- f
when 16#a66# => romdata <= X"20"; -- f
when 16#b66# => romdata <= X"00"; -- f
when 16#c66# => romdata <= X"00"; -- f
when 16#067# => romdata <= X"00"; -- g
when 16#167# => romdata <= X"00"; -- g
when 16#267# => romdata <= X"00"; -- g
when 16#367# => romdata <= X"00"; -- g
when 16#467# => romdata <= X"00"; -- g
when 16#567# => romdata <= X"3a"; -- g
when 16#667# => romdata <= X"44"; -- g
when 16#767# => romdata <= X"44"; -- g
when 16#867# => romdata <= X"38"; -- g
when 16#967# => romdata <= X"40"; -- g
when 16#a67# => romdata <= X"3c"; -- g
when 16#b67# => romdata <= X"42"; -- g
when 16#c67# => romdata <= X"3c"; -- g
when 16#068# => romdata <= X"00"; -- h
when 16#168# => romdata <= X"00"; -- h
when 16#268# => romdata <= X"40"; -- h
when 16#368# => romdata <= X"40"; -- h
when 16#468# => romdata <= X"40"; -- h
when 16#568# => romdata <= X"5c"; -- h
when 16#668# => romdata <= X"62"; -- h
when 16#768# => romdata <= X"42"; -- h
when 16#868# => romdata <= X"42"; -- h
when 16#968# => romdata <= X"42"; -- h
when 16#a68# => romdata <= X"42"; -- h
when 16#b68# => romdata <= X"00"; -- h
when 16#c68# => romdata <= X"00"; -- h
when 16#069# => romdata <= X"00"; -- i
when 16#169# => romdata <= X"00"; -- i
when 16#269# => romdata <= X"00"; -- i
when 16#369# => romdata <= X"10"; -- i
when 16#469# => romdata <= X"00"; -- i
when 16#569# => romdata <= X"30"; -- i
when 16#669# => romdata <= X"10"; -- i
when 16#769# => romdata <= X"10"; -- i
when 16#869# => romdata <= X"10"; -- i
when 16#969# => romdata <= X"10"; -- i
when 16#a69# => romdata <= X"7c"; -- i
when 16#b69# => romdata <= X"00"; -- i
when 16#c69# => romdata <= X"00"; -- i
when 16#06a# => romdata <= X"00"; -- j
when 16#16a# => romdata <= X"00"; -- j
when 16#26a# => romdata <= X"00"; -- j
when 16#36a# => romdata <= X"04"; -- j
when 16#46a# => romdata <= X"00"; -- j
when 16#56a# => romdata <= X"0c"; -- j
when 16#66a# => romdata <= X"04"; -- j
when 16#76a# => romdata <= X"04"; -- j
when 16#86a# => romdata <= X"04"; -- j
when 16#96a# => romdata <= X"04"; -- j
when 16#a6a# => romdata <= X"44"; -- j
when 16#b6a# => romdata <= X"44"; -- j
when 16#c6a# => romdata <= X"38"; -- j
when 16#06b# => romdata <= X"00"; -- k
when 16#16b# => romdata <= X"00"; -- k
when 16#26b# => romdata <= X"40"; -- k
when 16#36b# => romdata <= X"40"; -- k
when 16#46b# => romdata <= X"40"; -- k
when 16#56b# => romdata <= X"44"; -- k
when 16#66b# => romdata <= X"48"; -- k
when 16#76b# => romdata <= X"70"; -- k
when 16#86b# => romdata <= X"48"; -- k
when 16#96b# => romdata <= X"44"; -- k
when 16#a6b# => romdata <= X"42"; -- k
when 16#b6b# => romdata <= X"00"; -- k
when 16#c6b# => romdata <= X"00"; -- k
when 16#06c# => romdata <= X"00"; -- l
when 16#16c# => romdata <= X"00"; -- l
when 16#26c# => romdata <= X"30"; -- l
when 16#36c# => romdata <= X"10"; -- l
when 16#46c# => romdata <= X"10"; -- l
when 16#56c# => romdata <= X"10"; -- l
when 16#66c# => romdata <= X"10"; -- l
when 16#76c# => romdata <= X"10"; -- l
when 16#86c# => romdata <= X"10"; -- l
when 16#96c# => romdata <= X"10"; -- l
when 16#a6c# => romdata <= X"7c"; -- l
when 16#b6c# => romdata <= X"00"; -- l
when 16#c6c# => romdata <= X"00"; -- l
when 16#06d# => romdata <= X"00"; -- m
when 16#16d# => romdata <= X"00"; -- m
when 16#26d# => romdata <= X"00"; -- m
when 16#36d# => romdata <= X"00"; -- m
when 16#46d# => romdata <= X"00"; -- m
when 16#56d# => romdata <= X"ec"; -- m
when 16#66d# => romdata <= X"92"; -- m
when 16#76d# => romdata <= X"92"; -- m
when 16#86d# => romdata <= X"92"; -- m
when 16#96d# => romdata <= X"92"; -- m
when 16#a6d# => romdata <= X"82"; -- m
when 16#b6d# => romdata <= X"00"; -- m
when 16#c6d# => romdata <= X"00"; -- m
when 16#06e# => romdata <= X"00"; -- n
when 16#16e# => romdata <= X"00"; -- n
when 16#26e# => romdata <= X"00"; -- n
when 16#36e# => romdata <= X"00"; -- n
when 16#46e# => romdata <= X"00"; -- n
when 16#56e# => romdata <= X"5c"; -- n
when 16#66e# => romdata <= X"62"; -- n
when 16#76e# => romdata <= X"42"; -- n
when 16#86e# => romdata <= X"42"; -- n
when 16#96e# => romdata <= X"42"; -- n
when 16#a6e# => romdata <= X"42"; -- n
when 16#b6e# => romdata <= X"00"; -- n
when 16#c6e# => romdata <= X"00"; -- n
when 16#06f# => romdata <= X"00"; -- o
when 16#16f# => romdata <= X"00"; -- o
when 16#26f# => romdata <= X"00"; -- o
when 16#36f# => romdata <= X"00"; -- o
when 16#46f# => romdata <= X"00"; -- o
when 16#56f# => romdata <= X"3c"; -- o
when 16#66f# => romdata <= X"42"; -- o
when 16#76f# => romdata <= X"42"; -- o
when 16#86f# => romdata <= X"42"; -- o
when 16#96f# => romdata <= X"42"; -- o
when 16#a6f# => romdata <= X"3c"; -- o
when 16#b6f# => romdata <= X"00"; -- o
when 16#c6f# => romdata <= X"00"; -- o
when 16#070# => romdata <= X"00"; -- p
when 16#170# => romdata <= X"00"; -- p
when 16#270# => romdata <= X"00"; -- p
when 16#370# => romdata <= X"00"; -- p
when 16#470# => romdata <= X"00"; -- p
when 16#570# => romdata <= X"5c"; -- p
when 16#670# => romdata <= X"62"; -- p
when 16#770# => romdata <= X"42"; -- p
when 16#870# => romdata <= X"62"; -- p
when 16#970# => romdata <= X"5c"; -- p
when 16#a70# => romdata <= X"40"; -- p
when 16#b70# => romdata <= X"40"; -- p
when 16#c70# => romdata <= X"40"; -- p
when 16#071# => romdata <= X"00"; -- q
when 16#171# => romdata <= X"00"; -- q
when 16#271# => romdata <= X"00"; -- q
when 16#371# => romdata <= X"00"; -- q
when 16#471# => romdata <= X"00"; -- q
when 16#571# => romdata <= X"3a"; -- q
when 16#671# => romdata <= X"46"; -- q
when 16#771# => romdata <= X"42"; -- q
when 16#871# => romdata <= X"46"; -- q
when 16#971# => romdata <= X"3a"; -- q
when 16#a71# => romdata <= X"02"; -- q
when 16#b71# => romdata <= X"02"; -- q
when 16#c71# => romdata <= X"02"; -- q
when 16#072# => romdata <= X"00"; -- r
when 16#172# => romdata <= X"00"; -- r
when 16#272# => romdata <= X"00"; -- r
when 16#372# => romdata <= X"00"; -- r
when 16#472# => romdata <= X"00"; -- r
when 16#572# => romdata <= X"5c"; -- r
when 16#672# => romdata <= X"22"; -- r
when 16#772# => romdata <= X"20"; -- r
when 16#872# => romdata <= X"20"; -- r
when 16#972# => romdata <= X"20"; -- r
when 16#a72# => romdata <= X"20"; -- r
when 16#b72# => romdata <= X"00"; -- r
when 16#c72# => romdata <= X"00"; -- r
when 16#073# => romdata <= X"00"; -- s
when 16#173# => romdata <= X"00"; -- s
when 16#273# => romdata <= X"00"; -- s
when 16#373# => romdata <= X"00"; -- s
when 16#473# => romdata <= X"00"; -- s
when 16#573# => romdata <= X"3c"; -- s
when 16#673# => romdata <= X"42"; -- s
when 16#773# => romdata <= X"30"; -- s
when 16#873# => romdata <= X"0c"; -- s
when 16#973# => romdata <= X"42"; -- s
when 16#a73# => romdata <= X"3c"; -- s
when 16#b73# => romdata <= X"00"; -- s
when 16#c73# => romdata <= X"00"; -- s
when 16#074# => romdata <= X"00"; -- t
when 16#174# => romdata <= X"00"; -- t
when 16#274# => romdata <= X"00"; -- t
when 16#374# => romdata <= X"20"; -- t
when 16#474# => romdata <= X"20"; -- t
when 16#574# => romdata <= X"7c"; -- t
when 16#674# => romdata <= X"20"; -- t
when 16#774# => romdata <= X"20"; -- t
when 16#874# => romdata <= X"20"; -- t
when 16#974# => romdata <= X"22"; -- t
when 16#a74# => romdata <= X"1c"; -- t
when 16#b74# => romdata <= X"00"; -- t
when 16#c74# => romdata <= X"00"; -- t
when 16#075# => romdata <= X"00"; -- u
when 16#175# => romdata <= X"00"; -- u
when 16#275# => romdata <= X"00"; -- u
when 16#375# => romdata <= X"00"; -- u
when 16#475# => romdata <= X"00"; -- u
when 16#575# => romdata <= X"44"; -- u
when 16#675# => romdata <= X"44"; -- u
when 16#775# => romdata <= X"44"; -- u
when 16#875# => romdata <= X"44"; -- u
when 16#975# => romdata <= X"44"; -- u
when 16#a75# => romdata <= X"3a"; -- u
when 16#b75# => romdata <= X"00"; -- u
when 16#c75# => romdata <= X"00"; -- u
when 16#076# => romdata <= X"00"; -- v
when 16#176# => romdata <= X"00"; -- v
when 16#276# => romdata <= X"00"; -- v
when 16#376# => romdata <= X"00"; -- v
when 16#476# => romdata <= X"00"; -- v
when 16#576# => romdata <= X"44"; -- v
when 16#676# => romdata <= X"44"; -- v
when 16#776# => romdata <= X"44"; -- v
when 16#876# => romdata <= X"28"; -- v
when 16#976# => romdata <= X"28"; -- v
when 16#a76# => romdata <= X"10"; -- v
when 16#b76# => romdata <= X"00"; -- v
when 16#c76# => romdata <= X"00"; -- v
when 16#077# => romdata <= X"00"; -- w
when 16#177# => romdata <= X"00"; -- w
when 16#277# => romdata <= X"00"; -- w
when 16#377# => romdata <= X"00"; -- w
when 16#477# => romdata <= X"00"; -- w
when 16#577# => romdata <= X"82"; -- w
when 16#677# => romdata <= X"82"; -- w
when 16#777# => romdata <= X"92"; -- w
when 16#877# => romdata <= X"92"; -- w
when 16#977# => romdata <= X"aa"; -- w
when 16#a77# => romdata <= X"44"; -- w
when 16#b77# => romdata <= X"00"; -- w
when 16#c77# => romdata <= X"00"; -- w
when 16#078# => romdata <= X"00"; -- x
when 16#178# => romdata <= X"00"; -- x
when 16#278# => romdata <= X"00"; -- x
when 16#378# => romdata <= X"00"; -- x
when 16#478# => romdata <= X"00"; -- x
when 16#578# => romdata <= X"42"; -- x
when 16#678# => romdata <= X"24"; -- x
when 16#778# => romdata <= X"18"; -- x
when 16#878# => romdata <= X"18"; -- x
when 16#978# => romdata <= X"24"; -- x
when 16#a78# => romdata <= X"42"; -- x
when 16#b78# => romdata <= X"00"; -- x
when 16#c78# => romdata <= X"00"; -- x
when 16#079# => romdata <= X"00"; -- y
when 16#179# => romdata <= X"00"; -- y
when 16#279# => romdata <= X"00"; -- y
when 16#379# => romdata <= X"00"; -- y
when 16#479# => romdata <= X"00"; -- y
when 16#579# => romdata <= X"42"; -- y
when 16#679# => romdata <= X"42"; -- y
when 16#779# => romdata <= X"42"; -- y
when 16#879# => romdata <= X"46"; -- y
when 16#979# => romdata <= X"3a"; -- y
when 16#a79# => romdata <= X"02"; -- y
when 16#b79# => romdata <= X"42"; -- y
when 16#c79# => romdata <= X"3c"; -- y
when 16#07a# => romdata <= X"00"; -- z
when 16#17a# => romdata <= X"00"; -- z
when 16#27a# => romdata <= X"00"; -- z
when 16#37a# => romdata <= X"00"; -- z
when 16#47a# => romdata <= X"00"; -- z
when 16#57a# => romdata <= X"7e"; -- z
when 16#67a# => romdata <= X"04"; -- z
when 16#77a# => romdata <= X"08"; -- z
when 16#87a# => romdata <= X"10"; -- z
when 16#97a# => romdata <= X"20"; -- z
when 16#a7a# => romdata <= X"7e"; -- z
when 16#b7a# => romdata <= X"00"; -- z
when 16#c7a# => romdata <= X"00"; -- z
when 16#07b# => romdata <= X"00"; -- {
when 16#17b# => romdata <= X"00"; -- {
when 16#27b# => romdata <= X"0e"; -- {
when 16#37b# => romdata <= X"10"; -- {
when 16#47b# => romdata <= X"10"; -- {
when 16#57b# => romdata <= X"08"; -- {
when 16#67b# => romdata <= X"30"; -- {
when 16#77b# => romdata <= X"08"; -- {
when 16#87b# => romdata <= X"10"; -- {
when 16#97b# => romdata <= X"10"; -- {
when 16#a7b# => romdata <= X"0e"; -- {
when 16#b7b# => romdata <= X"00"; -- {
when 16#c7b# => romdata <= X"00"; -- {
when 16#07c# => romdata <= X"00"; -- |
when 16#17c# => romdata <= X"00"; -- |
when 16#27c# => romdata <= X"10"; -- |
when 16#37c# => romdata <= X"10"; -- |
when 16#47c# => romdata <= X"10"; -- |
when 16#57c# => romdata <= X"10"; -- |
when 16#67c# => romdata <= X"10"; -- |
when 16#77c# => romdata <= X"10"; -- |
when 16#87c# => romdata <= X"10"; -- |
when 16#97c# => romdata <= X"10"; -- |
when 16#a7c# => romdata <= X"10"; -- |
when 16#b7c# => romdata <= X"00"; -- |
when 16#c7c# => romdata <= X"00"; -- |
when 16#07d# => romdata <= X"00"; -- }
when 16#17d# => romdata <= X"00"; -- }
when 16#27d# => romdata <= X"70"; -- }
when 16#37d# => romdata <= X"08"; -- }
when 16#47d# => romdata <= X"08"; -- }
when 16#57d# => romdata <= X"10"; -- }
when 16#67d# => romdata <= X"0c"; -- }
when 16#77d# => romdata <= X"10"; -- }
when 16#87d# => romdata <= X"08"; -- }
when 16#97d# => romdata <= X"08"; -- }
when 16#a7d# => romdata <= X"70"; -- }
when 16#b7d# => romdata <= X"00"; -- }
when 16#c7d# => romdata <= X"00"; -- }
when 16#07e# => romdata <= X"00"; -- ~
when 16#17e# => romdata <= X"00"; -- ~
when 16#27e# => romdata <= X"24"; -- ~
when 16#37e# => romdata <= X"54"; -- ~
when 16#47e# => romdata <= X"48"; -- ~
when 16#57e# => romdata <= X"00"; -- ~
when 16#67e# => romdata <= X"00"; -- ~
when 16#77e# => romdata <= X"00"; -- ~
when 16#87e# => romdata <= X"00"; -- ~
when 16#97e# => romdata <= X"00"; -- ~
when 16#a7e# => romdata <= X"00"; -- ~
when 16#b7e# => romdata <= X"00"; -- ~
when 16#c7e# => romdata <= X"00"; -- ~
when 16#0a0# => romdata <= X"00"; --
when 16#1a0# => romdata <= X"00"; --
when 16#2a0# => romdata <= X"00"; --
when 16#3a0# => romdata <= X"00"; --
when 16#4a0# => romdata <= X"00"; --
when 16#5a0# => romdata <= X"00"; --
when 16#6a0# => romdata <= X"00"; --
when 16#7a0# => romdata <= X"00"; --
when 16#8a0# => romdata <= X"00"; --
when 16#9a0# => romdata <= X"00"; --
when 16#aa0# => romdata <= X"00"; --
when 16#ba0# => romdata <= X"00"; --
when 16#ca0# => romdata <= X"00"; --
when 16#0a1# => romdata <= X"00"; -- ¡
when 16#1a1# => romdata <= X"00"; -- ¡
when 16#2a1# => romdata <= X"10"; -- ¡
when 16#3a1# => romdata <= X"00"; -- ¡
when 16#4a1# => romdata <= X"10"; -- ¡
when 16#5a1# => romdata <= X"10"; -- ¡
when 16#6a1# => romdata <= X"10"; -- ¡
when 16#7a1# => romdata <= X"10"; -- ¡
when 16#8a1# => romdata <= X"10"; -- ¡
when 16#9a1# => romdata <= X"10"; -- ¡
when 16#aa1# => romdata <= X"10"; -- ¡
when 16#ba1# => romdata <= X"00"; -- ¡
when 16#ca1# => romdata <= X"00"; -- ¡
when 16#0a2# => romdata <= X"00"; -- ¢
when 16#1a2# => romdata <= X"00"; -- ¢
when 16#2a2# => romdata <= X"10"; -- ¢
when 16#3a2# => romdata <= X"38"; -- ¢
when 16#4a2# => romdata <= X"54"; -- ¢
when 16#5a2# => romdata <= X"50"; -- ¢
when 16#6a2# => romdata <= X"50"; -- ¢
when 16#7a2# => romdata <= X"54"; -- ¢
when 16#8a2# => romdata <= X"38"; -- ¢
when 16#9a2# => romdata <= X"10"; -- ¢
when 16#aa2# => romdata <= X"00"; -- ¢
when 16#ba2# => romdata <= X"00"; -- ¢
when 16#ca2# => romdata <= X"00"; -- ¢
when 16#0a3# => romdata <= X"00"; -- £
when 16#1a3# => romdata <= X"00"; -- £
when 16#2a3# => romdata <= X"1c"; -- £
when 16#3a3# => romdata <= X"22"; -- £
when 16#4a3# => romdata <= X"20"; -- £
when 16#5a3# => romdata <= X"70"; -- £
when 16#6a3# => romdata <= X"20"; -- £
when 16#7a3# => romdata <= X"20"; -- £
when 16#8a3# => romdata <= X"20"; -- £
when 16#9a3# => romdata <= X"62"; -- £
when 16#aa3# => romdata <= X"dc"; -- £
when 16#ba3# => romdata <= X"00"; -- £
when 16#ca3# => romdata <= X"00"; -- £
when 16#0a4# => romdata <= X"00"; -- ¤
when 16#1a4# => romdata <= X"00"; -- ¤
when 16#2a4# => romdata <= X"00"; -- ¤
when 16#3a4# => romdata <= X"00"; -- ¤
when 16#4a4# => romdata <= X"42"; -- ¤
when 16#5a4# => romdata <= X"3c"; -- ¤
when 16#6a4# => romdata <= X"24"; -- ¤
when 16#7a4# => romdata <= X"24"; -- ¤
when 16#8a4# => romdata <= X"3c"; -- ¤
when 16#9a4# => romdata <= X"42"; -- ¤
when 16#aa4# => romdata <= X"00"; -- ¤
when 16#ba4# => romdata <= X"00"; -- ¤
when 16#ca4# => romdata <= X"00"; -- ¤
when 16#0a5# => romdata <= X"00"; -- ¥
when 16#1a5# => romdata <= X"00"; -- ¥
when 16#2a5# => romdata <= X"82"; -- ¥
when 16#3a5# => romdata <= X"82"; -- ¥
when 16#4a5# => romdata <= X"44"; -- ¥
when 16#5a5# => romdata <= X"28"; -- ¥
when 16#6a5# => romdata <= X"7c"; -- ¥
when 16#7a5# => romdata <= X"10"; -- ¥
when 16#8a5# => romdata <= X"7c"; -- ¥
when 16#9a5# => romdata <= X"10"; -- ¥
when 16#aa5# => romdata <= X"10"; -- ¥
when 16#ba5# => romdata <= X"00"; -- ¥
when 16#ca5# => romdata <= X"00"; -- ¥
when 16#0a6# => romdata <= X"00"; -- ¦
when 16#1a6# => romdata <= X"00"; -- ¦
when 16#2a6# => romdata <= X"10"; -- ¦
when 16#3a6# => romdata <= X"10"; -- ¦
when 16#4a6# => romdata <= X"10"; -- ¦
when 16#5a6# => romdata <= X"10"; -- ¦
when 16#6a6# => romdata <= X"00"; -- ¦
when 16#7a6# => romdata <= X"10"; -- ¦
when 16#8a6# => romdata <= X"10"; -- ¦
when 16#9a6# => romdata <= X"10"; -- ¦
when 16#aa6# => romdata <= X"10"; -- ¦
when 16#ba6# => romdata <= X"00"; -- ¦
when 16#ca6# => romdata <= X"00"; -- ¦
when 16#0a7# => romdata <= X"00"; -- §
when 16#1a7# => romdata <= X"18"; -- §
when 16#2a7# => romdata <= X"24"; -- §
when 16#3a7# => romdata <= X"20"; -- §
when 16#4a7# => romdata <= X"18"; -- §
when 16#5a7# => romdata <= X"24"; -- §
when 16#6a7# => romdata <= X"24"; -- §
when 16#7a7# => romdata <= X"18"; -- §
when 16#8a7# => romdata <= X"04"; -- §
when 16#9a7# => romdata <= X"24"; -- §
when 16#aa7# => romdata <= X"18"; -- §
when 16#ba7# => romdata <= X"00"; -- §
when 16#ca7# => romdata <= X"00"; -- §
when 16#0a8# => romdata <= X"00"; -- ¨
when 16#1a8# => romdata <= X"24"; -- ¨
when 16#2a8# => romdata <= X"24"; -- ¨
when 16#3a8# => romdata <= X"00"; -- ¨
when 16#4a8# => romdata <= X"00"; -- ¨
when 16#5a8# => romdata <= X"00"; -- ¨
when 16#6a8# => romdata <= X"00"; -- ¨
when 16#7a8# => romdata <= X"00"; -- ¨
when 16#8a8# => romdata <= X"00"; -- ¨
when 16#9a8# => romdata <= X"00"; -- ¨
when 16#aa8# => romdata <= X"00"; -- ¨
when 16#ba8# => romdata <= X"00"; -- ¨
when 16#ca8# => romdata <= X"00"; -- ¨
when 16#0a9# => romdata <= X"00"; -- ©
when 16#1a9# => romdata <= X"38"; -- ©
when 16#2a9# => romdata <= X"44"; -- ©
when 16#3a9# => romdata <= X"92"; -- ©
when 16#4a9# => romdata <= X"aa"; -- ©
when 16#5a9# => romdata <= X"a2"; -- ©
when 16#6a9# => romdata <= X"aa"; -- ©
when 16#7a9# => romdata <= X"92"; -- ©
when 16#8a9# => romdata <= X"44"; -- ©
when 16#9a9# => romdata <= X"38"; -- ©
when 16#aa9# => romdata <= X"00"; -- ©
when 16#ba9# => romdata <= X"00"; -- ©
when 16#ca9# => romdata <= X"00"; -- ©
when 16#0aa# => romdata <= X"00"; -- ª
when 16#1aa# => romdata <= X"00"; -- ª
when 16#2aa# => romdata <= X"38"; -- ª
when 16#3aa# => romdata <= X"04"; -- ª
when 16#4aa# => romdata <= X"3c"; -- ª
when 16#5aa# => romdata <= X"44"; -- ª
when 16#6aa# => romdata <= X"3c"; -- ª
when 16#7aa# => romdata <= X"00"; -- ª
when 16#8aa# => romdata <= X"7c"; -- ª
when 16#9aa# => romdata <= X"00"; -- ª
when 16#aaa# => romdata <= X"00"; -- ª
when 16#baa# => romdata <= X"00"; -- ª
when 16#caa# => romdata <= X"00"; -- ª
when 16#0ab# => romdata <= X"00"; -- «
when 16#1ab# => romdata <= X"00"; -- «
when 16#2ab# => romdata <= X"00"; -- «
when 16#3ab# => romdata <= X"12"; -- «
when 16#4ab# => romdata <= X"24"; -- «
when 16#5ab# => romdata <= X"48"; -- «
when 16#6ab# => romdata <= X"90"; -- «
when 16#7ab# => romdata <= X"48"; -- «
when 16#8ab# => romdata <= X"24"; -- «
when 16#9ab# => romdata <= X"12"; -- «
when 16#aab# => romdata <= X"00"; -- «
when 16#bab# => romdata <= X"00"; -- «
when 16#cab# => romdata <= X"00"; -- «
when 16#0ac# => romdata <= X"00"; -- ¬
when 16#1ac# => romdata <= X"00"; -- ¬
when 16#2ac# => romdata <= X"00"; -- ¬
when 16#3ac# => romdata <= X"00"; -- ¬
when 16#4ac# => romdata <= X"00"; -- ¬
when 16#5ac# => romdata <= X"00"; -- ¬
when 16#6ac# => romdata <= X"7e"; -- ¬
when 16#7ac# => romdata <= X"02"; -- ¬
when 16#8ac# => romdata <= X"02"; -- ¬
when 16#9ac# => romdata <= X"02"; -- ¬
when 16#aac# => romdata <= X"00"; -- ¬
when 16#bac# => romdata <= X"00"; -- ¬
when 16#cac# => romdata <= X"00"; -- ¬
when 16#0ad# => romdata <= X"00"; --
when 16#1ad# => romdata <= X"00"; --
when 16#2ad# => romdata <= X"00"; --
when 16#3ad# => romdata <= X"00"; --
when 16#4ad# => romdata <= X"00"; --
when 16#5ad# => romdata <= X"00"; --
when 16#6ad# => romdata <= X"3c"; --
when 16#7ad# => romdata <= X"00"; --
when 16#8ad# => romdata <= X"00"; --
when 16#9ad# => romdata <= X"00"; --
when 16#aad# => romdata <= X"00"; --
when 16#bad# => romdata <= X"00"; --
when 16#cad# => romdata <= X"00"; --
when 16#0ae# => romdata <= X"00"; -- ®
when 16#1ae# => romdata <= X"38"; -- ®
when 16#2ae# => romdata <= X"44"; -- ®
when 16#3ae# => romdata <= X"92"; -- ®
when 16#4ae# => romdata <= X"aa"; -- ®
when 16#5ae# => romdata <= X"aa"; -- ®
when 16#6ae# => romdata <= X"b2"; -- ®
when 16#7ae# => romdata <= X"aa"; -- ®
when 16#8ae# => romdata <= X"44"; -- ®
when 16#9ae# => romdata <= X"38"; -- ®
when 16#aae# => romdata <= X"00"; -- ®
when 16#bae# => romdata <= X"00"; -- ®
when 16#cae# => romdata <= X"00"; -- ®
when 16#0af# => romdata <= X"00"; -- ¯
when 16#1af# => romdata <= X"00"; -- ¯
when 16#2af# => romdata <= X"7e"; -- ¯
when 16#3af# => romdata <= X"00"; -- ¯
when 16#4af# => romdata <= X"00"; -- ¯
when 16#5af# => romdata <= X"00"; -- ¯
when 16#6af# => romdata <= X"00"; -- ¯
when 16#7af# => romdata <= X"00"; -- ¯
when 16#8af# => romdata <= X"00"; -- ¯
when 16#9af# => romdata <= X"00"; -- ¯
when 16#aaf# => romdata <= X"00"; -- ¯
when 16#baf# => romdata <= X"00"; -- ¯
when 16#caf# => romdata <= X"00"; -- ¯
when 16#0b0# => romdata <= X"00"; -- °
when 16#1b0# => romdata <= X"00"; -- °
when 16#2b0# => romdata <= X"18"; -- °
when 16#3b0# => romdata <= X"24"; -- °
when 16#4b0# => romdata <= X"24"; -- °
when 16#5b0# => romdata <= X"18"; -- °
when 16#6b0# => romdata <= X"00"; -- °
when 16#7b0# => romdata <= X"00"; -- °
when 16#8b0# => romdata <= X"00"; -- °
when 16#9b0# => romdata <= X"00"; -- °
when 16#ab0# => romdata <= X"00"; -- °
when 16#bb0# => romdata <= X"00"; -- °
when 16#cb0# => romdata <= X"00"; -- °
when 16#0b1# => romdata <= X"00"; -- ±
when 16#1b1# => romdata <= X"00"; -- ±
when 16#2b1# => romdata <= X"00"; -- ±
when 16#3b1# => romdata <= X"10"; -- ±
when 16#4b1# => romdata <= X"10"; -- ±
when 16#5b1# => romdata <= X"7c"; -- ±
when 16#6b1# => romdata <= X"10"; -- ±
when 16#7b1# => romdata <= X"10"; -- ±
when 16#8b1# => romdata <= X"00"; -- ±
when 16#9b1# => romdata <= X"7c"; -- ±
when 16#ab1# => romdata <= X"00"; -- ±
when 16#bb1# => romdata <= X"00"; -- ±
when 16#cb1# => romdata <= X"00"; -- ±
when 16#0b2# => romdata <= X"00"; -- ²
when 16#1b2# => romdata <= X"30"; -- ²
when 16#2b2# => romdata <= X"48"; -- ²
when 16#3b2# => romdata <= X"08"; -- ²
when 16#4b2# => romdata <= X"30"; -- ²
when 16#5b2# => romdata <= X"40"; -- ²
when 16#6b2# => romdata <= X"78"; -- ²
when 16#7b2# => romdata <= X"00"; -- ²
when 16#8b2# => romdata <= X"00"; -- ²
when 16#9b2# => romdata <= X"00"; -- ²
when 16#ab2# => romdata <= X"00"; -- ²
when 16#bb2# => romdata <= X"00"; -- ²
when 16#cb2# => romdata <= X"00"; -- ²
when 16#0b3# => romdata <= X"00"; -- ³
when 16#1b3# => romdata <= X"30"; -- ³
when 16#2b3# => romdata <= X"48"; -- ³
when 16#3b3# => romdata <= X"10"; -- ³
when 16#4b3# => romdata <= X"08"; -- ³
when 16#5b3# => romdata <= X"48"; -- ³
when 16#6b3# => romdata <= X"30"; -- ³
when 16#7b3# => romdata <= X"00"; -- ³
when 16#8b3# => romdata <= X"00"; -- ³
when 16#9b3# => romdata <= X"00"; -- ³
when 16#ab3# => romdata <= X"00"; -- ³
when 16#bb3# => romdata <= X"00"; -- ³
when 16#cb3# => romdata <= X"00"; -- ³
when 16#0b4# => romdata <= X"00"; -- ´
when 16#1b4# => romdata <= X"08"; -- ´
when 16#2b4# => romdata <= X"10"; -- ´
when 16#3b4# => romdata <= X"00"; -- ´
when 16#4b4# => romdata <= X"00"; -- ´
when 16#5b4# => romdata <= X"00"; -- ´
when 16#6b4# => romdata <= X"00"; -- ´
when 16#7b4# => romdata <= X"00"; -- ´
when 16#8b4# => romdata <= X"00"; -- ´
when 16#9b4# => romdata <= X"00"; -- ´
when 16#ab4# => romdata <= X"00"; -- ´
when 16#bb4# => romdata <= X"00"; -- ´
when 16#cb4# => romdata <= X"00"; -- ´
when 16#0b5# => romdata <= X"00"; -- µ
when 16#1b5# => romdata <= X"00"; -- µ
when 16#2b5# => romdata <= X"00"; -- µ
when 16#3b5# => romdata <= X"00"; -- µ
when 16#4b5# => romdata <= X"00"; -- µ
when 16#5b5# => romdata <= X"42"; -- µ
when 16#6b5# => romdata <= X"42"; -- µ
when 16#7b5# => romdata <= X"42"; -- µ
when 16#8b5# => romdata <= X"42"; -- µ
when 16#9b5# => romdata <= X"66"; -- µ
when 16#ab5# => romdata <= X"5a"; -- µ
when 16#bb5# => romdata <= X"40"; -- µ
when 16#cb5# => romdata <= X"00"; -- µ
when 16#0b6# => romdata <= X"00"; -- ¶
when 16#1b6# => romdata <= X"00"; -- ¶
when 16#2b6# => romdata <= X"3e"; -- ¶
when 16#3b6# => romdata <= X"74"; -- ¶
when 16#4b6# => romdata <= X"74"; -- ¶
when 16#5b6# => romdata <= X"74"; -- ¶
when 16#6b6# => romdata <= X"34"; -- ¶
when 16#7b6# => romdata <= X"14"; -- ¶
when 16#8b6# => romdata <= X"14"; -- ¶
when 16#9b6# => romdata <= X"14"; -- ¶
when 16#ab6# => romdata <= X"14"; -- ¶
when 16#bb6# => romdata <= X"00"; -- ¶
when 16#cb6# => romdata <= X"00"; -- ¶
when 16#0b7# => romdata <= X"00"; -- ·
when 16#1b7# => romdata <= X"00"; -- ·
when 16#2b7# => romdata <= X"00"; -- ·
when 16#3b7# => romdata <= X"00"; -- ·
when 16#4b7# => romdata <= X"00"; -- ·
when 16#5b7# => romdata <= X"00"; -- ·
when 16#6b7# => romdata <= X"18"; -- ·
when 16#7b7# => romdata <= X"00"; -- ·
when 16#8b7# => romdata <= X"00"; -- ·
when 16#9b7# => romdata <= X"00"; -- ·
when 16#ab7# => romdata <= X"00"; -- ·
when 16#bb7# => romdata <= X"00"; -- ·
when 16#cb7# => romdata <= X"00"; -- ·
when 16#0b8# => romdata <= X"00"; -- ¸
when 16#1b8# => romdata <= X"00"; -- ¸
when 16#2b8# => romdata <= X"00"; -- ¸
when 16#3b8# => romdata <= X"00"; -- ¸
when 16#4b8# => romdata <= X"00"; -- ¸
when 16#5b8# => romdata <= X"00"; -- ¸
when 16#6b8# => romdata <= X"00"; -- ¸
when 16#7b8# => romdata <= X"00"; -- ¸
when 16#8b8# => romdata <= X"00"; -- ¸
when 16#9b8# => romdata <= X"00"; -- ¸
when 16#ab8# => romdata <= X"00"; -- ¸
when 16#bb8# => romdata <= X"08"; -- ¸
when 16#cb8# => romdata <= X"18"; -- ¸
when 16#0b9# => romdata <= X"00"; -- ¹
when 16#1b9# => romdata <= X"20"; -- ¹
when 16#2b9# => romdata <= X"60"; -- ¹
when 16#3b9# => romdata <= X"20"; -- ¹
when 16#4b9# => romdata <= X"20"; -- ¹
when 16#5b9# => romdata <= X"20"; -- ¹
when 16#6b9# => romdata <= X"70"; -- ¹
when 16#7b9# => romdata <= X"00"; -- ¹
when 16#8b9# => romdata <= X"00"; -- ¹
when 16#9b9# => romdata <= X"00"; -- ¹
when 16#ab9# => romdata <= X"00"; -- ¹
when 16#bb9# => romdata <= X"00"; -- ¹
when 16#cb9# => romdata <= X"00"; -- ¹
when 16#0ba# => romdata <= X"00"; -- º
when 16#1ba# => romdata <= X"00"; -- º
when 16#2ba# => romdata <= X"30"; -- º
when 16#3ba# => romdata <= X"48"; -- º
when 16#4ba# => romdata <= X"48"; -- º
when 16#5ba# => romdata <= X"30"; -- º
when 16#6ba# => romdata <= X"00"; -- º
when 16#7ba# => romdata <= X"78"; -- º
when 16#8ba# => romdata <= X"00"; -- º
when 16#9ba# => romdata <= X"00"; -- º
when 16#aba# => romdata <= X"00"; -- º
when 16#bba# => romdata <= X"00"; -- º
when 16#cba# => romdata <= X"00"; -- º
when 16#0bb# => romdata <= X"00"; -- »
when 16#1bb# => romdata <= X"00"; -- »
when 16#2bb# => romdata <= X"00"; -- »
when 16#3bb# => romdata <= X"90"; -- »
when 16#4bb# => romdata <= X"48"; -- »
when 16#5bb# => romdata <= X"24"; -- »
when 16#6bb# => romdata <= X"12"; -- »
when 16#7bb# => romdata <= X"24"; -- »
when 16#8bb# => romdata <= X"48"; -- »
when 16#9bb# => romdata <= X"90"; -- »
when 16#abb# => romdata <= X"00"; -- »
when 16#bbb# => romdata <= X"00"; -- »
when 16#cbb# => romdata <= X"00"; -- »
when 16#0bc# => romdata <= X"00"; -- ¼
when 16#1bc# => romdata <= X"40"; -- ¼
when 16#2bc# => romdata <= X"c0"; -- ¼
when 16#3bc# => romdata <= X"40"; -- ¼
when 16#4bc# => romdata <= X"40"; -- ¼
when 16#5bc# => romdata <= X"42"; -- ¼
when 16#6bc# => romdata <= X"e6"; -- ¼
when 16#7bc# => romdata <= X"0a"; -- ¼
when 16#8bc# => romdata <= X"12"; -- ¼
when 16#9bc# => romdata <= X"1a"; -- ¼
when 16#abc# => romdata <= X"06"; -- ¼
when 16#bbc# => romdata <= X"00"; -- ¼
when 16#cbc# => romdata <= X"00"; -- ¼
when 16#0bd# => romdata <= X"00"; -- ½
when 16#1bd# => romdata <= X"40"; -- ½
when 16#2bd# => romdata <= X"c0"; -- ½
when 16#3bd# => romdata <= X"40"; -- ½
when 16#4bd# => romdata <= X"40"; -- ½
when 16#5bd# => romdata <= X"4c"; -- ½
when 16#6bd# => romdata <= X"f2"; -- ½
when 16#7bd# => romdata <= X"02"; -- ½
when 16#8bd# => romdata <= X"0c"; -- ½
when 16#9bd# => romdata <= X"10"; -- ½
when 16#abd# => romdata <= X"1e"; -- ½
when 16#bbd# => romdata <= X"00"; -- ½
when 16#cbd# => romdata <= X"00"; -- ½
when 16#0be# => romdata <= X"00"; -- ¾
when 16#1be# => romdata <= X"60"; -- ¾
when 16#2be# => romdata <= X"90"; -- ¾
when 16#3be# => romdata <= X"20"; -- ¾
when 16#4be# => romdata <= X"10"; -- ¾
when 16#5be# => romdata <= X"92"; -- ¾
when 16#6be# => romdata <= X"66"; -- ¾
when 16#7be# => romdata <= X"0a"; -- ¾
when 16#8be# => romdata <= X"12"; -- ¾
when 16#9be# => romdata <= X"1a"; -- ¾
when 16#abe# => romdata <= X"06"; -- ¾
when 16#bbe# => romdata <= X"00"; -- ¾
when 16#cbe# => romdata <= X"00"; -- ¾
when 16#0bf# => romdata <= X"00"; -- ¿
when 16#1bf# => romdata <= X"00"; -- ¿
when 16#2bf# => romdata <= X"10"; -- ¿
when 16#3bf# => romdata <= X"00"; -- ¿
when 16#4bf# => romdata <= X"10"; -- ¿
when 16#5bf# => romdata <= X"10"; -- ¿
when 16#6bf# => romdata <= X"20"; -- ¿
when 16#7bf# => romdata <= X"40"; -- ¿
when 16#8bf# => romdata <= X"42"; -- ¿
when 16#9bf# => romdata <= X"42"; -- ¿
when 16#abf# => romdata <= X"3c"; -- ¿
when 16#bbf# => romdata <= X"00"; -- ¿
when 16#cbf# => romdata <= X"00"; -- ¿
when 16#0c0# => romdata <= X"00"; -- À
when 16#1c0# => romdata <= X"10"; -- À
when 16#2c0# => romdata <= X"08"; -- À
when 16#3c0# => romdata <= X"00"; -- À
when 16#4c0# => romdata <= X"18"; -- À
when 16#5c0# => romdata <= X"24"; -- À
when 16#6c0# => romdata <= X"42"; -- À
when 16#7c0# => romdata <= X"42"; -- À
when 16#8c0# => romdata <= X"7e"; -- À
when 16#9c0# => romdata <= X"42"; -- À
when 16#ac0# => romdata <= X"42"; -- À
when 16#bc0# => romdata <= X"00"; -- À
when 16#cc0# => romdata <= X"00"; -- À
when 16#0c1# => romdata <= X"00"; -- Á
when 16#1c1# => romdata <= X"08"; -- Á
when 16#2c1# => romdata <= X"10"; -- Á
when 16#3c1# => romdata <= X"00"; -- Á
when 16#4c1# => romdata <= X"18"; -- Á
when 16#5c1# => romdata <= X"24"; -- Á
when 16#6c1# => romdata <= X"42"; -- Á
when 16#7c1# => romdata <= X"42"; -- Á
when 16#8c1# => romdata <= X"7e"; -- Á
when 16#9c1# => romdata <= X"42"; -- Á
when 16#ac1# => romdata <= X"42"; -- Á
when 16#bc1# => romdata <= X"00"; -- Á
when 16#cc1# => romdata <= X"00"; -- Á
when 16#0c2# => romdata <= X"00"; -- Â
when 16#1c2# => romdata <= X"18"; -- Â
when 16#2c2# => romdata <= X"24"; -- Â
when 16#3c2# => romdata <= X"00"; -- Â
when 16#4c2# => romdata <= X"18"; -- Â
when 16#5c2# => romdata <= X"24"; -- Â
when 16#6c2# => romdata <= X"42"; -- Â
when 16#7c2# => romdata <= X"42"; -- Â
when 16#8c2# => romdata <= X"7e"; -- Â
when 16#9c2# => romdata <= X"42"; -- Â
when 16#ac2# => romdata <= X"42"; -- Â
when 16#bc2# => romdata <= X"00"; -- Â
when 16#cc2# => romdata <= X"00"; -- Â
when 16#0c3# => romdata <= X"00"; -- Ã
when 16#1c3# => romdata <= X"32"; -- Ã
when 16#2c3# => romdata <= X"4c"; -- Ã
when 16#3c3# => romdata <= X"00"; -- Ã
when 16#4c3# => romdata <= X"18"; -- Ã
when 16#5c3# => romdata <= X"24"; -- Ã
when 16#6c3# => romdata <= X"42"; -- Ã
when 16#7c3# => romdata <= X"42"; -- Ã
when 16#8c3# => romdata <= X"7e"; -- Ã
when 16#9c3# => romdata <= X"42"; -- Ã
when 16#ac3# => romdata <= X"42"; -- Ã
when 16#bc3# => romdata <= X"00"; -- Ã
when 16#cc3# => romdata <= X"00"; -- Ã
when 16#0c4# => romdata <= X"00"; -- Ä
when 16#1c4# => romdata <= X"24"; -- Ä
when 16#2c4# => romdata <= X"24"; -- Ä
when 16#3c4# => romdata <= X"00"; -- Ä
when 16#4c4# => romdata <= X"18"; -- Ä
when 16#5c4# => romdata <= X"24"; -- Ä
when 16#6c4# => romdata <= X"42"; -- Ä
when 16#7c4# => romdata <= X"42"; -- Ä
when 16#8c4# => romdata <= X"7e"; -- Ä
when 16#9c4# => romdata <= X"42"; -- Ä
when 16#ac4# => romdata <= X"42"; -- Ä
when 16#bc4# => romdata <= X"00"; -- Ä
when 16#cc4# => romdata <= X"00"; -- Ä
when 16#0c5# => romdata <= X"00"; -- Å
when 16#1c5# => romdata <= X"18"; -- Å
when 16#2c5# => romdata <= X"24"; -- Å
when 16#3c5# => romdata <= X"18"; -- Å
when 16#4c5# => romdata <= X"18"; -- Å
when 16#5c5# => romdata <= X"24"; -- Å
when 16#6c5# => romdata <= X"42"; -- Å
when 16#7c5# => romdata <= X"42"; -- Å
when 16#8c5# => romdata <= X"7e"; -- Å
when 16#9c5# => romdata <= X"42"; -- Å
when 16#ac5# => romdata <= X"42"; -- Å
when 16#bc5# => romdata <= X"00"; -- Å
when 16#cc5# => romdata <= X"00"; -- Å
when 16#0c6# => romdata <= X"00"; -- Æ
when 16#1c6# => romdata <= X"00"; -- Æ
when 16#2c6# => romdata <= X"6e"; -- Æ
when 16#3c6# => romdata <= X"90"; -- Æ
when 16#4c6# => romdata <= X"90"; -- Æ
when 16#5c6# => romdata <= X"90"; -- Æ
when 16#6c6# => romdata <= X"9c"; -- Æ
when 16#7c6# => romdata <= X"f0"; -- Æ
when 16#8c6# => romdata <= X"90"; -- Æ
when 16#9c6# => romdata <= X"90"; -- Æ
when 16#ac6# => romdata <= X"9e"; -- Æ
when 16#bc6# => romdata <= X"00"; -- Æ
when 16#cc6# => romdata <= X"00"; -- Æ
when 16#0c7# => romdata <= X"00"; -- Ç
when 16#1c7# => romdata <= X"00"; -- Ç
when 16#2c7# => romdata <= X"3c"; -- Ç
when 16#3c7# => romdata <= X"42"; -- Ç
when 16#4c7# => romdata <= X"40"; -- Ç
when 16#5c7# => romdata <= X"40"; -- Ç
when 16#6c7# => romdata <= X"40"; -- Ç
when 16#7c7# => romdata <= X"40"; -- Ç
when 16#8c7# => romdata <= X"40"; -- Ç
when 16#9c7# => romdata <= X"42"; -- Ç
when 16#ac7# => romdata <= X"3c"; -- Ç
when 16#bc7# => romdata <= X"08"; -- Ç
when 16#cc7# => romdata <= X"10"; -- Ç
when 16#0c8# => romdata <= X"00"; -- È
when 16#1c8# => romdata <= X"10"; -- È
when 16#2c8# => romdata <= X"08"; -- È
when 16#3c8# => romdata <= X"00"; -- È
when 16#4c8# => romdata <= X"7e"; -- È
when 16#5c8# => romdata <= X"40"; -- È
when 16#6c8# => romdata <= X"40"; -- È
when 16#7c8# => romdata <= X"78"; -- È
when 16#8c8# => romdata <= X"40"; -- È
when 16#9c8# => romdata <= X"40"; -- È
when 16#ac8# => romdata <= X"7e"; -- È
when 16#bc8# => romdata <= X"00"; -- È
when 16#cc8# => romdata <= X"00"; -- È
when 16#0c9# => romdata <= X"00"; -- É
when 16#1c9# => romdata <= X"08"; -- É
when 16#2c9# => romdata <= X"10"; -- É
when 16#3c9# => romdata <= X"00"; -- É
when 16#4c9# => romdata <= X"7e"; -- É
when 16#5c9# => romdata <= X"40"; -- É
when 16#6c9# => romdata <= X"40"; -- É
when 16#7c9# => romdata <= X"78"; -- É
when 16#8c9# => romdata <= X"40"; -- É
when 16#9c9# => romdata <= X"40"; -- É
when 16#ac9# => romdata <= X"7e"; -- É
when 16#bc9# => romdata <= X"00"; -- É
when 16#cc9# => romdata <= X"00"; -- É
when 16#0ca# => romdata <= X"00"; -- Ê
when 16#1ca# => romdata <= X"18"; -- Ê
when 16#2ca# => romdata <= X"24"; -- Ê
when 16#3ca# => romdata <= X"00"; -- Ê
when 16#4ca# => romdata <= X"7e"; -- Ê
when 16#5ca# => romdata <= X"40"; -- Ê
when 16#6ca# => romdata <= X"40"; -- Ê
when 16#7ca# => romdata <= X"78"; -- Ê
when 16#8ca# => romdata <= X"40"; -- Ê
when 16#9ca# => romdata <= X"40"; -- Ê
when 16#aca# => romdata <= X"7e"; -- Ê
when 16#bca# => romdata <= X"00"; -- Ê
when 16#cca# => romdata <= X"00"; -- Ê
when 16#0cb# => romdata <= X"00"; -- Ë
when 16#1cb# => romdata <= X"24"; -- Ë
when 16#2cb# => romdata <= X"24"; -- Ë
when 16#3cb# => romdata <= X"00"; -- Ë
when 16#4cb# => romdata <= X"7e"; -- Ë
when 16#5cb# => romdata <= X"40"; -- Ë
when 16#6cb# => romdata <= X"40"; -- Ë
when 16#7cb# => romdata <= X"78"; -- Ë
when 16#8cb# => romdata <= X"40"; -- Ë
when 16#9cb# => romdata <= X"40"; -- Ë
when 16#acb# => romdata <= X"7e"; -- Ë
when 16#bcb# => romdata <= X"00"; -- Ë
when 16#ccb# => romdata <= X"00"; -- Ë
when 16#0cc# => romdata <= X"00"; -- Ì
when 16#1cc# => romdata <= X"20"; -- Ì
when 16#2cc# => romdata <= X"10"; -- Ì
when 16#3cc# => romdata <= X"00"; -- Ì
when 16#4cc# => romdata <= X"7c"; -- Ì
when 16#5cc# => romdata <= X"10"; -- Ì
when 16#6cc# => romdata <= X"10"; -- Ì
when 16#7cc# => romdata <= X"10"; -- Ì
when 16#8cc# => romdata <= X"10"; -- Ì
when 16#9cc# => romdata <= X"10"; -- Ì
when 16#acc# => romdata <= X"7c"; -- Ì
when 16#bcc# => romdata <= X"00"; -- Ì
when 16#ccc# => romdata <= X"00"; -- Ì
when 16#0cd# => romdata <= X"00"; -- Í
when 16#1cd# => romdata <= X"08"; -- Í
when 16#2cd# => romdata <= X"10"; -- Í
when 16#3cd# => romdata <= X"00"; -- Í
when 16#4cd# => romdata <= X"7c"; -- Í
when 16#5cd# => romdata <= X"10"; -- Í
when 16#6cd# => romdata <= X"10"; -- Í
when 16#7cd# => romdata <= X"10"; -- Í
when 16#8cd# => romdata <= X"10"; -- Í
when 16#9cd# => romdata <= X"10"; -- Í
when 16#acd# => romdata <= X"7c"; -- Í
when 16#bcd# => romdata <= X"00"; -- Í
when 16#ccd# => romdata <= X"00"; -- Í
when 16#0ce# => romdata <= X"00"; -- Î
when 16#1ce# => romdata <= X"18"; -- Î
when 16#2ce# => romdata <= X"24"; -- Î
when 16#3ce# => romdata <= X"00"; -- Î
when 16#4ce# => romdata <= X"7c"; -- Î
when 16#5ce# => romdata <= X"10"; -- Î
when 16#6ce# => romdata <= X"10"; -- Î
when 16#7ce# => romdata <= X"10"; -- Î
when 16#8ce# => romdata <= X"10"; -- Î
when 16#9ce# => romdata <= X"10"; -- Î
when 16#ace# => romdata <= X"7c"; -- Î
when 16#bce# => romdata <= X"00"; -- Î
when 16#cce# => romdata <= X"00"; -- Î
when 16#0cf# => romdata <= X"00"; -- Ï
when 16#1cf# => romdata <= X"44"; -- Ï
when 16#2cf# => romdata <= X"44"; -- Ï
when 16#3cf# => romdata <= X"00"; -- Ï
when 16#4cf# => romdata <= X"7c"; -- Ï
when 16#5cf# => romdata <= X"10"; -- Ï
when 16#6cf# => romdata <= X"10"; -- Ï
when 16#7cf# => romdata <= X"10"; -- Ï
when 16#8cf# => romdata <= X"10"; -- Ï
when 16#9cf# => romdata <= X"10"; -- Ï
when 16#acf# => romdata <= X"7c"; -- Ï
when 16#bcf# => romdata <= X"00"; -- Ï
when 16#ccf# => romdata <= X"00"; -- Ï
when 16#0d0# => romdata <= X"00"; -- Ð
when 16#1d0# => romdata <= X"00"; -- Ð
when 16#2d0# => romdata <= X"78"; -- Ð
when 16#3d0# => romdata <= X"44"; -- Ð
when 16#4d0# => romdata <= X"42"; -- Ð
when 16#5d0# => romdata <= X"42"; -- Ð
when 16#6d0# => romdata <= X"e2"; -- Ð
when 16#7d0# => romdata <= X"42"; -- Ð
when 16#8d0# => romdata <= X"42"; -- Ð
when 16#9d0# => romdata <= X"44"; -- Ð
when 16#ad0# => romdata <= X"78"; -- Ð
when 16#bd0# => romdata <= X"00"; -- Ð
when 16#cd0# => romdata <= X"00"; -- Ð
when 16#0d1# => romdata <= X"00"; -- Ñ
when 16#1d1# => romdata <= X"64"; -- Ñ
when 16#2d1# => romdata <= X"98"; -- Ñ
when 16#3d1# => romdata <= X"00"; -- Ñ
when 16#4d1# => romdata <= X"82"; -- Ñ
when 16#5d1# => romdata <= X"c2"; -- Ñ
when 16#6d1# => romdata <= X"a2"; -- Ñ
when 16#7d1# => romdata <= X"92"; -- Ñ
when 16#8d1# => romdata <= X"8a"; -- Ñ
when 16#9d1# => romdata <= X"86"; -- Ñ
when 16#ad1# => romdata <= X"82"; -- Ñ
when 16#bd1# => romdata <= X"00"; -- Ñ
when 16#cd1# => romdata <= X"00"; -- Ñ
when 16#0d2# => romdata <= X"00"; -- Ò
when 16#1d2# => romdata <= X"20"; -- Ò
when 16#2d2# => romdata <= X"10"; -- Ò
when 16#3d2# => romdata <= X"00"; -- Ò
when 16#4d2# => romdata <= X"7c"; -- Ò
when 16#5d2# => romdata <= X"82"; -- Ò
when 16#6d2# => romdata <= X"82"; -- Ò
when 16#7d2# => romdata <= X"82"; -- Ò
when 16#8d2# => romdata <= X"82"; -- Ò
when 16#9d2# => romdata <= X"82"; -- Ò
when 16#ad2# => romdata <= X"7c"; -- Ò
when 16#bd2# => romdata <= X"00"; -- Ò
when 16#cd2# => romdata <= X"00"; -- Ò
when 16#0d3# => romdata <= X"00"; -- Ó
when 16#1d3# => romdata <= X"08"; -- Ó
when 16#2d3# => romdata <= X"10"; -- Ó
when 16#3d3# => romdata <= X"00"; -- Ó
when 16#4d3# => romdata <= X"7c"; -- Ó
when 16#5d3# => romdata <= X"82"; -- Ó
when 16#6d3# => romdata <= X"82"; -- Ó
when 16#7d3# => romdata <= X"82"; -- Ó
when 16#8d3# => romdata <= X"82"; -- Ó
when 16#9d3# => romdata <= X"82"; -- Ó
when 16#ad3# => romdata <= X"7c"; -- Ó
when 16#bd3# => romdata <= X"00"; -- Ó
when 16#cd3# => romdata <= X"00"; -- Ó
when 16#0d4# => romdata <= X"00"; -- Ô
when 16#1d4# => romdata <= X"18"; -- Ô
when 16#2d4# => romdata <= X"24"; -- Ô
when 16#3d4# => romdata <= X"00"; -- Ô
when 16#4d4# => romdata <= X"7c"; -- Ô
when 16#5d4# => romdata <= X"82"; -- Ô
when 16#6d4# => romdata <= X"82"; -- Ô
when 16#7d4# => romdata <= X"82"; -- Ô
when 16#8d4# => romdata <= X"82"; -- Ô
when 16#9d4# => romdata <= X"82"; -- Ô
when 16#ad4# => romdata <= X"7c"; -- Ô
when 16#bd4# => romdata <= X"00"; -- Ô
when 16#cd4# => romdata <= X"00"; -- Ô
when 16#0d5# => romdata <= X"00"; -- Õ
when 16#1d5# => romdata <= X"64"; -- Õ
when 16#2d5# => romdata <= X"98"; -- Õ
when 16#3d5# => romdata <= X"00"; -- Õ
when 16#4d5# => romdata <= X"7c"; -- Õ
when 16#5d5# => romdata <= X"82"; -- Õ
when 16#6d5# => romdata <= X"82"; -- Õ
when 16#7d5# => romdata <= X"82"; -- Õ
when 16#8d5# => romdata <= X"82"; -- Õ
when 16#9d5# => romdata <= X"82"; -- Õ
when 16#ad5# => romdata <= X"7c"; -- Õ
when 16#bd5# => romdata <= X"00"; -- Õ
when 16#cd5# => romdata <= X"00"; -- Õ
when 16#0d6# => romdata <= X"00"; -- Ö
when 16#1d6# => romdata <= X"44"; -- Ö
when 16#2d6# => romdata <= X"44"; -- Ö
when 16#3d6# => romdata <= X"00"; -- Ö
when 16#4d6# => romdata <= X"7c"; -- Ö
when 16#5d6# => romdata <= X"82"; -- Ö
when 16#6d6# => romdata <= X"82"; -- Ö
when 16#7d6# => romdata <= X"82"; -- Ö
when 16#8d6# => romdata <= X"82"; -- Ö
when 16#9d6# => romdata <= X"82"; -- Ö
when 16#ad6# => romdata <= X"7c"; -- Ö
when 16#bd6# => romdata <= X"00"; -- Ö
when 16#cd6# => romdata <= X"00"; -- Ö
when 16#0d7# => romdata <= X"00"; -- ×
when 16#1d7# => romdata <= X"00"; -- ×
when 16#2d7# => romdata <= X"00"; -- ×
when 16#3d7# => romdata <= X"00"; -- ×
when 16#4d7# => romdata <= X"42"; -- ×
when 16#5d7# => romdata <= X"24"; -- ×
when 16#6d7# => romdata <= X"18"; -- ×
when 16#7d7# => romdata <= X"18"; -- ×
when 16#8d7# => romdata <= X"24"; -- ×
when 16#9d7# => romdata <= X"42"; -- ×
when 16#ad7# => romdata <= X"00"; -- ×
when 16#bd7# => romdata <= X"00"; -- ×
when 16#cd7# => romdata <= X"00"; -- ×
when 16#0d8# => romdata <= X"00"; -- Ø
when 16#1d8# => romdata <= X"02"; -- Ø
when 16#2d8# => romdata <= X"3c"; -- Ø
when 16#3d8# => romdata <= X"46"; -- Ø
when 16#4d8# => romdata <= X"4a"; -- Ø
when 16#5d8# => romdata <= X"4a"; -- Ø
when 16#6d8# => romdata <= X"52"; -- Ø
when 16#7d8# => romdata <= X"52"; -- Ø
when 16#8d8# => romdata <= X"52"; -- Ø
when 16#9d8# => romdata <= X"62"; -- Ø
when 16#ad8# => romdata <= X"3c"; -- Ø
when 16#bd8# => romdata <= X"40"; -- Ø
when 16#cd8# => romdata <= X"00"; -- Ø
when 16#0d9# => romdata <= X"00"; -- Ù
when 16#1d9# => romdata <= X"20"; -- Ù
when 16#2d9# => romdata <= X"10"; -- Ù
when 16#3d9# => romdata <= X"00"; -- Ù
when 16#4d9# => romdata <= X"42"; -- Ù
when 16#5d9# => romdata <= X"42"; -- Ù
when 16#6d9# => romdata <= X"42"; -- Ù
when 16#7d9# => romdata <= X"42"; -- Ù
when 16#8d9# => romdata <= X"42"; -- Ù
when 16#9d9# => romdata <= X"42"; -- Ù
when 16#ad9# => romdata <= X"3c"; -- Ù
when 16#bd9# => romdata <= X"00"; -- Ù
when 16#cd9# => romdata <= X"00"; -- Ù
when 16#0da# => romdata <= X"00"; -- Ú
when 16#1da# => romdata <= X"08"; -- Ú
when 16#2da# => romdata <= X"10"; -- Ú
when 16#3da# => romdata <= X"00"; -- Ú
when 16#4da# => romdata <= X"42"; -- Ú
when 16#5da# => romdata <= X"42"; -- Ú
when 16#6da# => romdata <= X"42"; -- Ú
when 16#7da# => romdata <= X"42"; -- Ú
when 16#8da# => romdata <= X"42"; -- Ú
when 16#9da# => romdata <= X"42"; -- Ú
when 16#ada# => romdata <= X"3c"; -- Ú
when 16#bda# => romdata <= X"00"; -- Ú
when 16#cda# => romdata <= X"00"; -- Ú
when 16#0db# => romdata <= X"00"; -- Û
when 16#1db# => romdata <= X"18"; -- Û
when 16#2db# => romdata <= X"24"; -- Û
when 16#3db# => romdata <= X"00"; -- Û
when 16#4db# => romdata <= X"42"; -- Û
when 16#5db# => romdata <= X"42"; -- Û
when 16#6db# => romdata <= X"42"; -- Û
when 16#7db# => romdata <= X"42"; -- Û
when 16#8db# => romdata <= X"42"; -- Û
when 16#9db# => romdata <= X"42"; -- Û
when 16#adb# => romdata <= X"3c"; -- Û
when 16#bdb# => romdata <= X"00"; -- Û
when 16#cdb# => romdata <= X"00"; -- Û
when 16#0dc# => romdata <= X"00"; -- Ü
when 16#1dc# => romdata <= X"24"; -- Ü
when 16#2dc# => romdata <= X"24"; -- Ü
when 16#3dc# => romdata <= X"00"; -- Ü
when 16#4dc# => romdata <= X"42"; -- Ü
when 16#5dc# => romdata <= X"42"; -- Ü
when 16#6dc# => romdata <= X"42"; -- Ü
when 16#7dc# => romdata <= X"42"; -- Ü
when 16#8dc# => romdata <= X"42"; -- Ü
when 16#9dc# => romdata <= X"42"; -- Ü
when 16#adc# => romdata <= X"3c"; -- Ü
when 16#bdc# => romdata <= X"00"; -- Ü
when 16#cdc# => romdata <= X"00"; -- Ü
when 16#0dd# => romdata <= X"00"; -- Ý
when 16#1dd# => romdata <= X"08"; -- Ý
when 16#2dd# => romdata <= X"10"; -- Ý
when 16#3dd# => romdata <= X"00"; -- Ý
when 16#4dd# => romdata <= X"44"; -- Ý
when 16#5dd# => romdata <= X"44"; -- Ý
when 16#6dd# => romdata <= X"28"; -- Ý
when 16#7dd# => romdata <= X"10"; -- Ý
when 16#8dd# => romdata <= X"10"; -- Ý
when 16#9dd# => romdata <= X"10"; -- Ý
when 16#add# => romdata <= X"10"; -- Ý
when 16#bdd# => romdata <= X"00"; -- Ý
when 16#cdd# => romdata <= X"00"; -- Ý
when 16#0de# => romdata <= X"00"; -- Þ
when 16#1de# => romdata <= X"00"; -- Þ
when 16#2de# => romdata <= X"40"; -- Þ
when 16#3de# => romdata <= X"7c"; -- Þ
when 16#4de# => romdata <= X"42"; -- Þ
when 16#5de# => romdata <= X"42"; -- Þ
when 16#6de# => romdata <= X"42"; -- Þ
when 16#7de# => romdata <= X"7c"; -- Þ
when 16#8de# => romdata <= X"40"; -- Þ
when 16#9de# => romdata <= X"40"; -- Þ
when 16#ade# => romdata <= X"40"; -- Þ
when 16#bde# => romdata <= X"00"; -- Þ
when 16#cde# => romdata <= X"00"; -- Þ
when 16#0df# => romdata <= X"00"; -- ß
when 16#1df# => romdata <= X"00"; -- ß
when 16#2df# => romdata <= X"38"; -- ß
when 16#3df# => romdata <= X"44"; -- ß
when 16#4df# => romdata <= X"44"; -- ß
when 16#5df# => romdata <= X"48"; -- ß
when 16#6df# => romdata <= X"50"; -- ß
when 16#7df# => romdata <= X"4c"; -- ß
when 16#8df# => romdata <= X"42"; -- ß
when 16#9df# => romdata <= X"42"; -- ß
when 16#adf# => romdata <= X"5c"; -- ß
when 16#bdf# => romdata <= X"00"; -- ß
when 16#cdf# => romdata <= X"00"; -- ß
when 16#0e0# => romdata <= X"00"; -- à
when 16#1e0# => romdata <= X"00"; -- à
when 16#2e0# => romdata <= X"10"; -- à
when 16#3e0# => romdata <= X"08"; -- à
when 16#4e0# => romdata <= X"00"; -- à
when 16#5e0# => romdata <= X"3c"; -- à
when 16#6e0# => romdata <= X"02"; -- à
when 16#7e0# => romdata <= X"3e"; -- à
when 16#8e0# => romdata <= X"42"; -- à
when 16#9e0# => romdata <= X"46"; -- à
when 16#ae0# => romdata <= X"3a"; -- à
when 16#be0# => romdata <= X"00"; -- à
when 16#ce0# => romdata <= X"00"; -- à
when 16#0e1# => romdata <= X"00"; -- á
when 16#1e1# => romdata <= X"00"; -- á
when 16#2e1# => romdata <= X"04"; -- á
when 16#3e1# => romdata <= X"08"; -- á
when 16#4e1# => romdata <= X"00"; -- á
when 16#5e1# => romdata <= X"3c"; -- á
when 16#6e1# => romdata <= X"02"; -- á
when 16#7e1# => romdata <= X"3e"; -- á
when 16#8e1# => romdata <= X"42"; -- á
when 16#9e1# => romdata <= X"46"; -- á
when 16#ae1# => romdata <= X"3a"; -- á
when 16#be1# => romdata <= X"00"; -- á
when 16#ce1# => romdata <= X"00"; -- á
when 16#0e2# => romdata <= X"00"; -- â
when 16#1e2# => romdata <= X"00"; -- â
when 16#2e2# => romdata <= X"18"; -- â
when 16#3e2# => romdata <= X"24"; -- â
when 16#4e2# => romdata <= X"00"; -- â
when 16#5e2# => romdata <= X"3c"; -- â
when 16#6e2# => romdata <= X"02"; -- â
when 16#7e2# => romdata <= X"3e"; -- â
when 16#8e2# => romdata <= X"42"; -- â
when 16#9e2# => romdata <= X"46"; -- â
when 16#ae2# => romdata <= X"3a"; -- â
when 16#be2# => romdata <= X"00"; -- â
when 16#ce2# => romdata <= X"00"; -- â
when 16#0e3# => romdata <= X"00"; -- ã
when 16#1e3# => romdata <= X"00"; -- ã
when 16#2e3# => romdata <= X"32"; -- ã
when 16#3e3# => romdata <= X"4c"; -- ã
when 16#4e3# => romdata <= X"00"; -- ã
when 16#5e3# => romdata <= X"3c"; -- ã
when 16#6e3# => romdata <= X"02"; -- ã
when 16#7e3# => romdata <= X"3e"; -- ã
when 16#8e3# => romdata <= X"42"; -- ã
when 16#9e3# => romdata <= X"46"; -- ã
when 16#ae3# => romdata <= X"3a"; -- ã
when 16#be3# => romdata <= X"00"; -- ã
when 16#ce3# => romdata <= X"00"; -- ã
when 16#0e4# => romdata <= X"00"; -- ä
when 16#1e4# => romdata <= X"00"; -- ä
when 16#2e4# => romdata <= X"24"; -- ä
when 16#3e4# => romdata <= X"24"; -- ä
when 16#4e4# => romdata <= X"00"; -- ä
when 16#5e4# => romdata <= X"3c"; -- ä
when 16#6e4# => romdata <= X"02"; -- ä
when 16#7e4# => romdata <= X"3e"; -- ä
when 16#8e4# => romdata <= X"42"; -- ä
when 16#9e4# => romdata <= X"46"; -- ä
when 16#ae4# => romdata <= X"3a"; -- ä
when 16#be4# => romdata <= X"00"; -- ä
when 16#ce4# => romdata <= X"00"; -- ä
when 16#0e5# => romdata <= X"00"; -- å
when 16#1e5# => romdata <= X"18"; -- å
when 16#2e5# => romdata <= X"24"; -- å
when 16#3e5# => romdata <= X"18"; -- å
when 16#4e5# => romdata <= X"00"; -- å
when 16#5e5# => romdata <= X"3c"; -- å
when 16#6e5# => romdata <= X"02"; -- å
when 16#7e5# => romdata <= X"3e"; -- å
when 16#8e5# => romdata <= X"42"; -- å
when 16#9e5# => romdata <= X"46"; -- å
when 16#ae5# => romdata <= X"3a"; -- å
when 16#be5# => romdata <= X"00"; -- å
when 16#ce5# => romdata <= X"00"; -- å
when 16#0e6# => romdata <= X"00"; -- æ
when 16#1e6# => romdata <= X"00"; -- æ
when 16#2e6# => romdata <= X"00"; -- æ
when 16#3e6# => romdata <= X"00"; -- æ
when 16#4e6# => romdata <= X"00"; -- æ
when 16#5e6# => romdata <= X"6c"; -- æ
when 16#6e6# => romdata <= X"12"; -- æ
when 16#7e6# => romdata <= X"7c"; -- æ
when 16#8e6# => romdata <= X"90"; -- æ
when 16#9e6# => romdata <= X"92"; -- æ
when 16#ae6# => romdata <= X"6c"; -- æ
when 16#be6# => romdata <= X"00"; -- æ
when 16#ce6# => romdata <= X"00"; -- æ
when 16#0e7# => romdata <= X"00"; -- ç
when 16#1e7# => romdata <= X"00"; -- ç
when 16#2e7# => romdata <= X"00"; -- ç
when 16#3e7# => romdata <= X"00"; -- ç
when 16#4e7# => romdata <= X"00"; -- ç
when 16#5e7# => romdata <= X"3c"; -- ç
when 16#6e7# => romdata <= X"42"; -- ç
when 16#7e7# => romdata <= X"40"; -- ç
when 16#8e7# => romdata <= X"40"; -- ç
when 16#9e7# => romdata <= X"42"; -- ç
when 16#ae7# => romdata <= X"3c"; -- ç
when 16#be7# => romdata <= X"08"; -- ç
when 16#ce7# => romdata <= X"10"; -- ç
when 16#0e8# => romdata <= X"00"; -- è
when 16#1e8# => romdata <= X"00"; -- è
when 16#2e8# => romdata <= X"10"; -- è
when 16#3e8# => romdata <= X"08"; -- è
when 16#4e8# => romdata <= X"00"; -- è
when 16#5e8# => romdata <= X"3c"; -- è
when 16#6e8# => romdata <= X"42"; -- è
when 16#7e8# => romdata <= X"7e"; -- è
when 16#8e8# => romdata <= X"40"; -- è
when 16#9e8# => romdata <= X"42"; -- è
when 16#ae8# => romdata <= X"3c"; -- è
when 16#be8# => romdata <= X"00"; -- è
when 16#ce8# => romdata <= X"00"; -- è
when 16#0e9# => romdata <= X"00"; -- é
when 16#1e9# => romdata <= X"00"; -- é
when 16#2e9# => romdata <= X"08"; -- é
when 16#3e9# => romdata <= X"10"; -- é
when 16#4e9# => romdata <= X"00"; -- é
when 16#5e9# => romdata <= X"3c"; -- é
when 16#6e9# => romdata <= X"42"; -- é
when 16#7e9# => romdata <= X"7e"; -- é
when 16#8e9# => romdata <= X"40"; -- é
when 16#9e9# => romdata <= X"42"; -- é
when 16#ae9# => romdata <= X"3c"; -- é
when 16#be9# => romdata <= X"00"; -- é
when 16#ce9# => romdata <= X"00"; -- é
when 16#0ea# => romdata <= X"00"; -- ê
when 16#1ea# => romdata <= X"00"; -- ê
when 16#2ea# => romdata <= X"18"; -- ê
when 16#3ea# => romdata <= X"24"; -- ê
when 16#4ea# => romdata <= X"00"; -- ê
when 16#5ea# => romdata <= X"3c"; -- ê
when 16#6ea# => romdata <= X"42"; -- ê
when 16#7ea# => romdata <= X"7e"; -- ê
when 16#8ea# => romdata <= X"40"; -- ê
when 16#9ea# => romdata <= X"42"; -- ê
when 16#aea# => romdata <= X"3c"; -- ê
when 16#bea# => romdata <= X"00"; -- ê
when 16#cea# => romdata <= X"00"; -- ê
when 16#0eb# => romdata <= X"00"; -- ë
when 16#1eb# => romdata <= X"00"; -- ë
when 16#2eb# => romdata <= X"24"; -- ë
when 16#3eb# => romdata <= X"24"; -- ë
when 16#4eb# => romdata <= X"00"; -- ë
when 16#5eb# => romdata <= X"3c"; -- ë
when 16#6eb# => romdata <= X"42"; -- ë
when 16#7eb# => romdata <= X"7e"; -- ë
when 16#8eb# => romdata <= X"40"; -- ë
when 16#9eb# => romdata <= X"42"; -- ë
when 16#aeb# => romdata <= X"3c"; -- ë
when 16#beb# => romdata <= X"00"; -- ë
when 16#ceb# => romdata <= X"00"; -- ë
when 16#0ec# => romdata <= X"00"; -- ì
when 16#1ec# => romdata <= X"00"; -- ì
when 16#2ec# => romdata <= X"20"; -- ì
when 16#3ec# => romdata <= X"10"; -- ì
when 16#4ec# => romdata <= X"00"; -- ì
when 16#5ec# => romdata <= X"30"; -- ì
when 16#6ec# => romdata <= X"10"; -- ì
when 16#7ec# => romdata <= X"10"; -- ì
when 16#8ec# => romdata <= X"10"; -- ì
when 16#9ec# => romdata <= X"10"; -- ì
when 16#aec# => romdata <= X"7c"; -- ì
when 16#bec# => romdata <= X"00"; -- ì
when 16#cec# => romdata <= X"00"; -- ì
when 16#0ed# => romdata <= X"00"; -- í
when 16#1ed# => romdata <= X"00"; -- í
when 16#2ed# => romdata <= X"10"; -- í
when 16#3ed# => romdata <= X"20"; -- í
when 16#4ed# => romdata <= X"00"; -- í
when 16#5ed# => romdata <= X"30"; -- í
when 16#6ed# => romdata <= X"10"; -- í
when 16#7ed# => romdata <= X"10"; -- í
when 16#8ed# => romdata <= X"10"; -- í
when 16#9ed# => romdata <= X"10"; -- í
when 16#aed# => romdata <= X"7c"; -- í
when 16#bed# => romdata <= X"00"; -- í
when 16#ced# => romdata <= X"00"; -- í
when 16#0ee# => romdata <= X"00"; -- î
when 16#1ee# => romdata <= X"00"; -- î
when 16#2ee# => romdata <= X"30"; -- î
when 16#3ee# => romdata <= X"48"; -- î
when 16#4ee# => romdata <= X"00"; -- î
when 16#5ee# => romdata <= X"30"; -- î
when 16#6ee# => romdata <= X"10"; -- î
when 16#7ee# => romdata <= X"10"; -- î
when 16#8ee# => romdata <= X"10"; -- î
when 16#9ee# => romdata <= X"10"; -- î
when 16#aee# => romdata <= X"7c"; -- î
when 16#bee# => romdata <= X"00"; -- î
when 16#cee# => romdata <= X"00"; -- î
when 16#0ef# => romdata <= X"00"; -- ï
when 16#1ef# => romdata <= X"00"; -- ï
when 16#2ef# => romdata <= X"48"; -- ï
when 16#3ef# => romdata <= X"48"; -- ï
when 16#4ef# => romdata <= X"00"; -- ï
when 16#5ef# => romdata <= X"30"; -- ï
when 16#6ef# => romdata <= X"10"; -- ï
when 16#7ef# => romdata <= X"10"; -- ï
when 16#8ef# => romdata <= X"10"; -- ï
when 16#9ef# => romdata <= X"10"; -- ï
when 16#aef# => romdata <= X"7c"; -- ï
when 16#bef# => romdata <= X"00"; -- ï
when 16#cef# => romdata <= X"00"; -- ï
when 16#0f0# => romdata <= X"00"; -- ð
when 16#1f0# => romdata <= X"24"; -- ð
when 16#2f0# => romdata <= X"18"; -- ð
when 16#3f0# => romdata <= X"28"; -- ð
when 16#4f0# => romdata <= X"04"; -- ð
when 16#5f0# => romdata <= X"3c"; -- ð
when 16#6f0# => romdata <= X"42"; -- ð
when 16#7f0# => romdata <= X"42"; -- ð
when 16#8f0# => romdata <= X"42"; -- ð
when 16#9f0# => romdata <= X"42"; -- ð
when 16#af0# => romdata <= X"3c"; -- ð
when 16#bf0# => romdata <= X"00"; -- ð
when 16#cf0# => romdata <= X"00"; -- ð
when 16#0f1# => romdata <= X"00"; -- ñ
when 16#1f1# => romdata <= X"00"; -- ñ
when 16#2f1# => romdata <= X"32"; -- ñ
when 16#3f1# => romdata <= X"4c"; -- ñ
when 16#4f1# => romdata <= X"00"; -- ñ
when 16#5f1# => romdata <= X"5c"; -- ñ
when 16#6f1# => romdata <= X"62"; -- ñ
when 16#7f1# => romdata <= X"42"; -- ñ
when 16#8f1# => romdata <= X"42"; -- ñ
when 16#9f1# => romdata <= X"42"; -- ñ
when 16#af1# => romdata <= X"42"; -- ñ
when 16#bf1# => romdata <= X"00"; -- ñ
when 16#cf1# => romdata <= X"00"; -- ñ
when 16#0f2# => romdata <= X"00"; -- ò
when 16#1f2# => romdata <= X"00"; -- ò
when 16#2f2# => romdata <= X"20"; -- ò
when 16#3f2# => romdata <= X"10"; -- ò
when 16#4f2# => romdata <= X"00"; -- ò
when 16#5f2# => romdata <= X"3c"; -- ò
when 16#6f2# => romdata <= X"42"; -- ò
when 16#7f2# => romdata <= X"42"; -- ò
when 16#8f2# => romdata <= X"42"; -- ò
when 16#9f2# => romdata <= X"42"; -- ò
when 16#af2# => romdata <= X"3c"; -- ò
when 16#bf2# => romdata <= X"00"; -- ò
when 16#cf2# => romdata <= X"00"; -- ò
when 16#0f3# => romdata <= X"00"; -- ó
when 16#1f3# => romdata <= X"00"; -- ó
when 16#2f3# => romdata <= X"08"; -- ó
when 16#3f3# => romdata <= X"10"; -- ó
when 16#4f3# => romdata <= X"00"; -- ó
when 16#5f3# => romdata <= X"3c"; -- ó
when 16#6f3# => romdata <= X"42"; -- ó
when 16#7f3# => romdata <= X"42"; -- ó
when 16#8f3# => romdata <= X"42"; -- ó
when 16#9f3# => romdata <= X"42"; -- ó
when 16#af3# => romdata <= X"3c"; -- ó
when 16#bf3# => romdata <= X"00"; -- ó
when 16#cf3# => romdata <= X"00"; -- ó
when 16#0f4# => romdata <= X"00"; -- ô
when 16#1f4# => romdata <= X"00"; -- ô
when 16#2f4# => romdata <= X"18"; -- ô
when 16#3f4# => romdata <= X"24"; -- ô
when 16#4f4# => romdata <= X"00"; -- ô
when 16#5f4# => romdata <= X"3c"; -- ô
when 16#6f4# => romdata <= X"42"; -- ô
when 16#7f4# => romdata <= X"42"; -- ô
when 16#8f4# => romdata <= X"42"; -- ô
when 16#9f4# => romdata <= X"42"; -- ô
when 16#af4# => romdata <= X"3c"; -- ô
when 16#bf4# => romdata <= X"00"; -- ô
when 16#cf4# => romdata <= X"00"; -- ô
when 16#0f5# => romdata <= X"00"; -- õ
when 16#1f5# => romdata <= X"00"; -- õ
when 16#2f5# => romdata <= X"32"; -- õ
when 16#3f5# => romdata <= X"4c"; -- õ
when 16#4f5# => romdata <= X"00"; -- õ
when 16#5f5# => romdata <= X"3c"; -- õ
when 16#6f5# => romdata <= X"42"; -- õ
when 16#7f5# => romdata <= X"42"; -- õ
when 16#8f5# => romdata <= X"42"; -- õ
when 16#9f5# => romdata <= X"42"; -- õ
when 16#af5# => romdata <= X"3c"; -- õ
when 16#bf5# => romdata <= X"00"; -- õ
when 16#cf5# => romdata <= X"00"; -- õ
when 16#0f6# => romdata <= X"00"; -- ö
when 16#1f6# => romdata <= X"00"; -- ö
when 16#2f6# => romdata <= X"24"; -- ö
when 16#3f6# => romdata <= X"24"; -- ö
when 16#4f6# => romdata <= X"00"; -- ö
when 16#5f6# => romdata <= X"3c"; -- ö
when 16#6f6# => romdata <= X"42"; -- ö
when 16#7f6# => romdata <= X"42"; -- ö
when 16#8f6# => romdata <= X"42"; -- ö
when 16#9f6# => romdata <= X"42"; -- ö
when 16#af6# => romdata <= X"3c"; -- ö
when 16#bf6# => romdata <= X"00"; -- ö
when 16#cf6# => romdata <= X"00"; -- ö
when 16#0f7# => romdata <= X"00"; -- ÷
when 16#1f7# => romdata <= X"00"; -- ÷
when 16#2f7# => romdata <= X"00"; -- ÷
when 16#3f7# => romdata <= X"10"; -- ÷
when 16#4f7# => romdata <= X"10"; -- ÷
when 16#5f7# => romdata <= X"00"; -- ÷
when 16#6f7# => romdata <= X"7c"; -- ÷
when 16#7f7# => romdata <= X"00"; -- ÷
when 16#8f7# => romdata <= X"10"; -- ÷
when 16#9f7# => romdata <= X"10"; -- ÷
when 16#af7# => romdata <= X"00"; -- ÷
when 16#bf7# => romdata <= X"00"; -- ÷
when 16#cf7# => romdata <= X"00"; -- ÷
when 16#0f8# => romdata <= X"00"; -- ø
when 16#1f8# => romdata <= X"00"; -- ø
when 16#2f8# => romdata <= X"00"; -- ø
when 16#3f8# => romdata <= X"00"; -- ø
when 16#4f8# => romdata <= X"02"; -- ø
when 16#5f8# => romdata <= X"3c"; -- ø
when 16#6f8# => romdata <= X"46"; -- ø
when 16#7f8# => romdata <= X"4a"; -- ø
when 16#8f8# => romdata <= X"52"; -- ø
when 16#9f8# => romdata <= X"62"; -- ø
when 16#af8# => romdata <= X"3c"; -- ø
when 16#bf8# => romdata <= X"40"; -- ø
when 16#cf8# => romdata <= X"00"; -- ø
when 16#0f9# => romdata <= X"00"; -- ù
when 16#1f9# => romdata <= X"00"; -- ù
when 16#2f9# => romdata <= X"20"; -- ù
when 16#3f9# => romdata <= X"10"; -- ù
when 16#4f9# => romdata <= X"00"; -- ù
when 16#5f9# => romdata <= X"44"; -- ù
when 16#6f9# => romdata <= X"44"; -- ù
when 16#7f9# => romdata <= X"44"; -- ù
when 16#8f9# => romdata <= X"44"; -- ù
when 16#9f9# => romdata <= X"44"; -- ù
when 16#af9# => romdata <= X"3a"; -- ù
when 16#bf9# => romdata <= X"00"; -- ù
when 16#cf9# => romdata <= X"00"; -- ù
when 16#0fa# => romdata <= X"00"; -- ú
when 16#1fa# => romdata <= X"00"; -- ú
when 16#2fa# => romdata <= X"08"; -- ú
when 16#3fa# => romdata <= X"10"; -- ú
when 16#4fa# => romdata <= X"00"; -- ú
when 16#5fa# => romdata <= X"44"; -- ú
when 16#6fa# => romdata <= X"44"; -- ú
when 16#7fa# => romdata <= X"44"; -- ú
when 16#8fa# => romdata <= X"44"; -- ú
when 16#9fa# => romdata <= X"44"; -- ú
when 16#afa# => romdata <= X"3a"; -- ú
when 16#bfa# => romdata <= X"00"; -- ú
when 16#cfa# => romdata <= X"00"; -- ú
when 16#0fb# => romdata <= X"00"; -- û
when 16#1fb# => romdata <= X"00"; -- û
when 16#2fb# => romdata <= X"18"; -- û
when 16#3fb# => romdata <= X"24"; -- û
when 16#4fb# => romdata <= X"00"; -- û
when 16#5fb# => romdata <= X"44"; -- û
when 16#6fb# => romdata <= X"44"; -- û
when 16#7fb# => romdata <= X"44"; -- û
when 16#8fb# => romdata <= X"44"; -- û
when 16#9fb# => romdata <= X"44"; -- û
when 16#afb# => romdata <= X"3a"; -- û
when 16#bfb# => romdata <= X"00"; -- û
when 16#cfb# => romdata <= X"00"; -- û
when 16#0fc# => romdata <= X"00"; -- ü
when 16#1fc# => romdata <= X"00"; -- ü
when 16#2fc# => romdata <= X"28"; -- ü
when 16#3fc# => romdata <= X"28"; -- ü
when 16#4fc# => romdata <= X"00"; -- ü
when 16#5fc# => romdata <= X"44"; -- ü
when 16#6fc# => romdata <= X"44"; -- ü
when 16#7fc# => romdata <= X"44"; -- ü
when 16#8fc# => romdata <= X"44"; -- ü
when 16#9fc# => romdata <= X"44"; -- ü
when 16#afc# => romdata <= X"3a"; -- ü
when 16#bfc# => romdata <= X"00"; -- ü
when 16#cfc# => romdata <= X"00"; -- ü
when 16#0fd# => romdata <= X"00"; -- ý
when 16#1fd# => romdata <= X"00"; -- ý
when 16#2fd# => romdata <= X"08"; -- ý
when 16#3fd# => romdata <= X"10"; -- ý
when 16#4fd# => romdata <= X"00"; -- ý
when 16#5fd# => romdata <= X"42"; -- ý
when 16#6fd# => romdata <= X"42"; -- ý
when 16#7fd# => romdata <= X"42"; -- ý
when 16#8fd# => romdata <= X"46"; -- ý
when 16#9fd# => romdata <= X"3a"; -- ý
when 16#afd# => romdata <= X"02"; -- ý
when 16#bfd# => romdata <= X"42"; -- ý
when 16#cfd# => romdata <= X"3c"; -- ý
when 16#0fe# => romdata <= X"00"; -- þ
when 16#1fe# => romdata <= X"00"; -- þ
when 16#2fe# => romdata <= X"00"; -- þ
when 16#3fe# => romdata <= X"40"; -- þ
when 16#4fe# => romdata <= X"40"; -- þ
when 16#5fe# => romdata <= X"5c"; -- þ
when 16#6fe# => romdata <= X"62"; -- þ
when 16#7fe# => romdata <= X"42"; -- þ
when 16#8fe# => romdata <= X"42"; -- þ
when 16#9fe# => romdata <= X"62"; -- þ
when 16#afe# => romdata <= X"5c"; -- þ
when 16#bfe# => romdata <= X"40"; -- þ
when 16#cfe# => romdata <= X"40"; -- þ
when 16#0ff# => romdata <= X"00"; -- ÿ
when 16#1ff# => romdata <= X"00"; -- ÿ
when 16#2ff# => romdata <= X"24"; -- ÿ
when 16#3ff# => romdata <= X"24"; -- ÿ
when 16#4ff# => romdata <= X"00"; -- ÿ
when 16#5ff# => romdata <= X"42"; -- ÿ
when 16#6ff# => romdata <= X"42"; -- ÿ
when 16#7ff# => romdata <= X"42"; -- ÿ
when 16#8ff# => romdata <= X"46"; -- ÿ
when 16#9ff# => romdata <= X"3a"; -- ÿ
when 16#aff# => romdata <= X"02"; -- ÿ
when 16#bff# => romdata <= X"42"; -- ÿ
when 16#cff# => romdata <= X"3c"; -- ÿ
when others => romdata <= (others => '0');
end case;
end process;
end architecture;
| gpl-2.0 | a9abee90438bbaf8b245a210b5c89e1f | 0.422083 | 2.935949 | false | false | false | false |
a4a881d4/ringbus4xilinx | src/ep/EPMemOut.vhd | 2 | 4,778 | ---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point Send from Mem
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : EPMemOut.vhd
-- Generated : 2013/9/9
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring bus end point Send from Mem
--
-- assume RAM has one clock delay from addr to data
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
--
-- Todo:
-- 1. add speed level to module -- Done
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.rb_config.all;
entity EPMEMOUT is
generic(
Awidth : natural;
Bwidth : natural;
speed : natural := 0
);
port(
-- system interface
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- bus interface
tx_sop : in std_logic;
Req : out std_logic;
tx: out std_logic_vector(Bwidth-1 downto 0);
-- Mem interface
mD : in STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
mAddr : out std_logic_vector( Awidth-1 downto 0 );
mren : out STD_LOGIC;
-- Local Bus interface
header : in STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
laddr : in std_logic_vector( Awidth-1 downto 0 );
Req_in : in std_logic;
busy : out std_logic
);
end EPMEMOUT;
architecture behave of EPMEMOUT is
begin
fast_g: if speed=0 generate
signal addr_i : std_logic_vector( Awidth-1 downto 0 ) := (others => '0');
signal lenc : std_logic_vector( len_length-1 downto 0 ) := (others => '0');
signal hold : std_logic := '0';
signal state: natural;
begin
FSM:process(clk,rst)
begin
if rst='1' then
addr_i<=(others => '0');
lenc<=(others => '0');
hold<='0';
req<='0';
mren<='0';
busy<='0';
state<=state_idle;
elsif rising_edge(clk) then
case state is
when state_idle =>
if req_in='1' then
state<=state_pending;
end if;
when state_pending =>
req<='1';
addr_i<=laddr;
lenc<=header( len_end downto len_start )-1;
busy<='1';
mren<='1';
state<=state_ready;
when state_ready =>
if tx_sop='1' then
req<='0';
addr_i<=addr_i+1;
lenc<=lenc-1;
hold<='1';
state<=state_trans;
end if;
when state_trans =>
if lenc/=zeros( len_length-1 downto 0 ) then
addr_i<=addr_i+1;
lenc<=lenc-1;
end if;
if lenc=zeros( len_length-1 downto 0 ) then
hold<='0';
busy<='0';
if req_in='0' then
state<=state_idle;
else
state<=state_pending;
end if;
mren<='0';
end if;
when others =>
null;
end case;
end if;
end process;
maddr<=addr_i;
tx<=header when tx_sop='1' else mD;
end generate fast_g;
speed_g: if speed/=0 generate
signal addr_i : std_logic_vector( Awidth-1 downto 0 ) := (others => '0');
signal lenc : std_logic_vector( len_length-1 downto 0 ) := (others => '0');
signal hold : std_logic := '0';
signal state: natural;
signal delaycount : natural range 0 to speed+1;
begin
FSM:process(clk,rst)
begin
if rst='1' then
addr_i<=(others => '0');
lenc<=(others => '0');
hold<='0';
req<='0';
mren<='0';
busy<='0';
state<=state_idle;
delaycount<=0;
elsif rising_edge(clk) then
case state is
when state_idle =>
if req_in='1' then
state<=state_pending;
end if;
when state_pending =>
req<='1';
addr_i<=laddr;
lenc<=header( len_end downto len_start )-1;
busy<='1';
mren<='1';
state<=state_ready;
when state_ready =>
if tx_sop='1' then
req<='0';
addr_i<=addr_i+1;
lenc<=lenc-1;
hold<='1';
state<=state_trans;
end if;
when state_trans =>
if lenc/=zeros( len_length-1 downto 0 ) then
addr_i<=addr_i+1;
lenc<=lenc-1;
end if;
if lenc=zeros( len_length-1 downto 0 ) then
hold<='0';
busy<='0';
state<=state_end;
mren<='0';
end if;
delaycount<=0;
when state_end =>
if delaycount=speed then
state<=state_idle;
else
delaycount<=delaycount+1;
end if;
when others =>
null;
end case;
end if;
end process;
maddr<=addr_i;
tx<=header when tx_sop='1' else mD;
end generate speed_g;
end behave;
| gpl-2.0 | 1857a38ac8da7fff70d9841bf3653d8b | 0.492675 | 3.106632 | false | false | false | false |
dsaves/dsaves-hdl | crypto/aes_256/aes_256_pkg.vhdl | 1 | 12,393 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-- ############################################################################
-- The official specifications of the SHA-256 algorithm can be found here:
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes_256_pkg is
constant BYTE_SIZE : natural := 8;
constant NB : natural := 4;
--type BYTE_T is std_logic_vector(BYTE_SIZE-1 downto 0);
--type ROW is array(natural range <>) of BYTE_T
--type t_row_vector is array(natural range <>) of t_byte
--subtype t_byte is std_logic_vector(BYTE_SIZE-1 downto 0);
--type t_row_vector is array(natural range <>) of t_byte;
--subtype t_dim2 is t_row_vector(0 to c1_r2);
--type t_dim3_vector is array(natural range <>) of t_dim2;
--subtype t_dim3 is t_dim3_vector(0 to r1);
--function definitions
function SUB_BYTES (xy : std_logic_vector(BYTE_SIZE-1 downto 0))
return std_logic_vector;
--function SHIFT_ROW (r : ROW; n : natural ) return ROW;
end package;
package body aes_256_pkg is
function SUB_BYTES (xy : std_logic_vector(BYTE_SIZE-1 downto 0))
return std_logic_vector is
begin
case xy is
when X"00" => return X"63"; when X"01" => return X"7C";
when X"02" => return X"77"; when X"03" => return X"7B";
when X"04" => return X"F2"; when X"05" => return X"6B";
when X"06" => return X"6F"; when X"07" => return X"C5";
when X"08" => return X"30"; when X"09" => return X"01";
when X"0A" => return X"67"; when X"0B" => return X"2B";
when X"0C" => return X"FE"; when X"0D" => return X"D7";
when X"0E" => return X"AB"; when X"0F" => return X"76";
when X"10" => return X"CA"; when X"11" => return X"82";
when X"12" => return X"C9"; when X"13" => return X"7D";
when X"14" => return X"FA"; when X"15" => return X"59";
when X"16" => return X"47"; when X"17" => return X"F0";
when X"18" => return X"AD"; when X"19" => return X"D4";
when X"1A" => return X"A2"; when X"1B" => return X"AF";
when X"1C" => return X"9C"; when X"1D" => return X"A4";
when X"1E" => return X"72"; when X"1F" => return X"C0";
when X"20" => return X"B7"; when X"21" => return X"FD";
when X"22" => return X"93"; when X"23" => return X"26";
when X"24" => return X"36"; when X"25" => return X"3F";
when X"26" => return X"F7"; when X"27" => return X"CC";
when X"28" => return X"34"; when X"29" => return X"A5";
when X"2A" => return X"E5"; when X"2B" => return X"F1";
when X"2C" => return X"71"; when X"2D" => return X"D8";
when X"2E" => return X"31"; when X"2F" => return X"15";
when X"30" => return X"04"; when X"31" => return X"C7";
when X"32" => return X"23"; when X"33" => return X"C3";
when X"34" => return X"18"; when X"35" => return X"96";
when X"36" => return X"05"; when X"37" => return X"9A";
when X"38" => return X"07"; when X"39" => return X"12";
when X"3A" => return X"80"; when X"3B" => return X"E2";
when X"3C" => return X"EB"; when X"3D" => return X"27";
when X"3E" => return X"B2"; when X"3F" => return X"75";
when X"40" => return X"09"; when X"41" => return X"83";
when X"42" => return X"2C"; when X"43" => return X"1A";
when X"44" => return X"1B"; when X"45" => return X"6E";
when X"46" => return X"5A"; when X"47" => return X"A0";
when X"48" => return X"52"; when X"49" => return X"3B";
when X"4A" => return X"D6"; when X"4B" => return X"B3";
when X"4C" => return X"29"; when X"4D" => return X"E3";
when X"4E" => return X"2F"; when X"4F" => return X"84";
when X"50" => return X"53"; when X"51" => return X"D1";
when X"52" => return X"00"; when X"53" => return X"ED";
when X"54" => return X"20"; when X"55" => return X"FC";
when X"56" => return X"B1"; when X"57" => return X"5B";
when X"58" => return X"6A"; when X"59" => return X"CB";
when X"5A" => return X"BE"; when X"5B" => return X"39";
when X"5C" => return X"4A"; when X"5D" => return X"4C";
when X"5E" => return X"58"; when X"5F" => return X"CF";
when X"60" => return X"D0"; when X"61" => return X"EF";
when X"62" => return X"AA"; when X"63" => return X"FB";
when X"64" => return X"43"; when X"65" => return X"4D";
when X"66" => return X"33"; when X"67" => return X"85";
when X"68" => return X"45"; when X"69" => return X"F9";
when X"6A" => return X"02"; when X"6B" => return X"7F";
when X"6C" => return X"50"; when X"6D" => return X"3C";
when X"6E" => return X"9F"; when X"6F" => return X"A8";
when X"70" => return X"51"; when X"71" => return X"A3";
when X"72" => return X"40"; when X"73" => return X"8F";
when X"74" => return X"92"; when X"75" => return X"9D";
when X"76" => return X"38"; when X"77" => return X"F5";
when X"78" => return X"BC"; when X"79" => return X"B6";
when X"7A" => return X"DA"; when X"7B" => return X"21";
when X"7C" => return X"10"; when X"7D" => return X"FF";
when X"7E" => return X"F3"; when X"7F" => return X"D2";
when X"80" => return X"CD"; when X"81" => return X"0C";
when X"82" => return X"13"; when X"83" => return X"EC";
when X"84" => return X"5F"; when X"85" => return X"97";
when X"86" => return X"44"; when X"87" => return X"17";
when X"88" => return X"C4"; when X"89" => return X"A7";
when X"8A" => return X"7E"; when X"8B" => return X"3D";
when X"8C" => return X"64"; when X"8D" => return X"5D";
when X"8E" => return X"19"; when X"8F" => return X"73";
when X"90" => return X"60"; when X"91" => return X"81";
when X"92" => return X"4F"; when X"93" => return X"DC";
when X"94" => return X"22"; when X"95" => return X"2A";
when X"96" => return X"90"; when X"97" => return X"88";
when X"98" => return X"46"; when X"99" => return X"EE";
when X"9A" => return X"B8"; when X"9B" => return X"14";
when X"9C" => return X"DE"; when X"9D" => return X"5E";
when X"9E" => return X"0B"; when X"9F" => return X"DB";
when X"A0" => return X"E0"; when X"A1" => return X"32";
when X"A2" => return X"3A"; when X"A3" => return X"0A";
when X"A4" => return X"49"; when X"A5" => return X"06";
when X"A6" => return X"24"; when X"A7" => return X"5C";
when X"A8" => return X"C2"; when X"A9" => return X"D3";
when X"AA" => return X"AC"; when X"AB" => return X"62";
when X"AC" => return X"91"; when X"AD" => return X"95";
when X"AE" => return X"E4"; when X"AF" => return X"79";
when X"B0" => return X"E7"; when X"B1" => return X"C8";
when X"B2" => return X"37"; when X"B3" => return X"6D";
when X"B4" => return X"8D"; when X"B5" => return X"D5";
when X"B6" => return X"4E"; when X"B7" => return X"A9";
when X"B8" => return X"6C"; when X"B9" => return X"56";
when X"BA" => return X"F4"; when X"BB" => return X"EA";
when X"BC" => return X"65"; when X"BD" => return X"7A";
when X"BE" => return X"AE"; when X"BF" => return X"08";
when X"C0" => return X"BA"; when X"C1" => return X"78";
when X"C2" => return X"25"; when X"C3" => return X"2E";
when X"C4" => return X"1C"; when X"C5" => return X"A6";
when X"C6" => return X"B4"; when X"C7" => return X"C6";
when X"C8" => return X"E8"; when X"C9" => return X"DD";
when X"CA" => return X"74"; when X"CB" => return X"1F";
when X"CC" => return X"4B"; when X"CD" => return X"BD";
when X"CE" => return X"8B"; when X"CF" => return X"8A";
when X"D0" => return X"70"; when X"D1" => return X"3E";
when X"D2" => return X"B5"; when X"D3" => return X"66";
when X"D4" => return X"48"; when X"D5" => return X"03";
when X"D6" => return X"F6"; when X"D7" => return X"0E";
when X"D8" => return X"61"; when X"D9" => return X"35";
when X"DA" => return X"57"; when X"DB" => return X"B9";
when X"DC" => return X"86"; when X"DD" => return X"C1";
when X"DE" => return X"1D"; when X"DF" => return X"9E";
when X"E0" => return X"E1"; when X"E1" => return X"F8";
when X"E2" => return X"98"; when X"E3" => return X"11";
when X"E4" => return X"69"; when X"E5" => return X"D9";
when X"E6" => return X"8E"; when X"E7" => return X"94";
when X"E8" => return X"9B"; when X"E9" => return X"1E";
when X"EA" => return X"87"; when X"EB" => return X"E9";
when X"EC" => return X"CE"; when X"ED" => return X"55";
when X"EE" => return X"28"; when X"EF" => return X"DF";
when X"F0" => return X"8C"; when X"F1" => return X"A1";
when X"F2" => return X"89"; when X"F3" => return X"0D";
when X"F4" => return X"BF"; when X"F5" => return X"E6";
when X"F6" => return X"42"; when X"F7" => return X"68";
when X"F8" => return X"41"; when X"F9" => return X"99";
when X"FA" => return X"2D"; when X"FB" => return X"0F";
when X"FC" => return X"B0"; when X"FD" => return X"54";
when X"FE" => return X"BB"; when X"FF" => return X"16";
when others => return X"00";
end case;
end function;
--function SHIFT_ROW (r : ROW; n : natural ) return ROW is
-- variable temp_byte : std_logic_vector(BYTE_SIZE-1 downto 0);
--begin
-- return shift_left(unsigned(r), n*BYTE_SIZE);
--end function;
end package body;
| mit | 7ac5fa2e80e993852ec46b9ce58d978f | 0.475914 | 3.06454 | false | false | false | false |
khaledhassan/vhdl-examples | multiplexer/mux_2x1_tb.vhd | 1 | 2,554 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the 2-to-1 multiplexer.
library ieee;
use ieee.std_logic_1164.all;
entity mux_2x1_tb is
end mux_2x1_tb;
architecture TB of mux_2x1_tb is
signal sel : std_logic;
signal output, in0, in1 : std_logic_vector(0 downto 0);
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.mux_2x1
generic map (
WIDTH => 1
)
port map (
output => output,
sel => sel,
in0 => in0,
in1 => in1
);
-- Stimulus process
process
begin
in0(0) <= '0';
in1(0) <= '0';
sel <= '0';
wait for 10 ns;
in0(0) <= '1';
in1(0) <= '0';
sel <= '0';
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '1';
sel <= '0';
wait for 10 ns;
in0(0) <= '1';
in1(0) <= '1';
sel <= '0';
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
sel <= '1';
wait for 10 ns;
in0(0) <= '1';
in1(0) <= '0';
sel <= '1';
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '1';
sel <= '1';
wait for 10 ns;
in0(0) <= '1';
in1(0) <= '1';
sel <= '1';
wait;
end process;
end TB;
| mit | f46ef783e97452d6388bac6d5b792e8b | 0.566562 | 3.680115 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/Var6.vhd | 1 | 1,461 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Var6 is port(
W,X,Y,Z: in std_logic;
F: out std_logic
);
end Var6;
--
architecture structual of Var6 is
signal nW : std_logic;
signal nY : std_logic;
signal nWX : std_logic;
signal nWXY : std_logic;
signal WXY : std_logic;
signal T : std_logic;
signal nT : std_logic;
signal WZ : std_logic;
signal nWZ : std_logic;
component AND2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component OR2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
component AND3 is port(
A,B,C: in std_logic;
Z: out std_logic);
end component;
component OR3 is port (
A,B,C: in std_logic;
Z: out std_logic);
end component;
begin
M1: NOT1 port map (W, nW);
M2: OR2 port map (nW, X, nWX);
M3: AND2 port map (nWX, Y, nWXY);
M4: NOT1 port map (nWXY, WXY);
M5: NOT1 port map (Y, nY);
M6: OR3 port map (nW, X, nY, T);
M7: NOT1 port map (T, nT);
M8: OR2 port map (W, Z, WZ);
M9: NOT1 port map (WZ, nWZ);
M10: AND3 port map (nWZ, nT, WXY, F);
end structual;
architecture behavior of Var6 is
signal WX : std_logic;
signal WXY : std_logic;
signal WXY2 : std_logic;
signal WZ : std_logic;
begin
WX <= (not W) or X;
WXY <= not(WX and Y);
WXY2 <= not((not W) or X or (not Y));
WZ <= not(W or Z);
F <= WZ and WXY and WXY2;
end behavior; | mit | b6fe118c98d6e9d585d42e6131718d84 | 0.622177 | 2.356452 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_0_5/hdl/vhdl/convolve_kernel.vhd | 4 | 40,699 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=37942,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=860,HLS_SYN_LUT=1412}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (25 downto 0) := "00000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (25 downto 0) := "00000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (25 downto 0) := "00000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (25 downto 0) := "00000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (25 downto 0) := "00000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (25 downto 0) := "00000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (25 downto 0) := "00001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (25 downto 0) := "00010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (25 downto 0) := "00100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (25 downto 0) := "01000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (25 downto 0) := "10000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal row_b_cast6_cast_fu_164_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_cast6_cast_reg_454 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal row_b_cast_fu_168_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_cast_reg_459 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_1_fu_178_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal row_b_1_reg_467 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_cast5_cast_fu_184_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_cast5_cast_reg_472 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal col_b_cast_fu_188_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_cast_reg_477 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_1_fu_198_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_1_reg_485 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_cast_fu_226_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_cast_reg_490 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal tmp_11_fu_230_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_reg_495 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_501 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_1_fu_241_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal to_b_1_reg_505 : STD_LOGIC_VECTOR (1 downto 0);
signal bufo_addr_reg_510 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_17_fu_292_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_17_reg_515 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_19_cast_fu_316_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_19_cast_reg_520 : STD_LOGIC_VECTOR (6 downto 0);
signal ti_b_1_fu_326_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal ti_b_1_reg_528 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_22_fu_357_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_22_reg_533 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal i_1_fu_369_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_541 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_fu_375_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_reg_546 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_fu_363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_reg_551 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal bufw_addr_reg_556 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal j_1_fu_430_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_564 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_27_fu_445_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_27_reg_569 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_424_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal bufw_load_reg_579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal bufi_load_reg_584 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_160_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal bufo_load_reg_594 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_156_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal row_b_reg_90 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_1_fu_192_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_b_reg_101 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_fu_172_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_reg_112 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_5_fu_320_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ti_b_reg_123 : STD_LOGIC_VECTOR (1 downto 0);
signal i_reg_134 : STD_LOGIC_VECTOR (2 downto 0);
signal j_reg_145 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal tmp_14_cast_fu_262_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_cast_fu_419_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_27_cast_fu_450_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_8_fu_208_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl1_cast_fu_216_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_cast4_cast_fu_204_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_220_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_fu_247_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_13_fu_252_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_14_fu_257_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_cast3_cast_fu_267_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_15_fu_271_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_16_fu_280_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_cast_fu_276_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl3_fu_288_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_298_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl2_cast_fu_306_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_19_fu_310_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_cast2_fu_332_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_20_fu_336_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_fu_345_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_21_fu_341_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl4_cast_fu_349_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_cast_cast_fu_380_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_23_fu_383_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_28_fu_392_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl5_cast_fu_396_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_23_cast_fu_388_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal j_cast1_cast_fu_410_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_414_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_fu_436_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_2_cast_cast_fu_441_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (25 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufo_load_reg_594,
din1 => tmp_4_reg_589,
ce => ap_const_logic_1,
dout => grp_fu_156_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufw_load_reg_579,
din1 => bufi_load_reg_584,
ce => ap_const_logic_1,
dout => grp_fu_160_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
col_b_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_172_p2))) then
col_b_reg_101 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_1))) then
col_b_reg_101 <= col_b_1_reg_485;
end if;
end if;
end process;
i_reg_134_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = tmp_5_fu_320_p2))) then
i_reg_134 <= ap_const_lv3_0;
elsif (((tmp_s_fu_424_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state9))) then
i_reg_134 <= i_1_reg_541;
end if;
end if;
end process;
j_reg_145_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
j_reg_145 <= ap_const_lv3_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
j_reg_145 <= j_1_reg_564;
end if;
end if;
end process;
row_b_reg_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_1_fu_192_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
row_b_reg_90 <= row_b_1_reg_467;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
row_b_reg_90 <= ap_const_lv2_0;
end if;
end if;
end process;
ti_b_reg_123_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_0))) then
ti_b_reg_123 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_1))) then
ti_b_reg_123 <= ti_b_1_reg_528;
end if;
end if;
end process;
to_b_reg_112_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_1_fu_192_p2))) then
to_b_reg_112 <= ap_const_lv2_0;
elsif (((ap_const_lv1_1 = tmp_5_fu_320_p2) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
to_b_reg_112 <= to_b_1_reg_505;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
bufi_load_reg_584 <= bufi_Dout_A;
bufw_load_reg_579 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
bufo_addr_reg_510 <= tmp_14_cast_fu_262_p1(5 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
bufo_load_reg_594 <= bufo_Dout_A;
tmp_4_reg_589 <= grp_fu_160_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
bufw_addr_reg_556 <= tmp_26_cast_fu_419_p1(8 - 1 downto 0);
j_1_reg_564 <= j_1_fu_430_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
col_b_1_reg_485 <= col_b_1_fu_198_p2;
col_b_cast5_cast_reg_472(1 downto 0) <= col_b_cast5_cast_fu_184_p1(1 downto 0);
col_b_cast_reg_477(1 downto 0) <= col_b_cast_fu_188_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_1_reg_541 <= i_1_fu_369_p2;
tmp_22_reg_533 <= tmp_22_fu_357_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
row_b_1_reg_467 <= row_b_1_fu_178_p2;
row_b_cast6_cast_reg_454(1 downto 0) <= row_b_cast6_cast_fu_164_p1(1 downto 0);
row_b_cast_reg_459(1 downto 0) <= row_b_cast_fu_168_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
ti_b_1_reg_528 <= ti_b_1_fu_326_p2;
tmp_17_reg_515 <= tmp_17_fu_292_p2;
tmp_19_cast_reg_520 <= tmp_19_cast_fu_316_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_10_cast_reg_490 <= tmp_10_cast_fu_226_p1;
tmp_11_reg_495 <= tmp_11_fu_230_p2;
tmp_3_reg_501 <= tmp_3_fu_235_p2;
to_b_1_reg_505 <= to_b_1_fu_241_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_25_reg_551 <= tmp_25_fu_404_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (ap_const_lv1_0 = tmp_s_fu_424_p2))) then
tmp_27_reg_569 <= tmp_27_fu_445_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state25)) then
tmp_6_reg_599 <= grp_fu_156_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_0))) then
tmp_9_reg_546 <= tmp_9_fu_375_p2;
end if;
end if;
end process;
row_b_cast6_cast_reg_454(5 downto 2) <= "0000";
row_b_cast_reg_459(2) <= '0';
col_b_cast5_cast_reg_472(5 downto 2) <= "0000";
col_b_cast_reg_477(2) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, tmp_3_reg_501, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, tmp_7_fu_363_p2, ap_CS_fsm_state9, tmp_s_fu_424_p2, tmp_1_fu_192_p2, tmp_fu_172_p2, tmp_5_fu_320_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((tmp_1_fu_192_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_lv1_1 = tmp_5_fu_320_p2) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
if (((tmp_s_fu_424_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state9))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state25 <= ap_CS_fsm(24);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_172_p2)
begin
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_172_p2)
begin
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_Addr_A_orig <= tmp_27_cast_fu_450_p1(32 - 1 downto 0);
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv32_0;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst_n_inv;
bufi_WEN_A <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_510),32));
bufo_Clk_A <= ap_clk;
bufo_Din_A <= tmp_6_reg_599;
bufo_EN_A_assign_proc : process(ap_CS_fsm_state26, ap_CS_fsm_state15)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state26))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_state26)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_reg_556),32));
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv32_0;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst_n_inv;
bufw_WEN_A <= ap_const_lv4_0;
col_b_1_fu_198_p2 <= std_logic_vector(unsigned(col_b_reg_101) + unsigned(ap_const_lv2_1));
col_b_cast5_cast_fu_184_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_101),6));
col_b_cast_fu_188_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_101),3));
i_1_fu_369_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_reg_134));
i_cast2_fu_332_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_134),64));
j_1_fu_430_p2 <= std_logic_vector(unsigned(j_reg_145) + unsigned(ap_const_lv3_1));
j_cast1_cast_fu_410_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_145),9));
p_shl1_cast_fu_216_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_fu_208_p3),5));
p_shl2_cast_fu_306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_18_fu_298_p3),6));
p_shl3_fu_288_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_fu_280_p3),64));
p_shl4_cast_fu_349_p3 <= (tmp_24_fu_345_p1 & ap_const_lv2_0);
p_shl5_cast_fu_396_p3 <= (tmp_28_fu_392_p1 & ap_const_lv3_0);
row_b_1_fu_178_p2 <= std_logic_vector(unsigned(row_b_reg_90) + unsigned(ap_const_lv2_1));
row_b_cast6_cast_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_90),6));
row_b_cast_fu_168_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_90),3));
ti_b_1_fu_326_p2 <= std_logic_vector(unsigned(ti_b_reg_123) + unsigned(ap_const_lv2_1));
ti_b_cast3_cast_fu_267_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ti_b_reg_123),6));
tmp_10_cast_fu_226_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_10_fu_220_p2),6));
tmp_10_fu_220_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_216_p1) - unsigned(to_b_cast4_cast_fu_204_p1));
tmp_11_fu_230_p2 <= std_logic_vector(unsigned(row_b_cast6_cast_reg_454) + unsigned(tmp_10_cast_fu_226_p1));
tmp_12_fu_247_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_reg_495),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0)))));
tmp_13_fu_252_p2 <= std_logic_vector(unsigned(tmp_12_fu_247_p2) - unsigned(tmp_11_reg_495));
tmp_14_cast_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_14_fu_257_p2),64));
tmp_14_fu_257_p2 <= std_logic_vector(unsigned(col_b_cast5_cast_reg_472) + unsigned(tmp_13_fu_252_p2));
tmp_15_cast_fu_276_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_15_fu_271_p2),64));
tmp_15_fu_271_p2 <= std_logic_vector(signed(tmp_10_cast_reg_490) + signed(ti_b_cast3_cast_fu_267_p1));
tmp_16_fu_280_p3 <= (tmp_15_fu_271_p2 & ap_const_lv2_0);
tmp_17_fu_292_p2 <= std_logic_vector(signed(tmp_15_cast_fu_276_p1) + signed(p_shl3_fu_288_p1));
tmp_18_fu_298_p3 <= (ti_b_reg_123 & ap_const_lv3_0);
tmp_19_cast_fu_316_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_19_fu_310_p2),7));
tmp_19_fu_310_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_306_p1) - unsigned(ti_b_cast3_cast_fu_267_p1));
tmp_1_fu_192_p2 <= "1" when (col_b_reg_101 = ap_const_lv2_3) else "0";
tmp_20_fu_336_p2 <= std_logic_vector(unsigned(tmp_17_reg_515) + unsigned(i_cast2_fu_332_p1));
tmp_21_fu_341_p1 <= tmp_20_fu_336_p2(9 - 1 downto 0);
tmp_22_fu_357_p2 <= std_logic_vector(unsigned(tmp_21_fu_341_p1) + unsigned(p_shl4_cast_fu_349_p3));
tmp_23_cast_fu_388_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_23_fu_383_p2),9));
tmp_23_fu_383_p2 <= std_logic_vector(unsigned(tmp_9_cast_cast_fu_380_p1) + unsigned(tmp_19_cast_reg_520));
tmp_24_fu_345_p1 <= tmp_20_fu_336_p2(7 - 1 downto 0);
tmp_25_fu_404_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_396_p3) - unsigned(tmp_23_cast_fu_388_p1));
tmp_26_cast_fu_419_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_26_fu_414_p2),64));
tmp_26_fu_414_p2 <= std_logic_vector(unsigned(tmp_22_reg_533) + unsigned(j_cast1_cast_fu_410_p1));
tmp_27_cast_fu_450_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_569),64));
tmp_27_fu_445_p2 <= std_logic_vector(unsigned(tmp_25_reg_551) + unsigned(tmp_2_cast_cast_fu_441_p1));
tmp_28_fu_392_p1 <= tmp_23_fu_383_p2(6 - 1 downto 0);
tmp_2_cast_cast_fu_441_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_fu_436_p2),9));
tmp_2_fu_436_p2 <= std_logic_vector(unsigned(col_b_cast_reg_477) + unsigned(j_reg_145));
tmp_3_fu_235_p2 <= "1" when (to_b_reg_112 = ap_const_lv2_3) else "0";
tmp_5_fu_320_p2 <= "1" when (ti_b_reg_123 = ap_const_lv2_3) else "0";
tmp_7_fu_363_p2 <= "1" when (i_reg_134 = ap_const_lv3_5) else "0";
tmp_8_fu_208_p3 <= (to_b_reg_112 & ap_const_lv2_0);
tmp_9_cast_cast_fu_380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_546),7));
tmp_9_fu_375_p2 <= std_logic_vector(unsigned(i_reg_134) + unsigned(row_b_cast_reg_459));
tmp_fu_172_p2 <= "1" when (row_b_reg_90 = ap_const_lv2_3) else "0";
tmp_s_fu_424_p2 <= "1" when (j_reg_145 = ap_const_lv3_5) else "0";
to_b_1_fu_241_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(to_b_reg_112));
to_b_cast4_cast_fu_204_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(to_b_reg_112),5));
end behav;
| mit | 3ffa282fd11a4ba15d08d9f650626812 | 0.595887 | 2.871789 | false | false | false | false |
khaledhassan/vhdl-examples | multiplexer/mux_4x1.vhd | 1 | 2,004 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Multiplexer 4:1
-- Implements a 4-to-1 multiplexer of a given width.
library ieee;
use ieee.std_logic_1164.all;
entity mux_4x1 is
generic (
WIDTH : positive := 1
);
port (
output : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector(1 downto 0);
in0 : in std_logic_vector(WIDTH-1 downto 0);
in1 : in std_logic_vector(WIDTH-1 downto 0);
in2 : in std_logic_vector(WIDTH-1 downto 0);
in3 : in std_logic_vector(WIDTH-1 downto 0)
);
end mux_4x1;
architecture BHV of mux_4x1 is
begin
output <=
in0 when sel = "00" else
in1 when sel = "01" else
in2 when sel = "10" else
in3 when sel = "11" else
(others => '0');
end BHV;
| mit | ee80b6fd1b7b8398e7fa213fc256cd01 | 0.683134 | 3.846449 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/srmmu/libmmu.vhd | 1 | 11,294 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
subtype mmu_gpsz_typ is integer range 0 to 3;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
--# fault, todo: should we flush on a fault?
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
variable pagesize : integer range 0 to 3;
begin
--# merge data
transdata := (others => '0');
pagesize := MMU_getpagesize(mmupgsz, mmctrl);
case pagesize is
when 1 =>
-- 8k
case LVL is
when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 2 =>
-- 16k
case LVL is
when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 3 =>
-- 32k
case LVL is
when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when others =>
-- 4k
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ is
variable pagesize : mmu_gpsz_typ;
begin
if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
else pagesize := mmupgsz; end if;
return pagesize;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
| gpl-2.0 | 987f25fb1e318bcef05361fa3d530084 | 0.530104 | 3.57179 | false | false | false | false |
topazas/vhdl | b02.vhd | 2 | 1,643 | entity b02 is
port(reset : in bit;
clock : in bit;
linea : in bit;
u : out bit
);
end b02;
Architecture BEHAV of b02 is
constant A:integer:=0;
constant B:integer:=1;
constant C:integer:=2;
constant D:integer:=3;
constant E:integer:=4;
constant F:integer:=5;
constant G:integer:=6;
begin
process(reset,clock)
variable stato:integer range 6 downto 0;
begin
if reset='1' then
stato:=A;
u<='0';
elsif clock'event and clock='1' then
case stato is
when A =>
stato:=B;
u<='0';
when B =>
if linea='0' then
stato:=C;
else
stato:=F;
end if;
u<='0';
when C =>
if linea='0' then
stato:=D;
else
stato:=G;
end if;
u<='0';
when D =>
stato:=E;
u<='0';
when E =>
stato:=B;
u<='1';
when F =>
stato:=G;
u<='0';
when G =>
if linea='0' then
stato:=E;
else
stato:=A;
end if;
u<='0';
end case;
end if;
end process;
end BEHAV;
| mit | 95c313c62e35155e64ecd5ac217ddcc7 | 0.317712 | 4.846608 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/dma2ahb_tp.vhd | 1 | 67,479 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_TestPackage (package declaration)
--
-- File name : dma2ahb_tp.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 New package
-- 1.5 SH 1 Sep 2005 New library TOPNET
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
-- 1.9 SH 4 Jan 2006 Burst routines added
-- Fault reporting priority and timing improved
-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
-- Adjusted printouts
-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.4 MI 4 Aug 2008 Support for Lock
-- 1.9.5 SH 4 Mar 2011 Modifed burst accesses to mimic real hw
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDIO.all;
use GRLIB.DMA2AHB_Package.all;
use GRLIB.STDLIB.all;
package DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Vector of words
-----------------------------------------------------------------------------
type Data_Vector is array (Natural range <> ) of
Std_Logic_Vector(32-1 downto 0);
-----------------------------------------------------------------------------
-- Constants for comparison
-----------------------------------------------------------------------------
constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
----------------------------------------------------------------------------
-- Constant for calculating burst lengths
----------------------------------------------------------------------------
constant WordSize: integer := 32;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
end package DMA2AHB_TestPackage;
package body DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Std_Logic_Vector(
constant i: Integer;
w: Integer)
return Std_Logic_Vector is
variable tmp: Std_Logic_Vector(w-1 downto 0);
begin
tmp := Std_Logic_Vector(To_UnSigned(i, w));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Integer(
constant i: Std_Logic_Vector)
return Integer is
variable tmp: Integer;
begin
tmp := To_Integer(UnSigned(i));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clock: in Std_ULogic;
constant Offset: in Time := 5 ns;
constant Enable: in Boolean := True) is
begin
if Enable then
wait until Clock = '1'; -- synchronise
if Offset > 0 ns then
wait for Offset; -- output offset delay
end if;
end if;
end procedure Synchronise;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
dmai.Size <= "10";
dmai.Lock <= '0';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure DMAInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '1';
dmai.Data <= Data;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Data <= Data;
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Data := (others => 'X');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
Data := dmao.Data;
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Data := Temp;
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure DMARead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
Write (L, String'(" : expected: "));
HWrite(L, CxData);
Write (L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure DMAComp;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWriteQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWrite16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMAQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMARead16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1)='0' then
TmpCx := CxData & "----------------";
else
TmpCx := "----------------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
RxData := TmpRx(31 downto 16);
else
RxData := TmpRx(15 downto 0);
end if;
end procedure DMAComp16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWriteQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWrite8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMAQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMARead8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1 downto 0)="00" then
TmpCx := CxData & "--------" & "--------" & "--------";
elsif Address(1 downto 0)="01" then
TmpCx := "--------" & CxData & "--------" & "--------";
elsif Address(1 downto 0)="10" then
TmpCx := "--------" & "--------" & CxData & "--------";
else
TmpCx := "--------" & "--------" & "--------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
RxData := TmpRx(31 downto 24);
elsif Address(1 downto 0)="01" then
RxData := TmpRx(23 downto 16);
elsif Address(1 downto 0)="10" then
RxData := TmpRx(15 downto 8);
else
RxData := TmpRx( 7 downto 0);
end if;
end procedure DMAComp8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '1';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
-- first data
if Size=32 then
dmai.Data <= Data(0);
elsif Size=16 then
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
elsif Size=8 then
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
Data(0)(31 downto 24) & Data(0)(31 downto 24);
end if;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
Synchronise(HCLK, 0 ns);
exit;
elsif dmao.OKAY='1' then
-- for each OKAY, provide new data
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
while dmao.Ready='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if GCount/=0 then
report "DMAWriteQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
if Size=32 then
dmai.Data <= Data(DCount);
elsif Size=16 then
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
elsif Size=8 then
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
end if;
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end loop;
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWriteBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
variable DataPart: Integer := 0;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '0';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
if Address(1 downto 0) = "00" then
DataPart := 0;
else
DataPart := 1;
end if;
elsif Size=8 then
dmai.Size <= HSIZE8;
if Address(1 downto 0) = "00" then
DataPart := 0;
elsif Address(1 downto 0) = "01" then
DataPart := 1;
elsif Address(1 downto 0) = "10" then
DataPart := 2;
else
DataPart := 3;
end if;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response"));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
-- for each READY, store data
if Size=32 then
Data(DCount-1) := dmao.Data;
elsif Size=16 then
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
DataPart := (DataPart + 1) mod 2;
elsif Size=8 then
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
DataPart := (DataPart + 1) mod 4;
end if;
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
if GCount/=0 then
report "DMAQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Data_Vector(0 to Data'Length-1);
begin
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
Data := Temp;
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Temp(i));
WriteLine(Output, L);
end loop;
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Temp := (others => (others => '-'));
Data := Temp;
TP := False;
end if;
end procedure DMAReadBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Data_Vector(0 to CxData'Length-1);
begin
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
Data := (others => (others => '-'));
RxData := Data;
else
for i in 0 to Data'Length-1 loop
if not Compare(Data(i), CxData(i)) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
Write(L, String'(" : expected: "));
HWrite(L, CxData(i));
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end if;
end loop;
RxData := Data;
end if;
end procedure DMACompBurst;
end package body DMA2AHB_TestPackage; --======================================--
| gpl-2.0 | 639d84b15fd531db63b568f0561ab663 | 0.447176 | 4.716173 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-cpci-xc2v6000/testbench.vhd | 1 | 19,150 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := 'L';
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to 1);
can_rxd : in std_logic_vector(0 to 1);
can_stb : out std_logic_vector(0 to 1);
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal gtx_clk : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to 1);
signal can_rxd : std_logic_vector(0 to 1);
signal can_stb : std_logic_vector(0 to 1);
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => '1');
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_rxd, spw_rxdn, spw_rxs, spw_rxsn,
spw_txd, spw_txdn, spw_txs, spw_txsn);
-- optional sdram
sd0 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN = 1) and (CFG_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 6d2fbf84e866cc39cb88aa6b272e1086 | 0.568982 | 3.038236 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl | 1 | 719,637 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:16 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
\s_axi_arready[0]\ : out STD_LOGIC;
aa_mi_arvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_axi.read_cnt_reg[5]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
mi_arready_2 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC;
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_araddr[30]\ : in STD_LOGIC;
\s_axi_araddr[28]\ : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
\m_payload_i_reg[34]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \^gen_axi.s_axi_rid_i_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_valid_i_reg_0\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[16]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair6";
begin
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_axi.s_axi_rid_i_reg[11]\(0) <= \^gen_axi.s_axi_rid_i_reg[11]\(0);
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0);
\gen_no_arbiter.m_valid_i_reg_0\ <= \^gen_no_arbiter.m_valid_i_reg_0\;
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => mi_arready_2,
I3 => p_15_in,
O => E(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \gen_axi.read_cnt_reg[5]\,
I1 => p_15_in,
I2 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
I3 => \^m_axi_arqos[7]\(44),
I4 => \^m_axi_arqos[7]\(45),
I5 => \^m_axi_arqos[7]\(47),
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^m_axi_arqos[7]\(49),
I1 => p_15_in,
I2 => \^m_axi_arqos[7]\(48),
I3 => \^m_axi_arqos[7]\(46),
I4 => \^m_axi_arqos[7]\(51),
I5 => \^m_axi_arqos[7]\(50),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\,
I1 => \m_payload_i_reg[34]\,
I2 => r_issuing_cnt(0),
I3 => r_issuing_cnt(1),
I4 => r_issuing_cnt(2),
I5 => r_issuing_cnt(3),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(3),
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \m_payload_i_reg[34]\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(4),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I1 => \m_payload_i_reg[34]_0\,
I2 => r_issuing_cnt(4),
I3 => r_issuing_cnt(5),
I4 => r_issuing_cnt(6),
I5 => r_issuing_cnt(7),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(7),
I1 => r_issuing_cnt(6),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(4),
I4 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => aa_mi_artarget_hot(1),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080808080808080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
I2 => m_axi_arready(1),
I3 => s_axi_rready(0),
I4 => m_valid_i_reg,
I5 => Q(0),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => mi_arready_2,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => \^aa_mi_arvalid\,
O => \^gen_no_arbiter.m_valid_i_reg_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[7]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[7]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[7]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[7]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[7]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[7]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[7]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[7]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[7]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[7]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[7]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[7]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[7]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[7]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[7]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[7]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[7]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[7]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[7]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[7]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[7]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[7]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[7]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[7]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[7]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[7]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[7]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[7]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[7]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[7]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[7]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[7]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[7]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[7]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[7]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[7]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[7]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[7]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[7]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[7]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[7]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[7]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[7]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[7]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[7]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[7]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[7]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[7]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[7]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[7]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[7]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[7]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[7]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[7]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[7]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[7]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[7]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[7]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[7]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[7]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[7]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[7]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[7]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[7]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[7]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[7]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[7]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[7]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[7]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \s_axi_arqos[3]\(33),
I1 => \s_axi_arqos[3]\(36),
I2 => \s_axi_araddr[30]\,
I3 => \s_axi_araddr[28]\,
I4 => \s_axi_araddr[25]\,
O => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^gen_axi.s_axi_rid_i_reg[11]\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000002A"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I4 => \^gen_no_arbiter.m_valid_i_reg_0\,
I5 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFEFFFEFFFFF"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I1 => \^aa_mi_arvalid\,
I2 => s_axi_arvalid(0),
I3 => \^s_axi_arready[0]\,
I4 => \chosen_reg[0]\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\,
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^s_axi_arready[0]\,
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
O => m_axi_arvalid(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
aa_mi_awtarget_hot : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[9]\ : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
st_aa_awtarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\chosen_reg[1]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[0]\ : in STD_LOGIC;
mi_awready_2 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC;
\s_axi_awaddr[20]\ : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^aa_mi_awtarget_hot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \^gen_master_slots[1].w_issuing_cnt_reg[9]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal \^st_aa_awtarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[9]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair12";
begin
aa_mi_awtarget_hot(2 downto 0) <= \^aa_mi_awtarget_hot\(2 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
\gen_master_slots[1].w_issuing_cnt_reg[9]\ <= \^gen_master_slots[1].w_issuing_cnt_reg[9]\;
\m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\;
ss_aa_awready <= \^ss_aa_awready\;
st_aa_awtarget_hot(0) <= \^st_aa_awtarget_hot\(0);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(2),
I3 => mi_awready_2,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \chosen_reg[0]\,
I2 => m_axi_awready(0),
I3 => \^aa_mi_awtarget_hot\(0),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\,
I1 => w_issuing_cnt(3),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(2),
I4 => w_issuing_cnt(1),
I5 => \chosen_reg[0]\,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(0),
I3 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \chosen_reg[0]\,
I1 => m_axi_awready(0),
I2 => \^aa_mi_awtarget_hot\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(1),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\,
I1 => w_issuing_cnt(7),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(6),
I4 => w_issuing_cnt(5),
I5 => \chosen_reg[1]\,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(7),
I1 => w_issuing_cnt(4),
I2 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(1),
I3 => m_axi_awready(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_bready(0),
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_sa_awvalid\,
I5 => m_ready_d(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \chosen_reg[1]\,
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[1].w_issuing_cnt[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => m_ready_d(1),
O => \^gen_master_slots[1].w_issuing_cnt_reg[9]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\,
I1 => \s_axi_awaddr[26]\,
I2 => \s_axi_awaddr[20]\,
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
O => \^st_aa_awtarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(31),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(39),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => Q(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => Q(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => Q(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => Q(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => Q(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => Q(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => Q(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => Q(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => Q(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => Q(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => Q(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => Q(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => Q(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => Q(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => Q(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => Q(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => Q(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => Q(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => Q(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => Q(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => Q(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => Q(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => Q(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => Q(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => Q(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => Q(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => Q(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => Q(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => Q(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => Q(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => Q(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => Q(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => Q(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => Q(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => Q(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => Q(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => Q(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => Q(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => Q(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => Q(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => Q(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => Q(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => Q(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => Q(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => Q(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => Q(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => Q(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => Q(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => Q(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => Q(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => Q(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => Q(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => Q(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => Q(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => Q(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => Q(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => Q(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => Q(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => Q(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => Q(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => Q(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => Q(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => Q(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => Q(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => Q(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => Q(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => Q(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => Q(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => Q(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^st_aa_awtarget_hot\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^aa_mi_awtarget_hot\(2),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I2 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => m_ready_d(0),
I4 => \^m_ready_d_reg[1]\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^ss_aa_awready\,
I1 => m_ready_d_0(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(1),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(1)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555554FFFFFFFF"
)
port map (
I0 => \^m_ready_d_reg[1]\,
I1 => m_ready_d(0),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_mi_awtarget_hot\(0),
I5 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_mi_awtarget_hot\(2),
I2 => \^aa_mi_awtarget_hot\(1),
I3 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000777"
)
port map (
I0 => m_axi_awready(1),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => mi_awready_2,
I3 => \^aa_mi_awtarget_hot\(2),
I4 => \m_ready_d[1]_i_4_n_0\,
I5 => m_ready_d(1),
O => \^m_ready_d_reg[1]\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_awready(0),
I1 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
\chosen_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : out STD_LOGIC;
aresetn_d : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ : in STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_5\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \chosen[0]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1__0_n_0\ : STD_LOGIC;
signal \^chosen_reg[0]_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_master_slots[0].w_issuing_cnt_reg[1]\ : STD_LOGIC;
signal \^gen_master_slots[2].w_issuing_cnt_reg[16]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_6_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \chosen[2]_i_1__0\ : label is "soft_lutpair112";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_6\ : label is "soft_lutpair111";
begin
SR(0) <= \^sr\(0);
\chosen_reg[0]_0\ <= \^chosen_reg[0]_0\;
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[1]\;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ <= \^gen_master_slots[2].w_issuing_cnt_reg[16]\;
m_valid_i <= \^m_valid_i\;
\chosen[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^chosen_reg[0]_0\,
O => \chosen[0]_i_1__0_n_0\
);
\chosen[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1__0_n_0\
);
\chosen[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \chosen[2]_i_1__0_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1__0_n_0\,
Q => \^chosen_reg[0]_0\,
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1__0_n_0\,
Q => \^chosen_reg[1]_0\,
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1__0_n_0\,
Q => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
R => \^sr\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^chosen_reg[0]_0\,
I1 => p_80_out,
I2 => s_axi_bready(0),
O => \^gen_master_slots[0].w_issuing_cnt_reg[1]\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[1]_0\,
I2 => p_60_out,
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F7F00"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => s_axi_bready(0),
I3 => \m_ready_d_reg[1]_5\,
I4 => w_issuing_cnt(4),
O => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A956"
)
port map (
I0 => Q(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFF1100E"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE00000000FFFF"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AAAAAAAA999A"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \m_ready_d_reg[1]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_4\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_3\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_2\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \m_ready_d_reg[1]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AAAA80AA80AA80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[0]_0\,
I2 => p_80_out,
I3 => m_valid_i_reg,
I4 => p_38_out,
I5 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"1FFF1000"
)
port map (
I0 => \s_axi_awaddr[26]\(0),
I1 => st_aa_awtarget_hot(0),
I2 => \^m_valid_i\,
I3 => aresetn_d,
I4 => aa_mi_awtarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F022"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \s_axi_awaddr[26]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF40FFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I1 => Q(3),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => aa_sa_awvalid,
I4 => s_axi_awvalid(0),
I5 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => \^gen_master_slots[0].w_issuing_cnt_reg[1]\,
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(0),
I4 => w_issuing_cnt(3),
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEFEFAAEAEA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => st_aa_awtarget_hot(0),
I3 => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
I4 => \s_axi_awaddr[26]\(0),
I5 => \gen_master_slots[2].w_issuing_cnt_reg[16]_1\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1_n_0\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEE00000FEE"
)
port map (
I0 => p_60_out,
I1 => p_38_out,
I2 => \^chosen_reg[0]_0\,
I3 => p_80_out,
I4 => \last_rr_hot[2]_i_6_n_0\,
I5 => s_axi_bready(0),
O => need_arbitration
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_38_out,
I1 => p_60_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_80_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_60_out,
I1 => p_3_in,
I2 => p_80_out,
I3 => p_38_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_80_out,
I1 => p_4_in,
I2 => p_38_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_60_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
O => \last_rr_hot[2]_i_6_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1_n_0\,
Q => p_3_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1_n_0\,
Q => p_4_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
I4 => p_80_out,
I5 => \^chosen_reg[0]_0\,
O => s_axi_bvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.accept_cnt_reg[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\m_payload_i_reg[34]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_5\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
signal \chosen[0]_i_1_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1_n_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_multi_thread.accept_cnt_reg[2]\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[34]\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \chosen[2]_i_1\ : label is "soft_lutpair79";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_3\ : label is "soft_lutpair78";
begin
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_multi_thread.accept_cnt_reg[2]\ <= \^gen_multi_thread.accept_cnt_reg[2]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i_reg[34]\ <= \^m_payload_i_reg[34]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\chosen[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[0]_0\,
O => \chosen[0]_i_1_n_0\
);
\chosen[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1_n_0\
);
\chosen[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[34]\,
O => \chosen[2]_i_1_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1_n_0\,
Q => \^chosen_reg[1]_0\,
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1_n_0\,
Q => \^m_payload_i_reg[34]\,
R => SR(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A659"
)
port map (
I0 => Q(0),
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFF4400B"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[2]\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \^gen_multi_thread.accept_cnt_reg[2]\,
I5 => \gen_no_arbiter.s_ready_i_reg[0]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAA9A99"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_5\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_4\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => CO(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => E(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_3\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_2\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8880000"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => s_axi_rready(0),
O => \^gen_multi_thread.accept_cnt_reg[2]\
);
\i__carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(9),
I2 => \m_payload_i_reg[46]_0\(22),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(22),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(5),
I2 => \m_payload_i_reg[46]_0\(18),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(18),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(17),
I2 => \m_payload_i_reg[46]_1\(4),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]_0\(17),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(19),
I2 => \m_payload_i_reg[46]_1\(6),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(19),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(2),
I2 => \m_payload_i_reg[46]_0\(15),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(15),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(14),
I2 => \m_payload_i_reg[46]_1\(1),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(14),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(3),
I2 => \m_payload_i_reg[46]_0\(16),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(16),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_16_n_0\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0)
);
\i__carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(11),
I2 => \m_payload_i_reg[46]\(24),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(24),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(23),
I2 => \m_payload_i_reg[46]_1\(10),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(23),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(25),
I2 => \m_payload_i_reg[46]_1\(12),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(25),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(8),
I2 => \m_payload_i_reg[46]_0\(21),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(21),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(7),
I2 => \m_payload_i_reg[46]_0\(20),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(20),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_9_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1__0_n_0\
);
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBABBBABBBAB88"
)
port map (
I0 => s_axi_rready(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => p_54_out,
I5 => p_32_out,
O => need_arbitration
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_32_out,
I1 => p_54_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_74_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_54_out,
I1 => p_3_in,
I2 => p_74_out,
I3 => p_32_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_74_out,
I1 => p_4_in,
I2 => p_32_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_54_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1__0_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1__0_n_0\,
Q => p_3_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1__0_n_0\,
Q => p_4_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B3"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_74_out,
I2 => s_axi_rready(0),
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_rready(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
O => \m_payload_i_reg[34]_0\(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \i__carry_i_7_n_0\,
O => S(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \i__carry_i_10_n_0\,
O => S(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \i__carry_i_13_n_0\,
O => S(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \i__carry_i_16_n_0\,
O => S(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(14),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(1),
I4 => \m_payload_i_reg[46]_0\(14),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(0)
);
\s_axi_rid[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(24),
I2 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I3 => \m_payload_i_reg[46]\(24),
I4 => \m_payload_i_reg[46]_1\(11),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(10)
);
\s_axi_rid[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(25),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(12),
I4 => \m_payload_i_reg[46]_0\(25),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(11)
);
\s_axi_rid[11]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_1_n_0\
);
\s_axi_rid[11]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^chosen_reg[1]_0\,
I1 => p_54_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_32_out,
O => \s_axi_rid[11]_INST_0_i_2_n_0\
);
\s_axi_rid[11]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_3_n_0\
);
\s_axi_rid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(15),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(15),
I4 => \m_payload_i_reg[46]_1\(2),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(1)
);
\s_axi_rid[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(16),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(16),
I4 => \m_payload_i_reg[46]_1\(3),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(2)
);
\s_axi_rid[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(17),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(4),
I4 => \m_payload_i_reg[46]\(17),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => s_axi_rid(3)
);
\s_axi_rid[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(18),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(18),
I4 => \m_payload_i_reg[46]_1\(5),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(4)
);
\s_axi_rid[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(19),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(6),
I4 => \m_payload_i_reg[46]_0\(19),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(5)
);
\s_axi_rid[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(20),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(20),
I4 => \m_payload_i_reg[46]_1\(7),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(6)
);
\s_axi_rid[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(21),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(21),
I4 => \m_payload_i_reg[46]_1\(8),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(7)
);
\s_axi_rid[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(22),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(22),
I4 => \m_payload_i_reg[46]_1\(9),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(8)
);
\s_axi_rid[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(23),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(10),
I4 => \m_payload_i_reg[46]_0\(23),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(9)
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(0),
I2 => \m_payload_i_reg[46]\(13),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(13),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \^s_axi_rlast\(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FEAEAEA00EAEAEA"
)
port map (
I0 => \m_payload_i_reg[46]\(12),
I1 => p_32_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_54_out,
I4 => \^chosen_reg[1]_0\,
I5 => \m_payload_i_reg[46]_0\(12),
O => s_axi_rresp(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => p_54_out,
I1 => \^chosen_reg[1]_0\,
I2 => p_32_out,
I3 => \^m_payload_i_reg[34]\,
I4 => \^m_payload_i_reg[0]_0\,
I5 => p_74_out,
O => s_axi_rvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_2 : out STD_LOGIC;
p_14_in : out STD_LOGIC;
p_21_in : out STD_LOGIC;
p_15_in : out STD_LOGIC;
p_17_in : out STD_LOGIC;
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_2 : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
mi_rready_2 : in STD_LOGIC;
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
mi_bready_2 : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_arready_2\ : STD_LOGIC;
signal \^mi_awready_2\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_14_in\ : STD_LOGIC;
signal \^p_15_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal \^p_21_in\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair15";
begin
\gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\;
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
mi_arready_2 <= \^mi_arready_2\;
mi_awready_2 <= \^mi_awready_2\;
p_14_in <= \^p_14_in\;
p_15_in <= \^p_15_in\;
p_17_in <= \^p_17_in\;
p_21_in <= \^p_21_in\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \^p_15_in\,
I3 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9FFA900"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \^p_15_in\,
I4 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9FFFFAAA90000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
I4 => \^p_15_in\,
I5 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACAFAFACACACACA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_15_in\,
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt[4]_i_2_n_0\,
I5 => \gen_axi.read_cnt_reg__0\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3CAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^p_15_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE2E22E2"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \^p_15_in\,
I2 => \gen_axi.read_cnt[7]_i_3_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(5),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B874B8"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I3 => \gen_axi.read_cnt[7]_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg__0\(5),
I5 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(4),
I4 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FF80FF80FF80"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_15_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_2\,
I1 => \^p_15_in\,
I2 => mi_rready_2,
I3 => \^gen_axi.s_axi_arready_i_reg_0\,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
O => \^gen_axi.s_axi_arready_i_reg_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_2\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7F70F000F0F"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_reg\,
I1 => aa_mi_awtarget_hot(0),
I2 => write_cs(0),
I3 => mi_bready_2,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready_2\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_2\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \^mi_awready_2\,
I3 => aa_mi_awtarget_hot(0),
I4 => aa_sa_awvalid,
I5 => m_ready_d(0),
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => Q(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => Q(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => Q(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => Q(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => Q(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => Q(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => Q(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => Q(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => Q(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => Q(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => Q(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => Q(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFA888"
)
port map (
I0 => \storage_data1_reg[0]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => mi_bready_2,
I4 => \^p_21_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_21_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBA8888888A"
)
port map (
I0 => s_axi_rlast_i0,
I1 => E(0),
I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I5 => \^p_17_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \gen_axi.read_cnt_reg__0\(5),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^p_15_in\,
I1 => mi_rready_2,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF0202"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
I4 => \^p_14_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_14_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0252"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF10FA10"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => mi_bready_2,
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
ss_wr_awvalid : out STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair141";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"111F"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \gen_multi_thread.accept_cnt_reg[3]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030000000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000EC00000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_aa_awready,
I1 => \^m_ready_d\(0),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(1),
O => s_axi_awready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[0]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEEEEEC"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(0),
I2 => aa_mi_awtarget_hot(2),
I3 => aa_mi_awtarget_hot(1),
I4 => aa_mi_awtarget_hot(0),
I5 => \m_ready_d_reg[0]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(1),
I2 => aresetn_d,
I3 => \m_ready_d_reg[0]_0\,
I4 => \gen_no_arbiter.m_target_hot_i_reg[1]\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => \storage_data1_reg[0]\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC;
signal \^gen_rep[0].fifoaddr_reg[0]\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_rep[0].fifoaddr_reg[0]\ <= \^gen_rep[0].fifoaddr_reg[0]\;
push <= \^push\;
s_ready_i_reg <= \^s_ready_i_reg\;
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \FSM_onehot_state[3]_i_6_n_0\,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => m_avalid,
O => \^gen_rep[0].fifoaddr_reg[0]\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F035FF35"
)
port map (
I0 => m_axi_wready(0),
I1 => p_14_in,
I2 => \storage_data1_reg[1]_0\,
I3 => \storage_data1_reg[0]\,
I4 => m_axi_wready(1),
O => \FSM_onehot_state[3]_i_6_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg\,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0DFFFFFFDDFFFF"
)
port map (
I0 => out0(1),
I1 => \^gen_rep[0].fifoaddr_reg[0]\,
I2 => s_ready_i_reg_0,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => out0(0),
O => \^s_ready_i_reg\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F011FFFFF0110000"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => st_aa_awtarget_hot(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => \storage_data1_reg[1]_0\,
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_2\ : STD_LOGIC;
signal \s_axi_bid[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 35 downto 24 );
begin
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_2 <= \^mi_bready_2\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => w_issuing_cnt(0),
I1 => s_axi_bready(0),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(8),
Q => st_mr_bid(32),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(9),
Q => st_mr_bid(33),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(10),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(11),
Q => st_mr_bid(35),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(0),
Q => st_mr_bid(24),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(1),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(2),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(3),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(4),
Q => st_mr_bid(28),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(5),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(6),
Q => st_mr_bid(30),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(7),
Q => st_mr_bid(31),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_21_in,
I1 => \^mi_bready_2\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
O => \m_valid_i_i_1__1_n_0\
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => S(0)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_bid[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(0),
I1 => st_mr_bid(24),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(6)
);
\s_axi_bid[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(6),
I1 => st_mr_bid(35),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(13),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bid[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(1),
I1 => st_mr_bid(28),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[6]_INST_0_i_1_n_0\,
O => s_axi_bid(2)
);
\s_axi_bid[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(2),
I1 => st_mr_bid(30),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(9),
O => \s_axi_bid[6]_INST_0_i_1_n_0\
);
\s_axi_bid[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
O => s_axi_bid(3)
);
\s_axi_bid[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(3),
I1 => st_mr_bid(31),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(10),
O => \s_axi_bid[7]_INST_0_i_1_n_0\
);
\s_axi_bid[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => s_axi_bid(4)
);
\s_axi_bid[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5303030F53F3F3F"
)
port map (
I0 => st_mr_bid(32),
I1 => \m_payload_i_reg[13]_0\(11),
I2 => m_valid_i_reg_1,
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
I5 => \m_payload_i_reg[13]_0\(4),
O => \s_axi_bid[8]_INST_0_i_1_n_0\
);
\s_axi_bid[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(5)
);
\s_axi_bid[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(5),
I1 => st_mr_bid(33),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(12),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_21_in,
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^mi_bready_2\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
signal \^gen_multi_thread.accept_cnt_reg[3]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 22 downto 13 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi_bid[11]_INST_0_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair44";
begin
\gen_multi_thread.accept_cnt_reg[3]\ <= \^gen_multi_thread.accept_cnt_reg[3]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\;
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000700000000"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[3]\,
I1 => s_axi_bready(0),
I2 => Q(2),
I3 => Q(1),
I4 => Q(0),
I5 => Q(3),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => st_mr_bmesg(3),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(12),
Q => st_mr_bid(22),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => st_mr_bmesg(4),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => st_mr_bid(13),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => st_mr_bid(14),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => st_mr_bid(15),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(1),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => st_mr_bid(17),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(3),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \^m_payload_i_reg[0]_0\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
\s_axi_bid[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
O => s_axi_bid(4)
);
\s_axi_bid[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(4),
I1 => st_mr_bid(22),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(9),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\
);
\s_axi_bid[11]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => chosen(0),
O => \^gen_multi_thread.accept_cnt_reg[3]\
);
\s_axi_bid[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(0),
I1 => st_mr_bid(13),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(5),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(14),
I1 => \m_payload_i_reg[12]_0\(1),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(6),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(2)
);
\s_axi_bid[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(15),
I1 => \m_payload_i_reg[12]_0\(2),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_axi_bid[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(3)
);
\s_axi_bid[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(3),
I1 => st_mr_bid(17),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FBFBFBF3F808080"
)
port map (
I0 => st_mr_bmesg(3),
I1 => chosen(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => chosen(1),
I4 => p_38_out,
I5 => \m_payload_i_reg[1]_0\(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CCCFAAAFAAAFAAA"
)
port map (
I0 => \m_payload_i_reg[1]_0\(1),
I1 => st_mr_bmesg(4),
I2 => chosen(1),
I3 => p_38_out,
I4 => \^m_payload_i_reg[0]_0\,
I5 => chosen(0),
O => s_axi_bresp(1)
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \aresetn_d_reg[1]_1\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__0_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => chosen(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => s_axi_bready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair69";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"955555552AAAAAAA"
)
port map (
I0 => \gen_axi.s_axi_arready_i_reg\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I5 => r_issuing_cnt(0),
O => \gen_master_slots[2].r_issuing_cnt_reg[16]\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FF2020000F202"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\,
I2 => st_aa_artarget_hot(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I4 => st_aa_artarget_hot(1),
I5 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_17_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => chosen_0(0),
I2 => \^m_valid_i_reg_0\,
I3 => p_15_in,
I4 => \^skid_buffer_reg[34]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => p_15_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => s_axi_rready(0),
I3 => chosen_0(0),
I4 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_17_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 25 downto 0 );
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 35 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_valid_i_i_1__3\ : label is "soft_lutpair45";
begin
\gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
I1 => \^s_ready_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \^gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => chosen_0(0),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(1),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(2),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3),
I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
O => p_1_in_0
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(67),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(68),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF2AFFFF"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[1]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(50),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(51),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(52),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(53),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(54),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(55),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(56),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(39),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(59),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(12),
O => s_axi_rdata(12)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(61),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(13),
O => s_axi_rdata(13)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(62),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(14),
O => s_axi_rdata(14)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(63),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(15),
O => s_axi_rdata(15)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(64),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(16),
O => s_axi_rdata(16)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(66),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(17),
O => s_axi_rdata(17)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(67),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(18),
O => s_axi_rdata(18)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(40),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(68),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(19),
O => s_axi_rdata(19)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(41),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(43),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(45),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFACCCACCCACCC"
)
port map (
I0 => st_mr_rmesg(35),
I1 => \m_payload_i_reg[32]_0\(20),
I2 => \^s_ready_i_reg_0\,
I3 => chosen_0(0),
I4 => p_32_out,
I5 => chosen_0(1),
O => s_axi_rresp(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F4F4F"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[1]\,
I2 => \^s_ready_i_reg_0\,
I3 => s_axi_rready(0),
I4 => chosen_0(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair39";
begin
\gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => s_axi_rready(0),
I2 => \^m_valid_i_reg_0\,
I3 => chosen_0(0),
O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(2),
I3 => Q(3),
I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4CFFFF"
)
port map (
I0 => chosen_0(0),
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_rready(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[0]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF44FF"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[0]\,
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => s_axi_rready(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_artarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\s_axi_araddr[25]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\s_axi_araddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_0\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_1\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_20\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_21\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_22\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_23\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_24\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_25\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_26\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_27\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_28\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_29\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_30\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_31\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_32\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_33\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_34\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_35\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_36\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_37\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_38\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_39\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_40\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_41\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_42\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_43\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_44\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_45\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_46\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_47\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_48\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_49\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_50\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_51\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_6\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_7\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_8\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_artarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_24__0\ : label is "soft_lutpair99";
begin
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\;
m_valid_i <= \^m_valid_i\;
st_aa_artarget_hot(0) <= \^st_aa_artarget_hot\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I3 => \s_axi_araddr[31]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_araddr[31]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I3 => \s_axi_araddr[31]\(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I5 => \s_axi_araddr[31]\(6),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I3 => \s_axi_araddr[31]\(5),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I3 => \s_axi_araddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I5 => \s_axi_araddr[31]\(1),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(5),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
I2 => \s_axi_araddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_1\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
port map (
CO(0) => p_8_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_0\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_1\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_2\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\,
SR(0) => SR(0),
aclk => aclk,
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_multi_thread.accept_cnt_reg[2]\ => \gen_multi_thread.accept_cnt_reg[2]_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_27\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_31\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_35\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_8\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_7\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_43\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_6\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_47\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.arbiter_resp_inst_n_5\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_51\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]_1\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_2\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_3\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_4\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_5\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[0]_0\ => chosen(0),
\m_payload_i_reg[34]\ => chosen(2),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[46]\(25 downto 0) => \m_payload_i_reg[46]\(25 downto 0),
\m_payload_i_reg[46]_0\(25 downto 0) => \m_payload_i_reg[46]_0\(25 downto 0),
\m_payload_i_reg[46]_1\(12 downto 0) => \m_payload_i_reg[46]_1\(12 downto 0),
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid(0) => s_axi_rvalid(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0088888888"
)
port map (
I0 => aid_match_00,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8FFFFFFFF"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_artarget_hot\(0),
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF55FF55CF55FF55"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3B080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I4 => aid_match_10,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_artarget_hot\(0),
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_20,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_artarget_hot\(0),
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
I4 => aid_match_00,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A3A0A0A0A"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => aid_match_30,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => aid_match_10,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(57),
I2 => active_cnt(56),
I3 => active_cnt(58),
I4 => active_cnt(59),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(33),
I2 => active_cnt(32),
I3 => active_cnt(34),
I4 => active_cnt(35),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_artarget_hot\(0),
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(35),
I1 => active_cnt(34),
I2 => active_cnt(32),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545FFFFFFEFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I5 => aid_match_40,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_artarget_hot\(0),
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_50,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_artarget_hot\(0),
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000000"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => aid_match_60,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_artarget_hot\(0),
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(59),
I1 => active_cnt(58),
I2 => active_cnt(56),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \s_axi_araddr[31]\(17),
I1 => \s_axi_araddr[31]\(20),
I2 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\,
I3 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\,
I4 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\,
O => \^st_aa_artarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_araddr[31]\(13),
I1 => \s_axi_araddr[31]\(22),
I2 => \s_axi_araddr[31]\(15),
I3 => \s_axi_araddr[31]\(12),
I4 => \s_axi_araddr[31]\(14),
I5 => \s_axi_araddr[31]\(26),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(25),
I1 => \s_axi_araddr[31]\(27),
I2 => \s_axi_araddr[31]\(23),
I3 => \s_axi_araddr[31]\(24),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(18),
I1 => \s_axi_araddr[31]\(19),
I2 => \s_axi_araddr[31]\(16),
I3 => \s_axi_araddr[31]\(21),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_araddr[25]_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF5555CFFF5555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_artarget_hot\(0),
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F40"
)
port map (
I0 => \s_axi_araddr[25]_0\,
I1 => \^m_valid_i\,
I2 => aresetn_d,
I3 => \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDDFFFD"
)
port map (
I0 => aid_match_30,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(25),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"88880008"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(49),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_50,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(41),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(8),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I4 => aid_match_10,
I5 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010FF1010"
)
port map (
I0 => active_target(16),
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I2 => aid_match_20,
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => active_cnt(3),
I4 => active_cnt(2),
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(48),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F1000000"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[25]\(0),
I2 => active_target(32),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => \^st_aa_artarget_hot\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(49),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(17),
O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F007F7F7F7F7F7F"
)
port map (
I0 => active_target(33),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => aid_match_50,
I5 => active_target(41),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(3),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
I3 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000002F2"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
I2 => \^st_aa_artarget_hot\(0),
I3 => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I5 => \gen_no_arbiter.m_valid_i_reg\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000E00"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \s_axi_araddr[25]\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000111F"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I1 => active_target(9),
I2 => active_target(1),
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \s_axi_araddr[25]\(0),
I5 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => active_target(56),
I4 => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFAAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I5 => \s_axi_araddr[25]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F7F700F7F7F7F7"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => active_target(17),
I4 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(56),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_51\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_31\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_27\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_47\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_43\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_39\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_35\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : in STD_LOGIC;
\s_axi_awaddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_13\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_14\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_15\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_16\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_17\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_3\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_i_1_n_0 : STD_LOGIC;
signal p_10_out_carry_i_3_n_0 : STD_LOGIC;
signal p_10_out_carry_i_4_n_0 : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_i_1_n_0 : STD_LOGIC;
signal p_12_out_carry_i_3_n_0 : STD_LOGIC;
signal p_12_out_carry_i_4_n_0 : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_i_1_n_0 : STD_LOGIC;
signal p_14_out_carry_i_3_n_0 : STD_LOGIC;
signal p_14_out_carry_i_4_n_0 : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_i_1_n_0 : STD_LOGIC;
signal p_2_out_carry_i_3_n_0 : STD_LOGIC;
signal p_2_out_carry_i_4_n_0 : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_i_1_n_0 : STD_LOGIC;
signal p_4_out_carry_i_3_n_0 : STD_LOGIC;
signal p_4_out_carry_i_4_n_0 : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_i_1_n_0 : STD_LOGIC;
signal p_6_out_carry_i_3_n_0 : STD_LOGIC;
signal p_6_out_carry_i_4_n_0 : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_i_1_n_0 : STD_LOGIC;
signal p_8_out_carry_i_3_n_0 : STD_LOGIC;
signal p_8_out_carry_i_4_n_0 : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_awtarget_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_12\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_8__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_9__0\ : label is "soft_lutpair140";
begin
D(0) <= \^d\(0);
Q(2 downto 0) <= \^q\(2 downto 0);
SR(0) <= \^sr\(0);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\;
st_aa_awtarget_enc(0) <= \^st_aa_awtarget_enc\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^q\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^q\(2),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(9),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I3 => \s_axi_awaddr[31]\(10),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awaddr[31]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(6),
I1 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
I2 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
I3 => \s_axi_awaddr[31]\(8),
I4 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
I5 => \s_axi_awaddr[31]\(7),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I3 => \s_axi_awaddr[31]\(4),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awaddr[31]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I3 => \s_axi_awaddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I5 => \s_axi_awaddr[31]\(1),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
I4 => \s_axi_awaddr[31]\(7),
I5 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_3\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
CO(0) => p_0_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_2\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_3\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
SR(0) => \^sr\(0),
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[0]_0\ => chosen(0),
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_master_slots[0].w_issuing_cnt_reg[1]\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => chosen(2),
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].w_issuing_cnt_reg[16]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_17\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_16\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_15\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_14\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_13\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
\m_ready_d_reg[1]_0\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
\m_ready_d_reg[1]_1\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
\m_ready_d_reg[1]_2\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
\m_ready_d_reg[1]_3\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
\m_ready_d_reg[1]_4\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
\m_ready_d_reg[1]_5\ => \m_ready_d_reg[1]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[26]\(0) => \^st_aa_awtarget_enc\(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(6),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(7),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(8),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0500050035300500"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFFBBF0BBFFBB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_10,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08083B08"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDDFFDDF0DDFFDD"
)
port map (
I0 => aid_match_20,
I1 => \m_ready_d_reg[1]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"004400440F440044"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_30,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFFF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_10,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFAFAFAFACAFAF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(2),
I2 => active_cnt(3),
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAFFFFFACAFFCF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => aid_match_50,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => active_cnt(48),
I5 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\,
I1 => \s_axi_awaddr[31]\(17),
I2 => \s_axi_awaddr[31]\(20),
O => \^st_aa_awtarget_enc\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\,
I2 => \s_axi_awaddr[31]\(19),
I3 => \s_axi_awaddr[31]\(15),
I4 => \s_axi_awaddr[31]\(12),
I5 => \s_axi_awaddr[31]\(23),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awaddr[31]\(14),
I1 => \s_axi_awaddr[31]\(25),
I2 => \s_axi_awaddr[31]\(21),
I3 => \s_axi_awaddr[31]\(22),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \s_axi_awaddr[31]\(24),
I1 => \s_axi_awaddr[31]\(27),
I2 => \s_axi_awaddr[31]\(13),
I3 => \s_axi_awaddr[31]\(26),
I4 => \s_axi_awaddr[31]\(18),
I5 => \s_axi_awaddr[31]\(16),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^st_aa_awtarget_enc\(0),
I1 => st_aa_awtarget_hot(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(58),
I3 => active_cnt(59),
I4 => active_cnt(57),
I5 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(58),
I2 => active_cnt(59),
I3 => active_cnt(57),
I4 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(57),
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F100"
)
port map (
I0 => active_target(41),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(40),
I3 => aid_match_50,
I4 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_20,
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I2 => active_target(17),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(56),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(8),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I1 => aid_match_00,
I2 => active_target(1),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I1 => aid_match_30,
I2 => active_target(25),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => active_target(32),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I3 => active_target(8),
I4 => aid_match_10,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFB00FBFB"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => active_target(24),
I4 => aid_match_30,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(16),
I3 => active_target(0),
I4 => aid_match_00,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
I5 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(17),
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => aid_match_40,
I1 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I2 => active_target(33),
I3 => aid_match_70,
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
I5 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDF00DFDFDFDFDF"
)
port map (
I0 => active_target(41),
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => aid_match_50,
I3 => aid_match_10,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I5 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080FF8080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I2 => active_target(49),
I3 => aid_match_30,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(1),
I2 => \gen_multi_thread.accept_cnt_reg\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000DDD0"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004040400"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I4 => active_target(48),
I5 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => st_aa_awtarget_hot(0),
I1 => \^st_aa_awtarget_enc\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(32),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(33),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(48),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(49),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => \i__carry_i_4_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_1_n_0\,
S(2) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0),
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_10_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0),
S(1) => p_10_out_carry_i_3_n_0,
S(0) => p_10_out_carry_i_4_n_0
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_10_out_carry_i_1_n_0
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_10_out_carry_i_3_n_0
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_10_out_carry_i_4_n_0
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_12_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0),
S(1) => p_12_out_carry_i_3_n_0,
S(0) => p_12_out_carry_i_4_n_0
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_12_out_carry_i_1_n_0
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_12_out_carry_i_3_n_0
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_12_out_carry_i_4_n_0
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_14_out_carry_i_1_n_0,
S(2) => S(0),
S(1) => p_14_out_carry_i_3_n_0,
S(0) => p_14_out_carry_i_4_n_0
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_14_out_carry_i_1_n_0
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_14_out_carry_i_3_n_0
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_14_out_carry_i_4_n_0
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_2_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0),
S(1) => p_2_out_carry_i_3_n_0,
S(0) => p_2_out_carry_i_4_n_0
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_2_out_carry_i_1_n_0
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_2_out_carry_i_3_n_0
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_2_out_carry_i_4_n_0
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_4_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0),
S(1) => p_4_out_carry_i_3_n_0,
S(0) => p_4_out_carry_i_4_n_0
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_4_out_carry_i_1_n_0
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_4_out_carry_i_3_n_0
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_4_out_carry_i_4_n_0
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_6_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0),
S(1) => p_6_out_carry_i_3_n_0,
S(0) => p_6_out_carry_i_4_n_0
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_6_out_carry_i_1_n_0
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_6_out_carry_i_3_n_0
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_6_out_carry_i_4_n_0
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_8_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0),
S(1) => p_8_out_carry_i_3_n_0,
S(0) => p_8_out_carry_i_4_n_0
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_8_out_carry_i_1_n_0
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_8_out_carry_i_3_n_0
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_8_out_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
s_ready_i_reg_0 : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_3\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[0]\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[1]\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair142";
begin
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\/FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40440000"
)
port map (
I0 => p_9_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_0_in8_in,
O => \/FSM_onehot_state[0]_i_1_n_0\
);
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\/FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002A22"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_9_in,
O => \/FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I5 => fifoaddr(2),
O => p_0_in5_out
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => \gen_axi.write_cs_reg[1]_0\(0),
I3 => s_axi_wlast(0),
I4 => s_axi_wvalid(0),
I5 => m_avalid,
O => \gen_axi.write_cs_reg[1]\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C133DDFF3ECC2200"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \^s_ready_i_reg_0\,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFD5402A"
)
port map (
I0 => fifoaddr(0),
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFF77710000888"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_rep[0].fifoaddr_reg[0]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
load_s1 => load_s1,
m_avalid => m_avalid,
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(0) => m_ready_d(0),
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_14_in => p_14_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
s_ready_i_reg_0 => \^s_ready_i_reg_0\,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
\storage_data1_reg[0]\ => \storage_data1_reg_n_0_[0]\,
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
\storage_data1_reg[1]_0\ => \storage_data1_reg_n_0_[1]\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A8A008A0A800080"
)
port map (
I0 => m_avalid,
I1 => m_axi_wready(1),
I2 => \storage_data1_reg_n_0_[0]\,
I3 => \storage_data1_reg_n_0_[1]\,
I4 => p_14_in,
I5 => m_axi_wready(0),
O => s_axi_wready(0)
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFAAAAAAAA"
)
port map (
I0 => s_ready_i_i_2_n_0,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => fifoaddr(2),
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => areset_d1,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(0),
I3 => load_s1,
I4 => \storage_data1_reg_n_0_[0]\,
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888FFC88888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => p_0_in8_in,
I3 => p_9_in,
I4 => s_axi_awvalid(0),
I5 => m_ready_d(0),
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => \storage_data1_reg_n_0_[0]\,
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
Q => \storage_data1_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_80_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\
port map (
D(13 downto 0) => D(13 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_80_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
chosen_0(0) => chosen_0(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_74_out,
p_1_in => p_1_in,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_60_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_54_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\
port map (
D(13 downto 0) => D(13 downto 0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
chosen(1 downto 0) => chosen(1 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_multi_thread.accept_cnt_reg[3]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_60_out,
\m_payload_i_reg[12]_0\(9 downto 0) => \m_payload_i_reg[12]\(9 downto 0),
\m_payload_i_reg[1]_0\(1 downto 0) => \m_payload_i_reg[1]\(1 downto 0),
p_1_in => \^p_1_in\,
p_38_out => p_38_out,
s_axi_bid(4 downto 0) => s_axi_bid(4 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\
port map (
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
chosen_0(1 downto 0) => chosen_0(1 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].r_issuing_cnt_reg[11]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[32]_0\(20 downto 0) => \m_payload_i_reg[32]\(20 downto 0),
p_1_in => \^p_1_in\,
p_32_out => p_32_out,
s_axi_rdata(19 downto 0) => s_axi_rdata(19 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_ready_i_reg_0 => p_54_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_38_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
p_32_out : out STD_LOGIC;
mi_rready_2 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(4 downto 0) => Q(4 downto 0),
S(0) => S(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
\m_payload_i_reg[2]_0\ => p_38_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
m_valid_i_reg_1 => m_valid_i_reg_0,
mi_bready_2 => mi_bready_2,
p_1_in => p_1_in,
p_21_in => p_21_in,
s_axi_bid(6 downto 0) => s_axi_bid(6 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg,
w_issuing_cnt(0) => w_issuing_cnt(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
chosen_0(0) => chosen_0(0),
\gen_axi.s_axi_arready_i_reg\ => \gen_axi.s_axi_arready_i_reg\,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_valid_i_reg_0 => p_32_out,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
r_issuing_cnt(0) => r_issuing_cnt(0),
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_2,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(0) => D(0),
SR(0) => SR(0),
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_axi.write_cs_reg[1]\,
\gen_axi.write_cs_reg[1]_0\(0) => \gen_axi.write_cs_reg[1]_0\(0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(0),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 56 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 2 to 2 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_2 : STD_LOGIC;
signal addr_arbiter_ar_n_3 : STD_LOGIC;
signal addr_arbiter_ar_n_4 : STD_LOGIC;
signal addr_arbiter_ar_n_5 : STD_LOGIC;
signal addr_arbiter_ar_n_6 : STD_LOGIC;
signal addr_arbiter_ar_n_7 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_11 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_15 : STD_LOGIC;
signal addr_arbiter_aw_n_16 : STD_LOGIC;
signal addr_arbiter_aw_n_2 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_21 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_8 : STD_LOGIC;
signal addr_arbiter_aw_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_75\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_76\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_13\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_19\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_24\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_25\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_28\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_29\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_30\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_31\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_45\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_3 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_2 : STD_LOGIC;
signal mi_arready_2 : STD_LOGIC;
signal mi_awready_2 : STD_LOGIC;
signal mi_bready_2 : STD_LOGIC;
signal mi_rready_2 : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_21_in : STD_LOGIC;
signal p_24_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_32_out : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_54_out : STD_LOGIC;
signal p_56_out : STD_LOGIC;
signal p_60_out : STD_LOGIC;
signal p_74_out : STD_LOGIC;
signal p_76_out : STD_LOGIC;
signal p_80_out : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 34 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 35 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
addr_arbiter_ar: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
D(2) => addr_arbiter_ar_n_2,
D(1) => addr_arbiter_ar_n_3,
D(0) => addr_arbiter_ar_n_4,
E(0) => s_axi_rvalid_i,
Q(0) => p_56_out,
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.s_axi_rid_i_reg[11]\(0) => aa_mi_artarget_hot(2),
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_5,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_6,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_7,
\gen_master_slots[1].r_issuing_cnt_reg[8]\(0) => addr_arbiter_ar_n_85,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_82,
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) => st_aa_artarget_hot(0),
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_ar_n_80,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_81,
\m_axi_arqos[7]\(68 downto 0) => \^m_axi_arqos[7]\(68 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
\m_payload_i_reg[34]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\m_payload_i_reg[34]_0\ => \gen_master_slots[1].reg_slice_mi_n_27\,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_75\,
mi_arready_2 => mi_arready_2,
p_15_in => p_15_in,
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\s_axi_araddr[25]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\s_axi_araddr[28]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\s_axi_araddr[30]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\s_axi_arqos[3]\(68 downto 12) => \s_axi_arqos[3]\(56 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready\(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
s_axi_rready(0) => s_axi_rready(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
addr_arbiter_aw: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
D(2) => addr_arbiter_aw_n_7,
D(1) => addr_arbiter_aw_n_8,
D(0) => addr_arbiter_aw_n_9,
E(0) => addr_arbiter_aw_n_15,
Q(68 downto 0) => \^q\(68 downto 0),
SR(0) => reset,
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\chosen_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => addr_arbiter_aw_n_16,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_12,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_13,
\gen_master_slots[1].w_issuing_cnt_reg[9]\ => addr_arbiter_aw_n_10,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => addr_arbiter_aw_n_14,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ => addr_arbiter_aw_n_20,
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_2,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_3,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_21,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_awready_2 => mi_awready_2,
\s_axi_awaddr[20]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\s_axi_awaddr[26]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\s_axi_awqos[3]\(68 downto 12) => D(56 downto 0),
\s_axi_awqos[3]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
ss_aa_awready => ss_aa_awready,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(11 downto 0) => p_24_in(11 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[7]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[7]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_10,
m_ready_d(0) => m_ready_d_3(1),
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_14,
mi_arready_2 => mi_arready_2,
mi_awready_2 => mi_awready_2,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_14_in => p_14_in,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_21_in => p_21_in,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_20_in(11 downto 0),
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_4,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_3,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_2,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \r_pipe/p_1_in_0\,
Q(3 downto 0) => r_issuing_cnt(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(0),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_76_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_1_in => p_1_in,
p_74_out => p_74_out,
p_80_out => p_80_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_13,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_12,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_11,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_6,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_5,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_7,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
D(13 downto 2) => m_axi_bid(23 downto 12),
D(1 downto 0) => m_axi_bresp(3 downto 2),
Q(3 downto 0) => w_issuing_cnt(11 downto 8),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 1),
chosen_0(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 1),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].reg_slice_mi_n_75\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_27\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6) => st_mr_bid(23),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(5 downto 2) => st_mr_bid(21 downto 18),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => st_mr_bid(16),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => st_mr_bid(12),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 14) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13) => p_56_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12) => st_mr_rmesg(36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11) => st_mr_rmesg(69),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10) => st_mr_rmesg(65),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9) => st_mr_rmesg(60),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8 downto 7) => st_mr_rmesg(58 downto 57),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6 downto 3) => st_mr_rmesg(49 downto 46),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2) => st_mr_rmesg(44),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1) => st_mr_rmesg(42),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => st_mr_rmesg(38),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
\m_payload_i_reg[12]\(9) => st_mr_bid(34),
\m_payload_i_reg[12]\(8) => st_mr_bid(29),
\m_payload_i_reg[12]\(7 downto 5) => st_mr_bid(27 downto 25),
\m_payload_i_reg[12]\(4) => st_mr_bid(10),
\m_payload_i_reg[12]\(3) => st_mr_bid(5),
\m_payload_i_reg[12]\(2 downto 0) => st_mr_bid(3 downto 1),
\m_payload_i_reg[1]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\m_payload_i_reg[32]\(20) => st_mr_rmesg(0),
\m_payload_i_reg[32]\(19 downto 17) => st_mr_rmesg(33 downto 31),
\m_payload_i_reg[32]\(16 downto 13) => st_mr_rmesg(29 downto 26),
\m_payload_i_reg[32]\(12) => st_mr_rmesg(24),
\m_payload_i_reg[32]\(11 downto 5) => st_mr_rmesg(21 downto 15),
\m_payload_i_reg[32]\(4) => st_mr_rmesg(10),
\m_payload_i_reg[32]\(3) => st_mr_rmesg(8),
\m_payload_i_reg[32]\(2 downto 0) => st_mr_rmesg(6 downto 4),
p_1_in => p_1_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
p_54_out => p_54_out,
p_60_out => p_60_out,
s_axi_bid(4) => s_axi_bid(10),
s_axi_bid(3) => s_axi_bid(5),
s_axi_bid(2 downto 0) => s_axi_bid(3 downto 1),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_rdata(19 downto 17) => s_axi_rdata(30 downto 28),
s_axi_rdata(16 downto 13) => s_axi_rdata(26 downto 23),
s_axi_rdata(12) => s_axi_rdata(21),
s_axi_rdata(11 downto 5) => s_axi_rdata(18 downto 12),
s_axi_rdata(4) => s_axi_rdata(7),
s_axi_rdata(3) => s_axi_rdata(5),
s_axi_rdata(2 downto 0) => s_axi_rdata(3 downto 1),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_8,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_7,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_9,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[2].reg_slice_mi_n_45\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(11 downto 0) => p_24_in(11 downto 0),
E(0) => \r_pipe/p_1_in\,
Q(4) => st_mr_bid(34),
Q(3) => st_mr_bid(29),
Q(2 downto 0) => st_mr_bid(27 downto 25),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_ar_n_80,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_20_in(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_45\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 1) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => p_34_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\m_payload_i_reg[13]\(13) => st_mr_bid(23),
\m_payload_i_reg[13]\(12 downto 9) => st_mr_bid(21 downto 18),
\m_payload_i_reg[13]\(8) => st_mr_bid(16),
\m_payload_i_reg[13]\(7 downto 6) => st_mr_bid(12 downto 11),
\m_payload_i_reg[13]\(5 downto 2) => st_mr_bid(9 downto 6),
\m_payload_i_reg[13]\(1) => st_mr_bid(4),
\m_payload_i_reg[13]\(0) => st_mr_bid(0),
m_valid_i_reg => \gen_master_slots[2].reg_slice_mi_n_1\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_21_in => p_21_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
r_issuing_cnt(0) => r_issuing_cnt(16),
s_axi_bid(6) => s_axi_bid(11),
s_axi_bid(5 downto 2) => s_axi_bid(9 downto 6),
s_axi_bid(1) => s_axi_bid(4),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[2].reg_slice_mi_n_5\,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0),
w_issuing_cnt(0) => w_issuing_cnt(16)
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
E(0) => \r_pipe/p_1_in_0\,
SR(0) => reset,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 0),
\gen_multi_thread.accept_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_81,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready\(0),
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[46]\(25 downto 14) => st_mr_rid(11 downto 0),
\m_payload_i_reg[46]\(13) => p_76_out,
\m_payload_i_reg[46]\(12) => st_mr_rmesg(1),
\m_payload_i_reg[46]\(11) => st_mr_rmesg(34),
\m_payload_i_reg[46]\(10) => st_mr_rmesg(30),
\m_payload_i_reg[46]\(9) => st_mr_rmesg(25),
\m_payload_i_reg[46]\(8 downto 7) => st_mr_rmesg(23 downto 22),
\m_payload_i_reg[46]\(6 downto 3) => st_mr_rmesg(14 downto 11),
\m_payload_i_reg[46]\(2) => st_mr_rmesg(9),
\m_payload_i_reg[46]\(1) => st_mr_rmesg(7),
\m_payload_i_reg[46]\(0) => st_mr_rmesg(3),
\m_payload_i_reg[46]_0\(25 downto 14) => st_mr_rid(23 downto 12),
\m_payload_i_reg[46]_0\(13) => p_56_out,
\m_payload_i_reg[46]_0\(12) => st_mr_rmesg(36),
\m_payload_i_reg[46]_0\(11) => st_mr_rmesg(69),
\m_payload_i_reg[46]_0\(10) => st_mr_rmesg(65),
\m_payload_i_reg[46]_0\(9) => st_mr_rmesg(60),
\m_payload_i_reg[46]_0\(8 downto 7) => st_mr_rmesg(58 downto 57),
\m_payload_i_reg[46]_0\(6 downto 3) => st_mr_rmesg(49 downto 46),
\m_payload_i_reg[46]_0\(2) => st_mr_rmesg(44),
\m_payload_i_reg[46]_0\(1) => st_mr_rmesg(42),
\m_payload_i_reg[46]_0\(0) => st_mr_rmesg(38),
\m_payload_i_reg[46]_1\(12 downto 1) => st_mr_rid(35 downto 24),
\m_payload_i_reg[46]_1\(0) => p_34_out,
m_valid_i => m_valid_i,
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
\s_axi_araddr[25]\(0) => st_aa_artarget_hot(0),
\s_axi_araddr[25]_0\ => addr_arbiter_ar_n_82,
\s_axi_araddr[31]\(27 downto 12) => \s_axi_arqos[3]\(31 downto 16),
\s_axi_araddr[31]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_rdata(11) => s_axi_rdata(31),
s_axi_rdata(10) => s_axi_rdata(27),
s_axi_rdata(9) => s_axi_rdata(22),
s_axi_rdata(8 downto 7) => s_axi_rdata(20 downto 19),
s_axi_rdata(6 downto 3) => s_axi_rdata(11 downto 8),
s_axi_rdata(2) => s_axi_rdata(6),
s_axi_rdata(1) => s_axi_rdata(4),
s_axi_rdata(0) => s_axi_rdata(0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(1),
s_axi_rvalid(0) => s_axi_rvalid(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
Q(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
SR(0) => reset,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_20,
\m_payload_i_reg[11]\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\m_payload_i_reg[12]\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\m_payload_i_reg[13]\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\m_payload_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\m_payload_i_reg[4]\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\m_payload_i_reg[5]\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\m_payload_i_reg[6]\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\m_payload_i_reg[7]\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_14,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[31]\(27 downto 12) => D(31 downto 16),
\s_axi_awaddr[31]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4) => w_issuing_cnt(16),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
SR(0) => reset,
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(1),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
splitter_aw_mi: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
port map (
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_3,
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
\m_ready_d_reg[0]_0\ => addr_arbiter_aw_n_21,
\m_ready_d_reg[0]_1\ => addr_arbiter_aw_n_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_ONES : string;
attribute P_ONES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(63 downto 32);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(63 downto 32);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(3 downto 2);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(3 downto 2);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(7 downto 4);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(7 downto 4);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(1) <= \^m_axi_arlock\(1);
m_axi_arlock(0) <= \^m_axi_arlock\(1);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(5 downto 3);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(5 downto 3);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(7 downto 4);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(7 downto 4);
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(5 downto 3);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(5 downto 3);
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(3 downto 2);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(3 downto 2);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(7 downto 4);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(7 downto 4);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlock(1) <= \^m_axi_awlock\(1);
m_axi_awlock(0) <= \^m_axi_awlock\(1);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(5 downto 3);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(5 downto 3);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(7 downto 4);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(7 downto 4);
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(5 downto 3);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(5 downto 3);
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52 downto 49) => s_axi_awcache(3 downto 0),
D(48 downto 47) => s_axi_awburst(1 downto 0),
D(46 downto 44) => s_axi_awprot(2 downto 0),
D(43) => s_axi_awlock(0),
D(42 downto 40) => s_axi_awsize(2 downto 0),
D(39 downto 32) => s_axi_awlen(7 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
M_AXI_RREADY(1 downto 0) => m_axi_rready(1 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(7 downto 4),
Q(64 downto 61) => \^m_axi_awcache\(7 downto 4),
Q(60 downto 59) => \^m_axi_awburst\(3 downto 2),
Q(58 downto 56) => \^m_axi_awprot\(5 downto 3),
Q(55) => \^m_axi_awlock\(1),
Q(54 downto 52) => \^m_axi_awsize\(5 downto 3),
Q(51 downto 44) => \^m_axi_awlen\(15 downto 8),
Q(43 downto 12) => \^m_axi_awaddr\(63 downto 32),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[7]\(68 downto 65) => \^m_axi_arqos\(7 downto 4),
\m_axi_arqos[7]\(64 downto 61) => \^m_axi_arcache\(7 downto 4),
\m_axi_arqos[7]\(60 downto 59) => \^m_axi_arburst\(3 downto 2),
\m_axi_arqos[7]\(58 downto 56) => \^m_axi_arprot\(5 downto 3),
\m_axi_arqos[7]\(55) => \^m_axi_arlock\(1),
\m_axi_arqos[7]\(54 downto 52) => \^m_axi_arsize\(5 downto 3),
\m_axi_arqos[7]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[7]\(43 downto 12) => \^m_axi_araddr\(63 downto 32),
\m_axi_arqos[7]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arqos[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(52 downto 49) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(48 downto 47) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(46 downto 44) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(43) => s_axi_arlock(0),
\s_axi_arqos[3]\(42 downto 40) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(39 downto 32) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_xbar_0 : entity is "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end zynq_design_1_xbar_0;
architecture STRUCTURE of zynq_design_1_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "2'b11";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0),
m_axi_arburst(3 downto 0) => m_axi_arburst(3 downto 0),
m_axi_arcache(7 downto 0) => m_axi_arcache(7 downto 0),
m_axi_arid(23 downto 0) => m_axi_arid(23 downto 0),
m_axi_arlen(15 downto 0) => m_axi_arlen(15 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(5 downto 0) => m_axi_arprot(5 downto 0),
m_axi_arqos(7 downto 0) => m_axi_arqos(7 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arregion(7 downto 0) => m_axi_arregion(7 downto 0),
m_axi_arsize(5 downto 0) => m_axi_arsize(5 downto 0),
m_axi_aruser(1 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0),
m_axi_awburst(3 downto 0) => m_axi_awburst(3 downto 0),
m_axi_awcache(7 downto 0) => m_axi_awcache(7 downto 0),
m_axi_awid(23 downto 0) => m_axi_awid(23 downto 0),
m_axi_awlen(15 downto 0) => m_axi_awlen(15 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(5 downto 0) => m_axi_awprot(5 downto 0),
m_axi_awqos(7 downto 0) => m_axi_awqos(7 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awregion(7 downto 0) => m_axi_awregion(7 downto 0),
m_axi_awsize(5 downto 0) => m_axi_awsize(5 downto 0),
m_axi_awuser(1 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_buser(1 downto 0) => B"00",
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_ruser(1 downto 0) => B"00",
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(23 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(23 downto 0),
m_axi_wlast(1 downto 0) => m_axi_wlast(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(1 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 77da70fb3eaa6ca382144bc27a2c001f | 0.562699 | 2.590374 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml50x/grlib_config.vhd | 1 | 2,564 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
end;
| gpl-2.0 | df82e902371cd0a288b890191e9de338 | 0.654446 | 4.175896 | false | true | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/boards/terasic-de4/sgmii2gmii.vhd | 2 | 17,900 | -- megafunction wizard: %Triple-Speed Ethernet v13.1%
-- GENERATION: XML
-- sgmii2gmii.vhd
-- Generated using ACDS version 13.1 162 at 2013.11.29.14:56:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sgmii2gmii is
port (
ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
clk : in std_logic := '0'; -- control_port_clock_connection.clk
reset : in std_logic := '0'; -- reset_connection.reset
address : in std_logic_vector(4 downto 0) := (others => '0'); -- control_port.address
readdata : out std_logic_vector(15 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
waitrequest : out std_logic; -- .waitrequest
tx_clk : out std_logic; -- pcs_transmit_clock_connection.clk
rx_clk : out std_logic; -- pcs_receive_clock_connection.clk
reset_tx_clk : in std_logic := '0'; -- pcs_transmit_reset_connection.reset
reset_rx_clk : in std_logic := '0'; -- pcs_receive_reset_connection.reset
gmii_rx_dv : out std_logic; -- gmii_connection.gmii_rx_dv
gmii_rx_d : out std_logic_vector(7 downto 0); -- .gmii_rx_d
gmii_rx_err : out std_logic; -- .gmii_rx_err
gmii_tx_en : in std_logic := '0'; -- .gmii_tx_en
gmii_tx_d : in std_logic_vector(7 downto 0) := (others => '0'); -- .gmii_tx_d
gmii_tx_err : in std_logic := '0'; -- .gmii_tx_err
tx_clkena : out std_logic; -- clock_enable_connection.tx_clkena
rx_clkena : out std_logic; -- .rx_clkena
mii_rx_dv : out std_logic; -- mii_connection.mii_rx_dv
mii_rx_d : out std_logic_vector(3 downto 0); -- .mii_rx_d
mii_rx_err : out std_logic; -- .mii_rx_err
mii_tx_en : in std_logic := '0'; -- .mii_tx_en
mii_tx_d : in std_logic_vector(3 downto 0) := (others => '0'); -- .mii_tx_d
mii_tx_err : in std_logic := '0'; -- .mii_tx_err
mii_col : out std_logic; -- .mii_col
mii_crs : out std_logic; -- .mii_crs
set_10 : out std_logic; -- sgmii_status_connection.set_10
set_1000 : out std_logic; -- .set_1000
set_100 : out std_logic; -- .set_100
hd_ena : out std_logic; -- .hd_ena
led_crs : out std_logic; -- status_led_connection.crs
led_link : out std_logic; -- .link
led_col : out std_logic; -- .col
led_an : out std_logic; -- .an
led_char_err : out std_logic; -- .char_err
led_disp_err : out std_logic; -- .disp_err
rx_recovclkout : out std_logic; -- serdes_control_connection.export
txp : out std_logic; -- serial_connection.txp
rxp : in std_logic := '0' -- .rxp
);
end entity sgmii2gmii;
architecture rtl of sgmii2gmii is
component sgmii2gmii_0002 is
port (
ref_clk : in std_logic := 'X'; -- clk
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(15 downto 0); -- readdata
read : in std_logic := 'X'; -- read
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
waitrequest : out std_logic; -- waitrequest
tx_clk : out std_logic; -- clk
rx_clk : out std_logic; -- clk
reset_tx_clk : in std_logic := 'X'; -- reset
reset_rx_clk : in std_logic := 'X'; -- reset
gmii_rx_dv : out std_logic; -- gmii_rx_dv
gmii_rx_d : out std_logic_vector(7 downto 0); -- gmii_rx_d
gmii_rx_err : out std_logic; -- gmii_rx_err
gmii_tx_en : in std_logic := 'X'; -- gmii_tx_en
gmii_tx_d : in std_logic_vector(7 downto 0) := (others => 'X'); -- gmii_tx_d
gmii_tx_err : in std_logic := 'X'; -- gmii_tx_err
tx_clkena : out std_logic; -- tx_clkena
rx_clkena : out std_logic; -- rx_clkena
mii_rx_dv : out std_logic; -- mii_rx_dv
mii_rx_d : out std_logic_vector(3 downto 0); -- mii_rx_d
mii_rx_err : out std_logic; -- mii_rx_err
mii_tx_en : in std_logic := 'X'; -- mii_tx_en
mii_tx_d : in std_logic_vector(3 downto 0) := (others => 'X'); -- mii_tx_d
mii_tx_err : in std_logic := 'X'; -- mii_tx_err
mii_col : out std_logic; -- mii_col
mii_crs : out std_logic; -- mii_crs
set_10 : out std_logic; -- set_10
set_1000 : out std_logic; -- set_1000
set_100 : out std_logic; -- set_100
hd_ena : out std_logic; -- hd_ena
led_crs : out std_logic; -- crs
led_link : out std_logic; -- link
led_col : out std_logic; -- col
led_an : out std_logic; -- an
led_char_err : out std_logic; -- char_err
led_disp_err : out std_logic; -- disp_err
rx_recovclkout : out std_logic; -- export
txp : out std_logic; -- txp
rxp : in std_logic := 'X' -- rxp
);
end component sgmii2gmii_0002;
begin
sgmii2gmii_inst : component sgmii2gmii_0002
port map (
ref_clk => ref_clk, -- pcs_ref_clk_clock_connection.clk
clk => clk, -- control_port_clock_connection.clk
reset => reset, -- reset_connection.reset
address => address, -- control_port.address
readdata => readdata, -- .readdata
read => read, -- .read
writedata => writedata, -- .writedata
write => write, -- .write
waitrequest => waitrequest, -- .waitrequest
tx_clk => tx_clk, -- pcs_transmit_clock_connection.clk
rx_clk => rx_clk, -- pcs_receive_clock_connection.clk
reset_tx_clk => reset_tx_clk, -- pcs_transmit_reset_connection.reset
reset_rx_clk => reset_rx_clk, -- pcs_receive_reset_connection.reset
gmii_rx_dv => gmii_rx_dv, -- gmii_connection.gmii_rx_dv
gmii_rx_d => gmii_rx_d, -- .gmii_rx_d
gmii_rx_err => gmii_rx_err, -- .gmii_rx_err
gmii_tx_en => gmii_tx_en, -- .gmii_tx_en
gmii_tx_d => gmii_tx_d, -- .gmii_tx_d
gmii_tx_err => gmii_tx_err, -- .gmii_tx_err
tx_clkena => tx_clkena, -- clock_enable_connection.tx_clkena
rx_clkena => rx_clkena, -- .rx_clkena
mii_rx_dv => mii_rx_dv, -- mii_connection.mii_rx_dv
mii_rx_d => mii_rx_d, -- .mii_rx_d
mii_rx_err => mii_rx_err, -- .mii_rx_err
mii_tx_en => mii_tx_en, -- .mii_tx_en
mii_tx_d => mii_tx_d, -- .mii_tx_d
mii_tx_err => mii_tx_err, -- .mii_tx_err
mii_col => mii_col, -- .mii_col
mii_crs => mii_crs, -- .mii_crs
set_10 => set_10, -- sgmii_status_connection.set_10
set_1000 => set_1000, -- .set_1000
set_100 => set_100, -- .set_100
hd_ena => hd_ena, -- .hd_ena
led_crs => led_crs, -- status_led_connection.crs
led_link => led_link, -- .link
led_col => led_col, -- .col
led_an => led_an, -- .an
led_char_err => led_char_err, -- .char_err
led_disp_err => led_disp_err, -- .disp_err
rx_recovclkout => rx_recovclkout, -- serdes_control_connection.export
txp => txp, -- serial_connection.txp
rxp => rxp -- .rxp
);
end architecture rtl; -- of sgmii2gmii
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_eth_tse" version="13.1" >
-- Retrieval info: <generic name="deviceFamilyName" value="Stratix IV" />
-- Retrieval info: <generic name="core_variation" value="PCS_ONLY" />
-- Retrieval info: <generic name="ifGMII" value="MII_GMII" />
-- Retrieval info: <generic name="enable_use_internal_fifo" value="true" />
-- Retrieval info: <generic name="max_channels" value="1" />
-- Retrieval info: <generic name="use_misc_ports" value="true" />
-- Retrieval info: <generic name="transceiver_type" value="LVDS_IO" />
-- Retrieval info: <generic name="enable_hd_logic" value="true" />
-- Retrieval info: <generic name="enable_gmii_loopback" value="false" />
-- Retrieval info: <generic name="enable_sup_addr" value="false" />
-- Retrieval info: <generic name="stat_cnt_ena" value="true" />
-- Retrieval info: <generic name="ext_stat_cnt_ena" value="false" />
-- Retrieval info: <generic name="ena_hash" value="false" />
-- Retrieval info: <generic name="enable_shift16" value="true" />
-- Retrieval info: <generic name="enable_mac_flow_ctrl" value="false" />
-- Retrieval info: <generic name="enable_mac_vlan" value="false" />
-- Retrieval info: <generic name="enable_magic_detect" value="true" />
-- Retrieval info: <generic name="useMDIO" value="false" />
-- Retrieval info: <generic name="mdio_clk_div" value="40" />
-- Retrieval info: <generic name="enable_ena" value="32" />
-- Retrieval info: <generic name="eg_addr" value="11" />
-- Retrieval info: <generic name="ing_addr" value="11" />
-- Retrieval info: <generic name="phy_identifier" value="0" />
-- Retrieval info: <generic name="enable_sgmii" value="true" />
-- Retrieval info: <generic name="export_pwrdn" value="false" />
-- Retrieval info: <generic name="enable_alt_reconfig" value="false" />
-- Retrieval info: <generic name="starting_channel_number" value="0" />
-- Retrieval info: <generic name="phyip_pll_type" value="CMU" />
-- Retrieval info: <generic name="phyip_en_synce_support" value="false" />
-- Retrieval info: <generic name="phyip_pma_bonding_mode" value="x1" />
-- Retrieval info: <generic name="nf_phyip_rcfg_enable" value="false" />
-- Retrieval info: <generic name="enable_timestamping" value="false" />
-- Retrieval info: <generic name="enable_ptp_1step" value="false" />
-- Retrieval info: <generic name="tstamp_fp_width" value="4" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : sgmii2gmii.vho
-- RELATED_FILES: sgmii2gmii.vhd, sgmii2gmii_0002.v, altera_eth_tse_pcs_pma_lvds.v, altera_tse_align_sync.v, altera_tse_dec10b8b.v, altera_tse_dec_func.v, altera_tse_enc8b10b.v, altera_tse_top_autoneg.v, altera_tse_carrier_sense.v, altera_tse_clk_gen.v, altera_tse_sgmii_clk_div.v, altera_tse_sgmii_clk_enable.v, altera_tse_rx_encapsulation.v, altera_tse_tx_encapsulation.v, altera_tse_rx_encapsulation_strx_gx.v, altera_tse_pcs_control.v, altera_tse_pcs_host_control.v, altera_tse_mdio_reg.v, altera_tse_mii_rx_if_pcs.v, altera_tse_mii_tx_if_pcs.v, altera_tse_rx_sync.v, altera_tse_sgmii_clk_cntl.v, altera_tse_colision_detect.v, altera_tse_rx_converter.v, altera_tse_rx_fifo_rd.v, altera_tse_top_rx_converter.v, altera_tse_top_sgmii.v, altera_tse_top_sgmii_strx_gx.v, altera_tse_top_tx_converter.v, altera_tse_tx_converter.v, altera_tse_top_1000_base_x.v, altera_tse_top_1000_base_x_strx_gx.v, altera_tse_top_pcs.v, altera_tse_top_pcs_strx_gx.v, altera_tse_top_rx.v, altera_tse_top_tx.v, altera_tse_lvds_reset_sequencer.v, altera_tse_lvds_reverse_loopback.v, altera_tse_pma_lvds_rx_av.v, altera_tse_pma_lvds_rx.v, altera_tse_pma_lvds_tx.v, altera_tse_false_path_marker.v, altera_tse_reset_synchronizer.v, altera_tse_clock_crosser.v, altera_tse_a_fifo_13.v, altera_tse_a_fifo_24.v, altera_tse_a_fifo_34.v, altera_tse_a_fifo_opt_1246.v, altera_tse_a_fifo_opt_14_44.v, altera_tse_a_fifo_opt_36_10.v, altera_tse_gray_cnt.v, altera_tse_sdpm_altsyncram.v, altera_tse_altsyncram_dpm_fifo.v, altera_tse_bin_cnt.v, altera_tse_ph_calculator.sv, altera_tse_sdpm_gen.v, altera_tse_dc_fifo.v
| gpl-2.0 | 854f5a86bc6f815080b18def1511f100 | 0.458324 | 3.819889 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/TestBench/JS_test.vhd | 1 | 1,154 | library ieee;
use ieee.std_logic_1164.all;
entity JS_TEST is
end JS_TEST;
architecture Beh of JS_TEST is
component JC
port (
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 3);
Pout: out std_logic_vector(0 to 3)
);
end component;
signal CLK: std_logic := '0';
signal RST: std_logic := '0';
signal LS: std_logic := '0';
signal Pin: std_logic_vector(0 to 3) := (others => '0');
signal Pout: std_logic_vector(0 to 3);
constant CLK_Period: time := 10 ns;
begin
uut: JC port map (
CLK => CLK,
RST => RST,
LS => LS,
PIn => Pin,
POut => POut
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
stim_proc: process
begin
wait for CLK_Period;
RST <= '0'; wait for CLK_Period;
RST <= '1'; wait for 2*CLK_Period;
RST <= '0'; wait for CLK_Period;
PIn <= "1111"; wait for CLK_Period;
LS <= '1'; wait for 8*CLK_period;
end process;
end Beh;
configuration TESTBENCH_FOR_JS of JS_TEST is
for Beh
for UUT : jc
use entity work.jc(behavior);
end for;
end for;
end TESTBENCH_FOR_JS; | mit | 2ddfce4baaa3b617fb82a377d5ca6dfa | 0.618718 | 2.646789 | false | true | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-minimal/leon3mp.vhd | 1 | 10,459 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | cfbffd0ae9222b4302ff58fd08e933e0 | 0.51439 | 4.050736 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-atlys/leon3mp.vhd | 2 | 31,519 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- led(6) = dsuact (LED 6 ON when processor in debug mode)
-- led(7) = not errorn (LED 7 ON when processor in error mode)
-- switch(6) = dsubre (SWITCH 6 ON to force DSU break)
-- switch(7) = dsuen (SWITCH 7 ON to enable debug mode)
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
library unisim;
use unisim.vcomponents.OBUFDS;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 100 MHz board clock
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic;
ddr_ras : out std_ulogic;
ddr_cas : out std_ulogic;
ddr_dm : out std_logic_vector (1 downto 0);
ddr_dqs : inout std_logic_vector (1 downto 0);
ddr_dqsn : inout std_logic_vector (1 downto 0);
ddr_ad : out std_logic_vector (12 downto 0);
ddr_ba : out std_logic_vector (2 downto 0);
ddr_dq : inout std_logic_vector (15 downto 0);
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- switch(7)
-- dsubre : in std_ulogic; -- switch(6)
-- dsuact : out std_ulogic; -- led(6)
-- errorn : out std_ulogic; -- led(7)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- GPIO
pmoda : inout std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0);
button : in std_logic_vector(4 downto 0);
-- MII Ethernet
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erst : out std_ulogic;
egtxclk : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
emdint : in std_ulogic;
-- PS/2
kbd_clk : inout std_logic;
kbd_data : inout std_logic;
mou_clk : inout std_logic;
mou_data : inout std_logic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : inout std_ulogic;
-- HDMI port
tmdstx_clk_p : out std_logic;
tmdstx_clk_n : out std_logic;
tmdstx_dat_p : out std_logic_vector(2 downto 0);
tmdstx_dat_n : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_ulogic;
signal clk200 : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lock, calib_done, lclk : std_ulogic;
signal rstext : std_ulogic;
signal rstint : std_ulogic;
signal errorp : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddr2clk : std_ulogic;
signal ddr0_clk_fb : std_ulogic;
signal ddr0_clk : std_logic_vector(2 downto 0);
signal ddr0_clkb : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_ad : std_logic_vector(13 downto 0);
signal ddr0_lock: std_ulogic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal video_clk : std_logic;
signal video_fastclk : std_logic;
signal video_clksel : std_logic_vector(1 downto 0);
signal tmds_clk : std_logic;
signal tmds_dat : std_logic_vector(2 downto 0);
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
-- constant DDR2_FREQ : integer := 150000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of video_fastclk : signal is true;
attribute keep of video_fastclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkin => lclk, pciclkin => lclk,
clk => clkm, clkn => open, clk2x => open,
sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo,
clk4x => open, clk1xu => open, clk2xu => clk200);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rstext);
rst0 : rstgen -- reset generator
port map (rstint, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and ddr0_lock;
-- Generate clean internal reset from external reset and watchdog.
rst1 : process (lclk, rstext) is
variable v_shift: std_logic_vector(3 downto 0);
variable v_wdog: std_logic_vector(2 downto 0);
begin
if rstext = '0' then
rstint <= '0';
v_shift := (others => '0');
v_wdog := (others => '0');
elsif rising_edge(lclk) then
rstint <= v_shift(0);
if CFG_GPT_WDOGEN /= 0 and v_wdog(0) = '1' then
v_shift := (others => '0');
else
v_shift := '1' & v_shift(3 downto 1);
end if;
if CFG_GPT_WDOGEN /= 0 then
v_wdog(0) := v_wdog(2) and not v_wdog(1);
v_wdog(1) := v_wdog(2);
v_wdog(2) := gpto.wdog;
end if;
end if;
end process;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
-- LED(7) = error
errorp <= not dbgo(0).error;
led1_pad : outpad generic map (tech => padtech) port map (led(7), errorp);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- SWITCH(7) = dsuen
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
-- SWITCH(6) = dsubre
dsubre_pad : inpad generic map (tech => padtech) port map (switch(6), dsui.break);
-- LED(6) = dsuact
dsuact_pad : outpad generic map (tech => padtech) port map (led(6), dsuo.active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl_gen : if (CFG_MCTRL_LEON2 /= 0) generate
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
memi.data <= (others => '0'); -- Atlys board has no asynchronous memory bus
memi.sd <= (others => '0'); -- Atlys board has no classic SDRAM
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_gen : if (CFG_DDR2SP = 1) generate
ddr0: ddr2spa
generic map (
fabtech => fabtech,
memtech => memtech,
rskew => 0,
hindex => 4,
haddr => 16#400#,
hmask => 16#f80#,
ioaddr => 16#001#,
iomask => 16#fff#,
MHz => CPU_FREQ/1000,
TRFC => CFG_DDR2SP_TRFC,
clkmul => 6,
clkdiv => 2,
col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE,
rstdel => 200,
pwron => CFG_DDR2SP_INIT,
ddrbits => CFG_DDR2SP_DATAWIDTH,
ahbfreq => CPU_FREQ/1000,
readdly => 1,
norefclk => 0,
odten => 3,
dqsgating => 0,
nosync => CFG_DDR2SP_NOSYNC,
eightbanks => 1,
dqsse => 0,
burstlen => 8,
ft => CFG_DDR2SP_FTEN,
ftbits => CFG_DDR2SP_FTWIDTH,
bigmem => 0,
raspipe => 0 )
port map (
rst_ddr => rstraw,
rst_ahb => rstn,
clk_ddr => clkm,
clk_ahb => clkm,
clkref200 => clk200,
lock => ddr0_lock,
clkddro => ddr2clk,
clkddri => ddr2clk,
ahbsi => ahbsi,
ahbso => ahbso(4),
ddr_clk => ddr0_clk,
ddr_clkb => ddr0_clkb,
ddr_clk_fb_out => ddr0_clk_fb,
ddr_clk_fb => ddr0_clk_fb,
ddr_cke => ddr0_cke,
ddr_csb => open,
ddr_web => ddr_we,
ddr_rasb => ddr_ras,
ddr_casb => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr0_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr0_odt,
ce => open );
ddr_clk <= ddr0_clk(0);
ddr_clkb <= ddr0_clkb(0);
ddr_cke <= ddr0_cke(0);
ddr_odt <= ddr0_odt(0);
ddr_ad <= ddr0_ad(12 downto 0);
ddr_rzq <= 'Z';
ddr_zio <= 'Z';
end generate;
ddr_nogen : if (CFG_DDR2SP /= 1) generate
ddr0_lock <= '1';
ddrcke_nopad : outpad generic map (tech => padtech) port map (ddr_cke, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- Numonyx N25Q12 16 MByte SPI flash memory
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 11, faddr => 16#e00#, fmask => 16#ff0#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi, spmo.mosioen , spmi.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
spisel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
notxd : if CFG_UART1_ENABLE = 0 and CFG_AHB_UART = 0 generate
notxd_pad : outpad generic map (tech => padtech) port map (txd1, vcc);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbd_clk, kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbd_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (mou_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (mou_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map (pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
-- Map GPIO bits 0 to 5 to LEDS 0 to 5.
gpio_led_pads : outpadv
generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpioo.dout(5 downto 0));
-- Map GPIO bits 8 to 13 to SWITCHES 0 to 5.
gpio_sw_pads : inpadv
generic map (tech => padtech, width => 6)
port map (switch(5 downto 0), gpioi.din(13 downto 8));
-- Map GPIO bits 16 to 20 to BUTTONS 0 to 4.
gpio_button_pads : inpadv
generic map (tech => padtech, width => 5)
port map (button(4 downto 0), gpioi.din(20 downto 16));
-- Map GPIO bits 24 to 31 to PMODA port.
gpio_pmod_pads : for i in 0 to 7 generate
gpio_pmod_padi : iopad
generic map (tech => padtech)
port map (pmoda(i), gpioo.dout(24+i), gpioo.oen(24+i), gpioi.din(24+i));
end generate;
gpioi.din(7 downto 0) <= (others => '0');
gpioi.din(15 downto 14) <= (others => '0');
gpioi.din(23 downto 21) <= (others => '0');
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => 0)
port map (
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
end generate;
eth_nopads : if (CFG_GRETH /= 1) generate -- eth pads
etxd_nopad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, "00000000");
etxen_nopad : outpad generic map (tech => padtech)
port map (etx_en, '0');
etxer_nopad : outpad generic map (tech => padtech)
port map (etx_er, '0');
emdc_nopad : outpad generic map (tech => padtech)
port map (emdc, '0');
emdio_nopad : iopad generic map (tech => padtech)
port map (emdio, '0', '1', open);
end generate;
erst_pad : outpad generic map (tech => padtech)
port map (erst, rstraw);
egtxclk_pad : outpad generic map (tech => padtech)
port map (egtxclk, '0');
ethi.gtx_clk <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP )
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- VGA / HDMI ------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga
generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clksel <= "00"; -- fixed 25 MHz
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
clk0 => 40000, clk1 => 25000, clk2 => 40000, clk3 => 25000,
burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao,
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
video_clksel);
end generate;
tmds : if CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /= 0 generate
vgaclk0 : entity work.vga_clkgen
port map (resetn => rstraw, clk100 => lclk, sel => video_clksel,
vgaclk => video_clk, fastclk => video_fastclk);
tmds0 : entity work.vga2tmds
generic map (tech => fabtech)
port map (vgaclk => video_clk, fastclk => video_fastclk, vgao => vgao,
tmdsclk => tmds_clk, tmdsdat => tmds_dat );
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => tmds_clk);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => tmds_dat(i));
end generate;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => gnd);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => gnd);
end generate;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent-Atlys-XC6SLX45 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end architecture;
| gpl-2.0 | ed50d239c4a7ccc887e2c17e9cb012c8 | 0.55062 | 3.596007 | false | false | false | false |
quicky2000/top_optim_sharp_driver | driver_sharp.vhd | 1 | 28,890 | --
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity driver_sharp is
port (
clk : in std_logic; -- Clock input
rst : in std_logic; -- Reset input
-- Signals to drive the screen
vsync : out std_logic;
hsync : out std_logic;
enable : out std_logic;
-- Signals to communicate with block giving color
x_out : out std_logic_vector ( 9 downto 0);
y_out : out std_logic_vector ( 8 downto 0)
);
end driver_sharp;
architecture v1_0 of driver_sharp is
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 800; -- Horizontal sync signal cycle width in clock cycle
constant THp : positive := 96; -- Horizontal sync signal pulse width in clock cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
constant TV : positive := 525; -- Vertical sync signal period in clock cycle
begin -- behavorial
process(clk,rst)
variable x_counter : positive range 1 to TH := 1; -- counter for x axis
variable y_counter : positive range 1 to TV := 1; -- counter for y axis
variable x : natural range 0 to THd := 0; -- x coordinate of active pixel
variable y : natural range 0 to TVd := 0; -- x coordinate of active pixel
begin
if rst = '1' then
x_counter := 1;
y_counter := 1;
vsync <= '0';
hsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
x := 0;
y := 0;
elsif rising_edge(clk) then
if y_counter < 2 then
vsync <= '0';
else
vsync <= '1';
end if;
if x_counter < TH then
x_counter := x_counter + 1;
else
x_counter := 1;
if y_counter < TV then
y_counter := y_counter + 1;
else
y_counter := 1;
y := 0;
y_out <= (others => '0');
end if;
if y_counter > TVs and y < TVd then
y_out <= std_logic_vector(to_unsigned(y,9));
y := y +1;
end if;
end if;
if x_counter <= THp then
hsync <= '0';
x := 0;
x_out <= (others => '0');
else
hsync <= '1';
if x < THd and y_counter > TVs and y_counter <= TVd + TVs then
x_out <= std_logic_vector(to_unsigned(x,10));
x := x + 1;
enable <= '1';
else
enable <= '0';
x_out <= (others => '0');
end if;
end if;
end if;
end process;
end v1_0;
architecture v1_1 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Internal signals
signal x_counter : std_logic_vector( 9 downto 0) := (others => '0'); -- counter for x axis
signal y_counter : std_logic_vector( 9 downto 0) := (others => '0'); -- counter for x axis
signal x : std_logic_vector( 9 downto 0) := (others => '0');
signal y : std_logic_vector( 8 downto 0) := (others => '0');
-- FSM for hsync
type hsync_state_type is (low,high);
signal hsync_state : hsync_state_type := low;
signal hsync_next_state : hsync_state_type := low ;
-- FSM for vsync
type vsync_state_type is (low,high,ready_to_low);
signal vsync_state : vsync_state_type := low;
signal vsync_next_state : vsync_state_type := low ;
signal ycounter_next : std_logic_vector (9 downto 0):= (others => '0');
-- FSM for enable
type line_state_type is (virtual,real); -- State indicating if we are in non real lines or real lines
signal line_state : line_state_type := virtual; -- State of line
signal line_next_state : line_state_type := virtual; -- State of line
type enable_state_type is (active,inactive,done);
signal enable_state : enable_state_type := inactive;
signal enable_next_state : enable_state_type := inactive;
-- FSM for y
type y_state_type is (active,inactive,done,ready,ready_to_reset);
signal y_state : y_state_type := inactive;
signal y_next_state : y_state_type := inactive;
begin -- behavorial
x_counter_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(x_counter) = TH then
x_counter <= (others => '0');
else
x_counter <= std_logic_vector(unsigned(x_counter) + 1);
end if;
end if;
end process;
-- ycounter state register process
ycounter_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
y_counter <= (others => '0');
elsif unsigned(x_counter) = TH then
y_counter <= ycounter_next;
else
y_counter <= y_counter;
end if;
end if;
end process;
--ycounter state transition
y_counter_state_transition_process : process(y_counter)
begin
if unsigned(y_counter) = TV then
ycounter_next <= (others => '0');
else
ycounter_next <= std_logic_vector(unsigned(y_counter) + 1);
end if;
end process;
--hsync state register
hsync_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
hsync_state <= low;
else
hsync_state <= hsync_next_state;
end if;
end if;
end process;
--hsync state transition
hsync_state_transition_process : process(hsync_state,x_counter)
begin
case hsync_state is
when low => if unsigned(x_counter) = THp then
hsync_next_state <= high;
else
hsync_next_state <= low ;
end if;
when high => if unsigned(x_counter) = TH then
hsync_next_state <= low;
else
hsync_next_state <= high;
end if;
when others => hsync_next_state <= low ;
end case;
end process;
--hsync output function
hsync <= '1' when hsync_state = high else '0';
--vsync state register
vsync_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
vsync_state <= low;
else
vsync_state <= vsync_next_state;
end if;
end if;
end process;
--vsync state transition
vsync_state_transition_process : process(vsync_state,y_counter,x_counter)
begin
case vsync_state is
when low => if unsigned(y_counter) = TVp then
vsync_next_state <= high;
else
vsync_next_state <= low ;
end if;
when high => if unsigned(y_counter) = TV then
vsync_next_state <= ready_to_low;
else
vsync_next_state <= high;
end if;
when ready_to_low => if unsigned(x_counter) = TH then
vsync_next_state <= low;
else
vsync_next_state <= ready_to_low;
end if;
when others => vsync_next_state <= low ;
end case;
end process;
--vsync output function
vsync <= '0' when vsync_state = low else '1';
-- Process managing line state
line_state_register_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
line_state <= virtual;
else
line_state <= line_next_state;
end if;
end if;
end process;
--line_state transition
line_state_transition_process : process(line_state,y_counter)
begin
case line_state is
when virtual => if unsigned(y_counter) = TVs then
line_next_state <= real;
else
line_next_state <= virtual ;
end if;
when real => if unsigned(y_counter) = (TVd + TVs) then
line_next_state <= virtual;
else
line_next_state <= real;
end if;
when others => line_next_state <= virtual;
end case;
end process;
-- enable process management
enable_state_register_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
enable_state <= inactive;
else
enable_state <= enable_next_state;
end if;
end if;
end process;
--enable_state transition
enable_state_transition_process : process(enable_state,hsync_next_state,x,line_state)
begin
case enable_state is
when inactive => if hsync_next_state = high and line_state = real then
enable_next_state <= active;
else
enable_next_state <= inactive ;
end if;
when active => if unsigned(x) = (THd -1) then
enable_next_state <= done;
else
enable_next_state <= active;
end if;
when done => if hsync_next_state = low then
enable_next_state <= inactive;
else
enable_next_state <= done;
end if;
when others => enable_next_state <= inactive;
end case;
end process;
enable <= '1' when enable_state = active else '0';
x_out_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(x) = (THd -1) then
x <= (others => '0');
elsif enable_state = active then
x <= std_logic_vector(unsigned(x) + 1);
else
x <= x;
end if;
end if;
end process;
y_out_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
y_state <= inactive;
else
y_state <= y_next_state;
end if;
end if;
end process;
--y state transition
process(y_state,y_counter,hsync_state,hsync_next_state,vsync_state)
begin
case y_state is
when inactive => if unsigned(y_counter) = TVs then
y_next_state <= ready;
else
y_next_state <= inactive ;
end if;
when active => if hsync_state = low then
y_next_state <= done;
y <= std_logic_vector(unsigned(y) + 1);
else
y <= y;
y_next_state <= active;
end if;
when done => if unsigned(y) = (TVd - 1) then
y_next_state <= ready_to_reset;
else
y_next_state <= ready;
y <= y;
end if;
when ready_to_reset => if vsync_state = low then
y_next_state <= inactive;
y <= (others => '0');
else
y_next_state <= ready_to_reset;
y <= y;
end if;
when ready => if hsync_next_state = high then
y_next_state <= active;
else
y_next_state <= ready;
end if;
when others => y_next_state <= inactive ;
end case;
end process;
x_out <= x;
y_out <= y;
end v1_1;
architecture v1_2 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Constants for internal use
constant x_counter_low : positive := 1024 - THp ;
constant x_counter_low_start : positive := x_counter_low + 1;
constant x_counter_high : positive := 1024 - (TH - THp) + 1;
constant y_counter_low : positive := 1024 - TVp;
constant y_counter_high : positive := 1024 - (TV - TVp) + 1;
-- Internal signals
signal x_counter: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_low_start,11)); -- counter for x axis
signal x_counter_init: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_high,11)); -- counter for x axis
signal hsyncP : std_logic := '0';
signal hsyncN : std_logic := '1';
signal y_counterP: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(y_counter_low,11)); -- counter for x axis
signal y_counter_init: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(y_counter_high,11)); -- counter for x axis
-- FSM for vsync
type vsync_state_type is (low,after_low,high,ready_to_low,before_low);
signal vsyncP : vsync_state_type := low;
signal vsyncN : vsync_state_type := low ;
-- counter to determine if line is active or not
constant line_counter_low_start : positive := 512 - TVs;
constant line_counter_low : positive := 512 - (TV - TVd);
constant line_counter_high : positive := 512 - TVd + 1;
signal line_counter : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(line_counter_low_start,10));
signal line_counter_init : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(line_counter_low_start,10));
type line_state_type is(virtual,first_real,real,after_real);
signal line_stateP : line_state_type := virtual;
signal line_stateN : line_state_type := virtual;
begin -- behavorial
-- Process managing outputs
output_management : process(clk,rst)
begin
if rst = '1' then
-- vsync <= '0';
hsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
elsif rising_edge(clk) then
-- vsync <= vsyncP;
hsync <= hsyncP;
-- enable <= enableP;
-- x_out <= x_outP;
-- y_out <= x_outP;
end if;
end process;
-- process managing xcounter increment
xcounter_increment : process(clk,rst)
begin
if rst = '1' then
x_counter <= std_logic_vector(to_unsigned(x_counter_low_start,11));
hsyncP <= '0';
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_counter <= x_counter_init;
hsyncP <= hsyncN;
else
x_counter <= std_logic_vector(unsigned(x_counter)+1);
end if;
end if;
end process;
-- process preparing next hsync_value
prepare_next_hsync : process(hsyncP)
begin
case hsyncP is
when '0' => hsyncN <= '1';
when '1' => hsyncN <= '0';
when others => hsyncN <= '0';
end case;
end process;
-- process computing next x_counter_init
prepare_next_counter_init : process (hsyncP)
begin
case hsyncP is
when '0' => x_counter_init <= std_logic_vector(to_unsigned(x_counter_high,11));
when '1' => x_counter_init <= std_logic_vector(to_unsigned(x_counter_low,11));
when others => x_counter_init <= std_logic_vector(to_unsigned(x_counter_high,11));
end case;
end process;
-- process managing ycounter increment
ycounter_increment : process(clk,rst)
begin
if rst = '1' then
y_counterP <= std_logic_vector(to_unsigned(y_counter_low,11));
elsif rising_edge(clk) then
if x_counter(10) = '1' and hsyncP = '1' then
if y_counterP(10) = '1' then
y_counterP <= y_counter_init;
else
y_counterP <= std_logic_vector(unsigned(y_counterP) + 1);
end if;
else
y_counterP <= y_counterP;
end if;
end if;
end process;
-- prepare the init value for ycounter
prepare_ycounter_init : process(vsyncP)
begin
case vsyncP is
when low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
when after_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
when high => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,11));
when ready_to_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,11));
when others => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
end case;
end process;
--vsync state register
vsync_state_register_process : process(clk,rst)
begin
if rst = '1' then
vsyncP <= low;
elsif rising_edge(clk) then
vsyncP <= vsyncN;
end if;
end process;
--vsync state transition
vsync_state_transition_process : process(vsyncP,hsyncP,y_counterP,x_counter)
begin
case vsyncP is
when low => if y_counterP(10) = '1' then
vsyncN <= after_low;
else
vsyncN <= low ;
end if;
when after_low => if y_counterP(10) = '1' then
vsyncN <= after_low;
else
vsyncN <= high ;
end if;
when high => if y_counterP(10) = '1' and vsyncP = high then
vsyncN <= ready_to_low;
else
vsyncN <= high;
end if;
when ready_to_low => if x_counter(10) = '1' and hsyncP = '1' then
vsyncN <= before_low;
else
vsyncN <= ready_to_low;
end if;
when before_low => vsyncN <= low;
when others => vsyncN <= low ;
end case;
end process;
--vsync output function
apply_vsync : vsync <= '0' when vsyncP = low else '1';
-- Process managing line state
line_state_register: process(clk,rst)
begin
if rst = '1' then
line_stateP <= virtual;
elsif rising_edge(clk) then
line_stateP <= line_stateN;
end if;
end process;
--line_state transition
line_state_transition : process(line_stateP,line_counter(9))
begin
case line_stateP is
when virtual => if line_counter(9) = '1' then
line_stateN <= first_real ;
else
line_stateN <= virtual;
end if;
when first_real => if line_counter(9) = '0' then
line_stateN <= real;
else
line_stateN <= first_real;
end if;
when real => if line_counter(9) = '1' then
line_stateN <= after_real;
else
line_stateN <= real;
end if;
when after_real => if line_counter(9) = '0' then
line_stateN <= virtual;
else
line_stateN <= after_real;
end if;
when others => line_stateN <= virtual;
end case;
end process;
-- line counter increment
line_couter_increment : process(clk,rst)
begin
if rst = '1' then
line_counter <= std_logic_vector(to_unsigned(line_counter_low_start,10));
elsif rising_edge(clk) then
if x_counter(10) = '1' and hsyncP = '1' then
if line_counter(9) = '1' then
line_counter <= line_counter_init;
else
line_counter <= std_logic_vector(unsigned(line_counter) + 1);
end if;
end if;
end if;
end process;
prepare_line_counter_init : process(line_stateP)
begin
case line_stateP is
when virtual => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
when first_real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
when real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_low,10));
when after_real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_low,10));
when others => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
end case;
end process;
end v1_2;
architecture v1_3 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Constants for internal use
-- X axis
constant x_counter_low : positive := 1024 - THp ;
constant x_counter_low_start : positive := x_counter_low+1;
-- constant x_counter_low_start : positive := x_counter_low;
constant x_counter_valid : positive := 1024 - THd + 1;
constant x_counter_fill : positive := 1024 - (TH - THp - THd) + 1;
-- Y axis
constant y_counter_low : positive := 512 - TVp + 1;
constant y_counter_low_start : positive := y_counter_low;
constant y_counter_pre_fill : positive := 512 - (TVs - TVp) + 1;
constant y_counter_valid : positive := 512 - TVd + 1;
constant y_counter_post_fill : positive := 512 - (TV - TVp - TVs - TVd + 1) ;
-- Internal signals related to X axis
signal x_counter: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_low_start,11)); -- counter for x axis
signal x_counter_init: std_logic_vector( 10 downto 0) := (others => '0');
signal hsyncP : std_logic := '0';
signal enableP : std_logic := '0';
type x_fsm_state_type is (x_low,x_valid,x_fill);
signal x_fsm_stateP : x_fsm_state_type := x_low;
signal x_fsm_stateN : x_fsm_state_type := x_valid;
signal x : std_logic_vector(9 downto 0) := (others => '0');
-- Internal signals related to Y axis
signal y_counter: std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(y_counter_low_start,10)); -- counter for x axis
signal y_counter_init: std_logic_vector(9 downto 0) := (others => '0');
signal vsyncP : std_logic := '0';
type y_fsm_state_type is (y_low,y_pre_fill,y_valid,y_post_fill);
signal y_fsm_stateP : y_fsm_state_type;
signal y_fsm_stateN : y_fsm_state_type;
signal y : std_logic_vector(8 downto 0) := (others => '0');
begin -- behavorial
-- Process managing outputs
output_management : process(clk,rst)
begin
if rst = '1' then
hsync <= '0';
vsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
elsif rising_edge(clk) then
vsync <= vsyncP;
hsync <= hsyncP;
enable <= enableP;
x_out <= x;
y_out <= y;
end if;
end process;
-- process managing x_counter increment
x_counter_increment : process(clk,rst)
begin
if rst = '1' then
x_counter <= std_logic_vector(to_unsigned(x_counter_low_start,11));
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_counter <= x_counter_init;
else
x_counter <= std_logic_vector(unsigned(x_counter)+1);
end if;
end if;
end process;
-- process computing x_counter_init
prepare_x_counter_init : process (x_fsm_stateP)
begin
case x_fsm_stateP is
when x_low => x_counter_init <= std_logic_vector(to_unsigned(x_counter_valid,11));
when x_valid => x_counter_init <= std_logic_vector(to_unsigned(x_counter_fill,11));
when x_fill => x_counter_init <= std_logic_vector(to_unsigned(x_counter_low,11));
when others => x_counter_init <= (others => '0');
end case;
end process;
-- process computing next x_fsm_state
prepare_next_x_fsm_state : process (x_fsm_stateP)
begin
case x_fsm_stateP is
when x_low => x_fsm_stateN <= x_valid;
when x_valid => x_fsm_stateN <= x_fill;
when x_fill => x_fsm_stateN <= x_low;
when others => x_fsm_stateN <= x_low;
end case;
end process;
-- process managing x_fsm_state register
x_fsm_state_register : process(clk,rst)
begin
if rst = '1' then
x_fsm_stateP <= x_low;
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_fsm_stateP <= x_fsm_stateN;
else
x_fsm_stateP <= x_fsm_stateP;
end if;
end if;
end process;
apply_hsync : hsyncP <= '0' when x_fsm_stateP = x_low else '1';
-- process managing ycounter increment
ycounter_increment : process(clk,rst)
begin
if rst = '1' then
y_counter <= std_logic_vector(to_unsigned(y_counter_low_start,10));
elsif rising_edge(clk) then
if x_counter(10) = '1' and x_fsm_stateP = x_fill then
if y_counter(9) = '1' then
y_counter <= y_counter_init;
else
y_counter <= std_logic_vector(unsigned(y_counter) + 1);
end if;
else
y_counter <= y_counter;
end if;
end if;
end process;
-- prepare the init value for ycounter
prepare_ycounter_init : process(y_fsm_stateP)
begin
case y_fsm_stateP is
when y_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_pre_fill,10));
when y_pre_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_valid,10));
when y_valid => y_counter_init <= std_logic_vector(to_unsigned(y_counter_post_fill,10));
when y_post_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10));
when others => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10));
end case;
end process;
-- process computing next y_fsm_state
vsync_state_transition_process : process(y_fsm_stateP)
begin
case y_fsm_stateP is
when y_low => y_fsm_stateN <= y_pre_fill;
when y_pre_fill => y_fsm_stateN <= y_valid;
when y_valid => y_fsm_stateN <= y_post_fill;
when y_post_fill => y_fsm_stateN <= y_low;
when others => y_fsm_stateN <= y_low;
end case;
end process;
-- process managing y_fsm_state_register
y_fsm_state_register : process(clk,rst)
begin
if rst = '1' then
y_fsm_stateP <= y_low;
elsif rising_edge(clk) then
if y_counter(9) = '1' and x_counter(10) = '1' and x_fsm_stateP = x_fill then
y_fsm_stateP <= y_fsm_stateN;
else
y_fsm_stateP <= y_fsm_stateP;
end if;
end if;
end process;
--vsync output function
apply_vsync : vsyncP <= '0' when y_fsm_stateP = y_low else '1';
-- enable output function
apply_enable : enableP <= '1' when y_fsm_stateP = y_valid and x_fsm_stateP = x_valid else '0';
--process managing x increment
x_increment : process(clk,rst)
begin
if rst = '1' then
x <= (others => '0');
elsif rising_edge(clk) then
if x_fsm_stateP = x_valid and y_fsm_statep = y_valid then
if x_counter(10) = '0' then
x <= std_logic_vector(unsigned(x) + 1);
else
x <= (others => '0');
end if;
else
x <= x;
end if;
end if;
end process;
-- process managing y increment
y_increment : process(clk,rst)
begin
if rst = '1' then
y <= (others => '0');
elsif rising_edge(clk) then
if y_fsm_stateP = y_valid and x_fsm_stateP = x_fill then
if x_counter(10) = '1'then
if y_counter(9) = '0' then
y <= std_logic_vector(unsigned(y) + 1);
else
y <= (others => '0');
end if;
end if;
else
y <= y;
end if;
end if;
end process;
end v1_3;
| gpl-3.0 | df111b7ef508ea101ed737c9518a8b64 | 0.570163 | 3.616675 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-111/config.vhd | 1 | 5,587 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FC0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | f15820384ba6f2bb758cd3935a2dbc3c | 0.643458 | 3.673241 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-clock-gate/leon3mp.vhd | 1 | 32,044 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkx, clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal gclk : std_logic_vector(NCPU-1 downto 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkx, open, open, sdclkl, pciclk, cgi, cgo);
clkpwd : entity work.clkgate generic map (fabtech, NCPU, CFG_DSU)
port map (rstn, clkx, dsuo.pwd(NCPU-1 downto 0), clkm, gclk);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), gclk(i));
nodsu : if CFG_DSU = 0 generate
dsuo.pwd(i) <= dbgo(i).pwd and not dbgo(i).ipend;
end generate;
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
dbgi <= (others => dbgi_none);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0'; -- For second port
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, ports => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC,rmapbufs => CFG_SPW_RMAPBUF,
dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT, rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 69ae71595e0708aeb7b83a56c08c0eb5 | 0.560854 | 3.453762 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/synth/convolve_kernel_ap_fmul_3_max_dsp_32.vhd | 3 | 12,822 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_3_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_3_max_dsp_32_arch OF convolve_kernel_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=" &
"0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_" &
"THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_3_max_dsp_32_arch;
| mit | 70719938e38ab5a50a9973265933e81d | 0.651536 | 3.007036 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3mp/leon3mp.vhd | 1 | 31,994 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emddis : out std_logic;
epwrdwn : out std_ulogic;
ereset : out std_ulogic;
esleep : out std_ulogic;
epause : out std_ulogic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk : std_ulogic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED,
CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech, netlist => CFG_SPW_NETLIST,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
ports => 1, dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 6bdf998037ae9e5a1a53f2860ca15556 | 0.561293 | 3.466681 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/synth/zynq_design_1_rst_ps7_0_100M_0.vhd | 1 | 6,728 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_11;
USE proc_sys_reset_v5_0_11.proc_sys_reset;
ENTITY zynq_design_1_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zynq_design_1_rst_ps7_0_100M_0;
ARCHITECTURE zynq_design_1_rst_ps7_0_100M_0_arch OF zynq_design_1_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "zynq_design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "zynq_design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zynq_design_1_rst_ps7_0_100M_0_arch;
| mit | 7b8c1e6327419d954b3abd0e14010f70 | 0.71299 | 3.379206 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/sim/zynq_design_1_axi_gpio_0_0.vhd | 2 | 8,848 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zynq_design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zynq_design_1_axi_gpio_0_0;
ARCHITECTURE zynq_design_1_axi_gpio_0_0_arch OF zynq_design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_design_1_axi_gpio_0_0_arch;
| mit | b4bf4412a2dbe652b4b403609ff560b5 | 0.679476 | 3.231556 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/vga_clkgen.vhd | 3 | 1,981 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clkm : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clkm;
when "10" => clksel <= clk50;
when "11" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 | dab943c3637217ce81138ac732df72bc | 0.651691 | 3.675325 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/leon3s.vhd | 1 | 6,420 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc);
end;
| gpl-2.0 | ed1a73a2633ea3e9846730f68e3eba23 | 0.465576 | 3.965411 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-vc707/config.vhd | 1 | 11,155 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex7;
constant CFG_MEMTECH : integer := virtex7;
constant CFG_PADTECH : integer := virtex7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | ae731f30f40c7036b60bf6490dff0dc1 | 0.657463 | 3.534537 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-5/src/FinSM3.vhd | 1 | 1,162 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Task3 is
port (
CLK: in STD_LOGIC;
IP: in STD_LOGIC_VECTOR (3 downto 0);
RST: in STD_LOGIC;
OP: out STD_LOGIC_VECTOR (1 downto 0));
end Task3;
architecture Beh of Task3 is
type state_type is (
S0, S1, S2, S3, S4
);
signal state: state_type;
begin
state_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
state <= S0;
else
case state is
when S0 =>
if IP="0011" then
state <= S1;
end if;
when S1 =>
if IP="1111" then
state <= S4;
end if;
when S2 =>
if IP="1100" then
state <= S1;
end if;
when S3 =>
if IP="0000" then
state <= S2;
end if;
when S4 =>
if IP="1101" then
state <= S3;
end if;
when others =>
state <= S0;
end case;
end if;
end if;
end process;
OP_assignment:
OP <= "01" when (state = S0) else
"01" when (state = S1) else
"00" when (state = S2) else
"00" when (state = S3) else
"11" when (state = S4) else
"01";
end Beh;
| mit | c8a57d28e8301aa916807c4deaec0a19 | 0.551635 | 2.617117 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/srmmu/mmulru.vhd | 1 | 5,465 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
if (not RESET_ALL and (rst = '0')) or (reinit = '1') then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.bar <= lrui.mmctrl1.bar;
r.clear <= (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
r.clear(1 downto 0) <= "11"; -- reverse order
when "10" =>
r.clear(2 downto 0) <= "111"; -- reverse order
when "11" =>
r.clear(4 downto 0) <= "11111"; -- reverse order
when others =>
r.clear(0) <= '1';
end case;
end if;
end if;
end process p1;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
| gpl-2.0 | 9229d52b9664c57034e52dba1413ab68 | 0.562123 | 3.496481 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/sparc/cpu_disas.vhd | 1 | 4,306 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1'); --and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | a0c7c294aca75a965fd7f589991522f5 | 0.603344 | 3.4448 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_sfr.vhd | 1 | 16,654 | ------------------------------------------------------------------------------
-- Copyright (C) 2009 , Olivier Girard
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
-- *File Name: fmsp_sfr.v
--
-- *Module Description:
-- Processor Special function register
--
-- *Author(s):
-- - Olivier Girard, [email protected]
--
------------------------------------------------------------------------------
-- $Rev: 117 $
-- $LastChangedBy: olivier.girard $
-- $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_sfr is
generic (
INST_NR : integer := 0; -- Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; -- Program Memory Size
DMEM_SIZE : integer := 16384; -- Data Memory Size
PER_SIZE : integer := 16384; -- Peripheral Memory Size
MULTIPLIER : boolean := false; -- Include/Exclude Hardware Multiplier
USER_VERSION : integer := 0; -- Custom user version number
WATCHDOG : boolean := false; -- Include/Exclude Watchdog timer
NMI_EN : boolean := false -- Include/Exclude Non-Maskable-Interrupt support
);
port (
mclk : in std_logic; -- Main system clock
mrst : in std_logic; -- Main system reset
-- INPUTs
nmi : in std_logic; -- Non-maskable interrupt (asynchronous)
nmi_acc : in std_logic; -- Non-Maskable interrupt request accepted
per_addr : in std_logic_vector(13 downto 0); -- Peripheral address
per_din : in std_logic_vector(15 downto 0); -- Peripheral data input
per_en : in std_logic; -- Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); -- Peripheral write enable (high active)
wdtifg : in std_logic; -- Watchdog-timer interrupt flag
wdtnmies : in std_logic; -- Watchdog-timer NMI edge selection
-- OUTPUTs
cpu_id : out std_logic_vector(31 downto 0); -- CPU ID
nmi_pnd : out std_logic; -- NMI Pending
nmi_wkup : out std_logic; -- NMI Wakeup
per_dout : out std_logic_vector(15 downto 0); -- Peripheral data output
wdtie : out std_logic; -- Watchdog-timer interrupt enable
wdtifg_sw_clr : out std_logic; -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set : out std_logic -- Watchdog-timer interrupt flag software set
);
end entity fmsp_sfr;
architecture RTL of fmsp_sfr is
--=============================================================================
-- 1) PARAMETER DECLARATION
--=============================================================================
-- Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000000000000";
-- Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 4;
-- Register addresses offset
constant IE1 : integer := 0;
constant IFG1 : integer := 2;
constant CPU_ID_LO : integer := 4;
constant CPU_ID_HI : integer := 6;
constant CPU_NR : integer := 8;
-- Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
type fmsp_sfr_in_type is record
nmi : std_logic; -- Non-maskable interrupt (asynchronous)
nmi_acc : std_logic; -- Non-Maskable interrupt request accepted
per_addr : std_logic_vector(13 downto 0); -- Peripheral address
per_din : std_logic_vector(15 downto 0); -- Peripheral data input
per_en : std_logic; -- Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); -- Peripheral write enable (high active)
wdtifg : std_logic; -- Watchdog-timer interrupt flag
wdtnmies : std_logic; -- Watchdog-timer NMI edge selection
end record;
type reg_type is record
-- To outside of module
nmi_dly : std_logic; -- Non-maskable interrupt enable
nmie : std_logic; -- Non-maskable interrupt enable
wdtie : std_logic; -- Watchdog-timer interrupt enable
nmiifg : std_logic;
wdtifg : std_logic;
wdt_reset : std_logic; -- Watchdog-timer reset
end record;
signal d : fmsp_sfr_in_type;
signal r : reg_type := ( nmi_dly => '0',
nmie => '0',
wdtie => '0',
nmiifg => '0',
wdtifg => '0',
wdt_reset => '0'
);
signal rin : reg_type;
begin
d.nmi <= nmi;
d.nmi_acc <= nmi_acc;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
d.wdtifg <= wdtifg;
d.wdtnmies <= wdtnmies;
COMB : process (d, r)
variable v : reg_type;
-- Local register selection
variable v_reg_sel : std_logic;
-- Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
-- Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
-- Read/Write probes
variable v_reg_lo_write : std_logic;
variable v_reg_hi_write : std_logic;
variable v_reg_read : std_logic;
-- Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
-- IE1 Register
variable v_ie1 : std_logic_vector(7 downto 0);
variable v_ie1_wr : std_logic;
variable v_ie1_nxt : std_logic_vector(7 downto 0);
-- IFG1 Register
variable v_ifg1 : std_logic_vector(7 downto 0);
variable v_ifg1_wr : std_logic;
variable v_ifg1_nxt : std_logic_vector(7 downto 0);
variable v_wdtifg_sw_clr : std_logic; -- Watchdog-timer interrupt flag software clear
variable v_wdtifg_sw_set : std_logic; -- Watchdog-timer interrupt flag software set
variable v_cpu_version : std_logic_vector(2 downto 0);
variable v_cpu_asic : std_logic;
variable v_user_version : std_logic_vector(4 downto 0);
variable v_per_space : std_logic_vector(6 downto 0);
variable v_cpu_id_lo : std_logic_vector(15 downto 0);
variable v_mpy_info : std_logic;
variable v_dmem_size : std_logic_vector(8 downto 0);
variable v_pmem_size : std_logic_vector(5 downto 0);
variable v_cpu_id_hi : std_logic_vector(15 downto 0);
variable v_cpu_nr : std_logic_vector(15 downto 0);
-- Data output mux
variable v_reg_rdIE1 : std_logic_vector(15 downto 0);
variable v_reg_rdIFG1 : std_logic_vector(15 downto 0);
variable v_ie1_rd : std_logic_vector(15 downto 0);
variable v_ifg1_rd : std_logic_vector(15 downto 0);
variable v_cpu_id_lo_rd : std_logic_vector(15 downto 0);
variable v_cpu_id_hi_rd : std_logic_vector(15 downto 0);
variable v_cpu_nr_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
-- Watchdog reset generation
variable v_wdt_irq : std_logic; -- Watchdog-timer interrupt
variable v_nmie : std_logic; -- Non-maskable interrupt enable
variable v_wdt_reset : std_logic; -- Watchdog-timer reset
variable v_wdtie : std_logic; -- Watchdog-timer interrupt enable
variable v_nmi_s : std_logic; -- Non-maskable interrupt (synchronous)
variable v_nmi_edge : std_logic; -- Edge selection
variable v_nmi_pol : std_logic; -- Edge selection
variable v_nmi_pnd : std_logic; -- NMI Pending
variable v_nmi_wkup : std_logic; -- NMI Wakeup
begin
-- default assignment
v := r;
-- overriding assignments
--============================================================================
-- 2) REGISTER DECODER
--============================================================================
-- Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
-- Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
-- Register address decode
v_reg_dec := onehot(v_reg_addr);
-- Read/Write probes
v_reg_lo_write := v_reg_sel and d.per_we(0);
v_reg_hi_write := v_reg_sel and d.per_we(1);
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
-- Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_lo_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_hi_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
-- 3) REGISTERS
--============================================================================
-- IE1 Register
----------------
v_ie1_wr := v_reg_wr(IE1);
v_ie1_nxt := byte_per_select_din( IE1, d.per_din );
if (NMI_EN = true) then
if (d.nmi_acc = '1') then
v.nmie := '0';
elsif (v_ie1_wr = '1') then
v.nmie := v_ie1_nxt(4);
end if;
else
v.nmie := '0';
end if;
if (WATCHDOG = true) then
if (v_ie1_wr = '1') then
v.wdtie := v_ie1_nxt(0);
end if;
else
v.wdtie := '0';
end if;
v_ie1 := "000" & r.nmie & "000" & r.wdtie;
-- IFG1 Register
-----------------
v_ifg1_wr := v_reg_wr(IFG1);
v_ifg1_nxt := byte_per_select_din( IFG1, d.per_din );
-- if (NMI_EN = true) then
-- if (mrst = '1') then
-- v.nmiifg := '0';
-- else
-- if (v_nmi_edge = '1') then
-- v.nmiifg := '1';
-- elsif (v_ifg1_wr = '1') then
-- v.nmiifg := v_ifg1_nxt(4);
-- end if;
-- end if;
-- else
-- v.nmiifg := '0';
-- end if;
if (WATCHDOG = true) then
v_wdtifg_sw_clr := v_ifg1_wr and not(v_ifg1_nxt(0));
v_wdtifg_sw_set := v_ifg1_wr and v_ifg1_nxt(0);
else
v_wdtifg_sw_clr := '0';
v_wdtifg_sw_set := '0';
end if;
-- if (por = '1') then
-- v.wdtifg := '0';
-- else
-- if (d.wdtifg_set = '1') then
-- v.wdtifg := '1';
-- elsif ((d.wdttmsel and d.wdtifg_clr) = '1') then
-- v.wdtifg := '0';
-- elsif (v_ifg1_wr = '1') then
-- v.wdtifg := v_ifg1_nxt(0);
-- end if;
-- end if;
v_ifg1 := "000" & r.nmiifg & "000" & d.wdtifg;
-- CPU_ID Register (READ ONLY)
-------------------------------
-- -------------------------------------------------------------------
-- CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
-- |----------------------------+-----------------+------+-------------|
-- | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
-- --------------------------------------------------------------------
-- CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
-- |----------------------------+-------------------------------+------|
-- | PMEM_SIZE | DMEM_SIZE | MPY |
-- -------------------------------------------------------------------
v_cpu_version := STD_LOGIC_VECTOR(TO_UNSIGNED(C_CPU_VERSION,3));
v_cpu_asic := '0';
v_user_version := STD_LOGIC_VECTOR(TO_UNSIGNED(USER_VERSION,5));
v_per_space := STD_LOGIC_VECTOR(TO_UNSIGNED(PER_SIZE/512,7)); -- cpu_id_per * 512 = peripheral space size
if (MULTIPLIER = true) then
v_mpy_info := '1';
else
v_mpy_info := '0';
end if;
v_dmem_size := STD_LOGIC_VECTOR(TO_UNSIGNED(DMEM_SIZE/128,9)); -- cpu_id_dmem * 128 = data memory size
v_pmem_size := STD_LOGIC_VECTOR(TO_UNSIGNED(PMEM_SIZE/1024,6)); -- cpu_id_pmem * 1024 = program memory size
v_cpu_id_hi := v_pmem_size & v_dmem_size & v_mpy_info;
v_cpu_id_lo := v_per_space & v_user_version & v_cpu_asic & v_cpu_version;
-- CPU_NR Register (READ ONLY)
-------------------------------
-- -------------------------------------------------------------------
-- | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
-- |---------------------------------+---------------------------------|
-- | CPU_TOTAL_NR | CPU_INST_NR |
-- -------------------------------------------------------------------
v_cpu_nr := STD_LOGIC_VECTOR(TO_UNSIGNED(TOTAL_NR,8)) & STD_LOGIC_VECTOR(TO_UNSIGNED(INST_NR,8));
--============================================================================
-- 4) DATA OUTPUT GENERATION
--============================================================================
v_ie1_rd := byte_per_select_dout( IE1, v_reg_rd, v_ie1 );
v_ifg1_rd := byte_per_select_dout( IFG1, v_reg_rd, v_ifg1 );
v_cpu_id_lo_rd := word_per_select_dout( CPU_ID_LO, v_reg_rd, v_cpu_id_lo );
v_cpu_id_hi_rd := word_per_select_dout( CPU_ID_HI, v_reg_rd, v_cpu_id_hi );
v_cpu_nr_rd := word_per_select_dout( CPU_NR, v_reg_rd, v_cpu_nr );
v_per_dout := v_ie1_rd or v_ifg1_rd or v_cpu_id_lo_rd or v_cpu_id_hi_rd or v_cpu_nr_rd;
--=============================================================================
-- 5) NMI GENERATION
--=============================================================================
-- NOTE THAT THE NMI INPUT IS ASSUMED TO BE NON-GLITCHY
if (NMI_EN = true) then
-------------------------------------
-- Edge selection
-------------------------------------
v_nmi_pol := d.nmi xor d.wdtnmies;
-------------------------------------
-- Pulse capture and synchronization
v_nmi_s := v_nmi_pol;
-------------------------------------
-- NMI Pending flag
-------------------------------------
-- Delay
v.nmi_dly := v_nmi_s;
-- Edge detection
v_nmi_edge := not(r.nmi_dly) and v_nmi_s;
-- NMI pending
v_nmi_pnd := r.nmiifg and r.nmie;
-- NMI wakeup
v_nmi_wkup := '0';
else
v_nmi_pnd := '0';
v_nmi_wkup := '0';
end if;
if (NMI_EN = true) then
if (v_nmi_edge = '1') then
v.nmiifg := '1';
elsif (v_ifg1_wr = '1') then
v.nmiifg := v_ifg1_nxt(4);
end if;
else
v.nmiifg := '0';
end if;
-- drive register inputs
rin <= v;
-- drive module outputs
cpu_id <= v_cpu_id_hi & v_cpu_id_lo;
nmi_pnd <= v_nmi_pnd; -- NMI pending
nmi_wkup <= v_nmi_wkup; -- NMI wakeup
per_dout <= v_per_dout; -- Peripheral data output
wdtie <= r.wdtie; -- Watchdog-timer interrupt enable
wdtifg_sw_clr <= v_wdtifg_sw_clr; -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set <= v_wdtifg_sw_set; -- Watchdog-timer interrupt flag software set
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r.nmie <= '0';
r.nmi_dly <= '0';
r.wdtie <= '0';
r.nmiifg <= '0';
r.wdtifg <= '0';
r.wdt_reset <= '0';
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
end RTL; | bsd-3-clause | c10452697717d69ad5dc65625b1109ee | 0.537649 | 2.969157 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_core.vhd | 1 | 17,648 | ------------------------------------------------------------------------------
-- Copyright (C) 2009 , Emmanuel Amadio
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_core.vhd
--!
--! @brief fpgaMSP430 Core
--
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_core is
generic (
PMEM_SIZE : integer := 32768; -- Program Memory Size
DMEM_SIZE : integer := 16384; -- Data Memory Size
PER_SIZE : integer := 16384; -- Peripheral Memory Size
DMA_IF_EN : boolean := false; -- Include/Exclude DMA interface support
IRQ_NR : integer := 16; -- Number of IRQs
CPUOFF_EN : boolean := false -- Wakeup condition from DMA interface
);
port (
mclk : in std_logic; -- Main system clock
mrst : in std_logic; -- Main system reset
-- Debug Interface
dbg_halt_cmd : in std_logic := '0';
dbg_halt_st : out std_logic := '0';
dbg_reg_din : out std_logic_vector(15 downto 0) := x"0000";
dbg_reg_wr : in std_logic := '0';
dbg_mem_addr : in std_logic_vector(15 downto 0);
dbg_mem_dout : in std_logic_vector(15 downto 0) := x"0000";
dbg_mem_din : out std_logic_vector(15 downto 0) := x"0000";
dbg_mem_en : in std_logic := '0';
dbg_mem_wr : in std_logic_vector(1 downto 0) := "00";
-- Execution unit memory bus
eu_mem_addr : out std_logic_vector(15 downto 0); -- Execution-Unit Memory address bus
eu_mem_en : out std_logic; -- Execution-Unit Memory bus enable
eu_mem_wr : out std_logic_vector(1 downto 0); -- Execution-Unit Memory bus write transfer
-- Frontend memory bus
fe_mem_din : out std_logic_vector(15 downto 0); -- Frontend Memory data bus input
-- DMA access
dma_addr : in std_logic_vector(15 downto 1); -- Direct Memory Access address
dma_dout : out std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_din : in std_logic_vector(15 downto 0); -- Direct Memory Access data input
dma_en : in std_logic; -- Direct Memory Access enable (high active)
dma_we : in std_logic_vector(1 downto 0); -- Direct Memory Access write byte enable (high active)
dma_priority : in std_logic; -- Direct Memory Access priority (0:low / 1:high)
dma_ready : out std_logic; -- Direct Memory Access is complete
dma_resp : out std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr : out std_logic_vector(13 downto 0); -- Peripheral address
per_dout : in std_logic_vector(15 downto 0); -- Peripheral data output
per_din : out std_logic_vector(15 downto 0); -- Peripheral data input
per_en : out std_logic; -- Peripheral enable (high active)
per_we : out std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
-- Program memory
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); -- Program Memory address
pmem_dout : in std_logic_vector(15 downto 0); -- Program Memory data output
pmem_din : out std_logic_vector(15 downto 0); -- Program Memory data input (optional)
pmem_cen : out std_logic; -- Program Memory chip enable (low active)
pmem_wen : out std_logic_vector(1 downto 0); -- Program Memory write enable (low active) (optional)
-- Data memory
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); -- Data Memory address
dmem_dout : in std_logic_vector(15 downto 0); -- Data Memory data output
dmem_din : out std_logic_vector(15 downto 0); -- Data Memory data input
dmem_cen : out std_logic; -- Data Memory chip enable (low active)
dmem_wen : out std_logic_vector(1 downto 0); -- Data Memory write byte enable (low active)
-- Non maskable interrupt
nmi_acc : out std_logic;
nmi_pnd : in std_logic;
nmi_wkup : in std_logic;
-- Watchdog interrupt
wdt_irq : in std_logic;
wdt_wkup : in std_logic;
-- Interrupts
irq : in std_logic_vector(IRQ_NR-3 downto 0); -- Maskable interrupts (14, 30 or 62)
irq_acc : out std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
cpu_en_s : in std_logic;
decode_noirq : out std_logic;
pc : out std_logic_vector(15 downto 0);
cpuoff : out std_logic;
oscoff : out std_logic;
scg1 : out std_logic
);
end entity fmsp_core;
architecture RTL of fmsp_core is
--=============================================================================
-- 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
--=============================================================================
type core_wires_type is record
inst_ad : std_logic_vector(7 downto 0);
inst_as : std_logic_vector(7 downto 0);
inst_alu : std_logic_vector(11 downto 0);
inst_bw : std_logic;
inst_irq_rst : std_logic;
inst_mov : std_logic;
inst_dest : std_logic_vector(15 downto 0);
inst_dext : std_logic_vector(15 downto 0);
inst_sext : std_logic_vector(15 downto 0);
inst_so : std_logic_vector(7 downto 0);
inst_src : std_logic_vector(15 downto 0);
inst_type : std_logic_vector(2 downto 0);
inst_jmp : std_logic_vector(7 downto 0);
exec_state : std_logic_vector(3 downto 0);
exec_done : std_logic;
cpu_halt_st : std_logic;
cpu_halt_cmd : std_logic;
-- Execution unit memory bus
eu_mem_addr : std_logic_vector(15 downto 0);
eu_mem_dout : std_logic_vector(15 downto 0);
eu_mem_din : std_logic_vector(15 downto 0);
eu_mem_wr : std_logic_vector(1 downto 0);
eu_mem_en : std_logic;
-- Frontend memory bus
fe_mem_addr : std_logic_vector(15 downto 0);
fe_mem_din : std_logic_vector(15 downto 0);
fe_mem_en : std_logic;
fe_mem_wait : std_logic;
-- Program counter
eu_pc_sw_wr : std_logic;
eu_pc_sw : std_logic_vector(15 downto 0);
fe_pc : std_logic_vector(15 downto 0);
fe_pc_nxt : std_logic_vector(15 downto 0);
cpuoff : std_logic;
oscoff : std_logic;
scg1 : std_logic;
gie : std_logic;
end record;
signal wires : core_wires_type;
begin
--=============================================================================
-- 3) FRONTEND (<=> FETCH & DECODE)
--=============================================================================
frontend_0 : fmsp_frontend
generic map(
CPUOFF_EN => CPUOFF_EN, -- Wakeup condition from DMA interface
DMA_IF_EN => DMA_IF_EN, -- Wakeup condition from DMA interface
IRQ_NR => IRQ_NR -- Number of IRQs
)
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- Memory bus
mdb_in => wires.fe_mem_din, -- Frontend Memory data bus input
mab => wires.fe_mem_addr, -- Frontend Memory address bus
mb_en => wires.fe_mem_en, -- Frontend Memory bus enable
fe_pmem_wait => wires.fe_mem_wait, -- Frontend wait for Instruction fetch
-- INPUTs
cpu_en_s => cpu_en_s, -- Enable CPU code execution (synchronous)
cpu_halt_cmd => wires.cpu_halt_cmd, -- Halt CPU command
cpuoff => wires.cpuoff, -- Turns off the CPU
dbg_reg_sel => dbg_mem_addr(3 downto 0), -- Debug selected register for rd/wr access
dma_en => dma_en, -- Direct Memory Access enable (high active)
gie => wires.gie, -- General interrupt enable
-- Interrupts
irq => irq, -- Maskable interrupts
irq_acc => irq_acc, -- Interrupt request accepted
-- Non maskable interrupt
nmi_acc => nmi_acc, -- Non-Maskable interrupt request accepted
nmi_pnd => nmi_pnd, -- Non-maskable interrupt pending
nmi_wkup => nmi_wkup, -- NMI Wakeup
-- Watchdog interrupt
wdt_irq => wdt_irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_wkup, -- Watchdog Wakeup
-- OUTPUTs
cpu_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
decode_noirq => decode_noirq, -- Frontend decode instruction
-- Decoded signals to execution unit
e_state => wires.exec_state, -- Execution state
exec_done => wires.exec_done, -- Execution completed
inst_ad => wires.inst_ad, -- Decoded Inst: destination addressing mode
inst_as => wires.inst_as, -- Decoded Inst: source addressing mode
inst_alu => wires.inst_alu, -- ALU control signals
inst_bw => wires.inst_bw, -- Decoded Inst: byte width
inst_dest => wires.inst_dest, -- Decoded Inst: destination (one hot)
inst_dext => wires.inst_dext, -- Decoded Inst: destination extended instruction word
inst_irq_rst => wires.inst_irq_rst, -- Decoded Inst: Reset interrupt
inst_jmp => wires.inst_jmp, -- Decoded Inst: Conditional jump
inst_mov => wires.inst_mov, -- Decoded Inst: mov instruction
inst_sext => wires.inst_sext, -- Decoded Inst: source extended instruction word
inst_so => wires.inst_so, -- Decoded Inst: Single-operand arithmetic
inst_src => wires.inst_src, -- Decoded Inst: source (one hot)
inst_type => wires.inst_type, -- Decoded Instruction type
-- Program counter
pc_sw => wires.eu_pc_sw, -- Program counter software value
pc_sw_wr => wires.eu_pc_sw_wr, -- Program counter software write
pc => wires.fe_pc, -- Program counter
pc_nxt => wires.fe_pc_nxt -- Next PC value (for CALL & IRQ)
);
--=============================================================================
-- 4) EXECUTION UNIT
--=============================================================================
execution_unit_0 : fmsp_execution_unit
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- INPUTs
gie => wires.gie, -- General interrupt enable
dbg_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
dbg_mem_dout => dbg_mem_dout, -- Debug unit data output
dbg_reg_wr => dbg_reg_wr, -- Debug unit CPU register write
dbg_reg_din => dbg_reg_din, -- Debug unit CPU register data input
-- Memory bus
mdb_in => wires.eu_mem_din, -- Memory data bus input
mab => wires.eu_mem_addr, -- Memory address bus
mb_en => wires.eu_mem_en, -- Memory bus enable
mb_wr => wires.eu_mem_wr, -- Memory bus write transfer
mdb_out => wires.eu_mem_dout, -- Memory data bus output
-- Decoded signals from frontend
e_state => wires.exec_state, -- Execution state
exec_done => wires.exec_done, -- Execution completed
inst_ad => wires.inst_ad, -- Decoded Inst: destination addressing mode
inst_as => wires.inst_as, -- Decoded Inst: source addressing mode
inst_alu => wires.inst_alu, -- ALU control signals
inst_bw => wires.inst_bw, -- Decoded Inst: byte width
inst_dest => wires.inst_dest, -- Decoded Inst: destination (one hot)
inst_dext => wires.inst_dext, -- Decoded Inst: destination extended instruction word
inst_irq_rst => wires.inst_irq_rst, -- Decoded Inst: reset interrupt
inst_jmp => wires.inst_jmp, -- Decoded Inst: Conditional jump
inst_mov => wires.inst_mov, -- Decoded Inst: mov instruction
inst_sext => wires.inst_sext, -- Decoded Inst: source extended instruction word
inst_so => wires.inst_so, -- Decoded Inst: Single-operand arithmetic
inst_src => wires.inst_src, -- Decoded Inst: source (one hot)
inst_type => wires.inst_type, -- Decoded Instruction type
-- Program counter
pc => wires.fe_pc, -- Program counter
pc_nxt => wires.fe_pc_nxt, -- Next PC value (for CALL & IRQ)
pc_sw => wires.eu_pc_sw, -- Program counter software value
pc_sw_wr => wires.eu_pc_sw_wr, -- Program counter software write
-- OUTPUTs
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1 -- System clock generator 1. Turns off the SMCLK
);
--=============================================================================
-- 5) MEMORY BACKBONE
--=============================================================================
mem_backbone_0 : fmsp_mem_backbone
generic map(
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
DMA_IF_EN => DMA_IF_EN -- Wakeup condition from DMA interface
)
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- INPUTs
-- OUTPUTs
cpu_halt_cmd => wires.cpu_halt_cmd, -- Halt CPU command
cpu_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
-- Debug interface
dbg_halt_cmd => dbg_halt_cmd, -- Debug interface Halt CPU command
dbg_mem_addr => dbg_mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_mem_dout, -- Debug unit data output
dbg_mem_din => dbg_mem_din, -- Debug unit Memory data input
dbg_mem_en => dbg_mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_mem_wr, -- Debug unit memory write
-- Frontend memory bus
fe_mab => wires.fe_mem_addr(15 downto 1), -- Frontend Memory address bus
fe_mdb_in => wires.fe_mem_din, -- Frontend Memory data bus input
fe_mb_en => wires.fe_mem_en, -- Frontend Memory bus enable
fe_pmem_wait => wires.fe_mem_wait, -- Frontend wait for Instruction fetch
-- Execution Unit memory bus
eu_mab => wires.eu_mem_addr(15 downto 1), -- Execution Unit Memory address bus
eu_mdb_out => wires.eu_mem_dout, -- Execution Unit Memory data bus output
eu_mdb_in => wires.eu_mem_din, -- Execution Unit Memory data bus input
eu_mb_en => wires.eu_mem_en, -- Execution Unit Memory bus enable
eu_mb_wr => wires.eu_mem_wr, -- Execution Unit Memory bus write transfer
-- DMA bus
dma_addr => dma_addr&'0', -- Direct Memory Access address
dma_dout => dma_dout, -- Direct Memory Access data output
dma_din => dma_din, -- Direct Memory Access data input
dma_en => dma_en, -- Direct Memory Access enable (high active)
dma_we => dma_we, -- Direct Memory Access write byte enable (high active)
dma_priority => dma_priority, -- Direct Memory Access priority (0:low / 1:high)
dma_ready => dma_ready, -- Direct Memory Access is complete
dma_resp => dma_resp, -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr => per_addr, -- Peripheral address
per_dout => per_dout, -- Peripheral data output
per_din => per_din, -- Peripheral data input
per_en => per_en, -- Peripheral enable (high active)
per_we => per_we, -- Peripheral write enable (high active)
-- Data memory
dmem_addr => dmem_addr, -- Data Memory address
dmem_dout => dmem_dout, -- Data Memory data output
dmem_din => dmem_din, -- Data Memory data input
dmem_cen => dmem_cen, -- Data Memory chip enable (low active)
dmem_wen => dmem_wen, -- Data Memory write enable (low active)
-- Program memory
pmem_addr => pmem_addr, -- Program Memory address
pmem_dout => pmem_dout, -- Program Memory data output
pmem_din => pmem_din, -- Program Memory data input (optional)
pmem_cen => pmem_cen, -- Program Memory chip enable (low active)
pmem_wen => pmem_wen -- Program Memory write enable (low active) (optional)
);
-- Execution unit memory bus
eu_mem_addr <= wires.eu_mem_addr;
eu_mem_en <= wires.eu_mem_en;
eu_mem_wr <= wires.eu_mem_wr;
-- Frontend memory bus
fe_mem_din <= wires.fe_mem_din;
dbg_halt_st <= wires.cpu_halt_st;
cpuoff <= wires.cpuoff;
oscoff <= wires.oscoff;
pc <= wires.fe_pc;
scg1 <= wires.scg1;
end RTL; -- fmsp430
| bsd-3-clause | 433e54770747964750cb463af8388b09 | 0.615481 | 3.035432 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/GPR/src/OneHot.vhd | 1 | 3,816 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library gpr;
use gpr.OneHotGPR.all;
entity OneHot is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end OneHot;
architecture Beh_GPR of OneHot is
component MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end component;
component MRAM is
port (
RW: in std_logic;
CLK: in std_logic;
ADDR1: in mem_addr;
ADDR2: in mem_addr;
ADDRW: in mem_addr;
DWIN: in operand;
D1OUT: out operand;
D2OUT: out operand
);
end component;
component DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand 1
OP1 : in operand;
-- operand 2
OP2 : in operand;
-- result
RES: out operand;
-- zero flag
ZF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ROM
ROM_re: out std_logic;
ROM_addr: out mem_addr;
ROM_dout: in command;
-- RAM
RAM_rw: out std_logic;
RAM_addr1: out mem_addr;
RAM_addr2: out mem_addr;
RAM_addrw: out mem_addr;
RAM_dwin: out operand;
RAM_d1out: in operand;
RAM_d2out: in operand;
-- datapath
DP_op1: out operand;
DP_op2: out operand;
DP_ot: out operation;
DP_en: out std_logic;
DP_res: in operand;
DP_zf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_addr: mem_addr;
signal rom_dout: command;
signal ram_rw: std_logic;
signal ram_addr1: mem_addr;
signal ram_addr2: mem_addr;
signal ram_addrw: mem_addr;
signal ram_dwin: operand;
signal ram_d1out: operand;
signal ram_d2out: operand;
signal dp_op1: operand;
signal dp_op2: operand;
signal dp_ot: operation;
signal dp_en: std_logic;
signal dp_res: operand;
signal dp_zf: std_logic;
begin
UMRAM: MRAM
port map(
RW => ram_rw,
CLK => CLK,
ADDR1 => ram_addr1,
ADDR2 => ram_addr2,
ADDRW => ram_addrw,
DWIN => ram_dWin,
D1OUT => ram_d1out,
D2OUT => ram_d2out
);
UMROM: MROM
port map (
RE => rom_re,
ADDR => rom_addr,
DOUT => rom_dout
);
UDPATH: DPATH
port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
OP2 => dp_op2,
RES => dp_res,
ZF => dp_zf
);
UCTRL1: CTRL1
port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADDR => rom_addr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADDR1 => ram_addr1,
RAM_ADDR2 => ram_addr2,
RAM_ADDRW => ram_addrw,
RAM_DWIN => ram_dwin,
RAM_D1OUT => ram_d1out,
RAM_D2OUT => ram_d2out,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_OP2 => dp_op2,
DP_RES => dp_res,
DP_ZF => dp_zf
);
end Beh_GPR;
| mit | 2a2bd145d67a42922ae3f40b198d4a27 | 0.43501 | 3.812188 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/altera_mf/clkgen_altera_mf.vhd | 1 | 7,109 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 0e9e560d6f4ec64cc25cb427a3dd81d6 | 0.591926 | 3.476284 | false | false | false | false |
daniw/fpga-test | sp605/demo/blink.vhd | 1 | 585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blink is
Port ( en : in STD_LOGIC;
clk : in STD_LOGIC;
led : out STD_LOGIC);
end blink;
architecture behavioral of blink is
signal led_tmp : STD_LOGIC;
begin
BLINK : process(en,clk,led_tmp)
begin
if clk = '1' and clk'event then
if en = '0' then
led_tmp <= '0';
else
led_tmp <= not led_tmp;
end if;
else
led_tmp <= led_tmp;
end if;
end process;
led <= led_tmp;
end behavioral;
| gpl-2.0 | 41b4d10f36b7dbc80ab57fbd4d21bb30 | 0.504274 | 3.524096 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_multiplier.vhd | 1 | 15,694 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_multiplier.vhd
--!
--! @brief fpgaMSP430 16x16 Hardware multiplier.
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_multiplier is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! OUTPUTs
per_dout : out std_logic_vector(15 downto 0) --! Peripheral data output
);
end entity fmsp_multiplier;
architecture RTL of fmsp_multiplier is
--=============================================================================
--! 1) PARAMETER/REGISTERS & WIRE DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000100110000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 4;
--! Register addresses offset
constant OP1_MPY : integer := 0;
constant OP1_MPYS : integer := 2;
constant OP1_MAC : integer := 4;
constant OP1_MACS : integer := 6;
constant OP2 : integer := 8;
constant RESLO : integer := 10;
constant RESHI : integer := 12;
constant SUMEXT : integer := 14;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := 2**DEC_WD;
constant BASE_REG : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1, DEC_SZ));
constant OP1_MPY_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MPY, DEC_SZ));
constant OP1_MPYS_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MPYS, DEC_SZ));
constant OP1_MAC_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MAC, DEC_SZ));
constant OP1_MACS_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MACS, DEC_SZ));
constant OP2_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP2, DEC_SZ));
constant RESLO_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(RESLO, DEC_SZ));
constant RESHI_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(RESHI, DEC_SZ));
constant SUMEXT_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(SUMEXT, DEC_SZ));
type fmsp_multiplier_in_type is record
mrst : std_logic; --! Main system reset
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
end record;
type reg_type is record
op1 : std_logic_vector(15 downto 0);
op2 : std_logic_vector(15 downto 0);
reslo : std_logic_vector(15 downto 0);
reshi : std_logic_vector(15 downto 0);
sumext_s : std_logic_vector(1 downto 0);
sign_sel : std_logic; --! Detect signed mode
acc_sel : std_logic; --! Detect accumulate mode
cycle : std_logic;--! Detect start of a multiplication
--! To outside of module
nmie : std_logic; --! Non-maskable interrupt enable
wdtie : std_logic; --! Watchdog-timer interrupt enable
nmiifg : std_logic;
wdtifg : std_logic;
wdt_reset : std_logic; --! Watchdog-timer reset
end record;
signal d : fmsp_multiplier_in_type;
signal r : reg_type := ( op1 => x"0000",
op2 => x"0000",
reslo => x"0000",
reshi => x"0000",
sumext_s => "00",
sign_sel => '0', --! Detect signed mode
acc_sel => '0', --! Detect accumulate mode
cycle => '0', --! Detect start of a multiplication
nmie => '0',
wdtie => '0',
nmiifg => '0',
wdtifg => '0',
wdt_reset => '0'
);
signal rin : reg_type;
begin
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
COMB : process (d, r)
variable v : reg_type;
--! Wire pre-declarations
variable v_result_wr : std_logic;
variable v_result_clr : std_logic;
-- variable v_early_read : std_logic;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
--! OP1 Register
-------------------!
variable v_op1_wr : std_logic;
variable v_op1_rd : std_logic_vector(15 downto 0);
--! OP2 Register
-------------------!
variable v_op2_wr : std_logic;
variable v_op2_rd : std_logic_vector(15 downto 0);
--! RESLO Register
-------------------!
variable v_reslo_nxt : std_logic_vector(15 downto 0);
variable v_reslo_wr : std_logic;
variable v_reslo_rd : std_logic_vector(15 downto 0);
--! RESHI Register
-------------------!
variable v_reshi_nxt : std_logic_vector(15 downto 0);
variable v_reshi_wr : std_logic;
variable v_reshi_rd : std_logic_vector(15 downto 0);
--! SUMEXT Register
-------------------!
variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
variable v_sumext_nxt : std_logic_vector(15 downto 0);
variable v_sumext : std_logic_vector(15 downto 0);
variable v_sumext_rd : std_logic_vector(15 downto 0);
variable v_op1_mux : std_logic_vector(15 downto 0);
variable v_op2_mux : std_logic_vector(15 downto 0);
variable v_reslo_mux : std_logic_vector(15 downto 0);
variable v_reshi_mux : std_logic_vector(15 downto 0);
variable v_sumext_mux : std_logic_vector(15 downto 0);
--! Combine RESHI & RESLO
variable v_result : std_logic_vector(31 downto 0);
-- variable v_op1_xp : std_logic_vector(16 downto 0);
-- variable v_op2_xp : std_logic_vector(16 downto 0);
--! 17x17 signed multiplication
variable v_product : signed(33 downto 0);
--! Accumulate
variable v_result_nxt : signed(32 downto 0);
--! Next register values
-- variable v_reslo_nxt : std_logic_vector(15 downto 0);
-- variable v_reshi_nxt : std_logic_vector(15 downto 0);
-- variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
--! Expand the operands to support signed & unsigned operations
variable v_op1_xp : std_logic_vector(16 downto 0);
variable v_op2_xp : std_logic_vector(16 downto 0);
--! 17x9 signed multiplication
-- variable v_product : std_logic_vector(25 downto 0);
variable v_product_xp : std_logic_vector(31 downto 0);
--! Accumulate
-- variable v_result_nxt : std_logic_vector(32 downto 0);
--! Next register values
variable v_per_dout : std_logic_vector(15 downto 0);
-- variable v_reshi_nxt : std_logic_vector(15 downto 0);
-- variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Local register selection
if (d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD)) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_write := (d.per_we(1) or d.per_we(0)) and v_reg_sel;
v_reg_read := not(d.per_we(1) or d.per_we(0)) and v_reg_sel;
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 3) REGISTERS
--============================================================================
--! OP1 Register
-------------------!
v_op1_wr := v_reg_wr(OP1_MPY) or
v_reg_wr(OP1_MPYS) or
v_reg_wr(OP1_MAC) or
v_reg_wr(OP1_MACS);
if (v_op1_wr = '1') then
v.op1 := d.per_din;
end if;
v_op1_rd := r.op1;
--! OP2 Register
-------------------!
v_op2_wr := v_reg_wr(OP2);
if (v_op2_wr = '1') then
v.op2 := d.per_din;
end if;
v_op2_rd := r.op2;
--! RESLO Register
-------------------!
v_reslo_wr := v_reg_wr(RESLO);
if (v_reslo_wr = '1') then
v.reslo := d.per_din;
elsif (v_result_clr = '1') then
v.reslo := x"0000";
elsif (v_result_wr = '1') then
v.reslo := v_reslo_nxt;
end if;
-- if (v_early_read = '1') then
-- v_reslo_rd := v_reslo_nxt;
-- else
v_reslo_rd := r.reslo;
-- end if;
--! RESHI Register
-------------------!
v_reshi_wr := v_reg_wr(RESLO);
if (v_reshi_wr = '1') then
v.reshi := d.per_din;
elsif (v_result_clr = '1') then
v.reshi := x"0000";
elsif (v_result_wr = '1') then
v.reshi := v_reshi_nxt;
end if;
-- if (v_early_read = '1') then
-- v_reshi_rd := v_reshi_nxt;
-- else
v_reshi_rd := r.reshi;
-- end if;
--! SUMEXT Register
-------------------!
-- v_sumext_nxt := (0 => v_sumext_s_nxt(0), others => v_sumext_s_nxt(1));
v_sumext := (0 => r.sumext_s(0), others => r.sumext_s(1));
v_sumext_rd := v_sumext;
if (v_op2_wr = '1') then
v.sumext_s := (Others => '0');
elsif (v_result_wr = '1') then
v.sumext_s := v_sumext_s_nxt;
end if;
--============================================================================
--! 4) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_op1_mux := word_per_select_dout( OP1_MPY, v_reg_rd, v_op2_rd );
-- if ( (v_reg_rd(OP1_MPY) = '1') or (v_reg_rd(OP1_MPYS) = '1') or (v_reg_rd(OP1_MAC) = '1') or (v_reg_rd(OP1_MACS) = '1') ) then
if ( (v_reg_rd(OP1_MPYS) = '1') or (v_reg_rd(OP1_MAC) = '1') or (v_reg_rd(OP1_MACS) = '1') ) then
v_op1_mux := v_op1_rd;
end if;
v_op2_mux := word_per_select_dout( OP2, v_reg_rd, v_op2_rd );
v_reslo_mux := word_per_select_dout( RESLO, v_reg_rd, v_reslo_rd );
v_reshi_mux := word_per_select_dout( RESHI, v_reg_rd, v_reshi_rd );
v_sumext_mux := word_per_select_dout( SUMEXT, v_reg_rd, v_sumext_rd );
v_per_dout := v_op1_mux or
v_op2_mux or
v_reslo_mux or
v_reshi_mux or
v_sumext_mux;
--============================================================================
--! 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
--============================================================================
--! Multiplier configuration
----------------------------
--! Detect signed mode
if (v_op1_wr = '1') then
v.sign_sel := v_reg_wr(OP1_MPYS) or v_reg_wr(OP1_MACS);
end if;
--! Detect accumulate mode
if (v_op1_wr = '1') then
v.acc_sel := v_reg_wr(OP1_MAC) or v_reg_wr(OP1_MACS);
end if;
--! Detect whenever the RESHI and RESLO registers should be cleared
v_result_clr := v_op2_wr and not(r.acc_sel);
--! Combine RESHI & RESLO
v_result := r.reshi & r.reslo;
--! 16x16 Multiplier (result computed in 1 clock cycle)
-------------------------------------------------------
--! Detect start of a multiplication
v.cycle := v_op2_wr;
v_result_wr := r.cycle;
--! Expand the operands to support signed & unsigned operations
v_op1_xp := (r.sign_sel and r.op1(15)) & r.op1;
v_op2_xp := (r.sign_sel and r.op2(15)) & r.op2;
--! 17x17 signed multiplication
v_product := SIGNED(v_op1_xp) * SIGNED(v_op2_xp);
--! Accumulate
v_result_nxt := SIGNED('0' & v_result) + SIGNED('0' & v_product(31 downto 0));
--! Next register values
v_reslo_nxt := STD_LOGIC_VECTOR(v_result_nxt(15 downto 0));
v_reshi_nxt := STD_LOGIC_VECTOR(v_result_nxt(31 downto 16));
if (r.sign_sel = '1') then
v_sumext_s_nxt := v_result_nxt(31) & v_result_nxt(31);
else
v_sumext_s_nxt := '0' & v_result_nxt(31);
end if;
--! Since the MAC is completed within 1 clock cycle,
--! an early read can't happen.
-- v_early_read := '0';
--! drive register inputs
rin <= v;
--! drive module outputs
per_dout <= v_per_dout; --! Peripheral data output
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( op1 => x"0000",
op2 => x"0000",
reslo => x"0000",
reshi => x"0000",
sumext_s => "00",
sign_sel => '0', --! Detect signed mode
acc_sel => '0', --! Detect accumulate mode
cycle => '0', --! Detect start of a multiplication
nmie => '0',
wdtie => '0',
nmiifg => '0',
wdtifg => '0',
wdt_reset => '0'
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
end RTL; | bsd-3-clause | 048698bdf37377ca2b9eed9aac027b3e | 0.572002 | 2.814562 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/netcard/netcard.vhd | 1 | 10,799 | -----------------------------------------------------------------------------
-- Ethernet/PCI bridge Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use work.config.all;
entity netcard is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
emdio : inout std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_irq : out std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture rtl of netcard is
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, pciclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal dui : uart_in_type;
signal duo : uart_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal irqn, lclk, gnd : std_logic;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahb : integer := CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0,
0, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_clk, clkm, open, open, open, pciclk, cgi, cgo);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (nahbm => maxahb, nahbs => 4, ioen => 0)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e0 : greth generic map(hindex => log2x(CFG_PCI),
pindex => 0, paddr => 11, pirq => 11, memtech => memtech)
port map( rst => rstn, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo(log2x(CFG_PCI)),
apbi => apbi, apbo => apbo(0), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
irqn <= ahbso(3).hirq(11);
irq_pad : odpad generic map (tech => padtech, level => pci33)
port map (pci_irq, irqn);
----------------------------------------------------------------------
--- AHB/APB Bridge -------------------------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 0, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo );
----------------------------------------------------------------------
--- AHB RAM --------------------------------------------------------
----------------------------------------------------------------------
ram0 : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 2, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(2));
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => 0,
device_id => 16#0210#, vendor_id => 16#16E3#)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(0));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => 0,
fifodepth => 6, device_id => 16#0210#, vendor_id => 16#16E3#,
hslvndx => 1, pindex => 6, paddr => 2, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(6),
ahbmi, ahbmo(0), ahbsi, ahbso(1));
end generate;
pci_dma : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => 1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => 0,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(1),
apbi, apbo(4), ahbmi, ahbmo(0), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (memtech => memtech, pindex => 3,
paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(3));
end generate;
pcipads0 : pcipads generic map (padtech)
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
----------------------------------------------------------------------
--- Optional DSU UARTs ----------------------------------------------
----------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => log2x(CFG_PCI)+CFG_GRETH, pindex => 1, paddr => 1)
port map (rstn, clkm, dui, duo, apbi, apbo(1), ahbmi, ahbmo(log2x(CFG_PCI)+CFG_GRETH));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech,
hindex => log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi,
ahbmo(log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART), open, open, open,
open, open, open, open, gnd);
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "Ethernet/PCI Network Card Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 7f891a0bb993a961145f8f2d3fb77382 | 0.530142 | 3.783812 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/ahbstat.vhd | 1 | 4,316 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
| gpl-2.0 | cdeb3463b7550abdc3e33c1e06e54065 | 0.598703 | 3.523265 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd | 1 | 18,876 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package avnet_eval is
constant APPDATA_WIDTH : integer := 32; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 36; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#FE0#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_en : std_logic;
mig_rst : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.avnet_eval.all;
entity ahb2mig_avnet_eval is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
rst_50 : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clk_50 : in std_ulogic;
init_done : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_avnet_eval is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold1, rhold2, rhold3, rhold4, rhold5, rhold6, rhold7, dread,
whold1, whold2, whold3, whold4, whold5, whold6, whold7);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ddr_state_type;
addr : std_logic_vector(2 downto 0);
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
signal rdel : std_logic_vector(25 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(127 downto 0);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- delayed reset for the MIG, will not work otherwise ...
rstp : process(clk_50)
begin
if rising_edge(clk_50) then
if rdel(25) = '0' then rdel <= rdel + 1; end if;
if rst_50 = '0' then
rdel <= (others => '0');
-- pragma translate_off
rdel <= (25 => '0', 2 => '0', others => '1');
-- pragma translate_on
end if;
end if;
end process;
ddr_ctrl : process(rst_ddr, r, ra, migo, init_done, rdel)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
variable app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "100"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask := ra.write(0);
app_wdf_data := (others => '0');
app_wdf_data(31 downto 0) := ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_addr := '0' & app_cmd & "00000" & ra.acc.haddr(27 downto 5) & r.addr(0) & "000";
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
v.addr := "00" & ra.acc.haddr(4); app_addr(3) := ra.acc.haddr(4);
if (startsd = '1') and (migo.app_af_afull = '0') and (init_done = '1') then
if ra.acc.hwrite = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := dread; v.addr := r.addr + 1;
else v.dstate := rhold4; end if;
app_en := '1';
elsif migo.app_wdf_afull = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := whold1; v.addr := r.addr + 1;
else
v.dstate := whold5;
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
end if;
app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if r.addr(0) = '1' then
v.addr := r.addr + 1; app_en := '1';
end if;
if migo.app_rd_data_valid = '1' then
v.hrdata(31 downto 0) := migo.app_rd_data(31 downto 0);
v.dstate := rhold1;
end if;
when rhold1 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(63 downto 32) := migo.app_rd_data(31 downto 0);
v.dstate := rhold2;
end if;
when rhold2 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(95 downto 64) := migo.app_rd_data(31 downto 0);
v.dstate := rhold3;
end if;
when rhold3 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 96) := migo.app_rd_data(31 downto 0);
v.dstate := rhold4;
end if;
when rhold4 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(159 downto 128) := migo.app_rd_data(31 downto 0);
v.dstate := rhold5;
end if;
when rhold5 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(191 downto 160) := migo.app_rd_data(31 downto 0);
v.dstate := rhold6;
end if;
when rhold6 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(223 downto 192) := migo.app_rd_data(31 downto 0);
v.dstate := rhold7;
end if;
when rhold7 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 224) := migo.app_rd_data(31 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
end if;
when whold1 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(1);
app_wdf_data(31 downto 0) := ra.hwdata(1);
v.dstate := whold2;
when whold2 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(2);
app_wdf_data(31 downto 0) := ra.hwdata(2);
v.dstate := whold3;
when whold3 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(3);
app_wdf_data(31 downto 0) := ra.hwdata(3);
if (ra.write(4) = "0000") and (ra.write(5) = "0000") and (ra.write(6) = "0000") and
(ra.write(7) = "0000")
then v.startsd := not r.startsd; v.dstate := midle;
elsif migo.app_wdf_afull = '0' then v.dstate := whold4; app_en := '1'; end if;
when whold4 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
v.dstate := whold5;
when whold5 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(5);
app_wdf_data(31 downto 0) := ra.hwdata(5);
v.dstate := whold6;
when whold6 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(6);
app_wdf_data(31 downto 0) := ra.hwdata(6);
v.dstate := whold7;
when whold7 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(7);
app_wdf_data(31 downto 0) := ra.hwdata(7);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
v.addr := "000";
end if;
ri <= v;
migi.app_addr <= app_addr;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
migi.mig_rst <= rdel(25);
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 32-bit DDR controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | 20a0755ead0fa5ac829f9e27804f682e | 0.572844 | 3.178848 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-c5ekit/testbench.vhd | 1 | 19,705 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic;
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : out std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic;
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic;
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end component;
signal clk125, clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal eneta_rx_clk, eneta_tx_clk, enetb_rx_clk, enetb_tx_clk: std_ulogic;
signal eneta_intn, eneta_resetn, enetb_intn, enetb_resetn: std_ulogic;
signal eneta_mdio, enetb_mdio: std_logic;
signal eneta_mdc, enetb_mdc: std_ulogic;
signal eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_rx_dv: std_ulogic;
signal enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_rx_dv: std_ulogic;
signal eneta_rx_d, enetb_rx_d: std_logic_vector(7 downto 0);
signal eneta_tx_d, enetb_tx_d: std_logic_vector(7 downto 0);
signal eneta_tx_en, eneta_tx_er, enetb_tx_en, enetb_tx_er: std_ulogic;
signal lpddr2_ck, lpddr2_ck_n, lpddr2_cke, lpddr2_cs_n: std_ulogic;
signal lpddr2_ca: std_logic_vector(9 downto 0);
signal lpddr2_dm, lpddr2_dqs, lpddr2_dqs_n: std_logic_vector(3 downto 0);
signal lpddr2_dq: std_logic_vector(31 downto 0);
begin
-- clock and reset
clk125 <= not clk125 after 4 ns;
clk50 <= not clk50 after 10 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
-- Clock and reset
diff_clkin_top_125_p => clk125,
diff_clkin_bot_125_p => clk125,
clkin_50_fpga_right => clk50,
clkin_50_fpga_top => clk50,
clkout_sma => clkout,
cpu_resetn => rst,
-- DDR3
ddr3_ck_p => open,
ddr3_ck_n => open,
ddr3_cke => open,
ddr3_rstn => open,
ddr3_csn => open,
ddr3_rasn => open,
ddr3_casn => open,
ddr3_wen => open,
ddr3_ba => open,
ddr3_a => open,
ddr3_dqs_p => open,
ddr3_dqs_n => open,
ddr3_dq => open,
ddr3_dm => open,
ddr3_odt => open,
ddr3_oct_rzq => '0',
-- LPDDR2
lpddr2_ck_p => lpddr2_ck,
lpddr2_ck_n => lpddr2_ck_n,
lpddr2_cke => lpddr2_cke,
lpddr2_a => lpddr2_ca,
lpddr2_dqs_p => lpddr2_dqs(1 downto 0),
lpddr2_dqs_n => lpddr2_dqs_n(1 downto 0),
lpddr2_dq => lpddr2_dq(15 downto 0),
lpddr2_dm => lpddr2_dm(1 downto 0),
lpddr2_csn => lpddr2_cs_n,
lpddr2_oct_rzq => '0',
-- Flash and SSRAM interface
fm_a => address(26 downto 1),
fm_d => data,
flash_clk => open,
flash_resetn => open,
flash_cen => romsn,
flash_advn => open,
flash_wen => rwen,
flash_oen => oen,
flash_rdybsyn => '1',
ssram_clk => open,
ssram_oen => open,
sram_cen => open,
ssram_bwen => open,
ssram_bwan => open,
ssram_bwbn => open,
ssram_adscn => open,
ssram_adspn => open,
ssram_zzn => open,
ssram_advn => open,
-- EEPROM
eeprom_scl => open,
eeprom_sda => open,
-- UART
uart_rxd => rxd1,
uart_rts => '1',
uart_txd => txd1,
uart_cts => open,
-- USB UART Interface
usb_uart_rstn => '1',
usb_uart_ri => '0',
usb_uart_dcd => '1',
usb_uart_dtr => open,
usb_uart_dsr => '1',
usb_uart_txd => open,
usb_uart_rxd => '1',
usb_uart_rts => '1',
usb_uart_cts => open,
usb_uart_gpio2 => '0',
usb_uart_suspend => '0',
usb_uart_suspendn => '1',
-- Ethernet port A
eneta_rx_clk => eneta_rx_clk,
eneta_tx_clk => eneta_tx_clk,
eneta_intn => eneta_intn,
eneta_resetn => eneta_resetn,
eneta_mdio => eneta_mdio,
eneta_mdc => eneta_mdc,
eneta_rx_er => eneta_rx_er,
eneta_tx_er => eneta_tx_er,
eneta_rx_col => eneta_rx_col,
eneta_rx_crs => eneta_rx_crs,
eneta_tx_d => eneta_tx_d(3 downto 0),
eneta_rx_d => eneta_rx_d(3 downto 0),
eneta_gtx_clk => open,
eneta_tx_en => eneta_tx_en,
eneta_rx_dv => eneta_rx_dv,
-- Ethernet port B
enetb_rx_clk => enetb_rx_clk,
enetb_tx_clk => enetb_tx_clk,
enetb_intn => enetb_intn,
enetb_resetn => enetb_resetn,
enetb_mdio => enetb_mdio,
enetb_mdc => enetb_mdc,
enetb_rx_er => enetb_rx_er,
enetb_tx_er => enetb_tx_er,
enetb_rx_col => enetb_rx_col,
enetb_rx_crs => enetb_rx_crs,
enetb_tx_d => enetb_tx_d(3 downto 0),
enetb_rx_d => enetb_rx_d(3 downto 0),
enetb_gtx_clk => open,
enetb_tx_en => enetb_tx_en,
enetb_rx_dv => enetb_rx_dv,
-- LEDs, switches, GPIO
user_led => user_led,
user_dipsw => "1111",
dip_3p3V => '0',
user_pb => "0000",
overtemp_fpga => open,
header_p => "000000",
header_n => "000000",
header_d => "00000000",
-- LCD
lcd_data => "00000000",
lcd_wen => open,
lcd_csn => open,
lcd_d_cn => open,
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0 => '0',
-- hsmc_clk_out0 => open,
-- hsmc_clk_in_p => "00",
-- hsmc_clk_out_p => open,
-- hsmc_d => "0000",
-- hsmc_tx_d_p => open,
-- hsmc_rx_d_p => (others => '0'),
-- hsmc_rx_led => open,
-- hsmc_tx_led => open,
-- hsmc_scl => open,
-- hsmc_sda => '0',
-- hsmc_prsntn => '0',
-- MAX V CPLD interface
max5_csn => open,
max5_wen => open,
max5_oen => open,
max5_ben => open,
max5_clk => open,
-- USB Blaster II
usb_clk => '0',
usb_data => (others => '0'),
usb_addr => "00",
usb_scl => '0',
usb_sda => '0',
usb_resetn => '0',
usb_oen => '0',
usb_rdn => '0',
usb_wrn => '0',
usb_full => open,
usb_empty => open,
fx2_resetn => '1'
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
-- ROMSN is pulled down by the MAX V system controller after FPGA programming
-- completed (bug?)
romsn <= 'L';
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
eneta_mdio <= 'H';
enetb_mdio <= 'H';
eneta_tx_d(7 downto 4) <= "0000";
enetb_tx_d(7 downto 4) <= "0000";
p1: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 0)
port map(rst, eneta_mdio, eneta_tx_clk, eneta_rx_clk, eneta_rx_d, eneta_rx_dv,
eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_tx_d, eneta_tx_en, eneta_tx_er, eneta_mdc,
'0');
p2: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(rst, enetb_mdio, enetb_tx_clk, enetb_rx_clk, enetb_rx_d, enetb_rx_dv,
enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_tx_d, enetb_tx_en, enetb_tx_er, enetb_mdc,
'0');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 3181003d312fe23adefeaad6f16d5b4c | 0.572291 | 3.014841 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pkg.vhd | 1 | 29,021 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: pt_pkg
-- File: pt_pkg.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Test Framework - Main package
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
--use grlib.amba.all;
--use grlib.testlib.all;
use grlib.stdlib.all;
package pt_pkg is
-----------------------------------------------------------------------------
-- Constants and PCI signal
-----------------------------------------------------------------------------
-- Constants for PCI commands
constant INT_ACK : std_logic_vector(3 downto 0) := "0000";
constant SPEC_CYCLE : std_logic_vector(3 downto 0) := "0001";
constant IO_READ : std_logic_vector(3 downto 0) := "0010";
constant IO_WRITE : std_logic_vector(3 downto 0) := "0011";
constant MEM_READ : std_logic_vector(3 downto 0) := "0110";
constant MEM_WRITE : std_logic_vector(3 downto 0) := "0111";
constant CONF_READ : std_logic_vector(3 downto 0) := "1010";
constant CONF_WRITE : std_logic_vector(3 downto 0) := "1011";
constant MEM_R_MULT : std_logic_vector(3 downto 0) := "1100";
constant DAC : std_logic_vector(3 downto 0) := "1101";
constant MEM_R_LINE : std_logic_vector(3 downto 0) := "1110";
constant MEM_W_INV : std_logic_vector(3 downto 0) := "1111";
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
--type pci_int_type is record
-- inta : std_logic;
-- intb : std_logic;
-- intc : std_logic;
-- intd : std_logic;
--end record;
--constant int_const : pci_int_type := (
-- inta => 'H',
-- intb => 'H',
-- intc => 'H',
-- intd => 'H');
constant int_const : std_logic_vector(3 downto 0) := "HHHH";
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
--int : pci_int_type;
int : std_logic_vector(3 downto 0);
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-----------------------------------------------------------------------------
-- Types for PCI master
-----------------------------------------------------------------------------
type pt_pci_access_type is record
addr : std_logic_vector(31 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
data : std_logic_vector(31 downto 0);
cbe_data : std_logic_vector(3 downto 0);
ws : integer;
status : integer range 0 to 3;
id : integer;
debug : integer range 0 to 3;
last : boolean;
idle : boolean;
list_res : boolean;
valid : boolean;
parerr : integer range 0 to 2;
cod : integer range 0 to 2; -- Cancel on disconnect
end record;
type pt_pci_master_in_type is record
req : std_logic;
add : boolean;
remove : boolean;
rmall : boolean;
get_res : boolean;
add_res : boolean;
acc : pt_pci_access_type;
end record;
type pt_pci_master_out_type is record
ack : std_logic;
res_found : std_logic;
acc : pt_pci_access_type;
valid : boolean;
end record;
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
-----------------------------------------------------------------------------
-- Types for PCI target
-----------------------------------------------------------------------------
type pt_pci_response_type is record
addr : std_logic_vector(31 downto 0);
retry : integer;
ws : integer;
diswithout : integer;
diswith : integer;
abort : integer;
parerr : integer;
debug : integer;
valid : boolean;
end record;
type pt_pci_target_in_type is record
req : std_logic;
insert: std_logic;
remove: std_logic;
rmall : std_logic;
addr : std_logic_vector(31 downto 0);
resp : pt_pci_response_type;
end record;
type pt_pci_target_out_type is record
ack : std_logic;
resp : pt_pci_response_type;
valid : std_logic;
end record;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component pt_pci_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end component;
component pt_pci_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end component;
component pt_pci_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
--component pt_pci_monitor is
-- generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
-- port (pciin : in pci_type);
--end component;
end package pt_pkg;
package body pt_pkg is
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_master_sync_with_core;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= cod;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, cod, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= waits;
dbgi.acc.idle <= true;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
-- Add acc
pt_add_idle_nb(waits, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_target_sync_with_core;
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '1';
dbgi.remove <= '0';
dbgi.resp.addr <= addr;
dbgi.resp.retry <= retry;
dbgi.resp.ws <= waits;
dbgi.resp.parerr <= parerr;
dbgi.resp.abort <= abort;
dbgi.resp.debug <= debug;
if discon = 1 then
dbgi.resp.diswith <= 1;
elsif discon = 2 then
dbgi.resp.diswithout <= 1;
else
dbgi.resp.diswith <= 0;
dbgi.resp.diswithout <= 0;
end if;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.insert <= '0';
end procedure;
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '0';
dbgi.remove <= '1';
if rmall = true then dbgi.rmall <= '1';
else dbgi.rmall <= '0'; end if;
dbgi.addr <= addr;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.remove <= '0';
dbgi.rmall <= '0';
end procedure;
end pt_pkg;
| gpl-2.0 | 6928ab22b3d7bf999b557d2975212160 | 0.54688 | 3.556059 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c9b99754fd79eeaa/ip_design_xbar_0_sim_netlist.vhdl | 1 | 218,878 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:55:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_sim_netlist.vhdl
-- Design : ip_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd is
port (
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_ready_d0_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_2\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_3\ : in STD_LOGIC;
\m_atarget_hot_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
\gen_axilite.s_axi_rvalid_i_reg_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_atarget_enc_reg[2]_3\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_4\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_grant_any : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_1\ : STD_LOGIC;
signal \^gen_axilite.s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_enc[0]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_enc[0]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_enc[0]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_enc[0]_i_5_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_5_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_6_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_7_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_8_n_0\ : STD_LOGIC;
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_5\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_7\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_8\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_bready[5]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair17";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
SR(0) <= \^sr\(0);
aa_grant_rnw <= \^aa_grant_rnw\;
\gen_axilite.s_axi_bvalid_i_reg\ <= \^gen_axilite.s_axi_bvalid_i_reg\;
\gen_axilite.s_axi_bvalid_i_reg_0\ <= \^gen_axilite.s_axi_bvalid_i_reg_0\;
\gen_axilite.s_axi_bvalid_i_reg_1\ <= \^gen_axilite.s_axi_bvalid_i_reg_1\;
\gen_axilite.s_axi_rvalid_i_reg\ <= \^gen_axilite.s_axi_rvalid_i_reg\;
m_ready_d0(0) <= \^m_ready_d0\(0);
m_valid_i <= \^m_valid_i\;
\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5C505050F0F0F0F0"
)
port map (
I0 => \^gen_axilite.s_axi_bvalid_i_reg\,
I1 => mi_wready(0),
I2 => mi_bvalid(0),
I3 => \^gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \^gen_axilite.s_axi_bvalid_i_reg_1\,
I5 => \m_atarget_hot_reg[6]\(6),
O => \gen_axilite.s_axi_bvalid_i_reg_2\
);
\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => m_ready_d(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_bvalid_i_reg_1\
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d_1(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_rvalid_i_reg\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF5300000050"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aa_grant_any,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^q\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^q\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^q\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^q\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^q\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^q\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^q\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^q\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^q\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^q\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^q\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^q\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^q\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^q\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^q\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^q\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^q\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^q\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^q\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^q\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^q\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^q\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^q\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^q\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^q\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^q\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^q\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^q\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^q\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^q\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^q\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^q\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AAA800000000"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => aresetn_d,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00EFFFFFFFEFFFFF"
)
port map (
I0 => \m_ready_d_reg[0]_1\,
I1 => \m_ready_d_reg[1]\,
I2 => \^m_ready_d0\(0),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => \m_ready_d[0]_i_4_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30020002"
)
port map (
I0 => m_axi_wready(0),
I1 => \m_atarget_enc_reg[2]_5\(2),
I2 => \m_atarget_enc_reg[2]_5\(1),
I3 => \m_atarget_enc_reg[2]_5\(0),
I4 => m_axi_wready(1),
O => \gen_no_arbiter.m_valid_i_reg_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => aa_grant_any,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCC8C8C0C8"
)
port map (
I0 => \m_atarget_enc[0]_i_2_n_0\,
I1 => aresetn_d,
I2 => \m_atarget_hot[6]_i_6_n_0\,
I3 => \m_atarget_hot[6]_i_5_n_0\,
I4 => \m_atarget_enc[0]_i_3_n_0\,
I5 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(0)
);
\m_atarget_enc[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \^q\(16),
I1 => \m_atarget_hot[4]_i_2_n_0\,
I2 => \^q\(17),
I3 => \^q\(19),
I4 => \^q\(18),
O => \m_atarget_enc[0]_i_2_n_0\
);
\m_atarget_enc[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"000001FF"
)
port map (
I0 => \m_atarget_enc[0]_i_4_n_0\,
I1 => \^q\(16),
I2 => \m_atarget_hot[2]_i_2_n_0\,
I3 => \m_atarget_hot[4]_i_2_n_0\,
I4 => \m_atarget_enc[0]_i_5_n_0\,
O => \m_atarget_enc[0]_i_3_n_0\
);
\m_atarget_enc[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(14),
I1 => \^q\(15),
I2 => \^q\(13),
I3 => \^q\(12),
O => \m_atarget_enc[0]_i_4_n_0\
);
\m_atarget_enc[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^q\(17),
I1 => \^q\(19),
I2 => \^q\(18),
O => \m_atarget_enc[0]_i_5_n_0\
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_4_n_0\,
I2 => \m_atarget_hot[6]_i_3_n_0\,
I3 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(1)
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA0020AAAA"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_6_n_0\,
I2 => \m_atarget_hot[6]_i_5_n_0\,
I3 => \m_atarget_hot[6]_i_4_n_0\,
I4 => \m_atarget_hot[6]_i_3_n_0\,
I5 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(2)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_4_n_0\,
I1 => aa_grant_any,
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => aa_grant_any,
O => D(1)
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => aa_grant_any,
I1 => \^q\(16),
I2 => \^q\(17),
I3 => \^q\(18),
I4 => \^q\(19),
I5 => \m_atarget_hot[2]_i_2_n_0\,
O => D(2)
);
\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBFFFFFF"
)
port map (
I0 => \m_atarget_hot[4]_i_3_n_0\,
I1 => \^q\(23),
I2 => \^q\(21),
I3 => \^q\(25),
I4 => \^q\(22),
I5 => \m_atarget_hot[4]_i_4_n_0\,
O => \m_atarget_hot[2]_i_2_n_0\
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_6_n_0\,
I1 => aa_grant_any,
O => D(3)
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \m_atarget_hot[4]_i_2_n_0\,
I1 => aa_grant_any,
I2 => \^q\(16),
I3 => \^q\(18),
I4 => \^q\(19),
I5 => \^q\(17),
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \m_atarget_hot[4]_i_3_n_0\,
I1 => \^q\(22),
I2 => \^q\(23),
I3 => \^q\(21),
I4 => \^q\(25),
I5 => \m_atarget_hot[4]_i_4_n_0\,
O => \m_atarget_hot[4]_i_2_n_0\
);
\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \^q\(31),
I1 => \^q\(28),
I2 => \^q\(26),
I3 => \^q\(29),
I4 => \^q\(27),
I5 => \^q\(30),
O => \m_atarget_hot[4]_i_3_n_0\
);
\m_atarget_hot[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(20),
I1 => \^q\(24),
O => \m_atarget_hot[4]_i_4_n_0\
);
\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \m_atarget_hot[6]_i_3_n_0\,
I1 => \^q\(16),
I2 => aa_grant_any,
O => D(5)
);
\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[6]_i_3_n_0\,
I2 => \m_atarget_hot[6]_i_4_n_0\,
I3 => \m_atarget_hot[6]_i_5_n_0\,
I4 => \m_atarget_hot[6]_i_6_n_0\,
I5 => aa_grant_any,
O => D(6)
);
\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \^q\(16),
I2 => \^q\(17),
I3 => \^q\(19),
I4 => \^q\(18),
I5 => \^q\(15),
O => \m_atarget_hot[6]_i_2_n_0\
);
\m_atarget_hot[6]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
I2 => \^q\(17),
I3 => \m_atarget_hot[4]_i_2_n_0\,
O => \m_atarget_hot[6]_i_3_n_0\
);
\m_atarget_hot[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \m_atarget_hot[6]_i_7_n_0\,
I2 => \^q\(14),
I3 => \^q\(15),
I4 => \^q\(13),
I5 => \^q\(12),
O => \m_atarget_hot[6]_i_4_n_0\
);
\m_atarget_hot[6]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEFF"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \^q\(19),
I2 => \^q\(18),
I3 => \^q\(17),
I4 => \^q\(16),
O => \m_atarget_hot[6]_i_5_n_0\
);
\m_atarget_hot[6]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \^q\(16),
I2 => \^q\(15),
I3 => \^q\(14),
I4 => \m_atarget_hot[6]_i_8_n_0\,
O => \m_atarget_hot[6]_i_6_n_0\
);
\m_atarget_hot[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(16),
I1 => \^q\(18),
I2 => \^q\(19),
I3 => \^q\(17),
O => \m_atarget_hot[6]_i_7_n_0\
);
\m_atarget_hot[6]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^q\(19),
I1 => \^q\(18),
I2 => \^q\(17),
O => \m_atarget_hot[6]_i_8_n_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(3)
);
\m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(4)
);
\m_axi_arvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[6]\(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(5)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(3)
);
\m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(4)
);
\m_axi_awvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[6]\(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(5)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(0),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(1),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(2),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(3),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(4),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(4)
);
\m_axi_bready[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(5),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(5)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(0),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(1),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(2),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(3),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(3)
);
\m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(4),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(4)
);
\m_axi_wvalid[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[6]\(5),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(5)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(0),
I4 => sr_rvalid,
O => E(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(0),
O => \^gen_axilite.s_axi_bvalid_i_reg\
);
\m_ready_d[0]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \m_ready_d_reg[0]_0\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFA8AA"
)
port map (
I0 => \^gen_axilite.s_axi_rvalid_i_reg\,
I1 => \m_atarget_enc_reg[2]_3\,
I2 => \m_atarget_enc_reg[2]_4\,
I3 => \m_atarget_enc_reg[0]\,
I4 => m_ready_d_1(1),
I5 => m_valid_i_reg_0,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(1),
O => \^gen_axilite.s_axi_bvalid_i_reg_0\
);
\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFDFF00FF00FF00"
)
port map (
I0 => \m_atarget_enc_reg[0]\,
I1 => \m_atarget_enc_reg[2]_4\,
I2 => \m_atarget_enc_reg[2]_3\,
I3 => m_ready_d_1(1),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => m_ready_d0_0(0)
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FFFDFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \m_atarget_enc_reg[1]\,
I2 => \m_atarget_enc_reg[1]_0\,
I3 => m_ready_d(2),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \^m_ready_d0\(0)
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(1),
I1 => m_valid_i_i_2_n_0,
I2 => m_valid_i_i_3_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => sr_rvalid,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_rready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAA8AAA8AAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => \m_atarget_enc_reg[2]_2\,
I5 => \gen_axilite.s_axi_rvalid_i_reg_0\,
O => m_valid_i_i_3_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \gen_axilite.s_axi_bvalid_i_reg_3\,
O => s_axi_bvalid(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_grant_any,
I1 => sr_rvalid,
O => s_axi_rvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \m_atarget_enc_reg[2]_0\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(0),
I1 => m_valid_i_i_3_n_0,
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_3\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\m_ready_d_reg[2]_0\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F07F0000"
)
port map (
I0 => Q(0),
I1 => \m_ready_d_reg[1]_2\,
I2 => mi_arready(6),
I3 => mi_rvalid(6),
I4 => aresetn_d,
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
Q => mi_arready(6),
R => '0'
);
\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => \m_ready_d_reg[2]_0\,
I3 => Q(0),
I4 => \^mi_wready\(0),
O => \gen_axilite.s_axi_awready_i_i_1_n_0\
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_i_1_n_0\,
Q => \^mi_wready\(0),
R => SR(0)
);
\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_reg_0\,
Q => \^mi_bvalid\(0),
R => SR(0)
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF8800"
)
port map (
I0 => mi_arready(6),
I1 => \m_ready_d_reg[1]_2\,
I2 => aa_rready,
I3 => Q(0),
I4 => mi_rvalid(6),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
Q => mi_rvalid(6),
R => SR(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FFFF53FFFFFF53"
)
port map (
I0 => m_axi_arready(1),
I1 => m_axi_arready(0),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => mi_arready(6),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF035FFFFFF35FFF"
)
port map (
I0 => m_axi_awready(1),
I1 => m_axi_awready(0),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => \^mi_wready\(0),
O => \m_ready_d_reg[2]\
);
m_valid_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"F5FF03FFF5FFF3FF"
)
port map (
I0 => mi_rvalid(6),
I1 => m_axi_rvalid(0),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rvalid(1),
O => m_valid_i_reg
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2022000020222022"
)
port map (
I0 => \^m_ready_d_reg[0]_0\,
I1 => \m_atarget_enc_reg[2]_2\,
I2 => \m_atarget_enc_reg[2]_3\,
I3 => m_axi_bvalid(1),
I4 => \m_atarget_enc_reg[1]_0\,
I5 => m_axi_bvalid(0),
O => \m_ready_d_reg[0]\
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F530FFFFF53FFFFF"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => m_axi_bvalid(3),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_bvalid(2),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A008A8A"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[1]\,
I2 => m_axi_wready(0),
I3 => \m_atarget_enc_reg[2]_1\,
I4 => m_axi_wready(2),
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d_reg[1]\
);
\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B000800"
)
port map (
I0 => \^mi_wready\(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter is
port (
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[1]_2\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\m_ready_d_reg[0]_3\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\gen_axilite.s_axi_awready_i_reg\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
aresetn_d : in STD_LOGIC;
\gen_axilite.s_axi_bvalid_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_3_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_8_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_2\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_ready_d[2]_i_5\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_6\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_8\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_4\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_5\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_4\ : label is "soft_lutpair26";
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[0]_1\ <= \^m_ready_d_reg[0]_1\;
\m_ready_d_reg[0]_2\ <= \^m_ready_d_reg[0]_2\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \^m_ready_d_reg[1]_0\,
I2 => \m_atarget_enc_reg[2]_0\,
I3 => \gen_axilite.s_axi_awready_i_reg\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \gen_axilite.s_axi_bvalid_i_reg_0\,
I2 => \gen_no_arbiter.grant_rnw_reg_0\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_atarget_enc_reg[2]\,
I2 => \gen_no_arbiter.grant_rnw_reg\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_ready_d0(0),
I1 => \m_ready_d[2]_i_3_n_0\,
I2 => aresetn_d,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABBFFFF"
)
port map (
I0 => \^m_ready_d_reg[0]_1\,
I1 => \^m_ready_d\(1),
I2 => \m_atarget_enc_reg[2]\,
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => m_ready_d0(0),
O => \m_ready_d[2]_i_3_n_0\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_awready(2),
I1 => Q(1),
I2 => Q(2),
I3 => Q(0),
I4 => m_axi_awready(0),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_awready(3),
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => m_axi_awready(1),
O => \m_ready_d_reg[2]_1\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \gen_axilite.s_axi_bvalid_i_reg\,
I2 => \^m_ready_d_reg[0]_2\,
I3 => \m_ready_d[2]_i_8_n_0\,
I4 => \gen_no_arbiter.grant_rnw_reg_0\,
O => \^m_ready_d_reg[0]_1\
);
\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00380008"
)
port map (
I0 => m_axi_bvalid(2),
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => m_axi_bvalid(1),
O => \m_ready_d[2]_i_8_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"30020002"
)
port map (
I0 => m_axi_bvalid(0),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_bvalid(3),
O => \^m_ready_d_reg[0]_2\
);
\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => Q(2),
I1 => Q(0),
I2 => Q(1),
O => \m_ready_d_reg[0]_0\
);
\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => Q(2),
O => \m_ready_d_reg[0]_3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF530FFFFF53FF"
)
port map (
I0 => m_axi_wready(2),
I1 => m_axi_wready(0),
I2 => Q(2),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
O => \m_ready_d_reg[1]_2\
);
\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => \m_ready_d_reg[1]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
sr_rvalid : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_15_splitter";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0080"
)
port map (
I0 => sr_rvalid,
I1 => \m_payload_i_reg[0]\(0),
I2 => s_axi_rready(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^m_ready_d\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => m_valid_i_reg,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"2C002000"
)
port map (
I0 => m_axi_arready(1),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_arready(3),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"03080008"
)
port map (
I0 => m_axi_arready(2),
I1 => Q(2),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_arready(0),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
m_valid_i_reg_0 : out STD_LOGIC;
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_hot_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[10]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_3_n_0\ : STD_LOGIC;
signal m_valid_i_i_6_n_0 : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair24";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_rready <= \^aa_rready\;
m_valid_i_reg_1(1 downto 0) <= \^m_valid_i_reg_1\(1 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_1\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_1\(0),
Q => \^m_valid_i_reg_1\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(3),
O => m_axi_rready(3)
);
\m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(4),
O => m_axi_rready(4)
);
\m_axi_rready[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(5),
O => m_axi_rready(5)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(7),
I1 => m_axi_rdata(135),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(167),
O => \m_payload_i[10]_i_2_n_0\
);
\m_payload_i[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(71),
I1 => m_axi_rdata(39),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(103),
O => \m_payload_i[10]_i_3_n_0\
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(8),
I1 => m_axi_rdata(168),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(136),
O => \m_payload_i[11]_i_2_n_0\
);
\m_payload_i[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_axi_rdata(40),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(104),
O => \m_payload_i[11]_i_3_n_0\
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(9),
I1 => m_axi_rdata(137),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(169),
O => \m_payload_i[12]_i_2_n_0\
);
\m_payload_i[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_axi_rdata(41),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(105),
O => \m_payload_i[12]_i_3_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CA000F00CA0000"
)
port map (
I0 => m_axi_rdata(138),
I1 => m_axi_rdata(170),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(10),
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_axi_rdata(106),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(42),
O => \m_payload_i[13]_i_3_n_0\
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(11),
I1 => m_axi_rdata(139),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(171),
O => \m_payload_i[14]_i_2_n_0\
);
\m_payload_i[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(75),
I1 => m_axi_rdata(43),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(107),
O => \m_payload_i[14]_i_3_n_0\
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_axi_rdata(140),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(172),
O => \m_payload_i[15]_i_2_n_0\
);
\m_payload_i[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(76),
I1 => m_axi_rdata(44),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(108),
O => \m_payload_i[15]_i_3_n_0\
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(13),
I1 => m_axi_rdata(173),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(141),
O => \m_payload_i[16]_i_2_n_0\
);
\m_payload_i[16]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(109),
I1 => m_axi_rdata(45),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(77),
O => \m_payload_i[16]_i_3_n_0\
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(14),
I1 => m_axi_rdata(142),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(174),
O => \m_payload_i[17]_i_2_n_0\
);
\m_payload_i[17]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(78),
I1 => m_axi_rdata(46),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(110),
O => \m_payload_i[17]_i_3_n_0\
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(15),
I1 => m_axi_rdata(175),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(143),
O => \m_payload_i[18]_i_2_n_0\
);
\m_payload_i[18]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(79),
I1 => m_axi_rdata(47),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(111),
O => \m_payload_i[18]_i_3_n_0\
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(16),
I1 => m_axi_rdata(176),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(144),
O => \m_payload_i[19]_i_2_n_0\
);
\m_payload_i[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_axi_rdata(112),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(48),
O => \m_payload_i[19]_i_3_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[1]_i_2_n_0\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30080008"
)
port map (
I0 => m_axi_rresp(8),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => m_axi_rresp(6),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00320002"
)
port map (
I0 => m_axi_rresp(0),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(2),
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00AAA2AAA0AAA2A"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(4),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(10),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(113),
I1 => m_axi_rdata(49),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(81),
O => \m_payload_i[20]_i_2_n_0\
);
\m_payload_i[20]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(17),
I1 => m_axi_rdata(145),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(177),
O => \m_payload_i[20]_i_3_n_0\
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(18),
I1 => m_axi_rdata(146),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(178),
O => \m_payload_i[21]_i_2_n_0\
);
\m_payload_i[21]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(82),
I1 => m_axi_rdata(114),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(50),
O => \m_payload_i[21]_i_3_n_0\
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(19),
I1 => m_axi_rdata(147),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(179),
O => \m_payload_i[22]_i_2_n_0\
);
\m_payload_i[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(83),
I1 => m_axi_rdata(51),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(115),
O => \m_payload_i[22]_i_3_n_0\
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(20),
I1 => m_axi_rdata(180),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(148),
O => \m_payload_i[23]_i_2_n_0\
);
\m_payload_i[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(84),
I1 => m_axi_rdata(52),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(116),
O => \m_payload_i[23]_i_3_n_0\
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(21),
I1 => m_axi_rdata(181),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(149),
O => \m_payload_i[24]_i_2_n_0\
);
\m_payload_i[24]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_axi_rdata(53),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(117),
O => \m_payload_i[24]_i_3_n_0\
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(22),
I1 => m_axi_rdata(150),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(182),
O => \m_payload_i[25]_i_2_n_0\
);
\m_payload_i[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(86),
I1 => m_axi_rdata(54),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(118),
O => \m_payload_i[25]_i_3_n_0\
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_axi_rdata(183),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(151),
O => \m_payload_i[26]_i_2_n_0\
);
\m_payload_i[26]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(87),
I1 => m_axi_rdata(55),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(119),
O => \m_payload_i[26]_i_3_n_0\
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(24),
I1 => m_axi_rdata(152),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(184),
O => \m_payload_i[27]_i_2_n_0\
);
\m_payload_i[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(88),
I1 => m_axi_rdata(56),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(120),
O => \m_payload_i[27]_i_3_n_0\
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(121),
I1 => m_axi_rdata(57),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(89),
O => \m_payload_i[28]_i_2_n_0\
);
\m_payload_i[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_axi_rdata(153),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(185),
O => \m_payload_i[28]_i_3_n_0\
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(26),
I1 => m_axi_rdata(154),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(186),
O => \m_payload_i[29]_i_2_n_0\
);
\m_payload_i[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(90),
I1 => m_axi_rdata(122),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(58),
O => \m_payload_i[29]_i_3_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
I4 => \m_payload_i[2]_i_4_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_rresp(9),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(3),
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rresp(1),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rresp(5),
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00A2AAAA0AA2AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(7),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(11),
O => \m_payload_i[2]_i_4_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(27),
I1 => m_axi_rdata(155),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(187),
O => \m_payload_i[30]_i_2_n_0\
);
\m_payload_i[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_axi_rdata(59),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(123),
O => \m_payload_i[30]_i_3_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_axi_rdata(156),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(188),
O => \m_payload_i[31]_i_2_n_0\
);
\m_payload_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(92),
I1 => m_axi_rdata(60),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(124),
O => \m_payload_i[31]_i_3_n_0\
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[32]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(125),
I1 => m_axi_rdata(61),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(93),
O => \m_payload_i[32]_i_2_n_0\
);
\m_payload_i[32]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A000C0F0A000C00"
)
port map (
I0 => m_axi_rdata(189),
I1 => m_axi_rdata(157),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(0),
I5 => m_axi_rdata(29),
O => \m_payload_i[32]_i_3_n_0\
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(30),
I1 => m_axi_rdata(190),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(158),
O => \m_payload_i[33]_i_2_n_0\
);
\m_payload_i[33]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(94),
I1 => m_axi_rdata(62),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(126),
O => \m_payload_i[33]_i_3_n_0\
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(31),
I1 => m_axi_rdata(159),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(191),
O => \m_payload_i[34]_i_3_n_0\
);
\m_payload_i[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_axi_rdata(63),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(127),
O => \m_payload_i[34]_i_4_n_0\
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(0),
I1 => m_axi_rdata(128),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(160),
O => \m_payload_i[3]_i_2_n_0\
);
\m_payload_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_axi_rdata(32),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(96),
O => \m_payload_i[3]_i_3_n_0\
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(1),
I1 => m_axi_rdata(129),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(161),
O => \m_payload_i[4]_i_2_n_0\
);
\m_payload_i[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(65),
I1 => m_axi_rdata(97),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(33),
O => \m_payload_i[4]_i_3_n_0\
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(2),
I1 => m_axi_rdata(130),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(162),
O => \m_payload_i[5]_i_2_n_0\
);
\m_payload_i[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(66),
I1 => m_axi_rdata(34),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(98),
O => \m_payload_i[5]_i_3_n_0\
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_axi_rdata(131),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(163),
O => \m_payload_i[6]_i_2_n_0\
);
\m_payload_i[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_axi_rdata(35),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(99),
O => \m_payload_i[6]_i_3_n_0\
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(4),
I1 => m_axi_rdata(164),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(132),
O => \m_payload_i[7]_i_2_n_0\
);
\m_payload_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(68),
I1 => m_axi_rdata(36),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(100),
O => \m_payload_i[7]_i_3_n_0\
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(5),
I1 => m_axi_rdata(133),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(165),
O => \m_payload_i[8]_i_2_n_0\
);
\m_payload_i[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_axi_rdata(37),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(101),
O => \m_payload_i[8]_i_3_n_0\
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(6),
I1 => m_axi_rdata(166),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(134),
O => \m_payload_i[9]_i_2_n_0\
);
\m_payload_i[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(70),
I1 => m_axi_rdata(38),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(102),
O => \m_payload_i[9]_i_3_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => \^sr_rvalid\,
I1 => \^q\(0),
I2 => s_axi_rready(0),
I3 => aa_grant_rnw,
I4 => m_valid_i,
I5 => m_ready_d(0),
O => \m_ready_d_reg[1]\
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF30200020"
)
port map (
I0 => m_axi_rvalid(1),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rvalid(3),
I5 => m_valid_i_i_6_n_0,
O => m_valid_i_reg_0
);
m_valid_i_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rvalid(2),
O => m_valid_i_i_6_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7FFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]\(2),
I1 => \m_atarget_enc_reg[2]\(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \skid_buffer_reg_n_0_[0]\,
I4 => \^aa_rready\,
O => skid_buffer(0)
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd is
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_10 : STD_LOGIC;
signal addr_arbiter_inst_n_3 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_5 : STD_LOGIC;
signal addr_arbiter_inst_n_54 : STD_LOGIC;
signal addr_arbiter_inst_n_62 : STD_LOGIC;
signal addr_arbiter_inst_n_69 : STD_LOGIC;
signal addr_arbiter_inst_n_7 : STD_LOGIC;
signal addr_arbiter_inst_n_70 : STD_LOGIC;
signal addr_arbiter_inst_n_71 : STD_LOGIC;
signal addr_arbiter_inst_n_73 : STD_LOGIC;
signal addr_arbiter_inst_n_81 : STD_LOGIC;
signal addr_arbiter_inst_n_82 : STD_LOGIC;
signal addr_arbiter_inst_n_86 : STD_LOGIC;
signal addr_arbiter_inst_n_87 : STD_LOGIC;
signal addr_arbiter_inst_n_88 : STD_LOGIC;
signal addr_arbiter_inst_n_89 : STD_LOGIC;
signal addr_arbiter_inst_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_atarget_hot : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 4 downto 2 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 2 to 2 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_bvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal mi_wready : STD_LOGIC_VECTOR ( 6 to 6 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_37 : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
signal splitter_ar_n_1 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_1 : STD_LOGIC;
signal splitter_aw_n_10 : STD_LOGIC;
signal splitter_aw_n_11 : STD_LOGIC;
signal splitter_aw_n_12 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal splitter_aw_n_7 : STD_LOGIC;
signal splitter_aw_n_8 : STD_LOGIC;
signal splitter_aw_n_9 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
begin
addr_arbiter_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd
port map (
D(6) => addr_arbiter_inst_n_4,
D(5) => addr_arbiter_inst_n_5,
D(4) => m_atarget_hot0(4),
D(3) => addr_arbiter_inst_n_7,
D(2) => m_atarget_hot0(2),
D(1) => addr_arbiter_inst_n_9,
D(0) => addr_arbiter_inst_n_10,
E(0) => p_1_in,
Q(34 downto 0) => Q(34 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\aresetn_d_reg[1]\(1) => reg_slice_r_n_45,
\aresetn_d_reg[1]\(0) => reg_slice_r_n_46,
\gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_54,
\gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_62,
\gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_69,
\gen_axilite.s_axi_bvalid_i_reg_2\ => addr_arbiter_inst_n_89,
\gen_axilite.s_axi_bvalid_i_reg_3\ => \gen_decerr.decerr_slave_inst_n_5\,
\gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_73,
\gen_axilite.s_axi_rvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_2\,
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_82,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[1]\ => splitter_aw_n_8,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_11,
\m_atarget_enc_reg[2]\(2) => addr_arbiter_inst_n_86,
\m_atarget_enc_reg[2]\(1) => addr_arbiter_inst_n_87,
\m_atarget_enc_reg[2]\(0) => addr_arbiter_inst_n_88,
\m_atarget_enc_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_atarget_enc_reg[2]_2\ => reg_slice_r_n_38,
\m_atarget_enc_reg[2]_3\ => splitter_ar_n_1,
\m_atarget_enc_reg[2]_4\ => splitter_ar_n_0,
\m_atarget_enc_reg[2]_5\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_hot_reg[6]\(6 downto 0) => m_atarget_hot(6 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_wready(1) => m_axi_wready(3),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
m_ready_d0_0(0) => m_ready_d0(1),
m_ready_d_1(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_3,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_81,
\m_ready_d_reg[0]_1\ => splitter_aw_n_1,
\m_ready_d_reg[1]\ => splitter_aw_n_6,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_71,
m_valid_i_reg_0 => reg_slice_r_n_2,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_70,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave
port map (
Q(0) => m_atarget_hot(6),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_89,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_62,
\m_atarget_enc_reg[1]\ => splitter_aw_n_10,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_12,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[2]_0\ => splitter_aw_n_7,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_9,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_5,
\m_atarget_enc_reg[2]_3\ => splitter_aw_n_0,
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_awready(1) => m_axi_awready(5),
m_axi_awready(0) => m_axi_awready(2),
m_axi_bvalid(3 downto 2) => m_axi_bvalid(5 downto 4),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(2 downto 1),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(5 downto 4),
m_axi_wready(2 downto 1) => m_axi_wready(3 downto 2),
m_axi_wready(0) => m_axi_wready(0),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_4\,
\m_ready_d_reg[1]_1\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_ready_d_reg[1]_2\ => addr_arbiter_inst_n_73,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_69,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_2\,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6)
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_88,
Q => m_atarget_enc(0),
R => '0'
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_87,
Q => m_atarget_enc(1),
R => '0'
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_86,
Q => m_atarget_enc(2),
R => '0'
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_10,
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_9,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(2),
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_7,
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(4),
Q => m_atarget_hot(4),
R => reset
);
\m_atarget_hot_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_5,
Q => m_atarget_hot(5),
R => reset
);
\m_atarget_hot_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_4,
Q => m_atarget_hot(6),
R => reset
);
reg_slice_r: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
port map (
E(0) => p_1_in,
Q(34 downto 1) => \s_axi_rdata[31]\(33 downto 0),
Q(0) => reg_slice_r_n_37,
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_70,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_71,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_hot_reg[5]\(5 downto 0) => m_atarget_hot(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_38,
m_valid_i_reg_1(1) => reg_slice_r_n_45,
m_valid_i_reg_1(0) => reg_slice_r_n_46,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[0]_INST_0_i_2_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(0),
I1 => m_axi_bresp(8),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(10),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(4),
I1 => m_axi_bresp(2),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(6),
O => \s_axi_bresp[0]_INST_0_i_2_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[1]_INST_0_i_2_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(1),
I1 => m_axi_bresp(9),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(11),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(5),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(7),
O => \s_axi_bresp[1]_INST_0_i_2_n_0\
);
splitter_ar: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0\
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_3,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_81,
m_axi_arready(3 downto 0) => m_axi_arready(5 downto 2),
\m_payload_i_reg[0]\(0) => reg_slice_r_n_37,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0(1),
\m_ready_d_reg[1]_0\ => splitter_ar_n_0,
\m_ready_d_reg[1]_1\ => splitter_ar_n_1,
m_valid_i_reg => reg_slice_r_n_2,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg\ => \gen_decerr.decerr_slave_inst_n_4\,
\gen_axilite.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_6\,
\gen_axilite.s_axi_bvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_5\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_62,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_54,
\gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_6,
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_0\ => addr_arbiter_inst_n_82,
m_axi_awready(3 downto 2) => m_axi_awready(4 downto 3),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_wready(2 downto 1) => m_axi_wready(5 downto 4),
m_axi_wready(0) => m_axi_wready(1),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
\m_ready_d_reg[0]_0\ => splitter_aw_n_0,
\m_ready_d_reg[0]_1\ => splitter_aw_n_1,
\m_ready_d_reg[0]_2\ => splitter_aw_n_5,
\m_ready_d_reg[0]_3\ => splitter_aw_n_12,
\m_ready_d_reg[1]_0\ => splitter_aw_n_7,
\m_ready_d_reg[1]_1\ => splitter_aw_n_9,
\m_ready_d_reg[1]_2\ => splitter_aw_n_10,
\m_ready_d_reg[2]_0\ => splitter_aw_n_8,
\m_ready_d_reg[2]_1\ => splitter_aw_n_11
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 191 downto 172 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_arburst(11) <= \<const0>\;
m_axi_arburst(10) <= \<const0>\;
m_axi_arburst(9) <= \<const0>\;
m_axi_arburst(8) <= \<const0>\;
m_axi_arburst(7) <= \<const0>\;
m_axi_arburst(6) <= \<const0>\;
m_axi_arburst(5) <= \<const0>\;
m_axi_arburst(4) <= \<const0>\;
m_axi_arburst(3) <= \<const0>\;
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(23) <= \<const0>\;
m_axi_arcache(22) <= \<const0>\;
m_axi_arcache(21) <= \<const0>\;
m_axi_arcache(20) <= \<const0>\;
m_axi_arcache(19) <= \<const0>\;
m_axi_arcache(18) <= \<const0>\;
m_axi_arcache(17) <= \<const0>\;
m_axi_arcache(16) <= \<const0>\;
m_axi_arcache(15) <= \<const0>\;
m_axi_arcache(14) <= \<const0>\;
m_axi_arcache(13) <= \<const0>\;
m_axi_arcache(12) <= \<const0>\;
m_axi_arcache(11) <= \<const0>\;
m_axi_arcache(10) <= \<const0>\;
m_axi_arcache(9) <= \<const0>\;
m_axi_arcache(8) <= \<const0>\;
m_axi_arcache(7) <= \<const0>\;
m_axi_arcache(6) <= \<const0>\;
m_axi_arcache(5) <= \<const0>\;
m_axi_arcache(4) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(47) <= \<const0>\;
m_axi_arlen(46) <= \<const0>\;
m_axi_arlen(45) <= \<const0>\;
m_axi_arlen(44) <= \<const0>\;
m_axi_arlen(43) <= \<const0>\;
m_axi_arlen(42) <= \<const0>\;
m_axi_arlen(41) <= \<const0>\;
m_axi_arlen(40) <= \<const0>\;
m_axi_arlen(39) <= \<const0>\;
m_axi_arlen(38) <= \<const0>\;
m_axi_arlen(37) <= \<const0>\;
m_axi_arlen(36) <= \<const0>\;
m_axi_arlen(35) <= \<const0>\;
m_axi_arlen(34) <= \<const0>\;
m_axi_arlen(33) <= \<const0>\;
m_axi_arlen(32) <= \<const0>\;
m_axi_arlen(31) <= \<const0>\;
m_axi_arlen(30) <= \<const0>\;
m_axi_arlen(29) <= \<const0>\;
m_axi_arlen(28) <= \<const0>\;
m_axi_arlen(27) <= \<const0>\;
m_axi_arlen(26) <= \<const0>\;
m_axi_arlen(25) <= \<const0>\;
m_axi_arlen(24) <= \<const0>\;
m_axi_arlen(23) <= \<const0>\;
m_axi_arlen(22) <= \<const0>\;
m_axi_arlen(21) <= \<const0>\;
m_axi_arlen(20) <= \<const0>\;
m_axi_arlen(19) <= \<const0>\;
m_axi_arlen(18) <= \<const0>\;
m_axi_arlen(17) <= \<const0>\;
m_axi_arlen(16) <= \<const0>\;
m_axi_arlen(15) <= \<const0>\;
m_axi_arlen(14) <= \<const0>\;
m_axi_arlen(13) <= \<const0>\;
m_axi_arlen(12) <= \<const0>\;
m_axi_arlen(11) <= \<const0>\;
m_axi_arlen(10) <= \<const0>\;
m_axi_arlen(9) <= \<const0>\;
m_axi_arlen(8) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(5) <= \<const0>\;
m_axi_arlock(4) <= \<const0>\;
m_axi_arlock(3) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(23) <= \<const0>\;
m_axi_arqos(22) <= \<const0>\;
m_axi_arqos(21) <= \<const0>\;
m_axi_arqos(20) <= \<const0>\;
m_axi_arqos(19) <= \<const0>\;
m_axi_arqos(18) <= \<const0>\;
m_axi_arqos(17) <= \<const0>\;
m_axi_arqos(16) <= \<const0>\;
m_axi_arqos(15) <= \<const0>\;
m_axi_arqos(14) <= \<const0>\;
m_axi_arqos(13) <= \<const0>\;
m_axi_arqos(12) <= \<const0>\;
m_axi_arqos(11) <= \<const0>\;
m_axi_arqos(10) <= \<const0>\;
m_axi_arqos(9) <= \<const0>\;
m_axi_arqos(8) <= \<const0>\;
m_axi_arqos(7) <= \<const0>\;
m_axi_arqos(6) <= \<const0>\;
m_axi_arqos(5) <= \<const0>\;
m_axi_arqos(4) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(23) <= \<const0>\;
m_axi_arregion(22) <= \<const0>\;
m_axi_arregion(21) <= \<const0>\;
m_axi_arregion(20) <= \<const0>\;
m_axi_arregion(19) <= \<const0>\;
m_axi_arregion(18) <= \<const0>\;
m_axi_arregion(17) <= \<const0>\;
m_axi_arregion(16) <= \<const0>\;
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(17) <= \<const0>\;
m_axi_arsize(16) <= \<const0>\;
m_axi_arsize(15) <= \<const0>\;
m_axi_arsize(14) <= \<const0>\;
m_axi_arsize(13) <= \<const0>\;
m_axi_arsize(12) <= \<const0>\;
m_axi_arsize(11) <= \<const0>\;
m_axi_arsize(10) <= \<const0>\;
m_axi_arsize(9) <= \<const0>\;
m_axi_arsize(8) <= \<const0>\;
m_axi_arsize(7) <= \<const0>\;
m_axi_arsize(6) <= \<const0>\;
m_axi_arsize(5) <= \<const0>\;
m_axi_arsize(4) <= \<const0>\;
m_axi_arsize(3) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(5) <= \<const0>\;
m_axi_aruser(4) <= \<const0>\;
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_awburst(11) <= \<const0>\;
m_axi_awburst(10) <= \<const0>\;
m_axi_awburst(9) <= \<const0>\;
m_axi_awburst(8) <= \<const0>\;
m_axi_awburst(7) <= \<const0>\;
m_axi_awburst(6) <= \<const0>\;
m_axi_awburst(5) <= \<const0>\;
m_axi_awburst(4) <= \<const0>\;
m_axi_awburst(3) <= \<const0>\;
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(23) <= \<const0>\;
m_axi_awcache(22) <= \<const0>\;
m_axi_awcache(21) <= \<const0>\;
m_axi_awcache(20) <= \<const0>\;
m_axi_awcache(19) <= \<const0>\;
m_axi_awcache(18) <= \<const0>\;
m_axi_awcache(17) <= \<const0>\;
m_axi_awcache(16) <= \<const0>\;
m_axi_awcache(15) <= \<const0>\;
m_axi_awcache(14) <= \<const0>\;
m_axi_awcache(13) <= \<const0>\;
m_axi_awcache(12) <= \<const0>\;
m_axi_awcache(11) <= \<const0>\;
m_axi_awcache(10) <= \<const0>\;
m_axi_awcache(9) <= \<const0>\;
m_axi_awcache(8) <= \<const0>\;
m_axi_awcache(7) <= \<const0>\;
m_axi_awcache(6) <= \<const0>\;
m_axi_awcache(5) <= \<const0>\;
m_axi_awcache(4) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(47) <= \<const0>\;
m_axi_awlen(46) <= \<const0>\;
m_axi_awlen(45) <= \<const0>\;
m_axi_awlen(44) <= \<const0>\;
m_axi_awlen(43) <= \<const0>\;
m_axi_awlen(42) <= \<const0>\;
m_axi_awlen(41) <= \<const0>\;
m_axi_awlen(40) <= \<const0>\;
m_axi_awlen(39) <= \<const0>\;
m_axi_awlen(38) <= \<const0>\;
m_axi_awlen(37) <= \<const0>\;
m_axi_awlen(36) <= \<const0>\;
m_axi_awlen(35) <= \<const0>\;
m_axi_awlen(34) <= \<const0>\;
m_axi_awlen(33) <= \<const0>\;
m_axi_awlen(32) <= \<const0>\;
m_axi_awlen(31) <= \<const0>\;
m_axi_awlen(30) <= \<const0>\;
m_axi_awlen(29) <= \<const0>\;
m_axi_awlen(28) <= \<const0>\;
m_axi_awlen(27) <= \<const0>\;
m_axi_awlen(26) <= \<const0>\;
m_axi_awlen(25) <= \<const0>\;
m_axi_awlen(24) <= \<const0>\;
m_axi_awlen(23) <= \<const0>\;
m_axi_awlen(22) <= \<const0>\;
m_axi_awlen(21) <= \<const0>\;
m_axi_awlen(20) <= \<const0>\;
m_axi_awlen(19) <= \<const0>\;
m_axi_awlen(18) <= \<const0>\;
m_axi_awlen(17) <= \<const0>\;
m_axi_awlen(16) <= \<const0>\;
m_axi_awlen(15) <= \<const0>\;
m_axi_awlen(14) <= \<const0>\;
m_axi_awlen(13) <= \<const0>\;
m_axi_awlen(12) <= \<const0>\;
m_axi_awlen(11) <= \<const0>\;
m_axi_awlen(10) <= \<const0>\;
m_axi_awlen(9) <= \<const0>\;
m_axi_awlen(8) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(5) <= \<const0>\;
m_axi_awlock(4) <= \<const0>\;
m_axi_awlock(3) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(23) <= \<const0>\;
m_axi_awqos(22) <= \<const0>\;
m_axi_awqos(21) <= \<const0>\;
m_axi_awqos(20) <= \<const0>\;
m_axi_awqos(19) <= \<const0>\;
m_axi_awqos(18) <= \<const0>\;
m_axi_awqos(17) <= \<const0>\;
m_axi_awqos(16) <= \<const0>\;
m_axi_awqos(15) <= \<const0>\;
m_axi_awqos(14) <= \<const0>\;
m_axi_awqos(13) <= \<const0>\;
m_axi_awqos(12) <= \<const0>\;
m_axi_awqos(11) <= \<const0>\;
m_axi_awqos(10) <= \<const0>\;
m_axi_awqos(9) <= \<const0>\;
m_axi_awqos(8) <= \<const0>\;
m_axi_awqos(7) <= \<const0>\;
m_axi_awqos(6) <= \<const0>\;
m_axi_awqos(5) <= \<const0>\;
m_axi_awqos(4) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(23) <= \<const0>\;
m_axi_awregion(22) <= \<const0>\;
m_axi_awregion(21) <= \<const0>\;
m_axi_awregion(20) <= \<const0>\;
m_axi_awregion(19) <= \<const0>\;
m_axi_awregion(18) <= \<const0>\;
m_axi_awregion(17) <= \<const0>\;
m_axi_awregion(16) <= \<const0>\;
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(17) <= \<const0>\;
m_axi_awsize(16) <= \<const0>\;
m_axi_awsize(15) <= \<const0>\;
m_axi_awsize(14) <= \<const0>\;
m_axi_awsize(13) <= \<const0>\;
m_axi_awsize(12) <= \<const0>\;
m_axi_awsize(11) <= \<const0>\;
m_axi_awsize(10) <= \<const0>\;
m_axi_awsize(9) <= \<const0>\;
m_axi_awsize(8) <= \<const0>\;
m_axi_awsize(7) <= \<const0>\;
m_axi_awsize(6) <= \<const0>\;
m_axi_awsize(5) <= \<const0>\;
m_axi_awsize(4) <= \<const0>\;
m_axi_awsize(3) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(5) <= \<const0>\;
m_axi_awuser(4) <= \<const0>\;
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(191 downto 160) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(159 downto 128) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(5) <= \<const0>\;
m_axi_wlast(4) <= \<const0>\;
m_axi_wlast(3) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
m_axi_wstrb(23 downto 20) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(19 downto 16) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(5) <= \<const0>\;
m_axi_wuser(4) <= \<const0>\;
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
Q(31 downto 12) => \^m_axi_awaddr\(191 downto 172),
Q(11 downto 0) => \^m_axi_araddr\(11 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(33 downto 2) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000010000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5]";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20]";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(191 downto 0) => m_axi_araddr(191 downto 0),
m_axi_arburst(11 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(11 downto 0),
m_axi_arcache(23 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(23 downto 0),
m_axi_arid(5 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(5 downto 0),
m_axi_arlen(47 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(47 downto 0),
m_axi_arlock(5 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(5 downto 0),
m_axi_arprot(17 downto 0) => m_axi_arprot(17 downto 0),
m_axi_arqos(23 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(23 downto 0),
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arregion(23 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(23 downto 0),
m_axi_arsize(17 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(17 downto 0),
m_axi_aruser(5 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awaddr(191 downto 0) => m_axi_awaddr(191 downto 0),
m_axi_awburst(11 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(11 downto 0),
m_axi_awcache(23 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(23 downto 0),
m_axi_awid(5 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(5 downto 0),
m_axi_awlen(47 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(47 downto 0),
m_axi_awlock(5 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(5 downto 0),
m_axi_awprot(17 downto 0) => m_axi_awprot(17 downto 0),
m_axi_awqos(23 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(23 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awregion(23 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(23 downto 0),
m_axi_awsize(17 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(17 downto 0),
m_axi_awuser(5 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bid(5 downto 0) => B"000000",
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_buser(5 downto 0) => B"000000",
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rid(5 downto 0) => B"000000",
m_axi_rlast(5 downto 0) => B"111111",
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_ruser(5 downto 0) => B"000000",
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wdata(191 downto 0) => m_axi_wdata(191 downto 0),
m_axi_wid(5 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(5 downto 0),
m_axi_wlast(5 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wstrb(23 downto 0) => m_axi_wstrb(23 downto 0),
m_axi_wuser(5 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast(0) => '1',
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 7759e63aa26134581c100b9dab0517c2 | 0.557269 | 2.633277 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_processing_system7_0_1/zqynq_lab_1_design_processing_system7_0_1_sim_netlist.vhdl | 1 | 197,463 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:29:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_processing_system7_0_1 -prefix
-- zqynq_lab_1_design_processing_system7_0_1_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 : entity is 0;
end zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_processing_system7_0_1 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_processing_system7_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_processing_system7_0_1 : entity is "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_processing_system7_0_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_processing_system7_0_1 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end zqynq_lab_1_design_processing_system7_0_1;
architecture STRUCTURE of zqynq_lab_1_design_processing_system7_0_1 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.zqynq_lab_1_design_processing_system7_0_1_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 5b9dd9301929cd4e0c22f6ecffa7ea8e | 0.634499 | 2.750947 | false | false | false | false |
dsaves/dsaves-hdl | primitives/lut6.vhd | 1 | 2,095 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
entity LUT6 is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(63 downto 0);
wen : in std_logic;
s : in std_logic_vector(5 downto 0);
o : out std_logic
);
end entity;
architecture POS_EDGE of LUT6 is
begin
LUT6 : entity dsaves.LUT(POS_EDGE)
generic map(
N => 6
)
port map(
clk => clk,
rst => rst,
d => d,
wen => wen,
s => s,
o => o
);
end architecture;
architecture NEG_EDGE of LUT6 is
begin
LUT6 : entity dsaves.LUT(NEG_EDGE)
generic map(
N => 6
)
port map(
clk => clk,
rst => rst,
d => d,
wen => wen,
s => s,
o => o
);
end architecture;
| mit | f369785fe0c3923ab74151a902842dd6 | 0.600955 | 4.036609 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/syn/vhdl/convolve_kernel_fbkb.vhd | 5 | 3,080 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 5acda59b24db628199c2ac78aa80596b | 0.480844 | 3.671037 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/TestBench/var7/var7_TB.vhd | 1 | 2,023 | library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity var7_tb is
end var7_tb;
architecture TB_ARCHITECTURE of var7_tb is
-- Component declaration of the tested unit
component var7
port(
W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : in STD_LOGIC;
G : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal W : STD_LOGIC;
signal X : STD_LOGIC;
signal Y : STD_LOGIC;
signal Z : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal G, G1 : STD_LOGIC;
signal error : std_logic;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : var7
port map (
W => W,
X => X,
Y => Y,
Z => Z,
G => G
);
UUT2 : var7
port map (
W => W,
X => X,
Y => Y,
Z => Z,
G => G1
);
STIMULUS: process
begin -- of stimulus process
--wait for <time to next event>; -- <current time>
W <= '0';
Y <= '0';
Z <= '0';
X <= '0';
wait for 50 ns; --0 fs
X <= '1';
wait for 50 ns; --50 ns
Y <= '1';
X <= '0';
wait for 50 ns; --100 ns
X <= '1';
wait for 50 ns; --150 ns
Y <= '0';
Z <= '1';
X <= '0';
wait for 50 ns; --200 ns
X <= '1';
wait for 50 ns; --250 ns
Y <= '1';
X <= '0';
wait for 50 ns; --300 ns
X <= '1';
wait for 50 ns; --350 ns
W <= '1';
Y <= '0';
Z <= '0';
X <= '0';
wait for 50 ns; --400 ns
X <= '1';
wait for 50 ns; --450 ns
Y <= '1';
X <= '0';
wait for 50 ns; --500 ns
X <= '1';
wait for 50 ns; --550 ns
Y <= '0';
Z <= '1';
X <= '0';
wait for 50 ns; --600 ns
X <= '1';
wait for 50 ns; --650 ns
Y <= '1';
X <= '0';
wait for 50 ns; --700 ns
X <= '1';
wait for 50 ns; --750 ns
W <= '0';
Y <= '0';
Z <= '0';
X <= '0';
-- end of stimulus events 800 ns
wait;
end process; -- end of stimulus process
error <= G1 xor G;
-- Add your stimulus here ...
end TB_ARCHITECTURE;
| mit | 0c81a2621fc546f757ed0db8dd867758 | 0.522491 | 2.541457 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/misc/fmsp_sync_reset.vhd | 1 | 3,005 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_sync_reset.vhd
--!
--! @brief fpgaMSP430 Generic reset synchronizer
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_sync_reset is
port (
--! INPUTs
clk : in std_logic; --! Receiving clock
rst_a : in std_logic; --! Asynchronous reset
--! OUTPUTs
rst_s : out std_logic --! Synchronized resett
);
end entity fmsp_sync_reset;
architecture RTL of fmsp_sync_reset is
signal data_sync : std_logic_vector(1 downto 0);
begin
--=============================================================================
--! 1) SYNCHRONIZER
--=============================================================================
DATA_SYNC_REG : process(clk,rst_a)
begin
if (rst_a = '1') then
data_sync <= "11";
elsif rising_edge(clk) then
data_sync <= data_sync(0) & '0';
end if;
end process DATA_SYNC_REG;
rst_s <= data_sync(1);
end RTL; --! fmsp_sync_reset
| bsd-3-clause | 2d57132bd1cd65e5f98707886bfb080e | 0.6 | 4.380466 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution5/syn/vhdl/matrix_mult_mac_mcud.vhd | 3 | 3,020 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult_mac_mcud_DSP48_0 is
port (
clk: in std_logic;
rst: in std_logic;
ce: in std_logic;
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(8 - 1 downto 0);
in2: in std_logic_vector(16 - 1 downto 0);
dout: out std_logic_vector(16 - 1 downto 0));
attribute use_dsp48 : string;
attribute use_dsp48 of matrix_mult_mac_mcud_DSP48_0 : entity is "yes";
end entity;
architecture behav of matrix_mult_mac_mcud_DSP48_0 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
signal m_reg : signed(43-1 downto 0);
signal a_reg : signed(25-1 downto 0);
signal b_reg : signed(18-1 downto 0);
begin
a <= signed(resize(signed(in0), 25));
b <= signed(resize(signed(in1), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a_reg * b_reg;
p <= m_reg + c;
process (clk) begin
if (clk'event and clk = '1') then
if (ce = '1') then
m_reg <= m;
a_reg <= a;
b_reg <= b;
end if;
end if;
end process;
dout <= std_logic_vector(resize(unsigned(p), 16));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity matrix_mult_mac_mcud is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of matrix_mult_mac_mcud is
component matrix_mult_mac_mcud_DSP48_0 is
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ce : IN STD_LOGIC;
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
matrix_mult_mac_mcud_DSP48_0_U : component matrix_mult_mac_mcud_DSP48_0
port map (
clk => clk,
rst => reset,
ce => ce,
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
| mit | 9c446ff19c64b5f3b9575460b254b9f5 | 0.527152 | 3.28976 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/clkinv.vhd | 1 | 1,889 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-2.0 | 5163720d9547e58ece0d08f77dab7dac | 0.601376 | 4.097614 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_4/syn/vhdl/convolve_kernel.vhd | 1 | 355,520 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (15 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (127 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (127 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (15 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (127 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (127 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_EN_A : OUT STD_LOGIC;
bufo_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Clk_A : OUT STD_LOGIC;
bufo_0_Rst_A : OUT STD_LOGIC;
bufo_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_EN_A : OUT STD_LOGIC;
bufo_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Clk_A : OUT STD_LOGIC;
bufo_1_Rst_A : OUT STD_LOGIC;
bufo_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_EN_A : OUT STD_LOGIC;
bufo_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Clk_A : OUT STD_LOGIC;
bufo_2_Rst_A : OUT STD_LOGIC;
bufo_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_3_EN_A : OUT STD_LOGIC;
bufo_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_3_Clk_A : OUT STD_LOGIC;
bufo_3_Rst_A : OUT STD_LOGIC;
bufo_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_4_EN_A : OUT STD_LOGIC;
bufo_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_4_Clk_A : OUT STD_LOGIC;
bufo_4_Rst_A : OUT STD_LOGIC;
bufo_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_5_EN_A : OUT STD_LOGIC;
bufo_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_5_Clk_A : OUT STD_LOGIC;
bufo_5_Rst_A : OUT STD_LOGIC;
bufo_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_6_EN_A : OUT STD_LOGIC;
bufo_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_6_Clk_A : OUT STD_LOGIC;
bufo_6_Rst_A : OUT STD_LOGIC;
bufo_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_7_EN_A : OUT STD_LOGIC;
bufo_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_7_Clk_A : OUT STD_LOGIC;
bufo_7_Rst_A : OUT STD_LOGIC;
bufo_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_8_EN_A : OUT STD_LOGIC;
bufo_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_8_Clk_A : OUT STD_LOGIC;
bufo_8_Rst_A : OUT STD_LOGIC;
bufo_9_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_9_EN_A : OUT STD_LOGIC;
bufo_9_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_9_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_9_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_9_Clk_A : OUT STD_LOGIC;
bufo_9_Rst_A : OUT STD_LOGIC;
bufo_10_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_10_EN_A : OUT STD_LOGIC;
bufo_10_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_10_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_10_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_10_Clk_A : OUT STD_LOGIC;
bufo_10_Rst_A : OUT STD_LOGIC;
bufo_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_11_EN_A : OUT STD_LOGIC;
bufo_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_11_Clk_A : OUT STD_LOGIC;
bufo_11_Rst_A : OUT STD_LOGIC;
bufo_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_12_EN_A : OUT STD_LOGIC;
bufo_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_12_Clk_A : OUT STD_LOGIC;
bufo_12_Rst_A : OUT STD_LOGIC;
bufo_13_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_13_EN_A : OUT STD_LOGIC;
bufo_13_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_13_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_13_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_13_Clk_A : OUT STD_LOGIC;
bufo_13_Rst_A : OUT STD_LOGIC;
bufo_14_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_14_EN_A : OUT STD_LOGIC;
bufo_14_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_14_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_14_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_14_Clk_A : OUT STD_LOGIC;
bufo_14_Rst_A : OUT STD_LOGIC;
bufo_15_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_15_EN_A : OUT STD_LOGIC;
bufo_15_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_15_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_15_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_15_Clk_A : OUT STD_LOGIC;
bufo_15_Rst_A : OUT STD_LOGIC;
bufo_16_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_16_EN_A : OUT STD_LOGIC;
bufo_16_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_16_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_16_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_16_Clk_A : OUT STD_LOGIC;
bufo_16_Rst_A : OUT STD_LOGIC;
bufo_17_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_17_EN_A : OUT STD_LOGIC;
bufo_17_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_17_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_17_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_17_Clk_A : OUT STD_LOGIC;
bufo_17_Rst_A : OUT STD_LOGIC;
bufo_18_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_18_EN_A : OUT STD_LOGIC;
bufo_18_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_18_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_18_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_18_Clk_A : OUT STD_LOGIC;
bufo_18_Rst_A : OUT STD_LOGIC;
bufo_19_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_19_EN_A : OUT STD_LOGIC;
bufo_19_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_19_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_19_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_19_Clk_A : OUT STD_LOGIC;
bufo_19_Rst_A : OUT STD_LOGIC;
bufo_20_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_20_EN_A : OUT STD_LOGIC;
bufo_20_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_20_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_20_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_20_Clk_A : OUT STD_LOGIC;
bufo_20_Rst_A : OUT STD_LOGIC;
bufo_21_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_21_EN_A : OUT STD_LOGIC;
bufo_21_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_21_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_21_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_21_Clk_A : OUT STD_LOGIC;
bufo_21_Rst_A : OUT STD_LOGIC;
bufo_22_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_22_EN_A : OUT STD_LOGIC;
bufo_22_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_22_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_22_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_22_Clk_A : OUT STD_LOGIC;
bufo_22_Rst_A : OUT STD_LOGIC;
bufo_23_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_23_EN_A : OUT STD_LOGIC;
bufo_23_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_23_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_23_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_23_Clk_A : OUT STD_LOGIC;
bufo_23_Rst_A : OUT STD_LOGIC;
bufo_24_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_24_EN_A : OUT STD_LOGIC;
bufo_24_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_24_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_24_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_24_Clk_A : OUT STD_LOGIC;
bufo_24_Rst_A : OUT STD_LOGIC;
bufo_25_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_25_EN_A : OUT STD_LOGIC;
bufo_25_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_25_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_25_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_25_Clk_A : OUT STD_LOGIC;
bufo_25_Rst_A : OUT STD_LOGIC;
bufo_26_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_26_EN_A : OUT STD_LOGIC;
bufo_26_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_26_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_26_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_26_Clk_A : OUT STD_LOGIC;
bufo_26_Rst_A : OUT STD_LOGIC;
bufo_27_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_27_EN_A : OUT STD_LOGIC;
bufo_27_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_27_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_27_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_27_Clk_A : OUT STD_LOGIC;
bufo_27_Rst_A : OUT STD_LOGIC;
bufo_28_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_28_EN_A : OUT STD_LOGIC;
bufo_28_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_28_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_28_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_28_Clk_A : OUT STD_LOGIC;
bufo_28_Rst_A : OUT STD_LOGIC;
bufo_29_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_29_EN_A : OUT STD_LOGIC;
bufo_29_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_29_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_29_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_29_Clk_A : OUT STD_LOGIC;
bufo_29_Rst_A : OUT STD_LOGIC;
bufo_30_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_30_EN_A : OUT STD_LOGIC;
bufo_30_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_30_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_30_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_30_Clk_A : OUT STD_LOGIC;
bufo_30_Rst_A : OUT STD_LOGIC;
bufo_31_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_31_EN_A : OUT STD_LOGIC;
bufo_31_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_31_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_31_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_31_Clk_A : OUT STD_LOGIC;
bufo_31_Rst_A : OUT STD_LOGIC;
bufo_32_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_32_EN_A : OUT STD_LOGIC;
bufo_32_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_32_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_32_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_32_Clk_A : OUT STD_LOGIC;
bufo_32_Rst_A : OUT STD_LOGIC;
bufo_33_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_33_EN_A : OUT STD_LOGIC;
bufo_33_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_33_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_33_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_33_Clk_A : OUT STD_LOGIC;
bufo_33_Rst_A : OUT STD_LOGIC;
bufo_34_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_34_EN_A : OUT STD_LOGIC;
bufo_34_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_34_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_34_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_34_Clk_A : OUT STD_LOGIC;
bufo_34_Rst_A : OUT STD_LOGIC;
bufo_35_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_35_EN_A : OUT STD_LOGIC;
bufo_35_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_35_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_35_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_35_Clk_A : OUT STD_LOGIC;
bufo_35_Rst_A : OUT STD_LOGIC;
bufo_36_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_36_EN_A : OUT STD_LOGIC;
bufo_36_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_36_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_36_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_36_Clk_A : OUT STD_LOGIC;
bufo_36_Rst_A : OUT STD_LOGIC;
bufo_37_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_37_EN_A : OUT STD_LOGIC;
bufo_37_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_37_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_37_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_37_Clk_A : OUT STD_LOGIC;
bufo_37_Rst_A : OUT STD_LOGIC;
bufo_38_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_38_EN_A : OUT STD_LOGIC;
bufo_38_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_38_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_38_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_38_Clk_A : OUT STD_LOGIC;
bufo_38_Rst_A : OUT STD_LOGIC;
bufo_39_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_39_EN_A : OUT STD_LOGIC;
bufo_39_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_39_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_39_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_39_Clk_A : OUT STD_LOGIC;
bufo_39_Rst_A : OUT STD_LOGIC;
bufo_40_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_40_EN_A : OUT STD_LOGIC;
bufo_40_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_40_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_40_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_40_Clk_A : OUT STD_LOGIC;
bufo_40_Rst_A : OUT STD_LOGIC;
bufo_41_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_41_EN_A : OUT STD_LOGIC;
bufo_41_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_41_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_41_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_41_Clk_A : OUT STD_LOGIC;
bufo_41_Rst_A : OUT STD_LOGIC;
bufo_42_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_42_EN_A : OUT STD_LOGIC;
bufo_42_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_42_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_42_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_42_Clk_A : OUT STD_LOGIC;
bufo_42_Rst_A : OUT STD_LOGIC;
bufo_43_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_43_EN_A : OUT STD_LOGIC;
bufo_43_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_43_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_43_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_43_Clk_A : OUT STD_LOGIC;
bufo_43_Rst_A : OUT STD_LOGIC;
bufo_44_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_44_EN_A : OUT STD_LOGIC;
bufo_44_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_44_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_44_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_44_Clk_A : OUT STD_LOGIC;
bufo_44_Rst_A : OUT STD_LOGIC;
bufo_45_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_45_EN_A : OUT STD_LOGIC;
bufo_45_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_45_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_45_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_45_Clk_A : OUT STD_LOGIC;
bufo_45_Rst_A : OUT STD_LOGIC;
bufo_46_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_46_EN_A : OUT STD_LOGIC;
bufo_46_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_46_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_46_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_46_Clk_A : OUT STD_LOGIC;
bufo_46_Rst_A : OUT STD_LOGIC;
bufo_47_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_47_EN_A : OUT STD_LOGIC;
bufo_47_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_47_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_47_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_47_Clk_A : OUT STD_LOGIC;
bufo_47_Rst_A : OUT STD_LOGIC;
bufo_48_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_48_EN_A : OUT STD_LOGIC;
bufo_48_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_48_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_48_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_48_Clk_A : OUT STD_LOGIC;
bufo_48_Rst_A : OUT STD_LOGIC;
bufo_49_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_49_EN_A : OUT STD_LOGIC;
bufo_49_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_49_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_49_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_49_Clk_A : OUT STD_LOGIC;
bufo_49_Rst_A : OUT STD_LOGIC;
bufo_50_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_50_EN_A : OUT STD_LOGIC;
bufo_50_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_50_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_50_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_50_Clk_A : OUT STD_LOGIC;
bufo_50_Rst_A : OUT STD_LOGIC;
bufo_51_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_51_EN_A : OUT STD_LOGIC;
bufo_51_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_51_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_51_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_51_Clk_A : OUT STD_LOGIC;
bufo_51_Rst_A : OUT STD_LOGIC;
bufo_52_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_52_EN_A : OUT STD_LOGIC;
bufo_52_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_52_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_52_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_52_Clk_A : OUT STD_LOGIC;
bufo_52_Rst_A : OUT STD_LOGIC;
bufo_53_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_53_EN_A : OUT STD_LOGIC;
bufo_53_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_53_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_53_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_53_Clk_A : OUT STD_LOGIC;
bufo_53_Rst_A : OUT STD_LOGIC;
bufo_54_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_54_EN_A : OUT STD_LOGIC;
bufo_54_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_54_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_54_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_54_Clk_A : OUT STD_LOGIC;
bufo_54_Rst_A : OUT STD_LOGIC;
bufo_55_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_55_EN_A : OUT STD_LOGIC;
bufo_55_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_55_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_55_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_55_Clk_A : OUT STD_LOGIC;
bufo_55_Rst_A : OUT STD_LOGIC;
bufo_56_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_56_EN_A : OUT STD_LOGIC;
bufo_56_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_56_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_56_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_56_Clk_A : OUT STD_LOGIC;
bufo_56_Rst_A : OUT STD_LOGIC;
bufo_57_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_57_EN_A : OUT STD_LOGIC;
bufo_57_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_57_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_57_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_57_Clk_A : OUT STD_LOGIC;
bufo_57_Rst_A : OUT STD_LOGIC;
bufo_58_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_58_EN_A : OUT STD_LOGIC;
bufo_58_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_58_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_58_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_58_Clk_A : OUT STD_LOGIC;
bufo_58_Rst_A : OUT STD_LOGIC;
bufo_59_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_59_EN_A : OUT STD_LOGIC;
bufo_59_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_59_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_59_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_59_Clk_A : OUT STD_LOGIC;
bufo_59_Rst_A : OUT STD_LOGIC;
bufo_60_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_60_EN_A : OUT STD_LOGIC;
bufo_60_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_60_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_60_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_60_Clk_A : OUT STD_LOGIC;
bufo_60_Rst_A : OUT STD_LOGIC;
bufo_61_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_61_EN_A : OUT STD_LOGIC;
bufo_61_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_61_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_61_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_61_Clk_A : OUT STD_LOGIC;
bufo_61_Rst_A : OUT STD_LOGIC;
bufo_62_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_62_EN_A : OUT STD_LOGIC;
bufo_62_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_62_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_62_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_62_Clk_A : OUT STD_LOGIC;
bufo_62_Rst_A : OUT STD_LOGIC;
bufo_63_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_63_EN_A : OUT STD_LOGIC;
bufo_63_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_63_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_63_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_63_Clk_A : OUT STD_LOGIC;
bufo_63_Rst_A : OUT STD_LOGIC;
bufo_64_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_64_EN_A : OUT STD_LOGIC;
bufo_64_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_64_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_64_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_64_Clk_A : OUT STD_LOGIC;
bufo_64_Rst_A : OUT STD_LOGIC;
bufo_65_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_65_EN_A : OUT STD_LOGIC;
bufo_65_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_65_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_65_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_65_Clk_A : OUT STD_LOGIC;
bufo_65_Rst_A : OUT STD_LOGIC;
bufo_66_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_66_EN_A : OUT STD_LOGIC;
bufo_66_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_66_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_66_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_66_Clk_A : OUT STD_LOGIC;
bufo_66_Rst_A : OUT STD_LOGIC;
bufo_67_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_67_EN_A : OUT STD_LOGIC;
bufo_67_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_67_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_67_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_67_Clk_A : OUT STD_LOGIC;
bufo_67_Rst_A : OUT STD_LOGIC;
bufo_68_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_68_EN_A : OUT STD_LOGIC;
bufo_68_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_68_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_68_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_68_Clk_A : OUT STD_LOGIC;
bufo_68_Rst_A : OUT STD_LOGIC;
bufo_69_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_69_EN_A : OUT STD_LOGIC;
bufo_69_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_69_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_69_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_69_Clk_A : OUT STD_LOGIC;
bufo_69_Rst_A : OUT STD_LOGIC;
bufo_70_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_70_EN_A : OUT STD_LOGIC;
bufo_70_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_70_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_70_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_70_Clk_A : OUT STD_LOGIC;
bufo_70_Rst_A : OUT STD_LOGIC;
bufo_71_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_71_EN_A : OUT STD_LOGIC;
bufo_71_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_71_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_71_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_71_Clk_A : OUT STD_LOGIC;
bufo_71_Rst_A : OUT STD_LOGIC;
bufo_72_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_72_EN_A : OUT STD_LOGIC;
bufo_72_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_72_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_72_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_72_Clk_A : OUT STD_LOGIC;
bufo_72_Rst_A : OUT STD_LOGIC;
bufo_73_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_73_EN_A : OUT STD_LOGIC;
bufo_73_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_73_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_73_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_73_Clk_A : OUT STD_LOGIC;
bufo_73_Rst_A : OUT STD_LOGIC;
bufo_74_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_74_EN_A : OUT STD_LOGIC;
bufo_74_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_74_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_74_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_74_Clk_A : OUT STD_LOGIC;
bufo_74_Rst_A : OUT STD_LOGIC;
bufo_75_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_75_EN_A : OUT STD_LOGIC;
bufo_75_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_75_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_75_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_75_Clk_A : OUT STD_LOGIC;
bufo_75_Rst_A : OUT STD_LOGIC;
bufo_76_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_76_EN_A : OUT STD_LOGIC;
bufo_76_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_76_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_76_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_76_Clk_A : OUT STD_LOGIC;
bufo_76_Rst_A : OUT STD_LOGIC;
bufo_77_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_77_EN_A : OUT STD_LOGIC;
bufo_77_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_77_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_77_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_77_Clk_A : OUT STD_LOGIC;
bufo_77_Rst_A : OUT STD_LOGIC;
bufo_78_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_78_EN_A : OUT STD_LOGIC;
bufo_78_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_78_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_78_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_78_Clk_A : OUT STD_LOGIC;
bufo_78_Rst_A : OUT STD_LOGIC;
bufo_79_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_79_EN_A : OUT STD_LOGIC;
bufo_79_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_79_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_79_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_79_Clk_A : OUT STD_LOGIC;
bufo_79_Rst_A : OUT STD_LOGIC;
bufo_80_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_80_EN_A : OUT STD_LOGIC;
bufo_80_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_80_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_80_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_80_Clk_A : OUT STD_LOGIC;
bufo_80_Rst_A : OUT STD_LOGIC;
bufo_81_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_81_EN_A : OUT STD_LOGIC;
bufo_81_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_81_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_81_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_81_Clk_A : OUT STD_LOGIC;
bufo_81_Rst_A : OUT STD_LOGIC;
bufo_82_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_82_EN_A : OUT STD_LOGIC;
bufo_82_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_82_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_82_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_82_Clk_A : OUT STD_LOGIC;
bufo_82_Rst_A : OUT STD_LOGIC;
bufo_83_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_83_EN_A : OUT STD_LOGIC;
bufo_83_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_83_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_83_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_83_Clk_A : OUT STD_LOGIC;
bufo_83_Rst_A : OUT STD_LOGIC;
bufo_84_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_84_EN_A : OUT STD_LOGIC;
bufo_84_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_84_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_84_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_84_Clk_A : OUT STD_LOGIC;
bufo_84_Rst_A : OUT STD_LOGIC;
bufo_85_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_85_EN_A : OUT STD_LOGIC;
bufo_85_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_85_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_85_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_85_Clk_A : OUT STD_LOGIC;
bufo_85_Rst_A : OUT STD_LOGIC;
bufo_86_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_86_EN_A : OUT STD_LOGIC;
bufo_86_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_86_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_86_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_86_Clk_A : OUT STD_LOGIC;
bufo_86_Rst_A : OUT STD_LOGIC;
bufo_87_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_87_EN_A : OUT STD_LOGIC;
bufo_87_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_87_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_87_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_87_Clk_A : OUT STD_LOGIC;
bufo_87_Rst_A : OUT STD_LOGIC;
bufo_88_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_88_EN_A : OUT STD_LOGIC;
bufo_88_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_88_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_88_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_88_Clk_A : OUT STD_LOGIC;
bufo_88_Rst_A : OUT STD_LOGIC;
bufo_89_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_89_EN_A : OUT STD_LOGIC;
bufo_89_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_89_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_89_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_89_Clk_A : OUT STD_LOGIC;
bufo_89_Rst_A : OUT STD_LOGIC;
bufo_90_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_90_EN_A : OUT STD_LOGIC;
bufo_90_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_90_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_90_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_90_Clk_A : OUT STD_LOGIC;
bufo_90_Rst_A : OUT STD_LOGIC;
bufo_91_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_91_EN_A : OUT STD_LOGIC;
bufo_91_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_91_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_91_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_91_Clk_A : OUT STD_LOGIC;
bufo_91_Rst_A : OUT STD_LOGIC;
bufo_92_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_92_EN_A : OUT STD_LOGIC;
bufo_92_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_92_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_92_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_92_Clk_A : OUT STD_LOGIC;
bufo_92_Rst_A : OUT STD_LOGIC;
bufo_93_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_93_EN_A : OUT STD_LOGIC;
bufo_93_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_93_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_93_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_93_Clk_A : OUT STD_LOGIC;
bufo_93_Rst_A : OUT STD_LOGIC;
bufo_94_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_94_EN_A : OUT STD_LOGIC;
bufo_94_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_94_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_94_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_94_Clk_A : OUT STD_LOGIC;
bufo_94_Rst_A : OUT STD_LOGIC;
bufo_95_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_95_EN_A : OUT STD_LOGIC;
bufo_95_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_95_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_95_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_95_Clk_A : OUT STD_LOGIC;
bufo_95_Rst_A : OUT STD_LOGIC;
bufo_96_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_96_EN_A : OUT STD_LOGIC;
bufo_96_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_96_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_96_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_96_Clk_A : OUT STD_LOGIC;
bufo_96_Rst_A : OUT STD_LOGIC;
bufo_97_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_97_EN_A : OUT STD_LOGIC;
bufo_97_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_97_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_97_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_97_Clk_A : OUT STD_LOGIC;
bufo_97_Rst_A : OUT STD_LOGIC;
bufo_98_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_98_EN_A : OUT STD_LOGIC;
bufo_98_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_98_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_98_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_98_Clk_A : OUT STD_LOGIC;
bufo_98_Rst_A : OUT STD_LOGIC;
bufo_99_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_99_EN_A : OUT STD_LOGIC;
bufo_99_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_99_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_99_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_99_Clk_A : OUT STD_LOGIC;
bufo_99_Rst_A : OUT STD_LOGIC;
bufo_100_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_100_EN_A : OUT STD_LOGIC;
bufo_100_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_100_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_100_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_100_Clk_A : OUT STD_LOGIC;
bufo_100_Rst_A : OUT STD_LOGIC;
bufo_101_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_101_EN_A : OUT STD_LOGIC;
bufo_101_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_101_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_101_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_101_Clk_A : OUT STD_LOGIC;
bufo_101_Rst_A : OUT STD_LOGIC;
bufo_102_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_102_EN_A : OUT STD_LOGIC;
bufo_102_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_102_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_102_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_102_Clk_A : OUT STD_LOGIC;
bufo_102_Rst_A : OUT STD_LOGIC;
bufo_103_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_103_EN_A : OUT STD_LOGIC;
bufo_103_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_103_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_103_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_103_Clk_A : OUT STD_LOGIC;
bufo_103_Rst_A : OUT STD_LOGIC;
bufo_104_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_104_EN_A : OUT STD_LOGIC;
bufo_104_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_104_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_104_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_104_Clk_A : OUT STD_LOGIC;
bufo_104_Rst_A : OUT STD_LOGIC;
bufo_105_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_105_EN_A : OUT STD_LOGIC;
bufo_105_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_105_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_105_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_105_Clk_A : OUT STD_LOGIC;
bufo_105_Rst_A : OUT STD_LOGIC;
bufo_106_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_106_EN_A : OUT STD_LOGIC;
bufo_106_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_106_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_106_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_106_Clk_A : OUT STD_LOGIC;
bufo_106_Rst_A : OUT STD_LOGIC;
bufo_107_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_107_EN_A : OUT STD_LOGIC;
bufo_107_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_107_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_107_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_107_Clk_A : OUT STD_LOGIC;
bufo_107_Rst_A : OUT STD_LOGIC;
bufo_108_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_108_EN_A : OUT STD_LOGIC;
bufo_108_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_108_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_108_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_108_Clk_A : OUT STD_LOGIC;
bufo_108_Rst_A : OUT STD_LOGIC;
bufo_109_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_109_EN_A : OUT STD_LOGIC;
bufo_109_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_109_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_109_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_109_Clk_A : OUT STD_LOGIC;
bufo_109_Rst_A : OUT STD_LOGIC;
bufo_110_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_110_EN_A : OUT STD_LOGIC;
bufo_110_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_110_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_110_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_110_Clk_A : OUT STD_LOGIC;
bufo_110_Rst_A : OUT STD_LOGIC;
bufo_111_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_111_EN_A : OUT STD_LOGIC;
bufo_111_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_111_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_111_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_111_Clk_A : OUT STD_LOGIC;
bufo_111_Rst_A : OUT STD_LOGIC;
bufo_112_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_112_EN_A : OUT STD_LOGIC;
bufo_112_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_112_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_112_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_112_Clk_A : OUT STD_LOGIC;
bufo_112_Rst_A : OUT STD_LOGIC;
bufo_113_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_113_EN_A : OUT STD_LOGIC;
bufo_113_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_113_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_113_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_113_Clk_A : OUT STD_LOGIC;
bufo_113_Rst_A : OUT STD_LOGIC;
bufo_114_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_114_EN_A : OUT STD_LOGIC;
bufo_114_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_114_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_114_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_114_Clk_A : OUT STD_LOGIC;
bufo_114_Rst_A : OUT STD_LOGIC;
bufo_115_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_115_EN_A : OUT STD_LOGIC;
bufo_115_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_115_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_115_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_115_Clk_A : OUT STD_LOGIC;
bufo_115_Rst_A : OUT STD_LOGIC;
bufo_116_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_116_EN_A : OUT STD_LOGIC;
bufo_116_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_116_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_116_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_116_Clk_A : OUT STD_LOGIC;
bufo_116_Rst_A : OUT STD_LOGIC;
bufo_117_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_117_EN_A : OUT STD_LOGIC;
bufo_117_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_117_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_117_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_117_Clk_A : OUT STD_LOGIC;
bufo_117_Rst_A : OUT STD_LOGIC;
bufo_118_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_118_EN_A : OUT STD_LOGIC;
bufo_118_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_118_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_118_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_118_Clk_A : OUT STD_LOGIC;
bufo_118_Rst_A : OUT STD_LOGIC;
bufo_119_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_119_EN_A : OUT STD_LOGIC;
bufo_119_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_119_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_119_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_119_Clk_A : OUT STD_LOGIC;
bufo_119_Rst_A : OUT STD_LOGIC;
bufo_120_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_120_EN_A : OUT STD_LOGIC;
bufo_120_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_120_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_120_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_120_Clk_A : OUT STD_LOGIC;
bufo_120_Rst_A : OUT STD_LOGIC;
bufo_121_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_121_EN_A : OUT STD_LOGIC;
bufo_121_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_121_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_121_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_121_Clk_A : OUT STD_LOGIC;
bufo_121_Rst_A : OUT STD_LOGIC;
bufo_122_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_122_EN_A : OUT STD_LOGIC;
bufo_122_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_122_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_122_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_122_Clk_A : OUT STD_LOGIC;
bufo_122_Rst_A : OUT STD_LOGIC;
bufo_123_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_123_EN_A : OUT STD_LOGIC;
bufo_123_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_123_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_123_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_123_Clk_A : OUT STD_LOGIC;
bufo_123_Rst_A : OUT STD_LOGIC;
bufo_124_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_124_EN_A : OUT STD_LOGIC;
bufo_124_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_124_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_124_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_124_Clk_A : OUT STD_LOGIC;
bufo_124_Rst_A : OUT STD_LOGIC;
bufo_125_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_125_EN_A : OUT STD_LOGIC;
bufo_125_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_125_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_125_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_125_Clk_A : OUT STD_LOGIC;
bufo_125_Rst_A : OUT STD_LOGIC;
bufo_126_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_126_EN_A : OUT STD_LOGIC;
bufo_126_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_126_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_126_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_126_Clk_A : OUT STD_LOGIC;
bufo_126_Rst_A : OUT STD_LOGIC;
bufo_127_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_127_EN_A : OUT STD_LOGIC;
bufo_127_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_127_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_127_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_127_Clk_A : OUT STD_LOGIC;
bufo_127_Rst_A : OUT STD_LOGIC;
bufo_128_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_EN_A : OUT STD_LOGIC;
bufo_128_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_128_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Clk_A : OUT STD_LOGIC;
bufo_128_Rst_A : OUT STD_LOGIC;
bufo_128_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_EN_B : OUT STD_LOGIC;
bufo_128_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_128_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_128_Clk_B : OUT STD_LOGIC;
bufo_128_Rst_B : OUT STD_LOGIC;
bufo_129_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_EN_A : OUT STD_LOGIC;
bufo_129_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_129_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Clk_A : OUT STD_LOGIC;
bufo_129_Rst_A : OUT STD_LOGIC;
bufo_129_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_EN_B : OUT STD_LOGIC;
bufo_129_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_129_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_129_Clk_B : OUT STD_LOGIC;
bufo_129_Rst_B : OUT STD_LOGIC;
bufo_130_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_EN_A : OUT STD_LOGIC;
bufo_130_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_130_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Clk_A : OUT STD_LOGIC;
bufo_130_Rst_A : OUT STD_LOGIC;
bufo_130_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_EN_B : OUT STD_LOGIC;
bufo_130_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_130_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_130_Clk_B : OUT STD_LOGIC;
bufo_130_Rst_B : OUT STD_LOGIC;
bufo_131_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_EN_A : OUT STD_LOGIC;
bufo_131_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_131_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Clk_A : OUT STD_LOGIC;
bufo_131_Rst_A : OUT STD_LOGIC;
bufo_131_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_EN_B : OUT STD_LOGIC;
bufo_131_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_131_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_131_Clk_B : OUT STD_LOGIC;
bufo_131_Rst_B : OUT STD_LOGIC;
bufo_132_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_EN_A : OUT STD_LOGIC;
bufo_132_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_132_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Clk_A : OUT STD_LOGIC;
bufo_132_Rst_A : OUT STD_LOGIC;
bufo_132_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_EN_B : OUT STD_LOGIC;
bufo_132_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_132_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_132_Clk_B : OUT STD_LOGIC;
bufo_132_Rst_B : OUT STD_LOGIC;
bufo_133_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_EN_A : OUT STD_LOGIC;
bufo_133_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_133_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Clk_A : OUT STD_LOGIC;
bufo_133_Rst_A : OUT STD_LOGIC;
bufo_133_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_EN_B : OUT STD_LOGIC;
bufo_133_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_133_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_133_Clk_B : OUT STD_LOGIC;
bufo_133_Rst_B : OUT STD_LOGIC;
bufo_134_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_EN_A : OUT STD_LOGIC;
bufo_134_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_134_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Clk_A : OUT STD_LOGIC;
bufo_134_Rst_A : OUT STD_LOGIC;
bufo_134_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_EN_B : OUT STD_LOGIC;
bufo_134_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_134_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_134_Clk_B : OUT STD_LOGIC;
bufo_134_Rst_B : OUT STD_LOGIC;
bufo_135_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_EN_A : OUT STD_LOGIC;
bufo_135_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_135_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Clk_A : OUT STD_LOGIC;
bufo_135_Rst_A : OUT STD_LOGIC;
bufo_135_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_EN_B : OUT STD_LOGIC;
bufo_135_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_135_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_135_Clk_B : OUT STD_LOGIC;
bufo_135_Rst_B : OUT STD_LOGIC;
bufo_136_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_EN_A : OUT STD_LOGIC;
bufo_136_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_136_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Clk_A : OUT STD_LOGIC;
bufo_136_Rst_A : OUT STD_LOGIC;
bufo_136_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_EN_B : OUT STD_LOGIC;
bufo_136_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_136_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_136_Clk_B : OUT STD_LOGIC;
bufo_136_Rst_B : OUT STD_LOGIC;
bufo_137_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_EN_A : OUT STD_LOGIC;
bufo_137_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_137_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Clk_A : OUT STD_LOGIC;
bufo_137_Rst_A : OUT STD_LOGIC;
bufo_137_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_EN_B : OUT STD_LOGIC;
bufo_137_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_137_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_137_Clk_B : OUT STD_LOGIC;
bufo_137_Rst_B : OUT STD_LOGIC;
bufo_138_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_EN_A : OUT STD_LOGIC;
bufo_138_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_138_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Clk_A : OUT STD_LOGIC;
bufo_138_Rst_A : OUT STD_LOGIC;
bufo_138_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_EN_B : OUT STD_LOGIC;
bufo_138_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_138_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_138_Clk_B : OUT STD_LOGIC;
bufo_138_Rst_B : OUT STD_LOGIC;
bufo_139_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_EN_A : OUT STD_LOGIC;
bufo_139_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_139_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Clk_A : OUT STD_LOGIC;
bufo_139_Rst_A : OUT STD_LOGIC;
bufo_139_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_EN_B : OUT STD_LOGIC;
bufo_139_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_139_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_139_Clk_B : OUT STD_LOGIC;
bufo_139_Rst_B : OUT STD_LOGIC;
bufo_140_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_EN_A : OUT STD_LOGIC;
bufo_140_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_140_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Clk_A : OUT STD_LOGIC;
bufo_140_Rst_A : OUT STD_LOGIC;
bufo_140_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_EN_B : OUT STD_LOGIC;
bufo_140_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_140_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_140_Clk_B : OUT STD_LOGIC;
bufo_140_Rst_B : OUT STD_LOGIC;
bufo_141_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_EN_A : OUT STD_LOGIC;
bufo_141_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_141_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Clk_A : OUT STD_LOGIC;
bufo_141_Rst_A : OUT STD_LOGIC;
bufo_141_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_EN_B : OUT STD_LOGIC;
bufo_141_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_141_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_141_Clk_B : OUT STD_LOGIC;
bufo_141_Rst_B : OUT STD_LOGIC;
bufo_142_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_EN_A : OUT STD_LOGIC;
bufo_142_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_142_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Clk_A : OUT STD_LOGIC;
bufo_142_Rst_A : OUT STD_LOGIC;
bufo_142_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_EN_B : OUT STD_LOGIC;
bufo_142_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_142_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_142_Clk_B : OUT STD_LOGIC;
bufo_142_Rst_B : OUT STD_LOGIC;
bufo_143_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_EN_A : OUT STD_LOGIC;
bufo_143_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_143_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Clk_A : OUT STD_LOGIC;
bufo_143_Rst_A : OUT STD_LOGIC;
bufo_143_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_EN_B : OUT STD_LOGIC;
bufo_143_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_143_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_143_Clk_B : OUT STD_LOGIC;
bufo_143_Rst_B : OUT STD_LOGIC;
bufo_144_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_EN_A : OUT STD_LOGIC;
bufo_144_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_144_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Clk_A : OUT STD_LOGIC;
bufo_144_Rst_A : OUT STD_LOGIC;
bufo_144_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_EN_B : OUT STD_LOGIC;
bufo_144_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_144_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_144_Clk_B : OUT STD_LOGIC;
bufo_144_Rst_B : OUT STD_LOGIC;
bufo_145_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_EN_A : OUT STD_LOGIC;
bufo_145_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_145_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Clk_A : OUT STD_LOGIC;
bufo_145_Rst_A : OUT STD_LOGIC;
bufo_145_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_EN_B : OUT STD_LOGIC;
bufo_145_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_145_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_145_Clk_B : OUT STD_LOGIC;
bufo_145_Rst_B : OUT STD_LOGIC;
bufo_146_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_EN_A : OUT STD_LOGIC;
bufo_146_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_146_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Clk_A : OUT STD_LOGIC;
bufo_146_Rst_A : OUT STD_LOGIC;
bufo_146_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_EN_B : OUT STD_LOGIC;
bufo_146_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_146_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_146_Clk_B : OUT STD_LOGIC;
bufo_146_Rst_B : OUT STD_LOGIC;
bufo_147_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_EN_A : OUT STD_LOGIC;
bufo_147_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_147_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Clk_A : OUT STD_LOGIC;
bufo_147_Rst_A : OUT STD_LOGIC;
bufo_147_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_EN_B : OUT STD_LOGIC;
bufo_147_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_147_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_147_Clk_B : OUT STD_LOGIC;
bufo_147_Rst_B : OUT STD_LOGIC;
bufo_148_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_EN_A : OUT STD_LOGIC;
bufo_148_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_148_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Clk_A : OUT STD_LOGIC;
bufo_148_Rst_A : OUT STD_LOGIC;
bufo_148_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_EN_B : OUT STD_LOGIC;
bufo_148_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_148_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_148_Clk_B : OUT STD_LOGIC;
bufo_148_Rst_B : OUT STD_LOGIC;
bufo_149_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_EN_A : OUT STD_LOGIC;
bufo_149_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_149_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Clk_A : OUT STD_LOGIC;
bufo_149_Rst_A : OUT STD_LOGIC;
bufo_149_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_EN_B : OUT STD_LOGIC;
bufo_149_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_149_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_149_Clk_B : OUT STD_LOGIC;
bufo_149_Rst_B : OUT STD_LOGIC;
bufo_150_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_EN_A : OUT STD_LOGIC;
bufo_150_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_150_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Clk_A : OUT STD_LOGIC;
bufo_150_Rst_A : OUT STD_LOGIC;
bufo_150_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_EN_B : OUT STD_LOGIC;
bufo_150_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_150_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_150_Clk_B : OUT STD_LOGIC;
bufo_150_Rst_B : OUT STD_LOGIC;
bufo_151_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_EN_A : OUT STD_LOGIC;
bufo_151_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_151_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Clk_A : OUT STD_LOGIC;
bufo_151_Rst_A : OUT STD_LOGIC;
bufo_151_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_EN_B : OUT STD_LOGIC;
bufo_151_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_151_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_151_Clk_B : OUT STD_LOGIC;
bufo_151_Rst_B : OUT STD_LOGIC;
bufo_152_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_EN_A : OUT STD_LOGIC;
bufo_152_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_152_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Clk_A : OUT STD_LOGIC;
bufo_152_Rst_A : OUT STD_LOGIC;
bufo_152_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_EN_B : OUT STD_LOGIC;
bufo_152_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_152_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_152_Clk_B : OUT STD_LOGIC;
bufo_152_Rst_B : OUT STD_LOGIC;
bufo_153_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_EN_A : OUT STD_LOGIC;
bufo_153_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_153_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Clk_A : OUT STD_LOGIC;
bufo_153_Rst_A : OUT STD_LOGIC;
bufo_153_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_EN_B : OUT STD_LOGIC;
bufo_153_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_153_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_153_Clk_B : OUT STD_LOGIC;
bufo_153_Rst_B : OUT STD_LOGIC;
bufo_154_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_EN_A : OUT STD_LOGIC;
bufo_154_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_154_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Clk_A : OUT STD_LOGIC;
bufo_154_Rst_A : OUT STD_LOGIC;
bufo_154_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_EN_B : OUT STD_LOGIC;
bufo_154_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_154_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_154_Clk_B : OUT STD_LOGIC;
bufo_154_Rst_B : OUT STD_LOGIC;
bufo_155_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_EN_A : OUT STD_LOGIC;
bufo_155_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_155_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Clk_A : OUT STD_LOGIC;
bufo_155_Rst_A : OUT STD_LOGIC;
bufo_155_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_EN_B : OUT STD_LOGIC;
bufo_155_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_155_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_155_Clk_B : OUT STD_LOGIC;
bufo_155_Rst_B : OUT STD_LOGIC;
bufo_156_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_EN_A : OUT STD_LOGIC;
bufo_156_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_156_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Clk_A : OUT STD_LOGIC;
bufo_156_Rst_A : OUT STD_LOGIC;
bufo_156_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_EN_B : OUT STD_LOGIC;
bufo_156_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_156_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_156_Clk_B : OUT STD_LOGIC;
bufo_156_Rst_B : OUT STD_LOGIC;
bufo_157_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_EN_A : OUT STD_LOGIC;
bufo_157_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_157_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Clk_A : OUT STD_LOGIC;
bufo_157_Rst_A : OUT STD_LOGIC;
bufo_157_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_EN_B : OUT STD_LOGIC;
bufo_157_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_157_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_157_Clk_B : OUT STD_LOGIC;
bufo_157_Rst_B : OUT STD_LOGIC;
bufo_158_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_EN_A : OUT STD_LOGIC;
bufo_158_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_158_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Clk_A : OUT STD_LOGIC;
bufo_158_Rst_A : OUT STD_LOGIC;
bufo_158_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_EN_B : OUT STD_LOGIC;
bufo_158_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_158_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_158_Clk_B : OUT STD_LOGIC;
bufo_158_Rst_B : OUT STD_LOGIC;
bufo_159_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_EN_A : OUT STD_LOGIC;
bufo_159_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_159_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Clk_A : OUT STD_LOGIC;
bufo_159_Rst_A : OUT STD_LOGIC;
bufo_159_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_EN_B : OUT STD_LOGIC;
bufo_159_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_159_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_159_Clk_B : OUT STD_LOGIC;
bufo_159_Rst_B : OUT STD_LOGIC;
bufo_160_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_EN_A : OUT STD_LOGIC;
bufo_160_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_160_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Clk_A : OUT STD_LOGIC;
bufo_160_Rst_A : OUT STD_LOGIC;
bufo_160_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_EN_B : OUT STD_LOGIC;
bufo_160_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_160_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_160_Clk_B : OUT STD_LOGIC;
bufo_160_Rst_B : OUT STD_LOGIC;
bufo_161_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_EN_A : OUT STD_LOGIC;
bufo_161_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_161_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Clk_A : OUT STD_LOGIC;
bufo_161_Rst_A : OUT STD_LOGIC;
bufo_161_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_EN_B : OUT STD_LOGIC;
bufo_161_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_161_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_161_Clk_B : OUT STD_LOGIC;
bufo_161_Rst_B : OUT STD_LOGIC;
bufo_162_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_EN_A : OUT STD_LOGIC;
bufo_162_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_162_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Clk_A : OUT STD_LOGIC;
bufo_162_Rst_A : OUT STD_LOGIC;
bufo_162_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_EN_B : OUT STD_LOGIC;
bufo_162_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_162_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_162_Clk_B : OUT STD_LOGIC;
bufo_162_Rst_B : OUT STD_LOGIC;
bufo_163_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_EN_A : OUT STD_LOGIC;
bufo_163_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_163_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Clk_A : OUT STD_LOGIC;
bufo_163_Rst_A : OUT STD_LOGIC;
bufo_163_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_EN_B : OUT STD_LOGIC;
bufo_163_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_163_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_163_Clk_B : OUT STD_LOGIC;
bufo_163_Rst_B : OUT STD_LOGIC;
bufo_164_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_EN_A : OUT STD_LOGIC;
bufo_164_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_164_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Clk_A : OUT STD_LOGIC;
bufo_164_Rst_A : OUT STD_LOGIC;
bufo_164_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_EN_B : OUT STD_LOGIC;
bufo_164_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_164_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_164_Clk_B : OUT STD_LOGIC;
bufo_164_Rst_B : OUT STD_LOGIC;
bufo_165_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_EN_A : OUT STD_LOGIC;
bufo_165_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_165_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Clk_A : OUT STD_LOGIC;
bufo_165_Rst_A : OUT STD_LOGIC;
bufo_165_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_EN_B : OUT STD_LOGIC;
bufo_165_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_165_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_165_Clk_B : OUT STD_LOGIC;
bufo_165_Rst_B : OUT STD_LOGIC;
bufo_166_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_EN_A : OUT STD_LOGIC;
bufo_166_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_166_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Clk_A : OUT STD_LOGIC;
bufo_166_Rst_A : OUT STD_LOGIC;
bufo_166_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_EN_B : OUT STD_LOGIC;
bufo_166_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_166_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_166_Clk_B : OUT STD_LOGIC;
bufo_166_Rst_B : OUT STD_LOGIC;
bufo_167_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_EN_A : OUT STD_LOGIC;
bufo_167_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_167_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Clk_A : OUT STD_LOGIC;
bufo_167_Rst_A : OUT STD_LOGIC;
bufo_167_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_EN_B : OUT STD_LOGIC;
bufo_167_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_167_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_167_Clk_B : OUT STD_LOGIC;
bufo_167_Rst_B : OUT STD_LOGIC;
bufo_168_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_EN_A : OUT STD_LOGIC;
bufo_168_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_168_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Clk_A : OUT STD_LOGIC;
bufo_168_Rst_A : OUT STD_LOGIC;
bufo_168_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_EN_B : OUT STD_LOGIC;
bufo_168_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_168_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_168_Clk_B : OUT STD_LOGIC;
bufo_168_Rst_B : OUT STD_LOGIC;
bufo_169_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_EN_A : OUT STD_LOGIC;
bufo_169_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_169_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Clk_A : OUT STD_LOGIC;
bufo_169_Rst_A : OUT STD_LOGIC;
bufo_169_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_EN_B : OUT STD_LOGIC;
bufo_169_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_169_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_169_Clk_B : OUT STD_LOGIC;
bufo_169_Rst_B : OUT STD_LOGIC;
bufo_170_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_EN_A : OUT STD_LOGIC;
bufo_170_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_170_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Clk_A : OUT STD_LOGIC;
bufo_170_Rst_A : OUT STD_LOGIC;
bufo_170_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_EN_B : OUT STD_LOGIC;
bufo_170_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_170_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_170_Clk_B : OUT STD_LOGIC;
bufo_170_Rst_B : OUT STD_LOGIC;
bufo_171_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_EN_A : OUT STD_LOGIC;
bufo_171_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_171_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Clk_A : OUT STD_LOGIC;
bufo_171_Rst_A : OUT STD_LOGIC;
bufo_171_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_EN_B : OUT STD_LOGIC;
bufo_171_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_171_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_171_Clk_B : OUT STD_LOGIC;
bufo_171_Rst_B : OUT STD_LOGIC;
bufo_172_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_EN_A : OUT STD_LOGIC;
bufo_172_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_172_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Clk_A : OUT STD_LOGIC;
bufo_172_Rst_A : OUT STD_LOGIC;
bufo_172_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_EN_B : OUT STD_LOGIC;
bufo_172_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_172_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_172_Clk_B : OUT STD_LOGIC;
bufo_172_Rst_B : OUT STD_LOGIC;
bufo_173_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_EN_A : OUT STD_LOGIC;
bufo_173_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_173_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Clk_A : OUT STD_LOGIC;
bufo_173_Rst_A : OUT STD_LOGIC;
bufo_173_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_EN_B : OUT STD_LOGIC;
bufo_173_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_173_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_173_Clk_B : OUT STD_LOGIC;
bufo_173_Rst_B : OUT STD_LOGIC;
bufo_174_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_EN_A : OUT STD_LOGIC;
bufo_174_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_174_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Clk_A : OUT STD_LOGIC;
bufo_174_Rst_A : OUT STD_LOGIC;
bufo_174_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_EN_B : OUT STD_LOGIC;
bufo_174_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_174_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_174_Clk_B : OUT STD_LOGIC;
bufo_174_Rst_B : OUT STD_LOGIC;
bufo_175_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_EN_A : OUT STD_LOGIC;
bufo_175_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_175_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Clk_A : OUT STD_LOGIC;
bufo_175_Rst_A : OUT STD_LOGIC;
bufo_175_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_EN_B : OUT STD_LOGIC;
bufo_175_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_175_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_175_Clk_B : OUT STD_LOGIC;
bufo_175_Rst_B : OUT STD_LOGIC;
bufo_176_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_EN_A : OUT STD_LOGIC;
bufo_176_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_176_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Clk_A : OUT STD_LOGIC;
bufo_176_Rst_A : OUT STD_LOGIC;
bufo_176_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_EN_B : OUT STD_LOGIC;
bufo_176_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_176_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_176_Clk_B : OUT STD_LOGIC;
bufo_176_Rst_B : OUT STD_LOGIC;
bufo_177_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_EN_A : OUT STD_LOGIC;
bufo_177_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_177_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Clk_A : OUT STD_LOGIC;
bufo_177_Rst_A : OUT STD_LOGIC;
bufo_177_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_EN_B : OUT STD_LOGIC;
bufo_177_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_177_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_177_Clk_B : OUT STD_LOGIC;
bufo_177_Rst_B : OUT STD_LOGIC;
bufo_178_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_EN_A : OUT STD_LOGIC;
bufo_178_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_178_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Clk_A : OUT STD_LOGIC;
bufo_178_Rst_A : OUT STD_LOGIC;
bufo_178_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_EN_B : OUT STD_LOGIC;
bufo_178_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_178_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_178_Clk_B : OUT STD_LOGIC;
bufo_178_Rst_B : OUT STD_LOGIC;
bufo_179_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_EN_A : OUT STD_LOGIC;
bufo_179_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_179_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Clk_A : OUT STD_LOGIC;
bufo_179_Rst_A : OUT STD_LOGIC;
bufo_179_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_EN_B : OUT STD_LOGIC;
bufo_179_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_179_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_179_Clk_B : OUT STD_LOGIC;
bufo_179_Rst_B : OUT STD_LOGIC;
bufo_180_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_EN_A : OUT STD_LOGIC;
bufo_180_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_180_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Clk_A : OUT STD_LOGIC;
bufo_180_Rst_A : OUT STD_LOGIC;
bufo_180_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_EN_B : OUT STD_LOGIC;
bufo_180_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_180_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_180_Clk_B : OUT STD_LOGIC;
bufo_180_Rst_B : OUT STD_LOGIC;
bufo_181_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_EN_A : OUT STD_LOGIC;
bufo_181_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_181_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Clk_A : OUT STD_LOGIC;
bufo_181_Rst_A : OUT STD_LOGIC;
bufo_181_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_EN_B : OUT STD_LOGIC;
bufo_181_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_181_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_181_Clk_B : OUT STD_LOGIC;
bufo_181_Rst_B : OUT STD_LOGIC;
bufo_182_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_EN_A : OUT STD_LOGIC;
bufo_182_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_182_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Clk_A : OUT STD_LOGIC;
bufo_182_Rst_A : OUT STD_LOGIC;
bufo_182_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_EN_B : OUT STD_LOGIC;
bufo_182_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_182_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_182_Clk_B : OUT STD_LOGIC;
bufo_182_Rst_B : OUT STD_LOGIC;
bufo_183_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_EN_A : OUT STD_LOGIC;
bufo_183_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_183_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Clk_A : OUT STD_LOGIC;
bufo_183_Rst_A : OUT STD_LOGIC;
bufo_183_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_EN_B : OUT STD_LOGIC;
bufo_183_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_183_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_183_Clk_B : OUT STD_LOGIC;
bufo_183_Rst_B : OUT STD_LOGIC;
bufo_184_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_EN_A : OUT STD_LOGIC;
bufo_184_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_184_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Clk_A : OUT STD_LOGIC;
bufo_184_Rst_A : OUT STD_LOGIC;
bufo_184_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_EN_B : OUT STD_LOGIC;
bufo_184_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_184_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_184_Clk_B : OUT STD_LOGIC;
bufo_184_Rst_B : OUT STD_LOGIC;
bufo_185_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_EN_A : OUT STD_LOGIC;
bufo_185_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_185_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Clk_A : OUT STD_LOGIC;
bufo_185_Rst_A : OUT STD_LOGIC;
bufo_185_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_EN_B : OUT STD_LOGIC;
bufo_185_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_185_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_185_Clk_B : OUT STD_LOGIC;
bufo_185_Rst_B : OUT STD_LOGIC;
bufo_186_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_EN_A : OUT STD_LOGIC;
bufo_186_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_186_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Clk_A : OUT STD_LOGIC;
bufo_186_Rst_A : OUT STD_LOGIC;
bufo_186_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_EN_B : OUT STD_LOGIC;
bufo_186_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_186_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_186_Clk_B : OUT STD_LOGIC;
bufo_186_Rst_B : OUT STD_LOGIC;
bufo_187_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_EN_A : OUT STD_LOGIC;
bufo_187_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_187_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Clk_A : OUT STD_LOGIC;
bufo_187_Rst_A : OUT STD_LOGIC;
bufo_187_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_EN_B : OUT STD_LOGIC;
bufo_187_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_187_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_187_Clk_B : OUT STD_LOGIC;
bufo_187_Rst_B : OUT STD_LOGIC;
bufo_188_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_EN_A : OUT STD_LOGIC;
bufo_188_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_188_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Clk_A : OUT STD_LOGIC;
bufo_188_Rst_A : OUT STD_LOGIC;
bufo_188_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_EN_B : OUT STD_LOGIC;
bufo_188_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_188_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_188_Clk_B : OUT STD_LOGIC;
bufo_188_Rst_B : OUT STD_LOGIC;
bufo_189_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_EN_A : OUT STD_LOGIC;
bufo_189_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_189_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Clk_A : OUT STD_LOGIC;
bufo_189_Rst_A : OUT STD_LOGIC;
bufo_189_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_EN_B : OUT STD_LOGIC;
bufo_189_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_189_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_189_Clk_B : OUT STD_LOGIC;
bufo_189_Rst_B : OUT STD_LOGIC;
bufo_190_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_EN_A : OUT STD_LOGIC;
bufo_190_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_190_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Clk_A : OUT STD_LOGIC;
bufo_190_Rst_A : OUT STD_LOGIC;
bufo_190_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_EN_B : OUT STD_LOGIC;
bufo_190_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_190_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_190_Clk_B : OUT STD_LOGIC;
bufo_190_Rst_B : OUT STD_LOGIC;
bufo_191_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_EN_A : OUT STD_LOGIC;
bufo_191_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_191_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Clk_A : OUT STD_LOGIC;
bufo_191_Rst_A : OUT STD_LOGIC;
bufo_191_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_EN_B : OUT STD_LOGIC;
bufo_191_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_191_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_191_Clk_B : OUT STD_LOGIC;
bufo_191_Rst_B : OUT STD_LOGIC;
bufo_192_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_EN_A : OUT STD_LOGIC;
bufo_192_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_192_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Clk_A : OUT STD_LOGIC;
bufo_192_Rst_A : OUT STD_LOGIC;
bufo_192_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_EN_B : OUT STD_LOGIC;
bufo_192_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_192_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_192_Clk_B : OUT STD_LOGIC;
bufo_192_Rst_B : OUT STD_LOGIC;
bufo_193_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_EN_A : OUT STD_LOGIC;
bufo_193_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_193_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Clk_A : OUT STD_LOGIC;
bufo_193_Rst_A : OUT STD_LOGIC;
bufo_193_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_EN_B : OUT STD_LOGIC;
bufo_193_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_193_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_193_Clk_B : OUT STD_LOGIC;
bufo_193_Rst_B : OUT STD_LOGIC;
bufo_194_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_EN_A : OUT STD_LOGIC;
bufo_194_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_194_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Clk_A : OUT STD_LOGIC;
bufo_194_Rst_A : OUT STD_LOGIC;
bufo_194_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_EN_B : OUT STD_LOGIC;
bufo_194_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_194_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_194_Clk_B : OUT STD_LOGIC;
bufo_194_Rst_B : OUT STD_LOGIC;
bufo_195_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_EN_A : OUT STD_LOGIC;
bufo_195_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_195_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Clk_A : OUT STD_LOGIC;
bufo_195_Rst_A : OUT STD_LOGIC;
bufo_195_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_EN_B : OUT STD_LOGIC;
bufo_195_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_195_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_195_Clk_B : OUT STD_LOGIC;
bufo_195_Rst_B : OUT STD_LOGIC;
bufo_196_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_EN_A : OUT STD_LOGIC;
bufo_196_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_196_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Clk_A : OUT STD_LOGIC;
bufo_196_Rst_A : OUT STD_LOGIC;
bufo_196_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_EN_B : OUT STD_LOGIC;
bufo_196_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_196_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_196_Clk_B : OUT STD_LOGIC;
bufo_196_Rst_B : OUT STD_LOGIC;
bufo_197_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_EN_A : OUT STD_LOGIC;
bufo_197_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_197_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Clk_A : OUT STD_LOGIC;
bufo_197_Rst_A : OUT STD_LOGIC;
bufo_197_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_EN_B : OUT STD_LOGIC;
bufo_197_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_197_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_197_Clk_B : OUT STD_LOGIC;
bufo_197_Rst_B : OUT STD_LOGIC;
bufo_198_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_EN_A : OUT STD_LOGIC;
bufo_198_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_198_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Clk_A : OUT STD_LOGIC;
bufo_198_Rst_A : OUT STD_LOGIC;
bufo_198_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_EN_B : OUT STD_LOGIC;
bufo_198_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_198_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_198_Clk_B : OUT STD_LOGIC;
bufo_198_Rst_B : OUT STD_LOGIC;
bufo_199_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_EN_A : OUT STD_LOGIC;
bufo_199_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_199_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Clk_A : OUT STD_LOGIC;
bufo_199_Rst_A : OUT STD_LOGIC;
bufo_199_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_EN_B : OUT STD_LOGIC;
bufo_199_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_199_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_199_Clk_B : OUT STD_LOGIC;
bufo_199_Rst_B : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.633800,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=14,HLS_SYN_FF=5893,HLS_SYN_LUT=3947}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (55 downto 0) := "00000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (55 downto 0) := "00000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (55 downto 0) := "00000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (55 downto 0) := "00000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (55 downto 0) := "00000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (55 downto 0) := "00000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (55 downto 0) := "00001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (55 downto 0) := "00010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (55 downto 0) := "00100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (55 downto 0) := "01000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state56 : STD_LOGIC_VECTOR (55 downto 0) := "10000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110";
constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101";
constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100";
constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011";
constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010";
constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001";
constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000";
constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111";
constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110";
constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101";
constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100";
constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011";
constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010";
constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001";
constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000";
constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111";
constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110";
constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101";
constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100";
constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011";
constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010";
constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001";
constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000";
constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111";
constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110";
constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101";
constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100";
constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011";
constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010";
constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001";
constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000";
constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111";
constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110";
constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101";
constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100";
constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011";
constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010";
constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001";
constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000";
constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111";
constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110";
constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101";
constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100";
constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011";
constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000";
constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111";
constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110";
constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv64_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011001";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv128_lc_1 : STD_LOGIC_VECTOR (127 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal grp_fu_2558_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_2580 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal ap_CS_fsm_state35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
signal ap_CS_fsm_state44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state44 : signal is "none";
signal ap_CS_fsm_state55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state55 : signal is "none";
signal next_mul_fu_2714_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal next_mul_reg_3471 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_fu_2720_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_3481 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_1_fu_2724_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_3486 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_3491 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_reg_3496 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_3501 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_reg_3506 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_reg_3511 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_reg_3516 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_2564_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_reg_3561 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal grp_fu_2568_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_1_reg_3566 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_2_reg_3571 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_3_reg_3576 : STD_LOGIC_VECTOR (31 downto 0);
signal to_b_V_fu_2820_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal to_b_V_reg_3581 : STD_LOGIC_VECTOR (6 downto 0);
signal bufo_126_load_reg_3586 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state45 : signal is "none";
signal p_s_reg_2284 : STD_LOGIC_VECTOR (6 downto 0);
signal bufo_125_load_reg_3591 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_124_load_reg_3596 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_123_load_reg_3601 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_122_load_reg_3606 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_121_load_reg_3611 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_120_load_reg_3616 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_119_load_reg_3621 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_118_load_reg_3626 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_117_load_reg_3631 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_116_load_reg_3636 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_115_load_reg_3641 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_114_load_reg_3646 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_113_load_reg_3651 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_112_load_reg_3656 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_111_load_reg_3661 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_110_load_reg_3666 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_109_load_reg_3671 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_108_load_reg_3676 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_107_load_reg_3681 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_106_load_reg_3686 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_105_load_reg_3691 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_104_load_reg_3696 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_103_load_reg_3701 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_102_load_reg_3706 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_101_load_reg_3711 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_100_load_reg_3716 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_99_load_reg_3721 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_98_load_reg_3726 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_97_load_reg_3731 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_96_load_reg_3736 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_95_load_reg_3741 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_94_load_reg_3746 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_93_load_reg_3751 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_92_load_reg_3756 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_91_load_reg_3761 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_90_load_reg_3766 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_89_load_reg_3771 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_88_load_reg_3776 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_87_load_reg_3781 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_86_load_reg_3786 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_85_load_reg_3791 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_84_load_reg_3796 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_83_load_reg_3801 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_82_load_reg_3806 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_81_load_reg_3811 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_80_load_reg_3816 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_79_load_reg_3821 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_78_load_reg_3826 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_77_load_reg_3831 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_76_load_reg_3836 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_75_load_reg_3841 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_74_load_reg_3846 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_73_load_reg_3851 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_72_load_reg_3856 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_71_load_reg_3861 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_70_load_reg_3866 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_69_load_reg_3871 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_68_load_reg_3876 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_67_load_reg_3881 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_66_load_reg_3886 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_65_load_reg_3891 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_64_load_reg_3896 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_63_load_reg_3901 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_62_load_reg_3906 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_61_load_reg_3911 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_60_load_reg_3916 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_59_load_reg_3921 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_58_load_reg_3926 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_57_load_reg_3931 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_56_load_reg_3936 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_55_load_reg_3941 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_54_load_reg_3946 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_53_load_reg_3951 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_52_load_reg_3956 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_51_load_reg_3961 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_50_load_reg_3966 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_49_load_reg_3971 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_48_load_reg_3976 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_47_load_reg_3981 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_46_load_reg_3986 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_45_load_reg_3991 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_44_load_reg_3996 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_43_load_reg_4001 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_42_load_reg_4006 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_41_load_reg_4011 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_40_load_reg_4016 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_39_load_reg_4021 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_38_load_reg_4026 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_37_load_reg_4031 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_36_load_reg_4036 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_35_load_reg_4041 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_34_load_reg_4046 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_33_load_reg_4051 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_32_load_reg_4056 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_31_load_reg_4061 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_30_load_reg_4066 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_29_load_reg_4071 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_28_load_reg_4076 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_27_load_reg_4081 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_26_load_reg_4086 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_25_load_reg_4091 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_24_load_reg_4096 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_23_load_reg_4101 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_22_load_reg_4106 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_21_load_reg_4111 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_20_load_reg_4116 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_19_load_reg_4121 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_18_load_reg_4126 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_17_load_reg_4131 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_16_load_reg_4136 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_15_load_reg_4141 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_14_load_reg_4146 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_13_load_reg_4151 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_12_load_reg_4156 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_11_load_reg_4161 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_10_load_reg_4166 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_9_load_reg_4171 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_8_load_reg_4176 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_7_load_reg_4181 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_6_load_reg_4186 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_5_load_reg_4191 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_4_load_reg_4196 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_3_load_reg_4201 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_load_reg_4206 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_load_reg_4211 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_load_reg_4216 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_127_load_reg_4221 : STD_LOGIC_VECTOR (31 downto 0);
signal phi_mul_reg_2272 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state56 : signal is "none";
signal bufo_load_phi_reg_2296 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state46 : signal is "none";
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_126_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_125_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_124_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_123_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_122_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_121_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_120_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_119_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_118_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_117_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_116_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_115_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_114_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_113_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_112_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_111_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_110_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_109_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_108_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_107_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_106_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_105_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_104_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_103_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_102_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_101_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_100_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_99_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_98_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_97_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_96_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_95_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_94_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_93_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_92_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_91_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_90_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_89_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_88_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_87_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_86_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_85_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_84_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_83_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_82_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_81_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_80_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_79_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_78_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_77_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_76_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_75_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_74_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_73_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_72_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_71_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_70_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_69_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_68_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_67_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_66_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_65_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_64_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_63_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_62_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_61_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_60_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_59_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_58_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_57_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_56_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_55_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_54_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_53_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_52_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_51_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_50_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_49_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_48_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_47_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_46_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_45_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_44_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_43_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_42_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_41_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_40_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_39_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_38_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_37_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_36_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_35_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_34_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_33_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_32_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_31_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_30_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_29_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_28_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_27_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_26_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_25_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_24_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_23_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_22_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_21_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_20_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_19_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_18_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_17_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_16_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_15_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_14_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_13_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_12_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_11_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_10_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_9_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_8_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_7_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_127_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2558_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2558_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal ap_CS_fsm_state36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal ap_CS_fsm_state47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state47 : signal is "none";
signal grp_fu_2564_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2564_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2568_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2568_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2572_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_2576_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (55 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2558_p0,
din1 => grp_fu_2558_p1,
ce => ap_const_logic_1,
dout => grp_fu_2558_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2564_p0,
din1 => grp_fu_2564_p1,
ce => ap_const_logic_1,
dout => grp_fu_2564_p2);
convolve_kernel_fcud_U3 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2568_p0,
din1 => grp_fu_2568_p1,
ce => ap_const_logic_1,
dout => grp_fu_2568_p2);
convolve_kernel_fcud_U4 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2572_p0,
din1 => grp_fu_2572_p1,
ce => ap_const_logic_1,
dout => grp_fu_2572_p2);
convolve_kernel_fcud_U5 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_2576_p0,
din1 => grp_fu_2576_p1,
ce => ap_const_logic_1,
dout => grp_fu_2576_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
bufo_load_phi_reg_2296_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state46)) then
if ((p_s_reg_2284 = ap_const_lv7_7F)) then
bufo_load_phi_reg_2296 <= bufo_127_load_reg_4221;
elsif ((p_s_reg_2284 = ap_const_lv7_7E)) then
bufo_load_phi_reg_2296 <= bufo_126_load_reg_3586;
elsif ((p_s_reg_2284 = ap_const_lv7_7D)) then
bufo_load_phi_reg_2296 <= bufo_125_load_reg_3591;
elsif ((p_s_reg_2284 = ap_const_lv7_7C)) then
bufo_load_phi_reg_2296 <= bufo_124_load_reg_3596;
elsif ((p_s_reg_2284 = ap_const_lv7_7B)) then
bufo_load_phi_reg_2296 <= bufo_123_load_reg_3601;
elsif ((p_s_reg_2284 = ap_const_lv7_7A)) then
bufo_load_phi_reg_2296 <= bufo_122_load_reg_3606;
elsif ((p_s_reg_2284 = ap_const_lv7_79)) then
bufo_load_phi_reg_2296 <= bufo_121_load_reg_3611;
elsif ((p_s_reg_2284 = ap_const_lv7_78)) then
bufo_load_phi_reg_2296 <= bufo_120_load_reg_3616;
elsif ((p_s_reg_2284 = ap_const_lv7_77)) then
bufo_load_phi_reg_2296 <= bufo_119_load_reg_3621;
elsif ((p_s_reg_2284 = ap_const_lv7_76)) then
bufo_load_phi_reg_2296 <= bufo_118_load_reg_3626;
elsif ((p_s_reg_2284 = ap_const_lv7_75)) then
bufo_load_phi_reg_2296 <= bufo_117_load_reg_3631;
elsif ((p_s_reg_2284 = ap_const_lv7_74)) then
bufo_load_phi_reg_2296 <= bufo_116_load_reg_3636;
elsif ((p_s_reg_2284 = ap_const_lv7_73)) then
bufo_load_phi_reg_2296 <= bufo_115_load_reg_3641;
elsif ((p_s_reg_2284 = ap_const_lv7_72)) then
bufo_load_phi_reg_2296 <= bufo_114_load_reg_3646;
elsif ((p_s_reg_2284 = ap_const_lv7_71)) then
bufo_load_phi_reg_2296 <= bufo_113_load_reg_3651;
elsif ((p_s_reg_2284 = ap_const_lv7_70)) then
bufo_load_phi_reg_2296 <= bufo_112_load_reg_3656;
elsif ((p_s_reg_2284 = ap_const_lv7_6F)) then
bufo_load_phi_reg_2296 <= bufo_111_load_reg_3661;
elsif ((p_s_reg_2284 = ap_const_lv7_6E)) then
bufo_load_phi_reg_2296 <= bufo_110_load_reg_3666;
elsif ((p_s_reg_2284 = ap_const_lv7_6D)) then
bufo_load_phi_reg_2296 <= bufo_109_load_reg_3671;
elsif ((p_s_reg_2284 = ap_const_lv7_6C)) then
bufo_load_phi_reg_2296 <= bufo_108_load_reg_3676;
elsif ((p_s_reg_2284 = ap_const_lv7_6B)) then
bufo_load_phi_reg_2296 <= bufo_107_load_reg_3681;
elsif ((p_s_reg_2284 = ap_const_lv7_6A)) then
bufo_load_phi_reg_2296 <= bufo_106_load_reg_3686;
elsif ((p_s_reg_2284 = ap_const_lv7_69)) then
bufo_load_phi_reg_2296 <= bufo_105_load_reg_3691;
elsif ((p_s_reg_2284 = ap_const_lv7_68)) then
bufo_load_phi_reg_2296 <= bufo_104_load_reg_3696;
elsif ((p_s_reg_2284 = ap_const_lv7_67)) then
bufo_load_phi_reg_2296 <= bufo_103_load_reg_3701;
elsif ((p_s_reg_2284 = ap_const_lv7_66)) then
bufo_load_phi_reg_2296 <= bufo_102_load_reg_3706;
elsif ((p_s_reg_2284 = ap_const_lv7_65)) then
bufo_load_phi_reg_2296 <= bufo_101_load_reg_3711;
elsif ((p_s_reg_2284 = ap_const_lv7_64)) then
bufo_load_phi_reg_2296 <= bufo_100_load_reg_3716;
elsif ((p_s_reg_2284 = ap_const_lv7_63)) then
bufo_load_phi_reg_2296 <= bufo_99_load_reg_3721;
elsif ((p_s_reg_2284 = ap_const_lv7_62)) then
bufo_load_phi_reg_2296 <= bufo_98_load_reg_3726;
elsif ((p_s_reg_2284 = ap_const_lv7_61)) then
bufo_load_phi_reg_2296 <= bufo_97_load_reg_3731;
elsif ((p_s_reg_2284 = ap_const_lv7_60)) then
bufo_load_phi_reg_2296 <= bufo_96_load_reg_3736;
elsif ((p_s_reg_2284 = ap_const_lv7_5F)) then
bufo_load_phi_reg_2296 <= bufo_95_load_reg_3741;
elsif ((p_s_reg_2284 = ap_const_lv7_5E)) then
bufo_load_phi_reg_2296 <= bufo_94_load_reg_3746;
elsif ((p_s_reg_2284 = ap_const_lv7_5D)) then
bufo_load_phi_reg_2296 <= bufo_93_load_reg_3751;
elsif ((p_s_reg_2284 = ap_const_lv7_5C)) then
bufo_load_phi_reg_2296 <= bufo_92_load_reg_3756;
elsif ((p_s_reg_2284 = ap_const_lv7_5B)) then
bufo_load_phi_reg_2296 <= bufo_91_load_reg_3761;
elsif ((p_s_reg_2284 = ap_const_lv7_5A)) then
bufo_load_phi_reg_2296 <= bufo_90_load_reg_3766;
elsif ((p_s_reg_2284 = ap_const_lv7_59)) then
bufo_load_phi_reg_2296 <= bufo_89_load_reg_3771;
elsif ((p_s_reg_2284 = ap_const_lv7_58)) then
bufo_load_phi_reg_2296 <= bufo_88_load_reg_3776;
elsif ((p_s_reg_2284 = ap_const_lv7_57)) then
bufo_load_phi_reg_2296 <= bufo_87_load_reg_3781;
elsif ((p_s_reg_2284 = ap_const_lv7_56)) then
bufo_load_phi_reg_2296 <= bufo_86_load_reg_3786;
elsif ((p_s_reg_2284 = ap_const_lv7_55)) then
bufo_load_phi_reg_2296 <= bufo_85_load_reg_3791;
elsif ((p_s_reg_2284 = ap_const_lv7_54)) then
bufo_load_phi_reg_2296 <= bufo_84_load_reg_3796;
elsif ((p_s_reg_2284 = ap_const_lv7_53)) then
bufo_load_phi_reg_2296 <= bufo_83_load_reg_3801;
elsif ((p_s_reg_2284 = ap_const_lv7_52)) then
bufo_load_phi_reg_2296 <= bufo_82_load_reg_3806;
elsif ((p_s_reg_2284 = ap_const_lv7_51)) then
bufo_load_phi_reg_2296 <= bufo_81_load_reg_3811;
elsif ((p_s_reg_2284 = ap_const_lv7_50)) then
bufo_load_phi_reg_2296 <= bufo_80_load_reg_3816;
elsif ((p_s_reg_2284 = ap_const_lv7_4F)) then
bufo_load_phi_reg_2296 <= bufo_79_load_reg_3821;
elsif ((p_s_reg_2284 = ap_const_lv7_4E)) then
bufo_load_phi_reg_2296 <= bufo_78_load_reg_3826;
elsif ((p_s_reg_2284 = ap_const_lv7_4D)) then
bufo_load_phi_reg_2296 <= bufo_77_load_reg_3831;
elsif ((p_s_reg_2284 = ap_const_lv7_4C)) then
bufo_load_phi_reg_2296 <= bufo_76_load_reg_3836;
elsif ((p_s_reg_2284 = ap_const_lv7_4B)) then
bufo_load_phi_reg_2296 <= bufo_75_load_reg_3841;
elsif ((p_s_reg_2284 = ap_const_lv7_4A)) then
bufo_load_phi_reg_2296 <= bufo_74_load_reg_3846;
elsif ((p_s_reg_2284 = ap_const_lv7_49)) then
bufo_load_phi_reg_2296 <= bufo_73_load_reg_3851;
elsif ((p_s_reg_2284 = ap_const_lv7_48)) then
bufo_load_phi_reg_2296 <= bufo_72_load_reg_3856;
elsif ((p_s_reg_2284 = ap_const_lv7_47)) then
bufo_load_phi_reg_2296 <= bufo_71_load_reg_3861;
elsif ((p_s_reg_2284 = ap_const_lv7_46)) then
bufo_load_phi_reg_2296 <= bufo_70_load_reg_3866;
elsif ((p_s_reg_2284 = ap_const_lv7_45)) then
bufo_load_phi_reg_2296 <= bufo_69_load_reg_3871;
elsif ((p_s_reg_2284 = ap_const_lv7_44)) then
bufo_load_phi_reg_2296 <= bufo_68_load_reg_3876;
elsif ((p_s_reg_2284 = ap_const_lv7_43)) then
bufo_load_phi_reg_2296 <= bufo_67_load_reg_3881;
elsif ((p_s_reg_2284 = ap_const_lv7_42)) then
bufo_load_phi_reg_2296 <= bufo_66_load_reg_3886;
elsif ((p_s_reg_2284 = ap_const_lv7_41)) then
bufo_load_phi_reg_2296 <= bufo_65_load_reg_3891;
elsif ((p_s_reg_2284 = ap_const_lv7_40)) then
bufo_load_phi_reg_2296 <= bufo_64_load_reg_3896;
elsif ((p_s_reg_2284 = ap_const_lv7_3F)) then
bufo_load_phi_reg_2296 <= bufo_63_load_reg_3901;
elsif ((p_s_reg_2284 = ap_const_lv7_3E)) then
bufo_load_phi_reg_2296 <= bufo_62_load_reg_3906;
elsif ((p_s_reg_2284 = ap_const_lv7_3D)) then
bufo_load_phi_reg_2296 <= bufo_61_load_reg_3911;
elsif ((p_s_reg_2284 = ap_const_lv7_3C)) then
bufo_load_phi_reg_2296 <= bufo_60_load_reg_3916;
elsif ((p_s_reg_2284 = ap_const_lv7_3B)) then
bufo_load_phi_reg_2296 <= bufo_59_load_reg_3921;
elsif ((p_s_reg_2284 = ap_const_lv7_3A)) then
bufo_load_phi_reg_2296 <= bufo_58_load_reg_3926;
elsif ((p_s_reg_2284 = ap_const_lv7_39)) then
bufo_load_phi_reg_2296 <= bufo_57_load_reg_3931;
elsif ((p_s_reg_2284 = ap_const_lv7_38)) then
bufo_load_phi_reg_2296 <= bufo_56_load_reg_3936;
elsif ((p_s_reg_2284 = ap_const_lv7_37)) then
bufo_load_phi_reg_2296 <= bufo_55_load_reg_3941;
elsif ((p_s_reg_2284 = ap_const_lv7_36)) then
bufo_load_phi_reg_2296 <= bufo_54_load_reg_3946;
elsif ((p_s_reg_2284 = ap_const_lv7_35)) then
bufo_load_phi_reg_2296 <= bufo_53_load_reg_3951;
elsif ((p_s_reg_2284 = ap_const_lv7_34)) then
bufo_load_phi_reg_2296 <= bufo_52_load_reg_3956;
elsif ((p_s_reg_2284 = ap_const_lv7_33)) then
bufo_load_phi_reg_2296 <= bufo_51_load_reg_3961;
elsif ((p_s_reg_2284 = ap_const_lv7_32)) then
bufo_load_phi_reg_2296 <= bufo_50_load_reg_3966;
elsif ((p_s_reg_2284 = ap_const_lv7_31)) then
bufo_load_phi_reg_2296 <= bufo_49_load_reg_3971;
elsif ((p_s_reg_2284 = ap_const_lv7_30)) then
bufo_load_phi_reg_2296 <= bufo_48_load_reg_3976;
elsif ((p_s_reg_2284 = ap_const_lv7_2F)) then
bufo_load_phi_reg_2296 <= bufo_47_load_reg_3981;
elsif ((p_s_reg_2284 = ap_const_lv7_2E)) then
bufo_load_phi_reg_2296 <= bufo_46_load_reg_3986;
elsif ((p_s_reg_2284 = ap_const_lv7_2D)) then
bufo_load_phi_reg_2296 <= bufo_45_load_reg_3991;
elsif ((p_s_reg_2284 = ap_const_lv7_2C)) then
bufo_load_phi_reg_2296 <= bufo_44_load_reg_3996;
elsif ((p_s_reg_2284 = ap_const_lv7_2B)) then
bufo_load_phi_reg_2296 <= bufo_43_load_reg_4001;
elsif ((p_s_reg_2284 = ap_const_lv7_2A)) then
bufo_load_phi_reg_2296 <= bufo_42_load_reg_4006;
elsif ((p_s_reg_2284 = ap_const_lv7_29)) then
bufo_load_phi_reg_2296 <= bufo_41_load_reg_4011;
elsif ((p_s_reg_2284 = ap_const_lv7_28)) then
bufo_load_phi_reg_2296 <= bufo_40_load_reg_4016;
elsif ((p_s_reg_2284 = ap_const_lv7_27)) then
bufo_load_phi_reg_2296 <= bufo_39_load_reg_4021;
elsif ((p_s_reg_2284 = ap_const_lv7_26)) then
bufo_load_phi_reg_2296 <= bufo_38_load_reg_4026;
elsif ((p_s_reg_2284 = ap_const_lv7_25)) then
bufo_load_phi_reg_2296 <= bufo_37_load_reg_4031;
elsif ((p_s_reg_2284 = ap_const_lv7_24)) then
bufo_load_phi_reg_2296 <= bufo_36_load_reg_4036;
elsif ((p_s_reg_2284 = ap_const_lv7_23)) then
bufo_load_phi_reg_2296 <= bufo_35_load_reg_4041;
elsif ((p_s_reg_2284 = ap_const_lv7_22)) then
bufo_load_phi_reg_2296 <= bufo_34_load_reg_4046;
elsif ((p_s_reg_2284 = ap_const_lv7_21)) then
bufo_load_phi_reg_2296 <= bufo_33_load_reg_4051;
elsif ((p_s_reg_2284 = ap_const_lv7_20)) then
bufo_load_phi_reg_2296 <= bufo_32_load_reg_4056;
elsif ((p_s_reg_2284 = ap_const_lv7_1F)) then
bufo_load_phi_reg_2296 <= bufo_31_load_reg_4061;
elsif ((p_s_reg_2284 = ap_const_lv7_1E)) then
bufo_load_phi_reg_2296 <= bufo_30_load_reg_4066;
elsif ((p_s_reg_2284 = ap_const_lv7_1D)) then
bufo_load_phi_reg_2296 <= bufo_29_load_reg_4071;
elsif ((p_s_reg_2284 = ap_const_lv7_1C)) then
bufo_load_phi_reg_2296 <= bufo_28_load_reg_4076;
elsif ((p_s_reg_2284 = ap_const_lv7_1B)) then
bufo_load_phi_reg_2296 <= bufo_27_load_reg_4081;
elsif ((p_s_reg_2284 = ap_const_lv7_1A)) then
bufo_load_phi_reg_2296 <= bufo_26_load_reg_4086;
elsif ((p_s_reg_2284 = ap_const_lv7_19)) then
bufo_load_phi_reg_2296 <= bufo_25_load_reg_4091;
elsif ((p_s_reg_2284 = ap_const_lv7_18)) then
bufo_load_phi_reg_2296 <= bufo_24_load_reg_4096;
elsif ((p_s_reg_2284 = ap_const_lv7_17)) then
bufo_load_phi_reg_2296 <= bufo_23_load_reg_4101;
elsif ((p_s_reg_2284 = ap_const_lv7_16)) then
bufo_load_phi_reg_2296 <= bufo_22_load_reg_4106;
elsif ((p_s_reg_2284 = ap_const_lv7_15)) then
bufo_load_phi_reg_2296 <= bufo_21_load_reg_4111;
elsif ((p_s_reg_2284 = ap_const_lv7_14)) then
bufo_load_phi_reg_2296 <= bufo_20_load_reg_4116;
elsif ((p_s_reg_2284 = ap_const_lv7_13)) then
bufo_load_phi_reg_2296 <= bufo_19_load_reg_4121;
elsif ((p_s_reg_2284 = ap_const_lv7_12)) then
bufo_load_phi_reg_2296 <= bufo_18_load_reg_4126;
elsif ((p_s_reg_2284 = ap_const_lv7_11)) then
bufo_load_phi_reg_2296 <= bufo_17_load_reg_4131;
elsif ((p_s_reg_2284 = ap_const_lv7_10)) then
bufo_load_phi_reg_2296 <= bufo_16_load_reg_4136;
elsif ((p_s_reg_2284 = ap_const_lv7_F)) then
bufo_load_phi_reg_2296 <= bufo_15_load_reg_4141;
elsif ((p_s_reg_2284 = ap_const_lv7_E)) then
bufo_load_phi_reg_2296 <= bufo_14_load_reg_4146;
elsif ((p_s_reg_2284 = ap_const_lv7_D)) then
bufo_load_phi_reg_2296 <= bufo_13_load_reg_4151;
elsif ((p_s_reg_2284 = ap_const_lv7_C)) then
bufo_load_phi_reg_2296 <= bufo_12_load_reg_4156;
elsif ((p_s_reg_2284 = ap_const_lv7_B)) then
bufo_load_phi_reg_2296 <= bufo_11_load_reg_4161;
elsif ((p_s_reg_2284 = ap_const_lv7_A)) then
bufo_load_phi_reg_2296 <= bufo_10_load_reg_4166;
elsif ((p_s_reg_2284 = ap_const_lv7_9)) then
bufo_load_phi_reg_2296 <= bufo_9_load_reg_4171;
elsif ((p_s_reg_2284 = ap_const_lv7_8)) then
bufo_load_phi_reg_2296 <= bufo_8_load_reg_4176;
elsif ((p_s_reg_2284 = ap_const_lv7_7)) then
bufo_load_phi_reg_2296 <= bufo_7_load_reg_4181;
elsif ((p_s_reg_2284 = ap_const_lv7_6)) then
bufo_load_phi_reg_2296 <= bufo_6_load_reg_4186;
elsif ((p_s_reg_2284 = ap_const_lv7_5)) then
bufo_load_phi_reg_2296 <= bufo_5_load_reg_4191;
elsif ((p_s_reg_2284 = ap_const_lv7_4)) then
bufo_load_phi_reg_2296 <= bufo_4_load_reg_4196;
elsif ((p_s_reg_2284 = ap_const_lv7_3)) then
bufo_load_phi_reg_2296 <= bufo_3_load_reg_4201;
elsif ((p_s_reg_2284 = ap_const_lv7_2)) then
bufo_load_phi_reg_2296 <= bufo_2_load_reg_4206;
elsif ((p_s_reg_2284 = ap_const_lv7_1)) then
bufo_load_phi_reg_2296 <= bufo_1_load_reg_4211;
elsif ((p_s_reg_2284 = ap_const_lv7_0)) then
bufo_load_phi_reg_2296 <= bufo_0_load_reg_4216;
end if;
end if;
end if;
end process;
p_s_reg_2284_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state56)) then
p_s_reg_2284 <= to_b_V_reg_3581;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_s_reg_2284 <= ap_const_lv7_0;
end if;
end if;
end process;
phi_mul_reg_2272_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state56)) then
phi_mul_reg_2272 <= next_mul_reg_3471;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
phi_mul_reg_2272 <= ap_const_lv64_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_0))) then
bufo_0_load_reg_4216 <= bufo_0_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_64))) then
bufo_100_load_reg_3716 <= bufo_100_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_65))) then
bufo_101_load_reg_3711 <= bufo_101_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_66))) then
bufo_102_load_reg_3706 <= bufo_102_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_67))) then
bufo_103_load_reg_3701 <= bufo_103_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_68))) then
bufo_104_load_reg_3696 <= bufo_104_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_69))) then
bufo_105_load_reg_3691 <= bufo_105_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6A))) then
bufo_106_load_reg_3686 <= bufo_106_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6B))) then
bufo_107_load_reg_3681 <= bufo_107_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6C))) then
bufo_108_load_reg_3676 <= bufo_108_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6D))) then
bufo_109_load_reg_3671 <= bufo_109_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_A))) then
bufo_10_load_reg_4166 <= bufo_10_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6E))) then
bufo_110_load_reg_3666 <= bufo_110_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6F))) then
bufo_111_load_reg_3661 <= bufo_111_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_70))) then
bufo_112_load_reg_3656 <= bufo_112_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_71))) then
bufo_113_load_reg_3651 <= bufo_113_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_72))) then
bufo_114_load_reg_3646 <= bufo_114_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_73))) then
bufo_115_load_reg_3641 <= bufo_115_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_74))) then
bufo_116_load_reg_3636 <= bufo_116_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_75))) then
bufo_117_load_reg_3631 <= bufo_117_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_76))) then
bufo_118_load_reg_3626 <= bufo_118_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_77))) then
bufo_119_load_reg_3621 <= bufo_119_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_B))) then
bufo_11_load_reg_4161 <= bufo_11_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_78))) then
bufo_120_load_reg_3616 <= bufo_120_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_79))) then
bufo_121_load_reg_3611 <= bufo_121_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7A))) then
bufo_122_load_reg_3606 <= bufo_122_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7B))) then
bufo_123_load_reg_3601 <= bufo_123_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7C))) then
bufo_124_load_reg_3596 <= bufo_124_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7D))) then
bufo_125_load_reg_3591 <= bufo_125_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7E))) then
bufo_126_load_reg_3586 <= bufo_126_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7F))) then
bufo_127_load_reg_4221 <= bufo_127_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_C))) then
bufo_12_load_reg_4156 <= bufo_12_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_D))) then
bufo_13_load_reg_4151 <= bufo_13_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_E))) then
bufo_14_load_reg_4146 <= bufo_14_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_F))) then
bufo_15_load_reg_4141 <= bufo_15_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_10))) then
bufo_16_load_reg_4136 <= bufo_16_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_11))) then
bufo_17_load_reg_4131 <= bufo_17_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_12))) then
bufo_18_load_reg_4126 <= bufo_18_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_13))) then
bufo_19_load_reg_4121 <= bufo_19_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1))) then
bufo_1_load_reg_4211 <= bufo_1_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_14))) then
bufo_20_load_reg_4116 <= bufo_20_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_15))) then
bufo_21_load_reg_4111 <= bufo_21_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_16))) then
bufo_22_load_reg_4106 <= bufo_22_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_17))) then
bufo_23_load_reg_4101 <= bufo_23_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_18))) then
bufo_24_load_reg_4096 <= bufo_24_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_19))) then
bufo_25_load_reg_4091 <= bufo_25_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1A))) then
bufo_26_load_reg_4086 <= bufo_26_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1B))) then
bufo_27_load_reg_4081 <= bufo_27_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1C))) then
bufo_28_load_reg_4076 <= bufo_28_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1D))) then
bufo_29_load_reg_4071 <= bufo_29_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2))) then
bufo_2_load_reg_4206 <= bufo_2_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1E))) then
bufo_30_load_reg_4066 <= bufo_30_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_1F))) then
bufo_31_load_reg_4061 <= bufo_31_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_20))) then
bufo_32_load_reg_4056 <= bufo_32_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_21))) then
bufo_33_load_reg_4051 <= bufo_33_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_22))) then
bufo_34_load_reg_4046 <= bufo_34_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_23))) then
bufo_35_load_reg_4041 <= bufo_35_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_24))) then
bufo_36_load_reg_4036 <= bufo_36_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_25))) then
bufo_37_load_reg_4031 <= bufo_37_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_26))) then
bufo_38_load_reg_4026 <= bufo_38_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_27))) then
bufo_39_load_reg_4021 <= bufo_39_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3))) then
bufo_3_load_reg_4201 <= bufo_3_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_28))) then
bufo_40_load_reg_4016 <= bufo_40_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_29))) then
bufo_41_load_reg_4011 <= bufo_41_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2A))) then
bufo_42_load_reg_4006 <= bufo_42_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2B))) then
bufo_43_load_reg_4001 <= bufo_43_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2C))) then
bufo_44_load_reg_3996 <= bufo_44_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2D))) then
bufo_45_load_reg_3991 <= bufo_45_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2E))) then
bufo_46_load_reg_3986 <= bufo_46_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_2F))) then
bufo_47_load_reg_3981 <= bufo_47_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_30))) then
bufo_48_load_reg_3976 <= bufo_48_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_31))) then
bufo_49_load_reg_3971 <= bufo_49_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4))) then
bufo_4_load_reg_4196 <= bufo_4_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_32))) then
bufo_50_load_reg_3966 <= bufo_50_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_33))) then
bufo_51_load_reg_3961 <= bufo_51_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_34))) then
bufo_52_load_reg_3956 <= bufo_52_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_35))) then
bufo_53_load_reg_3951 <= bufo_53_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_36))) then
bufo_54_load_reg_3946 <= bufo_54_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_37))) then
bufo_55_load_reg_3941 <= bufo_55_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_38))) then
bufo_56_load_reg_3936 <= bufo_56_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_39))) then
bufo_57_load_reg_3931 <= bufo_57_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3A))) then
bufo_58_load_reg_3926 <= bufo_58_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3B))) then
bufo_59_load_reg_3921 <= bufo_59_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5))) then
bufo_5_load_reg_4191 <= bufo_5_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3C))) then
bufo_60_load_reg_3916 <= bufo_60_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3D))) then
bufo_61_load_reg_3911 <= bufo_61_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3E))) then
bufo_62_load_reg_3906 <= bufo_62_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_3F))) then
bufo_63_load_reg_3901 <= bufo_63_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_40))) then
bufo_64_load_reg_3896 <= bufo_64_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_41))) then
bufo_65_load_reg_3891 <= bufo_65_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_42))) then
bufo_66_load_reg_3886 <= bufo_66_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_43))) then
bufo_67_load_reg_3881 <= bufo_67_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_44))) then
bufo_68_load_reg_3876 <= bufo_68_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_45))) then
bufo_69_load_reg_3871 <= bufo_69_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_6))) then
bufo_6_load_reg_4186 <= bufo_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_46))) then
bufo_70_load_reg_3866 <= bufo_70_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_47))) then
bufo_71_load_reg_3861 <= bufo_71_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_48))) then
bufo_72_load_reg_3856 <= bufo_72_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_49))) then
bufo_73_load_reg_3851 <= bufo_73_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4A))) then
bufo_74_load_reg_3846 <= bufo_74_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4B))) then
bufo_75_load_reg_3841 <= bufo_75_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4C))) then
bufo_76_load_reg_3836 <= bufo_76_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4D))) then
bufo_77_load_reg_3831 <= bufo_77_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4E))) then
bufo_78_load_reg_3826 <= bufo_78_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_4F))) then
bufo_79_load_reg_3821 <= bufo_79_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_7))) then
bufo_7_load_reg_4181 <= bufo_7_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_50))) then
bufo_80_load_reg_3816 <= bufo_80_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_51))) then
bufo_81_load_reg_3811 <= bufo_81_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_52))) then
bufo_82_load_reg_3806 <= bufo_82_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_53))) then
bufo_83_load_reg_3801 <= bufo_83_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_54))) then
bufo_84_load_reg_3796 <= bufo_84_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_55))) then
bufo_85_load_reg_3791 <= bufo_85_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_56))) then
bufo_86_load_reg_3786 <= bufo_86_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_57))) then
bufo_87_load_reg_3781 <= bufo_87_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_58))) then
bufo_88_load_reg_3776 <= bufo_88_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_59))) then
bufo_89_load_reg_3771 <= bufo_89_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_8))) then
bufo_8_load_reg_4176 <= bufo_8_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5A))) then
bufo_90_load_reg_3766 <= bufo_90_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5B))) then
bufo_91_load_reg_3761 <= bufo_91_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5C))) then
bufo_92_load_reg_3756 <= bufo_92_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5D))) then
bufo_93_load_reg_3751 <= bufo_93_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5E))) then
bufo_94_load_reg_3746 <= bufo_94_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_5F))) then
bufo_95_load_reg_3741 <= bufo_95_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_60))) then
bufo_96_load_reg_3736 <= bufo_96_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_61))) then
bufo_97_load_reg_3731 <= bufo_97_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_62))) then
bufo_98_load_reg_3726 <= bufo_98_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_63))) then
bufo_99_load_reg_3721 <= bufo_99_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state45) and (p_s_reg_2284 = ap_const_lv7_9))) then
bufo_9_load_reg_4171 <= bufo_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
next_mul_reg_3471 <= next_mul_fu_2714_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state55))) then
reg_2580 <= grp_fu_2558_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
tmp_11_reg_3506 <= bufi_Dout_A(95 downto 64);
tmp_13_reg_3511 <= bufw_Dout_A(127 downto 96);
tmp_15_reg_3516 <= bufi_Dout_A(127 downto 96);
tmp_1_reg_3486 <= tmp_1_fu_2724_p1;
tmp_4_reg_3501 <= bufw_Dout_A(95 downto 64);
tmp_6_reg_3491 <= bufw_Dout_A(63 downto 32);
tmp_8_reg_3496 <= bufi_Dout_A(63 downto 32);
tmp_reg_3481 <= tmp_fu_2720_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_5_1_reg_3566 <= grp_fu_2568_p2;
tmp_5_2_reg_3571 <= grp_fu_2572_p2;
tmp_5_3_reg_3576 <= grp_fu_2576_p2;
tmp_s_reg_3561 <= grp_fu_2564_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state44)) then
to_b_V_reg_3581 <= to_b_V_fu_2820_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state39;
when ap_ST_fsm_state39 =>
ap_NS_fsm <= ap_ST_fsm_state40;
when ap_ST_fsm_state40 =>
ap_NS_fsm <= ap_ST_fsm_state41;
when ap_ST_fsm_state41 =>
ap_NS_fsm <= ap_ST_fsm_state42;
when ap_ST_fsm_state42 =>
ap_NS_fsm <= ap_ST_fsm_state43;
when ap_ST_fsm_state43 =>
ap_NS_fsm <= ap_ST_fsm_state44;
when ap_ST_fsm_state44 =>
ap_NS_fsm <= ap_ST_fsm_state45;
when ap_ST_fsm_state45 =>
ap_NS_fsm <= ap_ST_fsm_state46;
when ap_ST_fsm_state46 =>
ap_NS_fsm <= ap_ST_fsm_state47;
when ap_ST_fsm_state47 =>
ap_NS_fsm <= ap_ST_fsm_state48;
when ap_ST_fsm_state48 =>
ap_NS_fsm <= ap_ST_fsm_state49;
when ap_ST_fsm_state49 =>
ap_NS_fsm <= ap_ST_fsm_state50;
when ap_ST_fsm_state50 =>
ap_NS_fsm <= ap_ST_fsm_state51;
when ap_ST_fsm_state51 =>
ap_NS_fsm <= ap_ST_fsm_state52;
when ap_ST_fsm_state52 =>
ap_NS_fsm <= ap_ST_fsm_state53;
when ap_ST_fsm_state53 =>
ap_NS_fsm <= ap_ST_fsm_state54;
when ap_ST_fsm_state54 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when ap_ST_fsm_state55 =>
ap_NS_fsm <= ap_ST_fsm_state56;
when ap_ST_fsm_state56 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state35 <= ap_CS_fsm(34);
ap_CS_fsm_state36 <= ap_CS_fsm(35);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state44 <= ap_CS_fsm(43);
ap_CS_fsm_state45 <= ap_CS_fsm(44);
ap_CS_fsm_state46 <= ap_CS_fsm(45);
ap_CS_fsm_state47 <= ap_CS_fsm(46);
ap_CS_fsm_state55 <= ap_CS_fsm(54);
ap_CS_fsm_state56 <= ap_CS_fsm(55);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done <= ap_const_logic_0;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_const_logic_0;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_4(31-1 downto 0)))));
bufi_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv128_lc_1;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst;
bufi_WEN_A <= ap_const_lv16_0;
bufo_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_0_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_0_Clk_A <= ap_clk;
bufo_0_Din_A <= reg_2580;
bufo_0_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_0_EN_A <= ap_const_logic_1;
else
bufo_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_0_Rst_A <= ap_rst;
bufo_0_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_0) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_0_WEN_A <= ap_const_lv4_F;
else
bufo_0_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_100_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_100_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_100_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_100_Clk_A <= ap_clk;
bufo_100_Din_A <= reg_2580;
bufo_100_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_100_EN_A <= ap_const_logic_1;
else
bufo_100_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_100_Rst_A <= ap_rst;
bufo_100_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_64) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_100_WEN_A <= ap_const_lv4_F;
else
bufo_100_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_101_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_101_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_101_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_101_Clk_A <= ap_clk;
bufo_101_Din_A <= reg_2580;
bufo_101_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_101_EN_A <= ap_const_logic_1;
else
bufo_101_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_101_Rst_A <= ap_rst;
bufo_101_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_65) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_101_WEN_A <= ap_const_lv4_F;
else
bufo_101_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_102_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_102_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_102_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_102_Clk_A <= ap_clk;
bufo_102_Din_A <= reg_2580;
bufo_102_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_102_EN_A <= ap_const_logic_1;
else
bufo_102_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_102_Rst_A <= ap_rst;
bufo_102_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_66) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_102_WEN_A <= ap_const_lv4_F;
else
bufo_102_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_103_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_103_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_103_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_103_Clk_A <= ap_clk;
bufo_103_Din_A <= reg_2580;
bufo_103_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_103_EN_A <= ap_const_logic_1;
else
bufo_103_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_103_Rst_A <= ap_rst;
bufo_103_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_67) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_103_WEN_A <= ap_const_lv4_F;
else
bufo_103_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_104_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_104_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_104_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_104_Clk_A <= ap_clk;
bufo_104_Din_A <= reg_2580;
bufo_104_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_104_EN_A <= ap_const_logic_1;
else
bufo_104_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_104_Rst_A <= ap_rst;
bufo_104_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_68) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_104_WEN_A <= ap_const_lv4_F;
else
bufo_104_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_105_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_105_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_105_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_105_Clk_A <= ap_clk;
bufo_105_Din_A <= reg_2580;
bufo_105_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_105_EN_A <= ap_const_logic_1;
else
bufo_105_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_105_Rst_A <= ap_rst;
bufo_105_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_69) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_105_WEN_A <= ap_const_lv4_F;
else
bufo_105_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_106_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_106_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_106_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_106_Clk_A <= ap_clk;
bufo_106_Din_A <= reg_2580;
bufo_106_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_106_EN_A <= ap_const_logic_1;
else
bufo_106_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_106_Rst_A <= ap_rst;
bufo_106_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_106_WEN_A <= ap_const_lv4_F;
else
bufo_106_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_107_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_107_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_107_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_107_Clk_A <= ap_clk;
bufo_107_Din_A <= reg_2580;
bufo_107_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_107_EN_A <= ap_const_logic_1;
else
bufo_107_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_107_Rst_A <= ap_rst;
bufo_107_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_107_WEN_A <= ap_const_lv4_F;
else
bufo_107_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_108_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_108_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_108_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_108_Clk_A <= ap_clk;
bufo_108_Din_A <= reg_2580;
bufo_108_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_108_EN_A <= ap_const_logic_1;
else
bufo_108_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_108_Rst_A <= ap_rst;
bufo_108_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_108_WEN_A <= ap_const_lv4_F;
else
bufo_108_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_109_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_109_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_109_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_109_Clk_A <= ap_clk;
bufo_109_Din_A <= reg_2580;
bufo_109_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_109_EN_A <= ap_const_logic_1;
else
bufo_109_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_109_Rst_A <= ap_rst;
bufo_109_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_109_WEN_A <= ap_const_lv4_F;
else
bufo_109_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_10_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_10_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_10_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_10_Clk_A <= ap_clk;
bufo_10_Din_A <= reg_2580;
bufo_10_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_10_EN_A <= ap_const_logic_1;
else
bufo_10_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_10_Rst_A <= ap_rst;
bufo_10_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_10_WEN_A <= ap_const_lv4_F;
else
bufo_10_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_110_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_110_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_110_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_110_Clk_A <= ap_clk;
bufo_110_Din_A <= reg_2580;
bufo_110_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_110_EN_A <= ap_const_logic_1;
else
bufo_110_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_110_Rst_A <= ap_rst;
bufo_110_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_110_WEN_A <= ap_const_lv4_F;
else
bufo_110_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_111_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_111_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_111_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_111_Clk_A <= ap_clk;
bufo_111_Din_A <= reg_2580;
bufo_111_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_111_EN_A <= ap_const_logic_1;
else
bufo_111_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_111_Rst_A <= ap_rst;
bufo_111_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_111_WEN_A <= ap_const_lv4_F;
else
bufo_111_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_112_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_112_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_112_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_112_Clk_A <= ap_clk;
bufo_112_Din_A <= reg_2580;
bufo_112_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_112_EN_A <= ap_const_logic_1;
else
bufo_112_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_112_Rst_A <= ap_rst;
bufo_112_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_70) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_112_WEN_A <= ap_const_lv4_F;
else
bufo_112_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_113_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_113_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_113_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_113_Clk_A <= ap_clk;
bufo_113_Din_A <= reg_2580;
bufo_113_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_113_EN_A <= ap_const_logic_1;
else
bufo_113_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_113_Rst_A <= ap_rst;
bufo_113_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_71) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_113_WEN_A <= ap_const_lv4_F;
else
bufo_113_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_114_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_114_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_114_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_114_Clk_A <= ap_clk;
bufo_114_Din_A <= reg_2580;
bufo_114_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_114_EN_A <= ap_const_logic_1;
else
bufo_114_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_114_Rst_A <= ap_rst;
bufo_114_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_72) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_114_WEN_A <= ap_const_lv4_F;
else
bufo_114_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_115_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_115_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_115_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_115_Clk_A <= ap_clk;
bufo_115_Din_A <= reg_2580;
bufo_115_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_115_EN_A <= ap_const_logic_1;
else
bufo_115_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_115_Rst_A <= ap_rst;
bufo_115_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_73) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_115_WEN_A <= ap_const_lv4_F;
else
bufo_115_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_116_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_116_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_116_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_116_Clk_A <= ap_clk;
bufo_116_Din_A <= reg_2580;
bufo_116_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_116_EN_A <= ap_const_logic_1;
else
bufo_116_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_116_Rst_A <= ap_rst;
bufo_116_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_74) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_116_WEN_A <= ap_const_lv4_F;
else
bufo_116_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_117_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_117_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_117_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_117_Clk_A <= ap_clk;
bufo_117_Din_A <= reg_2580;
bufo_117_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_117_EN_A <= ap_const_logic_1;
else
bufo_117_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_117_Rst_A <= ap_rst;
bufo_117_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_75) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_117_WEN_A <= ap_const_lv4_F;
else
bufo_117_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_118_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_118_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_118_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_118_Clk_A <= ap_clk;
bufo_118_Din_A <= reg_2580;
bufo_118_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_118_EN_A <= ap_const_logic_1;
else
bufo_118_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_118_Rst_A <= ap_rst;
bufo_118_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_76) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_118_WEN_A <= ap_const_lv4_F;
else
bufo_118_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_119_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_119_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_119_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_119_Clk_A <= ap_clk;
bufo_119_Din_A <= reg_2580;
bufo_119_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_119_EN_A <= ap_const_logic_1;
else
bufo_119_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_119_Rst_A <= ap_rst;
bufo_119_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_77) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_119_WEN_A <= ap_const_lv4_F;
else
bufo_119_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_11_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_11_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_11_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_11_Clk_A <= ap_clk;
bufo_11_Din_A <= reg_2580;
bufo_11_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_11_EN_A <= ap_const_logic_1;
else
bufo_11_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_11_Rst_A <= ap_rst;
bufo_11_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_11_WEN_A <= ap_const_lv4_F;
else
bufo_11_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_120_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_120_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_120_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_120_Clk_A <= ap_clk;
bufo_120_Din_A <= reg_2580;
bufo_120_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_120_EN_A <= ap_const_logic_1;
else
bufo_120_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_120_Rst_A <= ap_rst;
bufo_120_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_78) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_120_WEN_A <= ap_const_lv4_F;
else
bufo_120_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_121_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_121_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_121_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_121_Clk_A <= ap_clk;
bufo_121_Din_A <= reg_2580;
bufo_121_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_121_EN_A <= ap_const_logic_1;
else
bufo_121_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_121_Rst_A <= ap_rst;
bufo_121_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_79) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_121_WEN_A <= ap_const_lv4_F;
else
bufo_121_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_122_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_122_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_122_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_122_Clk_A <= ap_clk;
bufo_122_Din_A <= reg_2580;
bufo_122_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_122_EN_A <= ap_const_logic_1;
else
bufo_122_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_122_Rst_A <= ap_rst;
bufo_122_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_122_WEN_A <= ap_const_lv4_F;
else
bufo_122_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_123_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_123_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_123_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_123_Clk_A <= ap_clk;
bufo_123_Din_A <= reg_2580;
bufo_123_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_123_EN_A <= ap_const_logic_1;
else
bufo_123_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_123_Rst_A <= ap_rst;
bufo_123_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_123_WEN_A <= ap_const_lv4_F;
else
bufo_123_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_124_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_124_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_124_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_124_Clk_A <= ap_clk;
bufo_124_Din_A <= reg_2580;
bufo_124_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_124_EN_A <= ap_const_logic_1;
else
bufo_124_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_124_Rst_A <= ap_rst;
bufo_124_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_124_WEN_A <= ap_const_lv4_F;
else
bufo_124_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_125_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_125_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_125_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_125_Clk_A <= ap_clk;
bufo_125_Din_A <= reg_2580;
bufo_125_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_125_EN_A <= ap_const_logic_1;
else
bufo_125_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_125_Rst_A <= ap_rst;
bufo_125_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_125_WEN_A <= ap_const_lv4_F;
else
bufo_125_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_126_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_126_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_126_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_126_Clk_A <= ap_clk;
bufo_126_Din_A <= reg_2580;
bufo_126_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_126_EN_A <= ap_const_logic_1;
else
bufo_126_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_126_Rst_A <= ap_rst;
bufo_126_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_126_WEN_A <= ap_const_lv4_F;
else
bufo_126_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_127_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_127_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_127_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_127_Clk_A <= ap_clk;
bufo_127_Din_A <= reg_2580;
bufo_127_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_127_EN_A <= ap_const_logic_1;
else
bufo_127_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_127_Rst_A <= ap_rst;
bufo_127_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_127_WEN_A <= ap_const_lv4_F;
else
bufo_127_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_128_Addr_A <= ap_const_lv32_0;
bufo_128_Addr_B <= ap_const_lv32_0;
bufo_128_Clk_A <= ap_clk;
bufo_128_Clk_B <= ap_clk;
bufo_128_Din_A <= ap_const_lv32_0;
bufo_128_Din_B <= ap_const_lv32_0;
bufo_128_EN_A <= ap_const_logic_0;
bufo_128_EN_B <= ap_const_logic_0;
bufo_128_Rst_A <= ap_rst;
bufo_128_Rst_B <= ap_rst;
bufo_128_WEN_A <= ap_const_lv4_0;
bufo_128_WEN_B <= ap_const_lv4_0;
bufo_129_Addr_A <= ap_const_lv32_0;
bufo_129_Addr_B <= ap_const_lv32_0;
bufo_129_Clk_A <= ap_clk;
bufo_129_Clk_B <= ap_clk;
bufo_129_Din_A <= ap_const_lv32_0;
bufo_129_Din_B <= ap_const_lv32_0;
bufo_129_EN_A <= ap_const_logic_0;
bufo_129_EN_B <= ap_const_logic_0;
bufo_129_Rst_A <= ap_rst;
bufo_129_Rst_B <= ap_rst;
bufo_129_WEN_A <= ap_const_lv4_0;
bufo_129_WEN_B <= ap_const_lv4_0;
bufo_12_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_12_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_12_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_12_Clk_A <= ap_clk;
bufo_12_Din_A <= reg_2580;
bufo_12_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_12_EN_A <= ap_const_logic_1;
else
bufo_12_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_12_Rst_A <= ap_rst;
bufo_12_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_12_WEN_A <= ap_const_lv4_F;
else
bufo_12_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_130_Addr_A <= ap_const_lv32_0;
bufo_130_Addr_B <= ap_const_lv32_0;
bufo_130_Clk_A <= ap_clk;
bufo_130_Clk_B <= ap_clk;
bufo_130_Din_A <= ap_const_lv32_0;
bufo_130_Din_B <= ap_const_lv32_0;
bufo_130_EN_A <= ap_const_logic_0;
bufo_130_EN_B <= ap_const_logic_0;
bufo_130_Rst_A <= ap_rst;
bufo_130_Rst_B <= ap_rst;
bufo_130_WEN_A <= ap_const_lv4_0;
bufo_130_WEN_B <= ap_const_lv4_0;
bufo_131_Addr_A <= ap_const_lv32_0;
bufo_131_Addr_B <= ap_const_lv32_0;
bufo_131_Clk_A <= ap_clk;
bufo_131_Clk_B <= ap_clk;
bufo_131_Din_A <= ap_const_lv32_0;
bufo_131_Din_B <= ap_const_lv32_0;
bufo_131_EN_A <= ap_const_logic_0;
bufo_131_EN_B <= ap_const_logic_0;
bufo_131_Rst_A <= ap_rst;
bufo_131_Rst_B <= ap_rst;
bufo_131_WEN_A <= ap_const_lv4_0;
bufo_131_WEN_B <= ap_const_lv4_0;
bufo_132_Addr_A <= ap_const_lv32_0;
bufo_132_Addr_B <= ap_const_lv32_0;
bufo_132_Clk_A <= ap_clk;
bufo_132_Clk_B <= ap_clk;
bufo_132_Din_A <= ap_const_lv32_0;
bufo_132_Din_B <= ap_const_lv32_0;
bufo_132_EN_A <= ap_const_logic_0;
bufo_132_EN_B <= ap_const_logic_0;
bufo_132_Rst_A <= ap_rst;
bufo_132_Rst_B <= ap_rst;
bufo_132_WEN_A <= ap_const_lv4_0;
bufo_132_WEN_B <= ap_const_lv4_0;
bufo_133_Addr_A <= ap_const_lv32_0;
bufo_133_Addr_B <= ap_const_lv32_0;
bufo_133_Clk_A <= ap_clk;
bufo_133_Clk_B <= ap_clk;
bufo_133_Din_A <= ap_const_lv32_0;
bufo_133_Din_B <= ap_const_lv32_0;
bufo_133_EN_A <= ap_const_logic_0;
bufo_133_EN_B <= ap_const_logic_0;
bufo_133_Rst_A <= ap_rst;
bufo_133_Rst_B <= ap_rst;
bufo_133_WEN_A <= ap_const_lv4_0;
bufo_133_WEN_B <= ap_const_lv4_0;
bufo_134_Addr_A <= ap_const_lv32_0;
bufo_134_Addr_B <= ap_const_lv32_0;
bufo_134_Clk_A <= ap_clk;
bufo_134_Clk_B <= ap_clk;
bufo_134_Din_A <= ap_const_lv32_0;
bufo_134_Din_B <= ap_const_lv32_0;
bufo_134_EN_A <= ap_const_logic_0;
bufo_134_EN_B <= ap_const_logic_0;
bufo_134_Rst_A <= ap_rst;
bufo_134_Rst_B <= ap_rst;
bufo_134_WEN_A <= ap_const_lv4_0;
bufo_134_WEN_B <= ap_const_lv4_0;
bufo_135_Addr_A <= ap_const_lv32_0;
bufo_135_Addr_B <= ap_const_lv32_0;
bufo_135_Clk_A <= ap_clk;
bufo_135_Clk_B <= ap_clk;
bufo_135_Din_A <= ap_const_lv32_0;
bufo_135_Din_B <= ap_const_lv32_0;
bufo_135_EN_A <= ap_const_logic_0;
bufo_135_EN_B <= ap_const_logic_0;
bufo_135_Rst_A <= ap_rst;
bufo_135_Rst_B <= ap_rst;
bufo_135_WEN_A <= ap_const_lv4_0;
bufo_135_WEN_B <= ap_const_lv4_0;
bufo_136_Addr_A <= ap_const_lv32_0;
bufo_136_Addr_B <= ap_const_lv32_0;
bufo_136_Clk_A <= ap_clk;
bufo_136_Clk_B <= ap_clk;
bufo_136_Din_A <= ap_const_lv32_0;
bufo_136_Din_B <= ap_const_lv32_0;
bufo_136_EN_A <= ap_const_logic_0;
bufo_136_EN_B <= ap_const_logic_0;
bufo_136_Rst_A <= ap_rst;
bufo_136_Rst_B <= ap_rst;
bufo_136_WEN_A <= ap_const_lv4_0;
bufo_136_WEN_B <= ap_const_lv4_0;
bufo_137_Addr_A <= ap_const_lv32_0;
bufo_137_Addr_B <= ap_const_lv32_0;
bufo_137_Clk_A <= ap_clk;
bufo_137_Clk_B <= ap_clk;
bufo_137_Din_A <= ap_const_lv32_0;
bufo_137_Din_B <= ap_const_lv32_0;
bufo_137_EN_A <= ap_const_logic_0;
bufo_137_EN_B <= ap_const_logic_0;
bufo_137_Rst_A <= ap_rst;
bufo_137_Rst_B <= ap_rst;
bufo_137_WEN_A <= ap_const_lv4_0;
bufo_137_WEN_B <= ap_const_lv4_0;
bufo_138_Addr_A <= ap_const_lv32_0;
bufo_138_Addr_B <= ap_const_lv32_0;
bufo_138_Clk_A <= ap_clk;
bufo_138_Clk_B <= ap_clk;
bufo_138_Din_A <= ap_const_lv32_0;
bufo_138_Din_B <= ap_const_lv32_0;
bufo_138_EN_A <= ap_const_logic_0;
bufo_138_EN_B <= ap_const_logic_0;
bufo_138_Rst_A <= ap_rst;
bufo_138_Rst_B <= ap_rst;
bufo_138_WEN_A <= ap_const_lv4_0;
bufo_138_WEN_B <= ap_const_lv4_0;
bufo_139_Addr_A <= ap_const_lv32_0;
bufo_139_Addr_B <= ap_const_lv32_0;
bufo_139_Clk_A <= ap_clk;
bufo_139_Clk_B <= ap_clk;
bufo_139_Din_A <= ap_const_lv32_0;
bufo_139_Din_B <= ap_const_lv32_0;
bufo_139_EN_A <= ap_const_logic_0;
bufo_139_EN_B <= ap_const_logic_0;
bufo_139_Rst_A <= ap_rst;
bufo_139_Rst_B <= ap_rst;
bufo_139_WEN_A <= ap_const_lv4_0;
bufo_139_WEN_B <= ap_const_lv4_0;
bufo_13_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_13_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_13_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_13_Clk_A <= ap_clk;
bufo_13_Din_A <= reg_2580;
bufo_13_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_13_EN_A <= ap_const_logic_1;
else
bufo_13_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_13_Rst_A <= ap_rst;
bufo_13_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_13_WEN_A <= ap_const_lv4_F;
else
bufo_13_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_140_Addr_A <= ap_const_lv32_0;
bufo_140_Addr_B <= ap_const_lv32_0;
bufo_140_Clk_A <= ap_clk;
bufo_140_Clk_B <= ap_clk;
bufo_140_Din_A <= ap_const_lv32_0;
bufo_140_Din_B <= ap_const_lv32_0;
bufo_140_EN_A <= ap_const_logic_0;
bufo_140_EN_B <= ap_const_logic_0;
bufo_140_Rst_A <= ap_rst;
bufo_140_Rst_B <= ap_rst;
bufo_140_WEN_A <= ap_const_lv4_0;
bufo_140_WEN_B <= ap_const_lv4_0;
bufo_141_Addr_A <= ap_const_lv32_0;
bufo_141_Addr_B <= ap_const_lv32_0;
bufo_141_Clk_A <= ap_clk;
bufo_141_Clk_B <= ap_clk;
bufo_141_Din_A <= ap_const_lv32_0;
bufo_141_Din_B <= ap_const_lv32_0;
bufo_141_EN_A <= ap_const_logic_0;
bufo_141_EN_B <= ap_const_logic_0;
bufo_141_Rst_A <= ap_rst;
bufo_141_Rst_B <= ap_rst;
bufo_141_WEN_A <= ap_const_lv4_0;
bufo_141_WEN_B <= ap_const_lv4_0;
bufo_142_Addr_A <= ap_const_lv32_0;
bufo_142_Addr_B <= ap_const_lv32_0;
bufo_142_Clk_A <= ap_clk;
bufo_142_Clk_B <= ap_clk;
bufo_142_Din_A <= ap_const_lv32_0;
bufo_142_Din_B <= ap_const_lv32_0;
bufo_142_EN_A <= ap_const_logic_0;
bufo_142_EN_B <= ap_const_logic_0;
bufo_142_Rst_A <= ap_rst;
bufo_142_Rst_B <= ap_rst;
bufo_142_WEN_A <= ap_const_lv4_0;
bufo_142_WEN_B <= ap_const_lv4_0;
bufo_143_Addr_A <= ap_const_lv32_0;
bufo_143_Addr_B <= ap_const_lv32_0;
bufo_143_Clk_A <= ap_clk;
bufo_143_Clk_B <= ap_clk;
bufo_143_Din_A <= ap_const_lv32_0;
bufo_143_Din_B <= ap_const_lv32_0;
bufo_143_EN_A <= ap_const_logic_0;
bufo_143_EN_B <= ap_const_logic_0;
bufo_143_Rst_A <= ap_rst;
bufo_143_Rst_B <= ap_rst;
bufo_143_WEN_A <= ap_const_lv4_0;
bufo_143_WEN_B <= ap_const_lv4_0;
bufo_144_Addr_A <= ap_const_lv32_0;
bufo_144_Addr_B <= ap_const_lv32_0;
bufo_144_Clk_A <= ap_clk;
bufo_144_Clk_B <= ap_clk;
bufo_144_Din_A <= ap_const_lv32_0;
bufo_144_Din_B <= ap_const_lv32_0;
bufo_144_EN_A <= ap_const_logic_0;
bufo_144_EN_B <= ap_const_logic_0;
bufo_144_Rst_A <= ap_rst;
bufo_144_Rst_B <= ap_rst;
bufo_144_WEN_A <= ap_const_lv4_0;
bufo_144_WEN_B <= ap_const_lv4_0;
bufo_145_Addr_A <= ap_const_lv32_0;
bufo_145_Addr_B <= ap_const_lv32_0;
bufo_145_Clk_A <= ap_clk;
bufo_145_Clk_B <= ap_clk;
bufo_145_Din_A <= ap_const_lv32_0;
bufo_145_Din_B <= ap_const_lv32_0;
bufo_145_EN_A <= ap_const_logic_0;
bufo_145_EN_B <= ap_const_logic_0;
bufo_145_Rst_A <= ap_rst;
bufo_145_Rst_B <= ap_rst;
bufo_145_WEN_A <= ap_const_lv4_0;
bufo_145_WEN_B <= ap_const_lv4_0;
bufo_146_Addr_A <= ap_const_lv32_0;
bufo_146_Addr_B <= ap_const_lv32_0;
bufo_146_Clk_A <= ap_clk;
bufo_146_Clk_B <= ap_clk;
bufo_146_Din_A <= ap_const_lv32_0;
bufo_146_Din_B <= ap_const_lv32_0;
bufo_146_EN_A <= ap_const_logic_0;
bufo_146_EN_B <= ap_const_logic_0;
bufo_146_Rst_A <= ap_rst;
bufo_146_Rst_B <= ap_rst;
bufo_146_WEN_A <= ap_const_lv4_0;
bufo_146_WEN_B <= ap_const_lv4_0;
bufo_147_Addr_A <= ap_const_lv32_0;
bufo_147_Addr_B <= ap_const_lv32_0;
bufo_147_Clk_A <= ap_clk;
bufo_147_Clk_B <= ap_clk;
bufo_147_Din_A <= ap_const_lv32_0;
bufo_147_Din_B <= ap_const_lv32_0;
bufo_147_EN_A <= ap_const_logic_0;
bufo_147_EN_B <= ap_const_logic_0;
bufo_147_Rst_A <= ap_rst;
bufo_147_Rst_B <= ap_rst;
bufo_147_WEN_A <= ap_const_lv4_0;
bufo_147_WEN_B <= ap_const_lv4_0;
bufo_148_Addr_A <= ap_const_lv32_0;
bufo_148_Addr_B <= ap_const_lv32_0;
bufo_148_Clk_A <= ap_clk;
bufo_148_Clk_B <= ap_clk;
bufo_148_Din_A <= ap_const_lv32_0;
bufo_148_Din_B <= ap_const_lv32_0;
bufo_148_EN_A <= ap_const_logic_0;
bufo_148_EN_B <= ap_const_logic_0;
bufo_148_Rst_A <= ap_rst;
bufo_148_Rst_B <= ap_rst;
bufo_148_WEN_A <= ap_const_lv4_0;
bufo_148_WEN_B <= ap_const_lv4_0;
bufo_149_Addr_A <= ap_const_lv32_0;
bufo_149_Addr_B <= ap_const_lv32_0;
bufo_149_Clk_A <= ap_clk;
bufo_149_Clk_B <= ap_clk;
bufo_149_Din_A <= ap_const_lv32_0;
bufo_149_Din_B <= ap_const_lv32_0;
bufo_149_EN_A <= ap_const_logic_0;
bufo_149_EN_B <= ap_const_logic_0;
bufo_149_Rst_A <= ap_rst;
bufo_149_Rst_B <= ap_rst;
bufo_149_WEN_A <= ap_const_lv4_0;
bufo_149_WEN_B <= ap_const_lv4_0;
bufo_14_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_14_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_14_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_14_Clk_A <= ap_clk;
bufo_14_Din_A <= reg_2580;
bufo_14_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_14_EN_A <= ap_const_logic_1;
else
bufo_14_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_14_Rst_A <= ap_rst;
bufo_14_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_14_WEN_A <= ap_const_lv4_F;
else
bufo_14_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_150_Addr_A <= ap_const_lv32_0;
bufo_150_Addr_B <= ap_const_lv32_0;
bufo_150_Clk_A <= ap_clk;
bufo_150_Clk_B <= ap_clk;
bufo_150_Din_A <= ap_const_lv32_0;
bufo_150_Din_B <= ap_const_lv32_0;
bufo_150_EN_A <= ap_const_logic_0;
bufo_150_EN_B <= ap_const_logic_0;
bufo_150_Rst_A <= ap_rst;
bufo_150_Rst_B <= ap_rst;
bufo_150_WEN_A <= ap_const_lv4_0;
bufo_150_WEN_B <= ap_const_lv4_0;
bufo_151_Addr_A <= ap_const_lv32_0;
bufo_151_Addr_B <= ap_const_lv32_0;
bufo_151_Clk_A <= ap_clk;
bufo_151_Clk_B <= ap_clk;
bufo_151_Din_A <= ap_const_lv32_0;
bufo_151_Din_B <= ap_const_lv32_0;
bufo_151_EN_A <= ap_const_logic_0;
bufo_151_EN_B <= ap_const_logic_0;
bufo_151_Rst_A <= ap_rst;
bufo_151_Rst_B <= ap_rst;
bufo_151_WEN_A <= ap_const_lv4_0;
bufo_151_WEN_B <= ap_const_lv4_0;
bufo_152_Addr_A <= ap_const_lv32_0;
bufo_152_Addr_B <= ap_const_lv32_0;
bufo_152_Clk_A <= ap_clk;
bufo_152_Clk_B <= ap_clk;
bufo_152_Din_A <= ap_const_lv32_0;
bufo_152_Din_B <= ap_const_lv32_0;
bufo_152_EN_A <= ap_const_logic_0;
bufo_152_EN_B <= ap_const_logic_0;
bufo_152_Rst_A <= ap_rst;
bufo_152_Rst_B <= ap_rst;
bufo_152_WEN_A <= ap_const_lv4_0;
bufo_152_WEN_B <= ap_const_lv4_0;
bufo_153_Addr_A <= ap_const_lv32_0;
bufo_153_Addr_B <= ap_const_lv32_0;
bufo_153_Clk_A <= ap_clk;
bufo_153_Clk_B <= ap_clk;
bufo_153_Din_A <= ap_const_lv32_0;
bufo_153_Din_B <= ap_const_lv32_0;
bufo_153_EN_A <= ap_const_logic_0;
bufo_153_EN_B <= ap_const_logic_0;
bufo_153_Rst_A <= ap_rst;
bufo_153_Rst_B <= ap_rst;
bufo_153_WEN_A <= ap_const_lv4_0;
bufo_153_WEN_B <= ap_const_lv4_0;
bufo_154_Addr_A <= ap_const_lv32_0;
bufo_154_Addr_B <= ap_const_lv32_0;
bufo_154_Clk_A <= ap_clk;
bufo_154_Clk_B <= ap_clk;
bufo_154_Din_A <= ap_const_lv32_0;
bufo_154_Din_B <= ap_const_lv32_0;
bufo_154_EN_A <= ap_const_logic_0;
bufo_154_EN_B <= ap_const_logic_0;
bufo_154_Rst_A <= ap_rst;
bufo_154_Rst_B <= ap_rst;
bufo_154_WEN_A <= ap_const_lv4_0;
bufo_154_WEN_B <= ap_const_lv4_0;
bufo_155_Addr_A <= ap_const_lv32_0;
bufo_155_Addr_B <= ap_const_lv32_0;
bufo_155_Clk_A <= ap_clk;
bufo_155_Clk_B <= ap_clk;
bufo_155_Din_A <= ap_const_lv32_0;
bufo_155_Din_B <= ap_const_lv32_0;
bufo_155_EN_A <= ap_const_logic_0;
bufo_155_EN_B <= ap_const_logic_0;
bufo_155_Rst_A <= ap_rst;
bufo_155_Rst_B <= ap_rst;
bufo_155_WEN_A <= ap_const_lv4_0;
bufo_155_WEN_B <= ap_const_lv4_0;
bufo_156_Addr_A <= ap_const_lv32_0;
bufo_156_Addr_B <= ap_const_lv32_0;
bufo_156_Clk_A <= ap_clk;
bufo_156_Clk_B <= ap_clk;
bufo_156_Din_A <= ap_const_lv32_0;
bufo_156_Din_B <= ap_const_lv32_0;
bufo_156_EN_A <= ap_const_logic_0;
bufo_156_EN_B <= ap_const_logic_0;
bufo_156_Rst_A <= ap_rst;
bufo_156_Rst_B <= ap_rst;
bufo_156_WEN_A <= ap_const_lv4_0;
bufo_156_WEN_B <= ap_const_lv4_0;
bufo_157_Addr_A <= ap_const_lv32_0;
bufo_157_Addr_B <= ap_const_lv32_0;
bufo_157_Clk_A <= ap_clk;
bufo_157_Clk_B <= ap_clk;
bufo_157_Din_A <= ap_const_lv32_0;
bufo_157_Din_B <= ap_const_lv32_0;
bufo_157_EN_A <= ap_const_logic_0;
bufo_157_EN_B <= ap_const_logic_0;
bufo_157_Rst_A <= ap_rst;
bufo_157_Rst_B <= ap_rst;
bufo_157_WEN_A <= ap_const_lv4_0;
bufo_157_WEN_B <= ap_const_lv4_0;
bufo_158_Addr_A <= ap_const_lv32_0;
bufo_158_Addr_B <= ap_const_lv32_0;
bufo_158_Clk_A <= ap_clk;
bufo_158_Clk_B <= ap_clk;
bufo_158_Din_A <= ap_const_lv32_0;
bufo_158_Din_B <= ap_const_lv32_0;
bufo_158_EN_A <= ap_const_logic_0;
bufo_158_EN_B <= ap_const_logic_0;
bufo_158_Rst_A <= ap_rst;
bufo_158_Rst_B <= ap_rst;
bufo_158_WEN_A <= ap_const_lv4_0;
bufo_158_WEN_B <= ap_const_lv4_0;
bufo_159_Addr_A <= ap_const_lv32_0;
bufo_159_Addr_B <= ap_const_lv32_0;
bufo_159_Clk_A <= ap_clk;
bufo_159_Clk_B <= ap_clk;
bufo_159_Din_A <= ap_const_lv32_0;
bufo_159_Din_B <= ap_const_lv32_0;
bufo_159_EN_A <= ap_const_logic_0;
bufo_159_EN_B <= ap_const_logic_0;
bufo_159_Rst_A <= ap_rst;
bufo_159_Rst_B <= ap_rst;
bufo_159_WEN_A <= ap_const_lv4_0;
bufo_159_WEN_B <= ap_const_lv4_0;
bufo_15_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_15_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_15_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_15_Clk_A <= ap_clk;
bufo_15_Din_A <= reg_2580;
bufo_15_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_15_EN_A <= ap_const_logic_1;
else
bufo_15_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_15_Rst_A <= ap_rst;
bufo_15_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_15_WEN_A <= ap_const_lv4_F;
else
bufo_15_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_160_Addr_A <= ap_const_lv32_0;
bufo_160_Addr_B <= ap_const_lv32_0;
bufo_160_Clk_A <= ap_clk;
bufo_160_Clk_B <= ap_clk;
bufo_160_Din_A <= ap_const_lv32_0;
bufo_160_Din_B <= ap_const_lv32_0;
bufo_160_EN_A <= ap_const_logic_0;
bufo_160_EN_B <= ap_const_logic_0;
bufo_160_Rst_A <= ap_rst;
bufo_160_Rst_B <= ap_rst;
bufo_160_WEN_A <= ap_const_lv4_0;
bufo_160_WEN_B <= ap_const_lv4_0;
bufo_161_Addr_A <= ap_const_lv32_0;
bufo_161_Addr_B <= ap_const_lv32_0;
bufo_161_Clk_A <= ap_clk;
bufo_161_Clk_B <= ap_clk;
bufo_161_Din_A <= ap_const_lv32_0;
bufo_161_Din_B <= ap_const_lv32_0;
bufo_161_EN_A <= ap_const_logic_0;
bufo_161_EN_B <= ap_const_logic_0;
bufo_161_Rst_A <= ap_rst;
bufo_161_Rst_B <= ap_rst;
bufo_161_WEN_A <= ap_const_lv4_0;
bufo_161_WEN_B <= ap_const_lv4_0;
bufo_162_Addr_A <= ap_const_lv32_0;
bufo_162_Addr_B <= ap_const_lv32_0;
bufo_162_Clk_A <= ap_clk;
bufo_162_Clk_B <= ap_clk;
bufo_162_Din_A <= ap_const_lv32_0;
bufo_162_Din_B <= ap_const_lv32_0;
bufo_162_EN_A <= ap_const_logic_0;
bufo_162_EN_B <= ap_const_logic_0;
bufo_162_Rst_A <= ap_rst;
bufo_162_Rst_B <= ap_rst;
bufo_162_WEN_A <= ap_const_lv4_0;
bufo_162_WEN_B <= ap_const_lv4_0;
bufo_163_Addr_A <= ap_const_lv32_0;
bufo_163_Addr_B <= ap_const_lv32_0;
bufo_163_Clk_A <= ap_clk;
bufo_163_Clk_B <= ap_clk;
bufo_163_Din_A <= ap_const_lv32_0;
bufo_163_Din_B <= ap_const_lv32_0;
bufo_163_EN_A <= ap_const_logic_0;
bufo_163_EN_B <= ap_const_logic_0;
bufo_163_Rst_A <= ap_rst;
bufo_163_Rst_B <= ap_rst;
bufo_163_WEN_A <= ap_const_lv4_0;
bufo_163_WEN_B <= ap_const_lv4_0;
bufo_164_Addr_A <= ap_const_lv32_0;
bufo_164_Addr_B <= ap_const_lv32_0;
bufo_164_Clk_A <= ap_clk;
bufo_164_Clk_B <= ap_clk;
bufo_164_Din_A <= ap_const_lv32_0;
bufo_164_Din_B <= ap_const_lv32_0;
bufo_164_EN_A <= ap_const_logic_0;
bufo_164_EN_B <= ap_const_logic_0;
bufo_164_Rst_A <= ap_rst;
bufo_164_Rst_B <= ap_rst;
bufo_164_WEN_A <= ap_const_lv4_0;
bufo_164_WEN_B <= ap_const_lv4_0;
bufo_165_Addr_A <= ap_const_lv32_0;
bufo_165_Addr_B <= ap_const_lv32_0;
bufo_165_Clk_A <= ap_clk;
bufo_165_Clk_B <= ap_clk;
bufo_165_Din_A <= ap_const_lv32_0;
bufo_165_Din_B <= ap_const_lv32_0;
bufo_165_EN_A <= ap_const_logic_0;
bufo_165_EN_B <= ap_const_logic_0;
bufo_165_Rst_A <= ap_rst;
bufo_165_Rst_B <= ap_rst;
bufo_165_WEN_A <= ap_const_lv4_0;
bufo_165_WEN_B <= ap_const_lv4_0;
bufo_166_Addr_A <= ap_const_lv32_0;
bufo_166_Addr_B <= ap_const_lv32_0;
bufo_166_Clk_A <= ap_clk;
bufo_166_Clk_B <= ap_clk;
bufo_166_Din_A <= ap_const_lv32_0;
bufo_166_Din_B <= ap_const_lv32_0;
bufo_166_EN_A <= ap_const_logic_0;
bufo_166_EN_B <= ap_const_logic_0;
bufo_166_Rst_A <= ap_rst;
bufo_166_Rst_B <= ap_rst;
bufo_166_WEN_A <= ap_const_lv4_0;
bufo_166_WEN_B <= ap_const_lv4_0;
bufo_167_Addr_A <= ap_const_lv32_0;
bufo_167_Addr_B <= ap_const_lv32_0;
bufo_167_Clk_A <= ap_clk;
bufo_167_Clk_B <= ap_clk;
bufo_167_Din_A <= ap_const_lv32_0;
bufo_167_Din_B <= ap_const_lv32_0;
bufo_167_EN_A <= ap_const_logic_0;
bufo_167_EN_B <= ap_const_logic_0;
bufo_167_Rst_A <= ap_rst;
bufo_167_Rst_B <= ap_rst;
bufo_167_WEN_A <= ap_const_lv4_0;
bufo_167_WEN_B <= ap_const_lv4_0;
bufo_168_Addr_A <= ap_const_lv32_0;
bufo_168_Addr_B <= ap_const_lv32_0;
bufo_168_Clk_A <= ap_clk;
bufo_168_Clk_B <= ap_clk;
bufo_168_Din_A <= ap_const_lv32_0;
bufo_168_Din_B <= ap_const_lv32_0;
bufo_168_EN_A <= ap_const_logic_0;
bufo_168_EN_B <= ap_const_logic_0;
bufo_168_Rst_A <= ap_rst;
bufo_168_Rst_B <= ap_rst;
bufo_168_WEN_A <= ap_const_lv4_0;
bufo_168_WEN_B <= ap_const_lv4_0;
bufo_169_Addr_A <= ap_const_lv32_0;
bufo_169_Addr_B <= ap_const_lv32_0;
bufo_169_Clk_A <= ap_clk;
bufo_169_Clk_B <= ap_clk;
bufo_169_Din_A <= ap_const_lv32_0;
bufo_169_Din_B <= ap_const_lv32_0;
bufo_169_EN_A <= ap_const_logic_0;
bufo_169_EN_B <= ap_const_logic_0;
bufo_169_Rst_A <= ap_rst;
bufo_169_Rst_B <= ap_rst;
bufo_169_WEN_A <= ap_const_lv4_0;
bufo_169_WEN_B <= ap_const_lv4_0;
bufo_16_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_16_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_16_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_16_Clk_A <= ap_clk;
bufo_16_Din_A <= reg_2580;
bufo_16_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_16_EN_A <= ap_const_logic_1;
else
bufo_16_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_16_Rst_A <= ap_rst;
bufo_16_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_10) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_16_WEN_A <= ap_const_lv4_F;
else
bufo_16_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_170_Addr_A <= ap_const_lv32_0;
bufo_170_Addr_B <= ap_const_lv32_0;
bufo_170_Clk_A <= ap_clk;
bufo_170_Clk_B <= ap_clk;
bufo_170_Din_A <= ap_const_lv32_0;
bufo_170_Din_B <= ap_const_lv32_0;
bufo_170_EN_A <= ap_const_logic_0;
bufo_170_EN_B <= ap_const_logic_0;
bufo_170_Rst_A <= ap_rst;
bufo_170_Rst_B <= ap_rst;
bufo_170_WEN_A <= ap_const_lv4_0;
bufo_170_WEN_B <= ap_const_lv4_0;
bufo_171_Addr_A <= ap_const_lv32_0;
bufo_171_Addr_B <= ap_const_lv32_0;
bufo_171_Clk_A <= ap_clk;
bufo_171_Clk_B <= ap_clk;
bufo_171_Din_A <= ap_const_lv32_0;
bufo_171_Din_B <= ap_const_lv32_0;
bufo_171_EN_A <= ap_const_logic_0;
bufo_171_EN_B <= ap_const_logic_0;
bufo_171_Rst_A <= ap_rst;
bufo_171_Rst_B <= ap_rst;
bufo_171_WEN_A <= ap_const_lv4_0;
bufo_171_WEN_B <= ap_const_lv4_0;
bufo_172_Addr_A <= ap_const_lv32_0;
bufo_172_Addr_B <= ap_const_lv32_0;
bufo_172_Clk_A <= ap_clk;
bufo_172_Clk_B <= ap_clk;
bufo_172_Din_A <= ap_const_lv32_0;
bufo_172_Din_B <= ap_const_lv32_0;
bufo_172_EN_A <= ap_const_logic_0;
bufo_172_EN_B <= ap_const_logic_0;
bufo_172_Rst_A <= ap_rst;
bufo_172_Rst_B <= ap_rst;
bufo_172_WEN_A <= ap_const_lv4_0;
bufo_172_WEN_B <= ap_const_lv4_0;
bufo_173_Addr_A <= ap_const_lv32_0;
bufo_173_Addr_B <= ap_const_lv32_0;
bufo_173_Clk_A <= ap_clk;
bufo_173_Clk_B <= ap_clk;
bufo_173_Din_A <= ap_const_lv32_0;
bufo_173_Din_B <= ap_const_lv32_0;
bufo_173_EN_A <= ap_const_logic_0;
bufo_173_EN_B <= ap_const_logic_0;
bufo_173_Rst_A <= ap_rst;
bufo_173_Rst_B <= ap_rst;
bufo_173_WEN_A <= ap_const_lv4_0;
bufo_173_WEN_B <= ap_const_lv4_0;
bufo_174_Addr_A <= ap_const_lv32_0;
bufo_174_Addr_B <= ap_const_lv32_0;
bufo_174_Clk_A <= ap_clk;
bufo_174_Clk_B <= ap_clk;
bufo_174_Din_A <= ap_const_lv32_0;
bufo_174_Din_B <= ap_const_lv32_0;
bufo_174_EN_A <= ap_const_logic_0;
bufo_174_EN_B <= ap_const_logic_0;
bufo_174_Rst_A <= ap_rst;
bufo_174_Rst_B <= ap_rst;
bufo_174_WEN_A <= ap_const_lv4_0;
bufo_174_WEN_B <= ap_const_lv4_0;
bufo_175_Addr_A <= ap_const_lv32_0;
bufo_175_Addr_B <= ap_const_lv32_0;
bufo_175_Clk_A <= ap_clk;
bufo_175_Clk_B <= ap_clk;
bufo_175_Din_A <= ap_const_lv32_0;
bufo_175_Din_B <= ap_const_lv32_0;
bufo_175_EN_A <= ap_const_logic_0;
bufo_175_EN_B <= ap_const_logic_0;
bufo_175_Rst_A <= ap_rst;
bufo_175_Rst_B <= ap_rst;
bufo_175_WEN_A <= ap_const_lv4_0;
bufo_175_WEN_B <= ap_const_lv4_0;
bufo_176_Addr_A <= ap_const_lv32_0;
bufo_176_Addr_B <= ap_const_lv32_0;
bufo_176_Clk_A <= ap_clk;
bufo_176_Clk_B <= ap_clk;
bufo_176_Din_A <= ap_const_lv32_0;
bufo_176_Din_B <= ap_const_lv32_0;
bufo_176_EN_A <= ap_const_logic_0;
bufo_176_EN_B <= ap_const_logic_0;
bufo_176_Rst_A <= ap_rst;
bufo_176_Rst_B <= ap_rst;
bufo_176_WEN_A <= ap_const_lv4_0;
bufo_176_WEN_B <= ap_const_lv4_0;
bufo_177_Addr_A <= ap_const_lv32_0;
bufo_177_Addr_B <= ap_const_lv32_0;
bufo_177_Clk_A <= ap_clk;
bufo_177_Clk_B <= ap_clk;
bufo_177_Din_A <= ap_const_lv32_0;
bufo_177_Din_B <= ap_const_lv32_0;
bufo_177_EN_A <= ap_const_logic_0;
bufo_177_EN_B <= ap_const_logic_0;
bufo_177_Rst_A <= ap_rst;
bufo_177_Rst_B <= ap_rst;
bufo_177_WEN_A <= ap_const_lv4_0;
bufo_177_WEN_B <= ap_const_lv4_0;
bufo_178_Addr_A <= ap_const_lv32_0;
bufo_178_Addr_B <= ap_const_lv32_0;
bufo_178_Clk_A <= ap_clk;
bufo_178_Clk_B <= ap_clk;
bufo_178_Din_A <= ap_const_lv32_0;
bufo_178_Din_B <= ap_const_lv32_0;
bufo_178_EN_A <= ap_const_logic_0;
bufo_178_EN_B <= ap_const_logic_0;
bufo_178_Rst_A <= ap_rst;
bufo_178_Rst_B <= ap_rst;
bufo_178_WEN_A <= ap_const_lv4_0;
bufo_178_WEN_B <= ap_const_lv4_0;
bufo_179_Addr_A <= ap_const_lv32_0;
bufo_179_Addr_B <= ap_const_lv32_0;
bufo_179_Clk_A <= ap_clk;
bufo_179_Clk_B <= ap_clk;
bufo_179_Din_A <= ap_const_lv32_0;
bufo_179_Din_B <= ap_const_lv32_0;
bufo_179_EN_A <= ap_const_logic_0;
bufo_179_EN_B <= ap_const_logic_0;
bufo_179_Rst_A <= ap_rst;
bufo_179_Rst_B <= ap_rst;
bufo_179_WEN_A <= ap_const_lv4_0;
bufo_179_WEN_B <= ap_const_lv4_0;
bufo_17_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_17_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_17_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_17_Clk_A <= ap_clk;
bufo_17_Din_A <= reg_2580;
bufo_17_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_17_EN_A <= ap_const_logic_1;
else
bufo_17_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_17_Rst_A <= ap_rst;
bufo_17_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_11) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_17_WEN_A <= ap_const_lv4_F;
else
bufo_17_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_180_Addr_A <= ap_const_lv32_0;
bufo_180_Addr_B <= ap_const_lv32_0;
bufo_180_Clk_A <= ap_clk;
bufo_180_Clk_B <= ap_clk;
bufo_180_Din_A <= ap_const_lv32_0;
bufo_180_Din_B <= ap_const_lv32_0;
bufo_180_EN_A <= ap_const_logic_0;
bufo_180_EN_B <= ap_const_logic_0;
bufo_180_Rst_A <= ap_rst;
bufo_180_Rst_B <= ap_rst;
bufo_180_WEN_A <= ap_const_lv4_0;
bufo_180_WEN_B <= ap_const_lv4_0;
bufo_181_Addr_A <= ap_const_lv32_0;
bufo_181_Addr_B <= ap_const_lv32_0;
bufo_181_Clk_A <= ap_clk;
bufo_181_Clk_B <= ap_clk;
bufo_181_Din_A <= ap_const_lv32_0;
bufo_181_Din_B <= ap_const_lv32_0;
bufo_181_EN_A <= ap_const_logic_0;
bufo_181_EN_B <= ap_const_logic_0;
bufo_181_Rst_A <= ap_rst;
bufo_181_Rst_B <= ap_rst;
bufo_181_WEN_A <= ap_const_lv4_0;
bufo_181_WEN_B <= ap_const_lv4_0;
bufo_182_Addr_A <= ap_const_lv32_0;
bufo_182_Addr_B <= ap_const_lv32_0;
bufo_182_Clk_A <= ap_clk;
bufo_182_Clk_B <= ap_clk;
bufo_182_Din_A <= ap_const_lv32_0;
bufo_182_Din_B <= ap_const_lv32_0;
bufo_182_EN_A <= ap_const_logic_0;
bufo_182_EN_B <= ap_const_logic_0;
bufo_182_Rst_A <= ap_rst;
bufo_182_Rst_B <= ap_rst;
bufo_182_WEN_A <= ap_const_lv4_0;
bufo_182_WEN_B <= ap_const_lv4_0;
bufo_183_Addr_A <= ap_const_lv32_0;
bufo_183_Addr_B <= ap_const_lv32_0;
bufo_183_Clk_A <= ap_clk;
bufo_183_Clk_B <= ap_clk;
bufo_183_Din_A <= ap_const_lv32_0;
bufo_183_Din_B <= ap_const_lv32_0;
bufo_183_EN_A <= ap_const_logic_0;
bufo_183_EN_B <= ap_const_logic_0;
bufo_183_Rst_A <= ap_rst;
bufo_183_Rst_B <= ap_rst;
bufo_183_WEN_A <= ap_const_lv4_0;
bufo_183_WEN_B <= ap_const_lv4_0;
bufo_184_Addr_A <= ap_const_lv32_0;
bufo_184_Addr_B <= ap_const_lv32_0;
bufo_184_Clk_A <= ap_clk;
bufo_184_Clk_B <= ap_clk;
bufo_184_Din_A <= ap_const_lv32_0;
bufo_184_Din_B <= ap_const_lv32_0;
bufo_184_EN_A <= ap_const_logic_0;
bufo_184_EN_B <= ap_const_logic_0;
bufo_184_Rst_A <= ap_rst;
bufo_184_Rst_B <= ap_rst;
bufo_184_WEN_A <= ap_const_lv4_0;
bufo_184_WEN_B <= ap_const_lv4_0;
bufo_185_Addr_A <= ap_const_lv32_0;
bufo_185_Addr_B <= ap_const_lv32_0;
bufo_185_Clk_A <= ap_clk;
bufo_185_Clk_B <= ap_clk;
bufo_185_Din_A <= ap_const_lv32_0;
bufo_185_Din_B <= ap_const_lv32_0;
bufo_185_EN_A <= ap_const_logic_0;
bufo_185_EN_B <= ap_const_logic_0;
bufo_185_Rst_A <= ap_rst;
bufo_185_Rst_B <= ap_rst;
bufo_185_WEN_A <= ap_const_lv4_0;
bufo_185_WEN_B <= ap_const_lv4_0;
bufo_186_Addr_A <= ap_const_lv32_0;
bufo_186_Addr_B <= ap_const_lv32_0;
bufo_186_Clk_A <= ap_clk;
bufo_186_Clk_B <= ap_clk;
bufo_186_Din_A <= ap_const_lv32_0;
bufo_186_Din_B <= ap_const_lv32_0;
bufo_186_EN_A <= ap_const_logic_0;
bufo_186_EN_B <= ap_const_logic_0;
bufo_186_Rst_A <= ap_rst;
bufo_186_Rst_B <= ap_rst;
bufo_186_WEN_A <= ap_const_lv4_0;
bufo_186_WEN_B <= ap_const_lv4_0;
bufo_187_Addr_A <= ap_const_lv32_0;
bufo_187_Addr_B <= ap_const_lv32_0;
bufo_187_Clk_A <= ap_clk;
bufo_187_Clk_B <= ap_clk;
bufo_187_Din_A <= ap_const_lv32_0;
bufo_187_Din_B <= ap_const_lv32_0;
bufo_187_EN_A <= ap_const_logic_0;
bufo_187_EN_B <= ap_const_logic_0;
bufo_187_Rst_A <= ap_rst;
bufo_187_Rst_B <= ap_rst;
bufo_187_WEN_A <= ap_const_lv4_0;
bufo_187_WEN_B <= ap_const_lv4_0;
bufo_188_Addr_A <= ap_const_lv32_0;
bufo_188_Addr_B <= ap_const_lv32_0;
bufo_188_Clk_A <= ap_clk;
bufo_188_Clk_B <= ap_clk;
bufo_188_Din_A <= ap_const_lv32_0;
bufo_188_Din_B <= ap_const_lv32_0;
bufo_188_EN_A <= ap_const_logic_0;
bufo_188_EN_B <= ap_const_logic_0;
bufo_188_Rst_A <= ap_rst;
bufo_188_Rst_B <= ap_rst;
bufo_188_WEN_A <= ap_const_lv4_0;
bufo_188_WEN_B <= ap_const_lv4_0;
bufo_189_Addr_A <= ap_const_lv32_0;
bufo_189_Addr_B <= ap_const_lv32_0;
bufo_189_Clk_A <= ap_clk;
bufo_189_Clk_B <= ap_clk;
bufo_189_Din_A <= ap_const_lv32_0;
bufo_189_Din_B <= ap_const_lv32_0;
bufo_189_EN_A <= ap_const_logic_0;
bufo_189_EN_B <= ap_const_logic_0;
bufo_189_Rst_A <= ap_rst;
bufo_189_Rst_B <= ap_rst;
bufo_189_WEN_A <= ap_const_lv4_0;
bufo_189_WEN_B <= ap_const_lv4_0;
bufo_18_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_18_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_18_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_18_Clk_A <= ap_clk;
bufo_18_Din_A <= reg_2580;
bufo_18_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_18_EN_A <= ap_const_logic_1;
else
bufo_18_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_18_Rst_A <= ap_rst;
bufo_18_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_12) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_18_WEN_A <= ap_const_lv4_F;
else
bufo_18_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_190_Addr_A <= ap_const_lv32_0;
bufo_190_Addr_B <= ap_const_lv32_0;
bufo_190_Clk_A <= ap_clk;
bufo_190_Clk_B <= ap_clk;
bufo_190_Din_A <= ap_const_lv32_0;
bufo_190_Din_B <= ap_const_lv32_0;
bufo_190_EN_A <= ap_const_logic_0;
bufo_190_EN_B <= ap_const_logic_0;
bufo_190_Rst_A <= ap_rst;
bufo_190_Rst_B <= ap_rst;
bufo_190_WEN_A <= ap_const_lv4_0;
bufo_190_WEN_B <= ap_const_lv4_0;
bufo_191_Addr_A <= ap_const_lv32_0;
bufo_191_Addr_B <= ap_const_lv32_0;
bufo_191_Clk_A <= ap_clk;
bufo_191_Clk_B <= ap_clk;
bufo_191_Din_A <= ap_const_lv32_0;
bufo_191_Din_B <= ap_const_lv32_0;
bufo_191_EN_A <= ap_const_logic_0;
bufo_191_EN_B <= ap_const_logic_0;
bufo_191_Rst_A <= ap_rst;
bufo_191_Rst_B <= ap_rst;
bufo_191_WEN_A <= ap_const_lv4_0;
bufo_191_WEN_B <= ap_const_lv4_0;
bufo_192_Addr_A <= ap_const_lv32_0;
bufo_192_Addr_B <= ap_const_lv32_0;
bufo_192_Clk_A <= ap_clk;
bufo_192_Clk_B <= ap_clk;
bufo_192_Din_A <= ap_const_lv32_0;
bufo_192_Din_B <= ap_const_lv32_0;
bufo_192_EN_A <= ap_const_logic_0;
bufo_192_EN_B <= ap_const_logic_0;
bufo_192_Rst_A <= ap_rst;
bufo_192_Rst_B <= ap_rst;
bufo_192_WEN_A <= ap_const_lv4_0;
bufo_192_WEN_B <= ap_const_lv4_0;
bufo_193_Addr_A <= ap_const_lv32_0;
bufo_193_Addr_B <= ap_const_lv32_0;
bufo_193_Clk_A <= ap_clk;
bufo_193_Clk_B <= ap_clk;
bufo_193_Din_A <= ap_const_lv32_0;
bufo_193_Din_B <= ap_const_lv32_0;
bufo_193_EN_A <= ap_const_logic_0;
bufo_193_EN_B <= ap_const_logic_0;
bufo_193_Rst_A <= ap_rst;
bufo_193_Rst_B <= ap_rst;
bufo_193_WEN_A <= ap_const_lv4_0;
bufo_193_WEN_B <= ap_const_lv4_0;
bufo_194_Addr_A <= ap_const_lv32_0;
bufo_194_Addr_B <= ap_const_lv32_0;
bufo_194_Clk_A <= ap_clk;
bufo_194_Clk_B <= ap_clk;
bufo_194_Din_A <= ap_const_lv32_0;
bufo_194_Din_B <= ap_const_lv32_0;
bufo_194_EN_A <= ap_const_logic_0;
bufo_194_EN_B <= ap_const_logic_0;
bufo_194_Rst_A <= ap_rst;
bufo_194_Rst_B <= ap_rst;
bufo_194_WEN_A <= ap_const_lv4_0;
bufo_194_WEN_B <= ap_const_lv4_0;
bufo_195_Addr_A <= ap_const_lv32_0;
bufo_195_Addr_B <= ap_const_lv32_0;
bufo_195_Clk_A <= ap_clk;
bufo_195_Clk_B <= ap_clk;
bufo_195_Din_A <= ap_const_lv32_0;
bufo_195_Din_B <= ap_const_lv32_0;
bufo_195_EN_A <= ap_const_logic_0;
bufo_195_EN_B <= ap_const_logic_0;
bufo_195_Rst_A <= ap_rst;
bufo_195_Rst_B <= ap_rst;
bufo_195_WEN_A <= ap_const_lv4_0;
bufo_195_WEN_B <= ap_const_lv4_0;
bufo_196_Addr_A <= ap_const_lv32_0;
bufo_196_Addr_B <= ap_const_lv32_0;
bufo_196_Clk_A <= ap_clk;
bufo_196_Clk_B <= ap_clk;
bufo_196_Din_A <= ap_const_lv32_0;
bufo_196_Din_B <= ap_const_lv32_0;
bufo_196_EN_A <= ap_const_logic_0;
bufo_196_EN_B <= ap_const_logic_0;
bufo_196_Rst_A <= ap_rst;
bufo_196_Rst_B <= ap_rst;
bufo_196_WEN_A <= ap_const_lv4_0;
bufo_196_WEN_B <= ap_const_lv4_0;
bufo_197_Addr_A <= ap_const_lv32_0;
bufo_197_Addr_B <= ap_const_lv32_0;
bufo_197_Clk_A <= ap_clk;
bufo_197_Clk_B <= ap_clk;
bufo_197_Din_A <= ap_const_lv32_0;
bufo_197_Din_B <= ap_const_lv32_0;
bufo_197_EN_A <= ap_const_logic_0;
bufo_197_EN_B <= ap_const_logic_0;
bufo_197_Rst_A <= ap_rst;
bufo_197_Rst_B <= ap_rst;
bufo_197_WEN_A <= ap_const_lv4_0;
bufo_197_WEN_B <= ap_const_lv4_0;
bufo_198_Addr_A <= ap_const_lv32_0;
bufo_198_Addr_B <= ap_const_lv32_0;
bufo_198_Clk_A <= ap_clk;
bufo_198_Clk_B <= ap_clk;
bufo_198_Din_A <= ap_const_lv32_0;
bufo_198_Din_B <= ap_const_lv32_0;
bufo_198_EN_A <= ap_const_logic_0;
bufo_198_EN_B <= ap_const_logic_0;
bufo_198_Rst_A <= ap_rst;
bufo_198_Rst_B <= ap_rst;
bufo_198_WEN_A <= ap_const_lv4_0;
bufo_198_WEN_B <= ap_const_lv4_0;
bufo_199_Addr_A <= ap_const_lv32_0;
bufo_199_Addr_B <= ap_const_lv32_0;
bufo_199_Clk_A <= ap_clk;
bufo_199_Clk_B <= ap_clk;
bufo_199_Din_A <= ap_const_lv32_0;
bufo_199_Din_B <= ap_const_lv32_0;
bufo_199_EN_A <= ap_const_logic_0;
bufo_199_EN_B <= ap_const_logic_0;
bufo_199_Rst_A <= ap_rst;
bufo_199_Rst_B <= ap_rst;
bufo_199_WEN_A <= ap_const_lv4_0;
bufo_199_WEN_B <= ap_const_lv4_0;
bufo_19_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_19_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_19_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_19_Clk_A <= ap_clk;
bufo_19_Din_A <= reg_2580;
bufo_19_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_19_EN_A <= ap_const_logic_1;
else
bufo_19_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_19_Rst_A <= ap_rst;
bufo_19_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_13) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_19_WEN_A <= ap_const_lv4_F;
else
bufo_19_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_1_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_1_Clk_A <= ap_clk;
bufo_1_Din_A <= reg_2580;
bufo_1_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_1_EN_A <= ap_const_logic_1;
else
bufo_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_1_Rst_A <= ap_rst;
bufo_1_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_1_WEN_A <= ap_const_lv4_F;
else
bufo_1_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_20_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_20_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_20_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_20_Clk_A <= ap_clk;
bufo_20_Din_A <= reg_2580;
bufo_20_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_20_EN_A <= ap_const_logic_1;
else
bufo_20_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_20_Rst_A <= ap_rst;
bufo_20_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_14) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_20_WEN_A <= ap_const_lv4_F;
else
bufo_20_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_21_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_21_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_21_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_21_Clk_A <= ap_clk;
bufo_21_Din_A <= reg_2580;
bufo_21_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_21_EN_A <= ap_const_logic_1;
else
bufo_21_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_21_Rst_A <= ap_rst;
bufo_21_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_15) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_21_WEN_A <= ap_const_lv4_F;
else
bufo_21_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_22_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_22_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_22_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_22_Clk_A <= ap_clk;
bufo_22_Din_A <= reg_2580;
bufo_22_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_22_EN_A <= ap_const_logic_1;
else
bufo_22_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_22_Rst_A <= ap_rst;
bufo_22_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_16) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_22_WEN_A <= ap_const_lv4_F;
else
bufo_22_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_23_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_23_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_23_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_23_Clk_A <= ap_clk;
bufo_23_Din_A <= reg_2580;
bufo_23_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_23_EN_A <= ap_const_logic_1;
else
bufo_23_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_23_Rst_A <= ap_rst;
bufo_23_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_17) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_23_WEN_A <= ap_const_lv4_F;
else
bufo_23_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_24_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_24_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_24_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_24_Clk_A <= ap_clk;
bufo_24_Din_A <= reg_2580;
bufo_24_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_24_EN_A <= ap_const_logic_1;
else
bufo_24_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_24_Rst_A <= ap_rst;
bufo_24_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_18) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_24_WEN_A <= ap_const_lv4_F;
else
bufo_24_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_25_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_25_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_25_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_25_Clk_A <= ap_clk;
bufo_25_Din_A <= reg_2580;
bufo_25_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_25_EN_A <= ap_const_logic_1;
else
bufo_25_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_25_Rst_A <= ap_rst;
bufo_25_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_19) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_25_WEN_A <= ap_const_lv4_F;
else
bufo_25_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_26_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_26_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_26_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_26_Clk_A <= ap_clk;
bufo_26_Din_A <= reg_2580;
bufo_26_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_26_EN_A <= ap_const_logic_1;
else
bufo_26_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_26_Rst_A <= ap_rst;
bufo_26_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_26_WEN_A <= ap_const_lv4_F;
else
bufo_26_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_27_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_27_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_27_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_27_Clk_A <= ap_clk;
bufo_27_Din_A <= reg_2580;
bufo_27_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_27_EN_A <= ap_const_logic_1;
else
bufo_27_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_27_Rst_A <= ap_rst;
bufo_27_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_27_WEN_A <= ap_const_lv4_F;
else
bufo_27_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_28_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_28_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_28_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_28_Clk_A <= ap_clk;
bufo_28_Din_A <= reg_2580;
bufo_28_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_28_EN_A <= ap_const_logic_1;
else
bufo_28_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_28_Rst_A <= ap_rst;
bufo_28_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_28_WEN_A <= ap_const_lv4_F;
else
bufo_28_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_29_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_29_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_29_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_29_Clk_A <= ap_clk;
bufo_29_Din_A <= reg_2580;
bufo_29_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_29_EN_A <= ap_const_logic_1;
else
bufo_29_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_29_Rst_A <= ap_rst;
bufo_29_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_29_WEN_A <= ap_const_lv4_F;
else
bufo_29_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_2_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_2_Clk_A <= ap_clk;
bufo_2_Din_A <= reg_2580;
bufo_2_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_2_EN_A <= ap_const_logic_1;
else
bufo_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_2_Rst_A <= ap_rst;
bufo_2_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_2_WEN_A <= ap_const_lv4_F;
else
bufo_2_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_30_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_30_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_30_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_30_Clk_A <= ap_clk;
bufo_30_Din_A <= reg_2580;
bufo_30_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_30_EN_A <= ap_const_logic_1;
else
bufo_30_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_30_Rst_A <= ap_rst;
bufo_30_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_30_WEN_A <= ap_const_lv4_F;
else
bufo_30_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_31_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_31_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_31_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_31_Clk_A <= ap_clk;
bufo_31_Din_A <= reg_2580;
bufo_31_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_31_EN_A <= ap_const_logic_1;
else
bufo_31_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_31_Rst_A <= ap_rst;
bufo_31_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_1F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_31_WEN_A <= ap_const_lv4_F;
else
bufo_31_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_32_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_32_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_32_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_32_Clk_A <= ap_clk;
bufo_32_Din_A <= reg_2580;
bufo_32_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_32_EN_A <= ap_const_logic_1;
else
bufo_32_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_32_Rst_A <= ap_rst;
bufo_32_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_20) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_32_WEN_A <= ap_const_lv4_F;
else
bufo_32_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_33_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_33_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_33_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_33_Clk_A <= ap_clk;
bufo_33_Din_A <= reg_2580;
bufo_33_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_33_EN_A <= ap_const_logic_1;
else
bufo_33_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_33_Rst_A <= ap_rst;
bufo_33_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_21) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_33_WEN_A <= ap_const_lv4_F;
else
bufo_33_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_34_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_34_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_34_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_34_Clk_A <= ap_clk;
bufo_34_Din_A <= reg_2580;
bufo_34_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_34_EN_A <= ap_const_logic_1;
else
bufo_34_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_34_Rst_A <= ap_rst;
bufo_34_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_22) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_34_WEN_A <= ap_const_lv4_F;
else
bufo_34_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_35_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_35_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_35_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_35_Clk_A <= ap_clk;
bufo_35_Din_A <= reg_2580;
bufo_35_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_35_EN_A <= ap_const_logic_1;
else
bufo_35_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_35_Rst_A <= ap_rst;
bufo_35_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_23) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_35_WEN_A <= ap_const_lv4_F;
else
bufo_35_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_36_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_36_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_36_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_36_Clk_A <= ap_clk;
bufo_36_Din_A <= reg_2580;
bufo_36_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_36_EN_A <= ap_const_logic_1;
else
bufo_36_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_36_Rst_A <= ap_rst;
bufo_36_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_24) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_36_WEN_A <= ap_const_lv4_F;
else
bufo_36_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_37_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_37_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_37_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_37_Clk_A <= ap_clk;
bufo_37_Din_A <= reg_2580;
bufo_37_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_37_EN_A <= ap_const_logic_1;
else
bufo_37_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_37_Rst_A <= ap_rst;
bufo_37_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_25) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_37_WEN_A <= ap_const_lv4_F;
else
bufo_37_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_38_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_38_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_38_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_38_Clk_A <= ap_clk;
bufo_38_Din_A <= reg_2580;
bufo_38_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_38_EN_A <= ap_const_logic_1;
else
bufo_38_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_38_Rst_A <= ap_rst;
bufo_38_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_26) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_38_WEN_A <= ap_const_lv4_F;
else
bufo_38_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_39_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_39_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_39_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_39_Clk_A <= ap_clk;
bufo_39_Din_A <= reg_2580;
bufo_39_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_39_EN_A <= ap_const_logic_1;
else
bufo_39_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_39_Rst_A <= ap_rst;
bufo_39_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_27) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_39_WEN_A <= ap_const_lv4_F;
else
bufo_39_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_3_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_3_Clk_A <= ap_clk;
bufo_3_Din_A <= reg_2580;
bufo_3_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_3_EN_A <= ap_const_logic_1;
else
bufo_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_3_Rst_A <= ap_rst;
bufo_3_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_3_WEN_A <= ap_const_lv4_F;
else
bufo_3_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_40_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_40_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_40_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_40_Clk_A <= ap_clk;
bufo_40_Din_A <= reg_2580;
bufo_40_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_40_EN_A <= ap_const_logic_1;
else
bufo_40_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_40_Rst_A <= ap_rst;
bufo_40_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_28) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_40_WEN_A <= ap_const_lv4_F;
else
bufo_40_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_41_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_41_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_41_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_41_Clk_A <= ap_clk;
bufo_41_Din_A <= reg_2580;
bufo_41_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_41_EN_A <= ap_const_logic_1;
else
bufo_41_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_41_Rst_A <= ap_rst;
bufo_41_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_29) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_41_WEN_A <= ap_const_lv4_F;
else
bufo_41_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_42_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_42_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_42_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_42_Clk_A <= ap_clk;
bufo_42_Din_A <= reg_2580;
bufo_42_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_42_EN_A <= ap_const_logic_1;
else
bufo_42_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_42_Rst_A <= ap_rst;
bufo_42_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_42_WEN_A <= ap_const_lv4_F;
else
bufo_42_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_43_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_43_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_43_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_43_Clk_A <= ap_clk;
bufo_43_Din_A <= reg_2580;
bufo_43_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_43_EN_A <= ap_const_logic_1;
else
bufo_43_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_43_Rst_A <= ap_rst;
bufo_43_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_43_WEN_A <= ap_const_lv4_F;
else
bufo_43_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_44_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_44_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_44_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_44_Clk_A <= ap_clk;
bufo_44_Din_A <= reg_2580;
bufo_44_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_44_EN_A <= ap_const_logic_1;
else
bufo_44_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_44_Rst_A <= ap_rst;
bufo_44_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_44_WEN_A <= ap_const_lv4_F;
else
bufo_44_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_45_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_45_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_45_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_45_Clk_A <= ap_clk;
bufo_45_Din_A <= reg_2580;
bufo_45_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_45_EN_A <= ap_const_logic_1;
else
bufo_45_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_45_Rst_A <= ap_rst;
bufo_45_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_45_WEN_A <= ap_const_lv4_F;
else
bufo_45_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_46_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_46_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_46_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_46_Clk_A <= ap_clk;
bufo_46_Din_A <= reg_2580;
bufo_46_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_46_EN_A <= ap_const_logic_1;
else
bufo_46_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_46_Rst_A <= ap_rst;
bufo_46_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_46_WEN_A <= ap_const_lv4_F;
else
bufo_46_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_47_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_47_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_47_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_47_Clk_A <= ap_clk;
bufo_47_Din_A <= reg_2580;
bufo_47_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_47_EN_A <= ap_const_logic_1;
else
bufo_47_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_47_Rst_A <= ap_rst;
bufo_47_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_2F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_47_WEN_A <= ap_const_lv4_F;
else
bufo_47_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_48_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_48_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_48_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_48_Clk_A <= ap_clk;
bufo_48_Din_A <= reg_2580;
bufo_48_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_48_EN_A <= ap_const_logic_1;
else
bufo_48_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_48_Rst_A <= ap_rst;
bufo_48_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_30) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_48_WEN_A <= ap_const_lv4_F;
else
bufo_48_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_49_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_49_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_49_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_49_Clk_A <= ap_clk;
bufo_49_Din_A <= reg_2580;
bufo_49_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_49_EN_A <= ap_const_logic_1;
else
bufo_49_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_49_Rst_A <= ap_rst;
bufo_49_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_31) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_49_WEN_A <= ap_const_lv4_F;
else
bufo_49_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_4_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_4_Clk_A <= ap_clk;
bufo_4_Din_A <= reg_2580;
bufo_4_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_4_EN_A <= ap_const_logic_1;
else
bufo_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_4_Rst_A <= ap_rst;
bufo_4_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_4_WEN_A <= ap_const_lv4_F;
else
bufo_4_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_50_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_50_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_50_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_50_Clk_A <= ap_clk;
bufo_50_Din_A <= reg_2580;
bufo_50_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_50_EN_A <= ap_const_logic_1;
else
bufo_50_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_50_Rst_A <= ap_rst;
bufo_50_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_32) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_50_WEN_A <= ap_const_lv4_F;
else
bufo_50_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_51_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_51_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_51_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_51_Clk_A <= ap_clk;
bufo_51_Din_A <= reg_2580;
bufo_51_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_51_EN_A <= ap_const_logic_1;
else
bufo_51_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_51_Rst_A <= ap_rst;
bufo_51_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_33) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_51_WEN_A <= ap_const_lv4_F;
else
bufo_51_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_52_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_52_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_52_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_52_Clk_A <= ap_clk;
bufo_52_Din_A <= reg_2580;
bufo_52_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_52_EN_A <= ap_const_logic_1;
else
bufo_52_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_52_Rst_A <= ap_rst;
bufo_52_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_34) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_52_WEN_A <= ap_const_lv4_F;
else
bufo_52_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_53_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_53_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_53_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_53_Clk_A <= ap_clk;
bufo_53_Din_A <= reg_2580;
bufo_53_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_53_EN_A <= ap_const_logic_1;
else
bufo_53_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_53_Rst_A <= ap_rst;
bufo_53_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_35) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_53_WEN_A <= ap_const_lv4_F;
else
bufo_53_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_54_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_54_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_54_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_54_Clk_A <= ap_clk;
bufo_54_Din_A <= reg_2580;
bufo_54_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_54_EN_A <= ap_const_logic_1;
else
bufo_54_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_54_Rst_A <= ap_rst;
bufo_54_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_36) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_54_WEN_A <= ap_const_lv4_F;
else
bufo_54_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_55_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_55_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_55_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_55_Clk_A <= ap_clk;
bufo_55_Din_A <= reg_2580;
bufo_55_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_55_EN_A <= ap_const_logic_1;
else
bufo_55_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_55_Rst_A <= ap_rst;
bufo_55_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_37) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_55_WEN_A <= ap_const_lv4_F;
else
bufo_55_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_56_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_56_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_56_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_56_Clk_A <= ap_clk;
bufo_56_Din_A <= reg_2580;
bufo_56_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_56_EN_A <= ap_const_logic_1;
else
bufo_56_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_56_Rst_A <= ap_rst;
bufo_56_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_38) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_56_WEN_A <= ap_const_lv4_F;
else
bufo_56_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_57_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_57_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_57_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_57_Clk_A <= ap_clk;
bufo_57_Din_A <= reg_2580;
bufo_57_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_57_EN_A <= ap_const_logic_1;
else
bufo_57_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_57_Rst_A <= ap_rst;
bufo_57_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_39) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_57_WEN_A <= ap_const_lv4_F;
else
bufo_57_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_58_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_58_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_58_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_58_Clk_A <= ap_clk;
bufo_58_Din_A <= reg_2580;
bufo_58_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_58_EN_A <= ap_const_logic_1;
else
bufo_58_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_58_Rst_A <= ap_rst;
bufo_58_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_58_WEN_A <= ap_const_lv4_F;
else
bufo_58_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_59_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_59_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_59_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_59_Clk_A <= ap_clk;
bufo_59_Din_A <= reg_2580;
bufo_59_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_59_EN_A <= ap_const_logic_1;
else
bufo_59_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_59_Rst_A <= ap_rst;
bufo_59_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_59_WEN_A <= ap_const_lv4_F;
else
bufo_59_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_5_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_5_Clk_A <= ap_clk;
bufo_5_Din_A <= reg_2580;
bufo_5_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_5_EN_A <= ap_const_logic_1;
else
bufo_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_5_Rst_A <= ap_rst;
bufo_5_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_5_WEN_A <= ap_const_lv4_F;
else
bufo_5_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_60_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_60_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_60_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_60_Clk_A <= ap_clk;
bufo_60_Din_A <= reg_2580;
bufo_60_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_60_EN_A <= ap_const_logic_1;
else
bufo_60_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_60_Rst_A <= ap_rst;
bufo_60_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_60_WEN_A <= ap_const_lv4_F;
else
bufo_60_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_61_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_61_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_61_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_61_Clk_A <= ap_clk;
bufo_61_Din_A <= reg_2580;
bufo_61_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_61_EN_A <= ap_const_logic_1;
else
bufo_61_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_61_Rst_A <= ap_rst;
bufo_61_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_61_WEN_A <= ap_const_lv4_F;
else
bufo_61_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_62_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_62_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_62_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_62_Clk_A <= ap_clk;
bufo_62_Din_A <= reg_2580;
bufo_62_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_62_EN_A <= ap_const_logic_1;
else
bufo_62_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_62_Rst_A <= ap_rst;
bufo_62_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_62_WEN_A <= ap_const_lv4_F;
else
bufo_62_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_63_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_63_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_63_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_63_Clk_A <= ap_clk;
bufo_63_Din_A <= reg_2580;
bufo_63_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_63_EN_A <= ap_const_logic_1;
else
bufo_63_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_63_Rst_A <= ap_rst;
bufo_63_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_3F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_63_WEN_A <= ap_const_lv4_F;
else
bufo_63_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_64_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_64_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_64_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_64_Clk_A <= ap_clk;
bufo_64_Din_A <= reg_2580;
bufo_64_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_64_EN_A <= ap_const_logic_1;
else
bufo_64_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_64_Rst_A <= ap_rst;
bufo_64_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_40) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_64_WEN_A <= ap_const_lv4_F;
else
bufo_64_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_65_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_65_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_65_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_65_Clk_A <= ap_clk;
bufo_65_Din_A <= reg_2580;
bufo_65_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_65_EN_A <= ap_const_logic_1;
else
bufo_65_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_65_Rst_A <= ap_rst;
bufo_65_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_41) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_65_WEN_A <= ap_const_lv4_F;
else
bufo_65_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_66_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_66_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_66_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_66_Clk_A <= ap_clk;
bufo_66_Din_A <= reg_2580;
bufo_66_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_66_EN_A <= ap_const_logic_1;
else
bufo_66_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_66_Rst_A <= ap_rst;
bufo_66_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_42) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_66_WEN_A <= ap_const_lv4_F;
else
bufo_66_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_67_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_67_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_67_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_67_Clk_A <= ap_clk;
bufo_67_Din_A <= reg_2580;
bufo_67_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_67_EN_A <= ap_const_logic_1;
else
bufo_67_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_67_Rst_A <= ap_rst;
bufo_67_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_43) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_67_WEN_A <= ap_const_lv4_F;
else
bufo_67_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_68_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_68_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_68_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_68_Clk_A <= ap_clk;
bufo_68_Din_A <= reg_2580;
bufo_68_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_68_EN_A <= ap_const_logic_1;
else
bufo_68_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_68_Rst_A <= ap_rst;
bufo_68_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_44) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_68_WEN_A <= ap_const_lv4_F;
else
bufo_68_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_69_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_69_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_69_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_69_Clk_A <= ap_clk;
bufo_69_Din_A <= reg_2580;
bufo_69_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_69_EN_A <= ap_const_logic_1;
else
bufo_69_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_69_Rst_A <= ap_rst;
bufo_69_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_45) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_69_WEN_A <= ap_const_lv4_F;
else
bufo_69_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_6_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_6_Clk_A <= ap_clk;
bufo_6_Din_A <= reg_2580;
bufo_6_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_6_EN_A <= ap_const_logic_1;
else
bufo_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_6_Rst_A <= ap_rst;
bufo_6_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_6) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_6_WEN_A <= ap_const_lv4_F;
else
bufo_6_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_70_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_70_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_70_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_70_Clk_A <= ap_clk;
bufo_70_Din_A <= reg_2580;
bufo_70_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_70_EN_A <= ap_const_logic_1;
else
bufo_70_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_70_Rst_A <= ap_rst;
bufo_70_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_46) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_70_WEN_A <= ap_const_lv4_F;
else
bufo_70_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_71_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_71_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_71_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_71_Clk_A <= ap_clk;
bufo_71_Din_A <= reg_2580;
bufo_71_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_71_EN_A <= ap_const_logic_1;
else
bufo_71_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_71_Rst_A <= ap_rst;
bufo_71_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_47) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_71_WEN_A <= ap_const_lv4_F;
else
bufo_71_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_72_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_72_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_72_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_72_Clk_A <= ap_clk;
bufo_72_Din_A <= reg_2580;
bufo_72_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_72_EN_A <= ap_const_logic_1;
else
bufo_72_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_72_Rst_A <= ap_rst;
bufo_72_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_48) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_72_WEN_A <= ap_const_lv4_F;
else
bufo_72_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_73_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_73_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_73_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_73_Clk_A <= ap_clk;
bufo_73_Din_A <= reg_2580;
bufo_73_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_73_EN_A <= ap_const_logic_1;
else
bufo_73_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_73_Rst_A <= ap_rst;
bufo_73_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_49) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_73_WEN_A <= ap_const_lv4_F;
else
bufo_73_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_74_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_74_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_74_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_74_Clk_A <= ap_clk;
bufo_74_Din_A <= reg_2580;
bufo_74_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_74_EN_A <= ap_const_logic_1;
else
bufo_74_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_74_Rst_A <= ap_rst;
bufo_74_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_74_WEN_A <= ap_const_lv4_F;
else
bufo_74_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_75_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_75_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_75_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_75_Clk_A <= ap_clk;
bufo_75_Din_A <= reg_2580;
bufo_75_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_75_EN_A <= ap_const_logic_1;
else
bufo_75_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_75_Rst_A <= ap_rst;
bufo_75_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_75_WEN_A <= ap_const_lv4_F;
else
bufo_75_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_76_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_76_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_76_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_76_Clk_A <= ap_clk;
bufo_76_Din_A <= reg_2580;
bufo_76_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_76_EN_A <= ap_const_logic_1;
else
bufo_76_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_76_Rst_A <= ap_rst;
bufo_76_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_76_WEN_A <= ap_const_lv4_F;
else
bufo_76_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_77_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_77_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_77_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_77_Clk_A <= ap_clk;
bufo_77_Din_A <= reg_2580;
bufo_77_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_77_EN_A <= ap_const_logic_1;
else
bufo_77_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_77_Rst_A <= ap_rst;
bufo_77_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_77_WEN_A <= ap_const_lv4_F;
else
bufo_77_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_78_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_78_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_78_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_78_Clk_A <= ap_clk;
bufo_78_Din_A <= reg_2580;
bufo_78_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_78_EN_A <= ap_const_logic_1;
else
bufo_78_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_78_Rst_A <= ap_rst;
bufo_78_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_78_WEN_A <= ap_const_lv4_F;
else
bufo_78_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_79_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_79_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_79_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_79_Clk_A <= ap_clk;
bufo_79_Din_A <= reg_2580;
bufo_79_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_79_EN_A <= ap_const_logic_1;
else
bufo_79_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_79_Rst_A <= ap_rst;
bufo_79_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_4F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_79_WEN_A <= ap_const_lv4_F;
else
bufo_79_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_7_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_7_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_7_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_7_Clk_A <= ap_clk;
bufo_7_Din_A <= reg_2580;
bufo_7_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_7_EN_A <= ap_const_logic_1;
else
bufo_7_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_7_Rst_A <= ap_rst;
bufo_7_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_7) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_7_WEN_A <= ap_const_lv4_F;
else
bufo_7_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_80_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_80_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_80_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_80_Clk_A <= ap_clk;
bufo_80_Din_A <= reg_2580;
bufo_80_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_80_EN_A <= ap_const_logic_1;
else
bufo_80_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_80_Rst_A <= ap_rst;
bufo_80_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_50) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_80_WEN_A <= ap_const_lv4_F;
else
bufo_80_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_81_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_81_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_81_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_81_Clk_A <= ap_clk;
bufo_81_Din_A <= reg_2580;
bufo_81_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_81_EN_A <= ap_const_logic_1;
else
bufo_81_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_81_Rst_A <= ap_rst;
bufo_81_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_51) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_81_WEN_A <= ap_const_lv4_F;
else
bufo_81_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_82_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_82_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_82_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_82_Clk_A <= ap_clk;
bufo_82_Din_A <= reg_2580;
bufo_82_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_82_EN_A <= ap_const_logic_1;
else
bufo_82_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_82_Rst_A <= ap_rst;
bufo_82_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_52) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_82_WEN_A <= ap_const_lv4_F;
else
bufo_82_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_83_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_83_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_83_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_83_Clk_A <= ap_clk;
bufo_83_Din_A <= reg_2580;
bufo_83_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_83_EN_A <= ap_const_logic_1;
else
bufo_83_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_83_Rst_A <= ap_rst;
bufo_83_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_53) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_83_WEN_A <= ap_const_lv4_F;
else
bufo_83_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_84_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_84_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_84_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_84_Clk_A <= ap_clk;
bufo_84_Din_A <= reg_2580;
bufo_84_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_84_EN_A <= ap_const_logic_1;
else
bufo_84_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_84_Rst_A <= ap_rst;
bufo_84_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_54) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_84_WEN_A <= ap_const_lv4_F;
else
bufo_84_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_85_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_85_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_85_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_85_Clk_A <= ap_clk;
bufo_85_Din_A <= reg_2580;
bufo_85_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_85_EN_A <= ap_const_logic_1;
else
bufo_85_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_85_Rst_A <= ap_rst;
bufo_85_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_55) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_85_WEN_A <= ap_const_lv4_F;
else
bufo_85_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_86_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_86_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_86_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_86_Clk_A <= ap_clk;
bufo_86_Din_A <= reg_2580;
bufo_86_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_86_EN_A <= ap_const_logic_1;
else
bufo_86_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_86_Rst_A <= ap_rst;
bufo_86_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_56) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_86_WEN_A <= ap_const_lv4_F;
else
bufo_86_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_87_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_87_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_87_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_87_Clk_A <= ap_clk;
bufo_87_Din_A <= reg_2580;
bufo_87_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_87_EN_A <= ap_const_logic_1;
else
bufo_87_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_87_Rst_A <= ap_rst;
bufo_87_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_57) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_87_WEN_A <= ap_const_lv4_F;
else
bufo_87_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_88_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_88_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_88_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_88_Clk_A <= ap_clk;
bufo_88_Din_A <= reg_2580;
bufo_88_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_88_EN_A <= ap_const_logic_1;
else
bufo_88_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_88_Rst_A <= ap_rst;
bufo_88_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_58) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_88_WEN_A <= ap_const_lv4_F;
else
bufo_88_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_89_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_89_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_89_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_89_Clk_A <= ap_clk;
bufo_89_Din_A <= reg_2580;
bufo_89_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_89_EN_A <= ap_const_logic_1;
else
bufo_89_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_89_Rst_A <= ap_rst;
bufo_89_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_59) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_89_WEN_A <= ap_const_lv4_F;
else
bufo_89_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_8_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_8_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_8_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_8_Clk_A <= ap_clk;
bufo_8_Din_A <= reg_2580;
bufo_8_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_8_EN_A <= ap_const_logic_1;
else
bufo_8_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_8_Rst_A <= ap_rst;
bufo_8_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_8) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_8_WEN_A <= ap_const_lv4_F;
else
bufo_8_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_90_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_90_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_90_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_90_Clk_A <= ap_clk;
bufo_90_Din_A <= reg_2580;
bufo_90_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_90_EN_A <= ap_const_logic_1;
else
bufo_90_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_90_Rst_A <= ap_rst;
bufo_90_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5A) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_90_WEN_A <= ap_const_lv4_F;
else
bufo_90_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_91_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_91_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_91_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_91_Clk_A <= ap_clk;
bufo_91_Din_A <= reg_2580;
bufo_91_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_91_EN_A <= ap_const_logic_1;
else
bufo_91_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_91_Rst_A <= ap_rst;
bufo_91_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5B) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_91_WEN_A <= ap_const_lv4_F;
else
bufo_91_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_92_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_92_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_92_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_92_Clk_A <= ap_clk;
bufo_92_Din_A <= reg_2580;
bufo_92_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_92_EN_A <= ap_const_logic_1;
else
bufo_92_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_92_Rst_A <= ap_rst;
bufo_92_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5C) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_92_WEN_A <= ap_const_lv4_F;
else
bufo_92_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_93_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_93_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_93_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_93_Clk_A <= ap_clk;
bufo_93_Din_A <= reg_2580;
bufo_93_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_93_EN_A <= ap_const_logic_1;
else
bufo_93_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_93_Rst_A <= ap_rst;
bufo_93_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5D) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_93_WEN_A <= ap_const_lv4_F;
else
bufo_93_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_94_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_94_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_94_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_94_Clk_A <= ap_clk;
bufo_94_Din_A <= reg_2580;
bufo_94_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_94_EN_A <= ap_const_logic_1;
else
bufo_94_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_94_Rst_A <= ap_rst;
bufo_94_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5E) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_94_WEN_A <= ap_const_lv4_F;
else
bufo_94_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_95_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_95_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_95_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_95_Clk_A <= ap_clk;
bufo_95_Din_A <= reg_2580;
bufo_95_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_95_EN_A <= ap_const_logic_1;
else
bufo_95_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_95_Rst_A <= ap_rst;
bufo_95_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_5F) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_95_WEN_A <= ap_const_lv4_F;
else
bufo_95_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_96_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_96_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_96_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_96_Clk_A <= ap_clk;
bufo_96_Din_A <= reg_2580;
bufo_96_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_96_EN_A <= ap_const_logic_1;
else
bufo_96_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_96_Rst_A <= ap_rst;
bufo_96_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_60) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_96_WEN_A <= ap_const_lv4_F;
else
bufo_96_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_97_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_97_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_97_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_97_Clk_A <= ap_clk;
bufo_97_Din_A <= reg_2580;
bufo_97_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_97_EN_A <= ap_const_logic_1;
else
bufo_97_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_97_Rst_A <= ap_rst;
bufo_97_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_61) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_97_WEN_A <= ap_const_lv4_F;
else
bufo_97_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_98_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_98_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_98_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_98_Clk_A <= ap_clk;
bufo_98_Din_A <= reg_2580;
bufo_98_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_98_EN_A <= ap_const_logic_1;
else
bufo_98_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_98_Rst_A <= ap_rst;
bufo_98_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_62) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_98_WEN_A <= ap_const_lv4_F;
else
bufo_98_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_99_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_99_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_99_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_99_Clk_A <= ap_clk;
bufo_99_Din_A <= reg_2580;
bufo_99_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_99_EN_A <= ap_const_logic_1;
else
bufo_99_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_99_Rst_A <= ap_rst;
bufo_99_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_63) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_99_WEN_A <= ap_const_lv4_F;
else
bufo_99_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufo_9_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_9_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_9_Addr_A_orig <= ap_const_lv64_0(32 - 1 downto 0);
bufo_9_Clk_A <= ap_clk;
bufo_9_Din_A <= reg_2580;
bufo_9_EN_A_assign_proc : process(ap_CS_fsm_state44, ap_CS_fsm_state56)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_9_EN_A <= ap_const_logic_1;
else
bufo_9_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_9_Rst_A <= ap_rst;
bufo_9_WEN_A_assign_proc : process(p_s_reg_2284, ap_CS_fsm_state56)
begin
if (((p_s_reg_2284 = ap_const_lv7_9) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
bufo_9_WEN_A <= ap_const_lv4_F;
else
bufo_9_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_4(31-1 downto 0)))));
bufw_Addr_A_orig <= phi_mul_reg_2272(32 - 1 downto 0);
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv128_lc_1;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst;
bufw_WEN_A <= ap_const_lv16_0;
grp_fu_2558_p0_assign_proc : process(reg_2580, tmp_s_reg_3561, bufo_load_phi_reg_2296, ap_CS_fsm_state9, ap_CS_fsm_state18, ap_CS_fsm_state27, ap_CS_fsm_state36, ap_CS_fsm_state47)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state47)) then
grp_fu_2558_p0 <= bufo_load_phi_reg_2296;
elsif (((ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state36))) then
grp_fu_2558_p0 <= reg_2580;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
grp_fu_2558_p0 <= tmp_s_reg_3561;
else
grp_fu_2558_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_2558_p1_assign_proc : process(reg_2580, tmp_5_1_reg_3566, tmp_5_2_reg_3571, tmp_5_3_reg_3576, ap_CS_fsm_state9, ap_CS_fsm_state18, ap_CS_fsm_state27, ap_CS_fsm_state36, ap_CS_fsm_state47)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state47)) then
grp_fu_2558_p1 <= reg_2580;
elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then
grp_fu_2558_p1 <= tmp_5_3_reg_3576;
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
grp_fu_2558_p1 <= tmp_5_2_reg_3571;
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
grp_fu_2558_p1 <= tmp_5_1_reg_3566;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
grp_fu_2558_p1 <= ap_const_lv32_0;
else
grp_fu_2558_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_2564_p0 <= tmp_reg_3481;
grp_fu_2564_p1 <= tmp_1_reg_3486;
grp_fu_2568_p0 <= tmp_6_reg_3491;
grp_fu_2568_p1 <= tmp_8_reg_3496;
grp_fu_2572_p0 <= tmp_4_reg_3501;
grp_fu_2572_p1 <= tmp_11_reg_3506;
grp_fu_2576_p0 <= tmp_13_reg_3511;
grp_fu_2576_p1 <= tmp_15_reg_3516;
next_mul_fu_2714_p2 <= std_logic_vector(unsigned(ap_const_lv64_19) + unsigned(phi_mul_reg_2272));
tmp_1_fu_2724_p1 <= bufi_Dout_A(32 - 1 downto 0);
tmp_fu_2720_p1 <= bufw_Dout_A(32 - 1 downto 0);
to_b_V_fu_2820_p2 <= std_logic_vector(unsigned(ap_const_lv7_1) + unsigned(p_s_reg_2284));
end behav;
| mit | 4b3efcd5babf740ba42643fc1710bc79 | 0.58919 | 2.640974 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-xc6s/leon3mp.vhd | 1 | 50,077 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant use_eth_data_output_delay : integer := 0;
constant use_eth_input_delay_clk : integer := 0;
constant use_gtx_clk : integer := 0;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal leds : std_logic_vector(3 downto 0); -- I/O port
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
end generate;
noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
erx_clk0 : if (use_eth_input_delay_clk /= 0) generate
delay_rgmii_rx_clk : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_clk,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_clk,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 10 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
end generate;
ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 15, use90degtxclk => 0)
port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erx_clk1 : if (use_eth_input_delay_clk = 0) generate
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
end generate;
erx_clk2 : if (use_eth_input_delay_clk /= 0) generate
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, rgmii_pad.rx_clk);
erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk);
end generate;
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
gtx_clk0 : if (use_gtx_clk = 0) generate
-- Use MIG PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
gtx_clk1 : if (use_gtx_clk = 1) generate
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 3)
port map (clk125, rgmiii.gtx_clk);
end generate;
gtx_clk2 : if (use_gtx_clk = 2) generate
-- Use Separate PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE;
-- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator
generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open);
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 20b5d171794879f03c69fe80c9c0d290 | 0.55175 | 3.427818 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Max/MaxFinder.vhd | 1 | 2,754 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity MaxFinder is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end MaxFinder;
architecture Beh of MaxFinder is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out std_logic_vector(8 downto 0)
);
end component;
component MRAM is
port (
RW: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DIN: in std_logic_vector (7 downto 0);
DOUT: out std_logic_vector (7 downto 0)
);
end component;
component DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF: out std_logic;
-- significant bit set flag
SBF: out std_logic
);
end component;
component CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ÏÇÓ
ROM_re: out std_logic;
ROM_adr: out std_logic_vector(5 downto 0);
ROM_dout: in std_logic_vector(8 downto 0);
-- ÎÇÓ
RAM_rw: out std_logic;
RAM_adr: out std_logic_vector(5 downto 0);
RAM_din: out std_logic_vector(7 downto 0);
RAM_dout: in std_logic_vector(7 downto 0);
--datapath
DP_op1: out std_logic_vector(7 downto 0);
DP_ot: out std_logic_vector(2 downto 0);
DP_en: out std_logic;
DP_res: in std_logic_vector(7 downto 0);
DP_zf: in std_logic;
DP_sbf: in std_logic
);
end component;
signal rom_re: std_logic;
signal rom_adr: std_logic_vector(5 downto 0);
signal rom_dout: std_logic_vector(8 downto 0);
signal ram_rw: std_logic;
signal ram_adr: std_logic_vector(5 downto 0);
signal ram_din: std_logic_vector(7 downto 0);
signal ram_dout: std_logic_vector(7 downto 0);
signal dp_op1: std_logic_vector(7 downto 0);
signal dp_ot: std_logic_vector(2 downto 0);
signal dp_en: std_logic;
signal dp_res: std_logic_vector(7 downto 0);
signal dp_zf: std_logic;
signal dp_sbf: std_logic;
begin
UMRAM: entity MRAM (Beh_Max) port map(
RW => ram_rw,
ADR => ram_adr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Max) port map (
RE => rom_re,
ADR => rom_adr,
DOUT => rom_dout
);
UDPATH: DPATH port map(
EN => dp_en,
OT => dp_ot,
OP1 => dp_op1,
RES => dp_res,
ZF => dp_zf,
SBF => dp_sbf
);
UCTRL1: CTRL1 port map(
CLK => CLK,
RST => RST,
START => Start,
STOP => STOP,
ROM_RE => rom_re,
ROM_ADR => rom_adr,
ROM_DOUT => rom_dout,
RAM_RW => ram_rw,
RAM_ADR => ram_adr,
RAM_DIN => ram_din,
RAM_DOUT => ram_dout,
DP_EN => dp_en,
DP_OT => dp_ot,
DP_OP1 => dp_op1,
DP_RES => dp_res,
DP_ZF => dp_zf,
DP_SBF => dp_sbf
);
end Beh;
| mit | e45cc2569aadf61acd318e69fff4b05d | 0.625272 | 2.533579 | false | false | false | false |
davidhorrocks/1541UltimateII | fpga/6502/vhdl_source/proc_registers.vhd | 2 | 11,117 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
new_flags : in std_logic_vector(7 downto 0);
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
interrupt : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
rwn : in std_logic;
latch_dreg : in std_logic;
irq_done : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
-- signal a_reg : std_logic_vector(7 downto 0);
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : std_logic_vector(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : std_logic_vector(7 downto 0) := X"FF";
signal adl, adh : std_logic_vector(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal vect : std_logic_vector(3 downto 0) := "1111";
signal dreg_zero : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
begin
dreg_zero <= '1' when dreg=X"00" else '0';
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : std_logic_vector(8 downto 0);
variable adl_t : std_logic_vector(8 downto 0);
begin
if rising_edge(clock) then
-- if reg_update='1' and I_flag /= new_flags(2) then
-- p_reg_i(2) <= '0'; -- set/clear I outside ready
-- end if;
if clock_en='1' then
if ready='1' or rwn='0' then
-- Data Register
if latch_dreg='1' then
dreg <= data_in;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
end if;
if irq_done='1' then
I_flag <= '1';
end if;
if so_n='0' then -- only 1 bit is affected, so no syncronization needed
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
i_reg_i <= data_in;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= data_in;
when from_alu =>
pcl_t := ('0' & pcl) + (dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := ('0' & dreg) + ('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= data_in;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= data_in;
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data; --dreg; -- alu is okay, too (they should be the same)
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if set_s='1' then
s_reg_i <= set_data;
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
adh & adl when 1,
X"01" & s_reg_i when 2,
pch & pcl when 3;
with i_reg_i(1 downto 0) select reg_out <=
y_reg_i when "00",
a_reg_i when "01",
x_reg_i when "10",
a_reg_i and x_reg_i when others;
with dout_mux select data_out <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
mem_data when shift_res,
X"FF" when others;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= s_reg_i;
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= pch & pcl;
end gideon;
| gpl-3.0 | b30ffa5684471870e08629307473ef4c | 0.386795 | 3.990309 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_1/zynq_design_1_axi_bram_ctrl_0_1_sim_netlist.vhdl | 1 | 330,721 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:00 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_1/zynq_design_1_axi_bram_ctrl_0_1_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_SRL_FIFO : entity is "SRL_FIFO";
end zynq_design_1_axi_bram_ctrl_0_1_SRL_FIFO;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_wrap_brst : entity is "wrap_brst";
end zynq_design_1_axi_bram_ctrl_0_1_wrap_brst;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_wrap_brst_0 : entity is "wrap_brst";
end zynq_design_1_axi_bram_ctrl_0_1_wrap_brst_0;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_rd_chnl : entity is "rd_chnl";
end zynq_design_1_axi_bram_ctrl_0_1_rd_chnl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.zynq_design_1_axi_bram_ctrl_0_1_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_wr_chnl : entity is "wr_chnl";
end zynq_design_1_axi_bram_ctrl_0_1_wr_chnl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.zynq_design_1_axi_bram_ctrl_0_1_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.zynq_design_1_axi_bram_ctrl_0_1_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_full_axi : entity is "full_axi";
end zynq_design_1_axi_bram_ctrl_0_1_full_axi;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.zynq_design_1_axi_bram_ctrl_0_1_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.zynq_design_1_axi_bram_ctrl_0_1_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top";
end zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.zynq_design_1_axi_bram_ctrl_0_1_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "axi_bram_ctrl";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "yes";
end zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_bram_ctrl_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_bram_ctrl_0_1 : entity is "zynq_design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_bram_ctrl_0_1 : entity is "axi_bram_ctrl,Vivado 2017.2";
end zynq_design_1_axi_bram_ctrl_0_1;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_1 is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zynq_design_1_axi_bram_ctrl_0_1_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | defcc739985de3fa43c31554db65bf53 | 0.545021 | 2.562418 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/greth/greth_gbit.vhd | 1 | 12,073 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit
-- File: greth_gbit.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_gbit is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
signal gnd : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
gnd <= '0';
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
gbit => etho.gbit,
speed => etho.speed,
--cfg
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, ahbmi.testin);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, ahbmi.testin);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), ahbmi.testin);
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), ahbmi.testin);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 | 60edbb4255c4346237a669c5889895b5 | 0.517021 | 4.202228 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25/config.vhd | 1 | 5,549 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | dd7c57047708ca84872024a9aa3c4cb4 | 0.643359 | 3.66029 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-xc3s-1500/testbench.vhd | 1 | 16,236 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk3 : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal read : std_ulogic;
signal iosn : std_ulogic;
signal bexcn : std_ulogic;
signal brdyn : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal wdogn : std_logic;
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0);
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal pllref : std_ulogic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal errorn : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt : std_logic_vector(7 downto 0);
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal eth_macclk : std_ulogic := '0';
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal clk3 : std_ulogic := '0';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_ulogic := '0';
signal usb_d : std_logic_vector(15 downto 0);
signal usb_linestate : std_logic_vector(1 downto 0);
signal usb_opmode : std_logic_vector(1 downto 0);
signal usb_reset : std_ulogic;
signal usb_rxactive : std_ulogic;
signal usb_rxerror : std_ulogic;
signal usb_rxvalid : std_ulogic;
signal usb_suspend : std_ulogic;
signal usb_termsel : std_ulogic;
signal usb_txready : std_ulogic;
signal usb_txvalid : std_ulogic;
signal usb_validh : std_logic;
signal usb_xcvrsel : std_ulogic;
signal usb_vbus : std_ulogic;
signal rhvalid : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk3 <= not clk3 after 20 ns;
rst <= dsurst and wdogn;
dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0'; pllref <= sdclk;
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
usb_clkout <= not usb_clkout after 8.33 ns; -- ~60MHz
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk3, pllref, errorn, wdogn, address(27 downto 0), data,
ramsn, ramoen, rwen, oen, writen, read, iosn, bexcn, brdyn, romsn,
sdclk, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsuen, dsubre, dsuact,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, emdint,
etxd, etx_en, etx_er, emdc, ps2clk, ps2data, vid_clock, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b, spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn, usb_clkout,
usb_d, usb_linestate, usb_opmode, usb_reset, usb_rxactive, usb_rxerror,
usb_rxvalid, usb_suspend, usb_termsel, usb_txready, usb_txvalid, usb_validh,
usb_xcvrsel, usb_vbus
);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn(0),
writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, errorn, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | 4f39cd757d7f4f1e846187d0a442304e | 0.587645 | 3.038742 | false | false | false | false |
davidhorrocks/1541UltimateII | fpga/6502/vhdl_source/proc_core.vhd | 2 | 7,984 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic := '1';
clock_en_f : in std_logic := '1';
reset : in std_logic;
ready : in std_logic := '1';
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
read_strobe : out std_logic;
write_strobe : out std_logic;
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal clock_en_i : std_logic;
signal clock_en_d : std_logic := '0';
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal vectoring : std_logic;
signal irq_done : std_logic;
signal vect_sel : std_logic_vector(2 downto 1);
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal a16 : std_logic;
attribute keep : string;
attribute keep of interrupt : signal is "true";
begin
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
clock_en_i <= clock_en and (ready or not rwn);
write_strobe <= clock_en_d and not rwn;
read_strobe <= clock_en_d and rwn;
process(clock)
begin
if rising_edge(clock) then
clock_en_d <= clock_en_i;
end if;
end process;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
interrupt => interrupt,
vectoring => vectoring,
vect_sel => vect_sel,
irq_done => irq_done,
vect_addr => vect_addr,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
copy_d2p => copy_d2p,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
interrupt => interrupt,
-- from processor state machine and decoder
sync => sync,
rwn => rwn,
latch_dreg => latch_dreg,
irq_done => irq_done,
vectoring => vectoring,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
clock_en_f => clock_en_f,
ready => ready,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
interrupt => interrupt,
irq_done => irq_done,
vect_sel => vect_sel );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
| gpl-3.0 | e37de76ad63dcdf1978d0365d4a6f5c1 | 0.438001 | 3.526502 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/core/eth_edcl_ahb_mst.vhd | 1 | 4,674 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_edcl_ahb_mst
-- File: eth_edcl_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet EDCL MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_edcl_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable tretry : std_ulogic;
variable tready : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; tready := '0'; tretry := '0';
terror := '0'; tgrant := '0';
hsize := HSIZE_WORD;
hwdata := tmsti.data;
hbusreq := tmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
tgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
| gpl-2.0 | 8883d53e2ffd294f933f2b4251fa0c43 | 0.567394 | 3.634526 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pci_arb.vhd | 1 | 4,003 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
| gpl-2.0 | a00dd7f2e547ec02e42e587c718372cc | 0.553835 | 3.49607 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/sram.vhd | 1 | 5,400 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram
-- File: sram.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity sram is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(7 downto 0);
ce1 : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram is
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**Abits)-1)) of BYTE;
signal DINT,DI,DO : BYTE;
constant ahigh : integer := abits - 1;
signal wrpre : std_ulogic;
function Vpar(vec : std_logic_vector) return std_ulogic is
variable par : std_ulogic := '1';
begin
for i in vec'range loop --'
par := par xor vec(i);
end loop;
return par;
end;
begin
RAM : process(CE1,WE,DI,A,OE,D)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if FIRST then
if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
if index = 6 then
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
elsif (index = 4) or (index = 5) then
recaddr(31 downto abits+1) := (others => '0');
ai := conv_integer(recaddr)/2;
for i in 0 to 7 loop
MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7));
end loop;
else
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
end loop;
end if;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
else
if (TO_X01(not CE1) = '1') then
if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if;
dint <= mema(ai);
end if;
if (TO_X01(CE1 or WE) = '1') then
if wrpre = '1' then
mema(ai) := to_x01(std_logic_vector(DI));
end if;
end if;
end if;
wrpre <= TO_X01((not CE1) and (not WE));
DI <= D;
end process;
BUFS : process(CE1,WE,DINT,OE)
variable DRIVEB : std_logic;
begin
DRIVEB := TO_X01((not CE1) and (not OE) and WE);
case DRIVEB is
when '1' => D <= DINT after tacc * 1 ns;
when '0' => D <= "ZZZZZZZZ" after 8 ns;
when others => D <= "XXXXXXXX";
end case;
end process;
end sim;
-- pragma translate_on
| gpl-2.0 | 6d34824bec88515c5b2fec0f1589b6be | 0.546852 | 3.534031 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/amba_tp.vhd | 1 | 72,448 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : AMBA_TestPackage (Package and body declarations)
--
-- File name : amba_tp.vhd
--
-- Purpose : AMBA AHB and APB interface access procedures
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.aeroflex.com/gaisler
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
-- 0.1 SH 15 Mar 2002 New package
-- 0.2 SH 17 Mar 2003 Updated most packages
-- 0.3 SH 20 May 2003 Memory based on Integer elements
-- 0.4 SH 1 Jul 2003 Name of package changed
-- Compare function improved
-- AHB 32 bit memory with preload added
-- AHB initialisation added
-- 0.5 SH 21 Jul 2003 AHB 32 memory with diagnostics added
-- 0.6 SH 1 Nov 2003 APB read access data sample made earlier
-- AHB 32 memory extended with byte/halfword
-- 0.7 SH 25 Jan 2004 AHB read access data output corrected
-- AHB 32 memory allows overlay addressing
-- 1.7 SH 1 Oct 2004 Ported to GRLIB
-- 1.8 SH 1 Jul 2005 Added configuration support for memories
-- Modified all procedure declarations
-- 1.9 SH 10 Nov 2005 AHB 32 responds with HREADY=0 when error
-- 1.11 SH 27 Dec 2004 Split support added, using HSPLIT element
-- Proper two-cycle error response implemented
-- 1.12 SH 15 Feb 2006 Added bank select to AHB bus accesses
-- 1.13 SH 1 May 2009 AHBQuite gave incorrect TP on error resps.
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.StdLib.all;
use GRLIB.StdIO.all;
package AMBA_TestPackage is
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Initialise AMBA AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Diagnstics types for behavioural model of memory with AHB interface
-----------------------------------------------------------------------------
type AHB_Diagnostics_In_Type is
record
HADDR: Std_Logic_Vector(31 downto 0);
HWRITE: Std_ULogic;
HWDATA: Std_Logic_Vector(31 downto 0);
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HSPLIT: Std_Logic_Vector(NAHBMST-1 downto 0); -- split completion
end record AHB_Diagnostics_In_Type;
type AHB_Diagnostics_Out_Type is
record
HRDATA: Std_Logic_Vector(31 downto 0);
end record AHB_Diagnostics_Out_Type;
constant AHB_Diagnostics_Init: AHB_Diagnostics_In_Type :=
(X"00000000", '0', X"00000000", HRESP_OKAY, zero32(NAHBMST-1 downto 0));
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AMBA AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
end AMBA_TestPackage;
--============================================================================--
package body AMBA_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (O(i)=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clk: in Std_ULogic;
constant Offset: in Time := 5 ns) is
begin
wait until CLK = '1'; -- Synchronise
wait for Offset; -- output offset delay
end procedure Synchronise;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '0');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB initalised"));
WriteLine(Output, L);
end if;
end procedure APBInit;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '1';
APBIn.PWDATA <= Data;
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
end procedure APBWrite;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
wait for 5 ns;
Data := APBOut.PRDATA;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
end procedure APBQuiet;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Temp, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
Data := Temp;
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : APB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
end if;
end procedure APBRead;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Data, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
if not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
RxData := Data;
end procedure APBComp;
-----------------------------------------------------------------------------
-- Initialise AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '0');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '0';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure AHBInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK); -- first clock period
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= ahbdrivedata(Data);
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
begin
AHBWriteQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure AHBWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
Data := AHBOut.HRDATA(31 downto 0);
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
AHBQuiet(Address, Temp, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Data := Temp;
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure AHBRead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
variable Failed: Boolean;
begin
AHBQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure AHBComp;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
subtype ARange is Natural range 0 to 2**gAWidth-1;
subtype DRange is Natural range 0 to gDWidth-1;
type MType is array (ARange) of Integer;
-- memory initialisation
function Init return MType is
variable r: MType;
begin
for i in ARange loop
r(i) := -1;
end loop;
return r;
end function Init;
variable M: MType;
variable A: Std_Logic_Vector(gAWidth-1 downto 0);
variable D: Std_Logic_Vector(0 to gDWidth-1);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
variable alow : std_logic_vector(1 downto 0);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
alow := A(1 downto 0);
case alow is
when "00" =>
D := AHBIn.HWDATA(31 downto 24);
when "01" =>
D := AHBIn.HWDATA(23 downto 16);
when "10" =>
D := AHBIn.HWDATA(15 downto 8);
when others =>
D := AHBIn.HWDATA( 7 downto 0);
end case;
M(Conv_Integer(A)) := Conv_Integer(D);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_BYTE and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 0);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
D := Conv_Std_Logic_Vector(
M(Conv_Integer(A)), D'Length);
case alow is
when "00" =>
AHBOut.HRDATA(31 downto 24) <= D;
when "01" =>
AHBOut.HRDATA(23 downto 16) <= D;
when "10" =>
AHBOut.HRDATA(15 downto 8) <= D;
when others =>
AHBOut.HRDATA( 7 downto 0) <= D;
end case;
else
w :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
M(Conv_Integer(A)) := AHBIn.HWDATA(31 downto 0);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_WORD and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
else
W :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
variable L: Line;
constant Padding: Std_ULogic_Vector(1 to
(4-((gAWidth-2) mod 4))) :=
(others => '0');
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable B: Std_Logic_Vector(1 downto 0);
variable W: Std_Logic;
variable S: Std_Logic_Vector(2 downto 0);
variable D: Std_Logic_Vector(31 downto 0);
variable twocycle:Boolean := False;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
twocycle := False;
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
-- read back memory
D := M(Conv_Integer(A));
-- replace with new data
if S="000" then -- byte
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 24) &
D(23 downto 0);
elsif B(1 downto 0)="01" then
D := D(31 downto 24) &
AHBIn.HWDATA(23 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 8) &
D(7 downto 0);
elsif B(1 downto 0)="11" then
D := D(31 downto 8) &
AHBIn.HWDATA(7 downto 0);
end if;
elsif S="001" then -- halfword
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 0);
end if;
else
D := AHBIn.HWDATA(31 downto 0);
end if;
-- write back memory
M(Conv_Integer(A)) := D;
W := '0';
-- comment
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath & " Write acces to address :");
if Padding'Length > 0 and Padding'Length < 4 then
HWrite(L, Std_Logic_Vector(Padding) & Std_Logic_Vector(A));
else
HWrite(L, Std_Logic_Vector(A));
end if;
Write(L, String'(" data :"));
HWrite(L, D);
Write(L, String'(" data :"));
Write(L, To_BitVector(D));
Write(L, String'(" size :"));
HWrite(L, "0" & S);
WriteLine(Output, L);
end if;
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
(AHBIn.HSIZE=HSIZE_BYTE or
AHBIn.HSIZE=HSIZE_HWORD or
AHBIn.HSIZE=HSIZE_WORD) and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
if AHBInDiag.HRESP=HRESP_OKAY then
W := AHBIn.HWRITE;
S := AHBIn.HSIZE;
B := AHBIn.HADDR( 1 downto 0);
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
elsif AHBInDiag.HRESP=HRESP_RETRY then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_RETRY;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
elsif AHBInDiag.HRESP=HRESP_SPLIT then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_SPLIT;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
else
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_ERROR;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
end if;
else
W :='0';
AHBOut.HREADY <= '1';
if twocycle then
twocycle := False;
else
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
end if;
if HCLK'Event and HCLK='1' then -- rising edge
-- diagnostics
AHBOutDiag.HRData <= M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2)));
if AHBInDiag.HWrite='1' then
M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2))) := AHBInDiag.HWData;
-- Print("Diagnostic write to memory, address: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HAddr)) &
-- " data: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HWData)));
end if;
AHBOut.HSPLIT <= AHBInDiag.HSplit;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : WrAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWData <= Data;
AHBInDiag.HWrite <= '1';
Synchronise(HCLK);
AHBInDiag.HWrite <= '0';
end procedure WrAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RdAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(AHBOutDiag.HRData));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RdAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable Data: Std_Logic_Vector(31 downto 0);
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if not Compare(Data, Expected) then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(", value: "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(", expected: "));
HWrite(L, Std_Logic_Vector(Expected));
Write(L, String'(" # Error "));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
TP := False;
elsif Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Expected));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RcAHBMem32;
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
AHBInDiag.HSPLIT(Split) <= '1';
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : SplitAHBMem32: split acknowledge to master: "));
Write(L, Split);
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure SplitAHBMem32;
end package body AMBA_TestPackage; --=========================================--
| gpl-2.0 | 43de2e196e89bf22f964aa92dda2ac86 | 0.444581 | 4.829545 | false | false | false | false |
freecores/mdct | source/MDCT_PKG.vhd | 1 | 2,190 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCT_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCT_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for MDCT core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package MDCT_PKG is
constant IP_W : INTEGER := 8;
constant OP_W : INTEGER := 12;
constant N : INTEGER := 8;
constant COE_W : INTEGER := 12;
constant ROMDATA_W : INTEGER := COE_W+2;
constant ROMADDR_W : INTEGER := 6;
constant RAMDATA_W : INTEGER := 10;
constant RAMADRR_W : INTEGER := 6;
constant COL_MAX : INTEGER := N-1;
constant ROW_MAX : INTEGER := N-1;
constant LEVEL_SHIFT : INTEGER := 128;
constant DA_W : INTEGER := ROMDATA_W+IP_W;
constant DA2_W : INTEGER := DA_W+2;
-- 2's complement numbers
constant AP : INTEGER := 1448;
constant BP : INTEGER := 1892;
constant CP : INTEGER := 784;
constant DP : INTEGER := 2009;
constant EP : INTEGER := 1703;
constant FP : INTEGER := 1138;
constant GP : INTEGER := 400;
constant AM : INTEGER := -1448;
constant BM : INTEGER := -1892;
constant CM : INTEGER := -784;
constant DM : INTEGER := -2009;
constant EM : INTEGER := -1703;
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
end MDCT_PKG; | lgpl-3.0 | 9fbe733c77492549a7fb85891db016e3 | 0.373516 | 4.877506 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/memctrl/sdmctrl.vhd | 1 | 25,493 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
| gpl-2.0 | 2731e1ada1e9e21478f6e842704e8492 | 0.525242 | 3.132588 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/unisim/ise/unisim_VCOMP.vhd | 2 | 174,848 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: vcomponents
-- File: vcomponents.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declartions of some XILINX primitives
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
-- synopsys translate_off
-----------------------------------------
----------- FPGA Globals --------------
-----------------------------------------
signal GSR : std_logic := '0';
signal GTS : std_logic := '0';
signal GWE : std_logic := '0';
signal PLL_LOCKG : std_logic := 'H';
signal PROGB_GLBL : std_logic := '0';
signal CCLKO_GLBL : std_logic := 'H';
-----------------------------------------
----------- CPLD Globals --------------
-----------------------------------------
signal PRLD : std_logic := '0';
-----------------------------------------
----------- JTAG Globals --------------
-----------------------------------------
signal JTAG_TDO_GLBL : std_logic;
signal JTAG_TDI_GLBL : std_logic := '0';
signal JTAG_TMS_GLBL : std_logic := '0';
signal JTAG_TCK_GLBL : std_logic := '0';
signal JTAG_TRST_GLBL : std_logic := '0';
signal JTAG_CAPTURE_GLBL : std_logic := '0';
signal JTAG_RESET_GLBL : std_logic := '1';
signal JTAG_SHIFT_GLBL : std_logic := '1';
signal JTAG_UPDATE_GLBL : std_logic := '0';
signal JTAG_RUNTEST_GLBL : std_logic := '0';
signal JTAG_SEL1_GLBL : std_logic := '0';
signal JTAG_SEL2_GLBL : std_logic := '0';
signal JTAG_SEL3_GLBL : std_logic := '0';
signal JTAG_SEL4_GLBL : std_logic := '0';
signal JTAG_USER_TDO1_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO2_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO3_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO4_GLBL : std_logic := 'Z';
-- synopsys translate_on
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB16_S1
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4_S4
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component DCM_SP
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component PLL_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_DESKEW_ADJUST : string := "NONE";
CLKFBOUT_MULT : integer := 1;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DESKEW_ADJUST : string := "NONE";
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DESKEW_ADJUST : string := "NONE";
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DESKEW_ADJUST : string := "NONE";
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DESKEW_ADJUST : string := "NONE";
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DESKEW_ADJUST : string := "NONE";
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DESKEW_ADJUST : string := "NONE";
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
EN_REL : boolean := FALSE;
PLL_PMCD_MODE : boolean := FALSE;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE;
RST_DEASSERT_CLK : string := "CLKIN1";
SIM_DEVICE : string := "VIRTEX5"
);
port (
CLKFBDCM : out std_ulogic := '0';
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUTDCM0 : out std_ulogic := '0';
CLKOUTDCM1 : out std_ulogic := '0';
CLKOUTDCM2 : out std_ulogic := '0';
CLKOUTDCM3 : out std_ulogic := '0';
CLKOUTDCM4 : out std_ulogic := '0';
CLKOUTDCM5 : out std_ulogic := '0';
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(4 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
REL : in std_ulogic;
RST : in std_ulogic
);
end component;
component PLL_BASE
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 1;
CLKFBOUT_PHASE : real := 0.0;
CLKIN_PERIOD : real := 0.000;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
LOCKED : out std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic
);
end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGP port (O : out std_logic; I : in std_logic); end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE;
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component IBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IBUFDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IOBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component OBUFDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component FDCPE
generic ( INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic);
end component;
component IDDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC");
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component OFDDRRSE
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDDRRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFIO
port ( O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4");
port ( O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component SYSMON
generic
(
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port
(
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
component FDRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDR
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FDRE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDRS
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic);
end component;
component MUXF5
port ( O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic);
end component;
component VCC
port ( P : out std_ulogic := '1');
end component;
component GND
port ( G : out std_ulogic := '0');
end component;
component INV
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT2_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component LUT4
generic
(
INIT : bit_vector := X"0000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component LUT3
generic
(
INIT : bit_vector := X"00"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT2
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component FDC
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component LUT3_L
generic
(
INIT : bit_vector := X"00"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT1
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic
);
end component;
component LUT4_L
generic
(
INIT : bit_vector := X"0000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component FDCE
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDC_1
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDP
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component LUT1_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXF6
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component FDSE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MULT_AND
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component SRL16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component ROM256X1
generic
(
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end component;
component FDPE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component MULT18X18
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end component;
component MULT18X18S
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end component;
component MUXF7
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component IODELAY
generic
(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port
(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDES
generic
(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port
(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end component;
component RAM16X1S
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM16X1D
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component ROM32X1
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end component;
component DSP48
generic
(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port
(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end component;
component RAMB16
generic
(
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port
(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end component;
component MUXF8
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component RAM64X1D
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component BUF
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT5
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT5_L
generic
(
INIT : bit_vector := X"00000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT6
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component LUT6_L
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component RAM128X1S
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component SRLC16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component LD_1
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic := '0';
D : in std_ulogic;
G : in std_ulogic
);
end component;
component RAM32X1D
generic (
INIT : bit_vector(31 downto 0) := X"00000000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component FD_1
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component XORCY_L
port(
LO : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component RAM32M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
DOC : out std_logic_vector (1 downto 0);
DOD : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector(4 downto 0);
ADDRB : in std_logic_vector(4 downto 0);
ADDRC : in std_logic_vector(4 downto 0);
ADDRD : in std_logic_vector(4 downto 0);
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
DIC : in std_logic_vector (1 downto 0);
DID : in std_logic_vector (1 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM128X1D
generic
(
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A : in std_logic_vector(6 downto 0);
D : in std_ulogic;
DPRA : in std_logic_vector(6 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM64M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_ulogic;
DOB : out std_ulogic;
DOC : out std_ulogic;
DOD : out std_ulogic;
ADDRA : in std_logic_vector(5 downto 0);
ADDRB : in std_logic_vector(5 downto 0);
ADDRC : in std_logic_vector(5 downto 0);
ADDRD : in std_logic_vector(5 downto 0);
DIA : in std_ulogic;
DIB : in std_ulogic;
DIC : in std_ulogic;
DID : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component XOR2
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component SRL16
generic ( INIT : bit_vector := X"0000");
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
component LUT6_2
generic(
INIT : bit_vector := X"0000000000000000"
);
port(
O5 : out std_ulogic;
O6 : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component DSP48E
generic(
SIM_MODE : string := "SAFE";
ACASCREG : integer := 1;
ALUMODEREG : integer := 1;
AREG : integer := 1;
AUTORESET_PATTERN_DETECT : boolean := FALSE;
AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH";
A_INPUT : string := "DIRECT";
BCASCREG : integer := 1;
BREG : integer := 1;
B_INPUT : string := "DIRECT";
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
MASK : bit_vector := X"3FFFFFFFFFFF";
MREG : integer := 1;
MULTCARRYINREG : integer := 1;
OPMODEREG : integer := 1;
PATTERN : bit_vector := X"000000000000";
PREG : integer := 1;
SEL_MASK : string := "MASK";
SEL_PATTERN : string := "PATTERN";
SEL_ROUNDING_MASK : string := "SEL_MASK";
USE_MULT : string := "MULT_S";
USE_PATTERN_DETECT : string := "NO_PATDET";
USE_SIMD : string := "ONE48"
);
port(
ACOUT : out std_logic_vector(29 downto 0);
BCOUT : out std_logic_vector(17 downto 0);
CARRYCASCOUT : out std_ulogic;
CARRYOUT : out std_logic_vector(3 downto 0);
MULTSIGNOUT : out std_ulogic;
OVERFLOW : out std_ulogic;
P : out std_logic_vector(47 downto 0);
PATTERNBDETECT : out std_ulogic;
PATTERNDETECT : out std_ulogic;
PCOUT : out std_logic_vector(47 downto 0);
UNDERFLOW : out std_ulogic;
A : in std_logic_vector(29 downto 0);
ACIN : in std_logic_vector(29 downto 0);
ALUMODE : in std_logic_vector(3 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYCASCIN : in std_ulogic;
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(2 downto 0);
CEA1 : in std_ulogic;
CEA2 : in std_ulogic;
CEALUMODE : in std_ulogic;
CEB1 : in std_ulogic;
CEB2 : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEMULTCARRYIN : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
MULTSIGNIN : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTALLCARRYIN : in std_ulogic;
RSTALUMODE : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic
);
end component;
component RAMB18
generic (
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
INIT_FILE : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOPB : out std_logic_vector(1 downto 0);
ADDRA : in std_logic_vector(13 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
DIPA : in std_logic_vector(1 downto 0);
DIPB : in std_logic_vector(1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(1 downto 0);
WEB : in std_logic_vector(1 downto 0)
);
end component;
component RAMB36
generic (
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INIT_FILE : string := "NONE";
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(3 downto 0);
WEB : in std_logic_vector(3 downto 0)
);
end component;
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
component RAM64X1S
generic (
INIT : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component IBUFDS_GTXE1
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
REFCLKOUT_DLY : bit_vector := b"0000000000"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component MMCM_ADV -----
component MMCM_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : boolean := FALSE;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : boolean := FALSE;
CLOCK_HOLD : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component OSERDESE1
generic (
DATA_RATE_OQ : string := "DDR";
DATA_RATE_TQ : string := "DDR";
DATA_WIDTH : integer := 4;
DDR3_DATA : integer := 1;
INIT_OQ : bit := '0';
INIT_TQ : bit := '0';
INTERFACE_TYPE : string := "DEFAULT";
ODELAY_USED : integer := 0;
SERDES_MODE : string := "MASTER";
SRVAL_OQ : bit := '0';
SRVAL_TQ : bit := '0';
TRISTATE_WIDTH : integer := 4
);
port (
OCBEXTEND : out std_ulogic;
OFB : out std_ulogic;
OQ : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
TFB : out std_ulogic;
TQ : out std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
CLKPERF : in std_ulogic;
CLKPERFDELAY : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
D3 : in std_ulogic;
D4 : in std_ulogic;
D5 : in std_ulogic;
D6 : in std_ulogic;
OCE : in std_ulogic;
ODV : in std_ulogic;
RST : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
T1 : in std_ulogic;
T2 : in std_ulogic;
T3 : in std_ulogic;
T4 : in std_ulogic;
TCE : in std_ulogic;
WC : in std_ulogic
);
end component;
component IODELAYE1
generic (
CINVCTRL_SEL : boolean := FALSE;
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := FALSE;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_TYPE : string := "FIXED";
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDESE1
generic (
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
DYN_CLKDIV_INV_EN : boolean := FALSE;
DYN_CLK_INV_EN : boolean := FALSE;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
NUM_CE : integer := 2;
OFB_USED : boolean := FALSE;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port (
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKB : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DDLY : in std_ulogic;
DYNCLKDIVSEL : in std_ulogic;
DYNCLKSEL : in std_ulogic;
OCLK : in std_ulogic;
OFB : in std_ulogic;
RST : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic
);
end component;
component IOBUFDS_DIFF_OUT
generic (
DIFF_TERM : boolean := FALSE;
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "DEFAULT"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
TM : in std_ulogic;
TS : in std_ulogic
);
end component;
component SRLC32E
generic (
INIT : bit_vector := X"00000000"
);
port (
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
end;
| gpl-2.0 | f2044a2d24824f8b86fa1f772c407c84 | 0.733431 | 4.592682 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/memory_virtex.vhd | 1 | 14,229 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_virtex.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Memory generators for Xilinx Virtex rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB4 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits <= 32)) generate
r0 : RAMB4_S16_S16
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if (((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits > 32)) or (abits = 8)) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-2.0 | dfe70a897b3b4df32a6c9fd3cc5dcd69 | 0.600042 | 2.976156 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_0_5/hdl/vhdl/convolve_kernel_fcud.vhd | 4 | 3,594 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
| mit | 0bb123bee5eb8403e788ad95be8682c7 | 0.483862 | 3.608434 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/7cc4809675563003/ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl | 1 | 177,327 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:31 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl
-- Design : ip_design_zed_audio_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WVALID_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
\DataTx_R_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
s_axi_bvalid_i_reg_1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^datatx_r_reg[0]\ : STD_LOGIC;
signal \^datatx_r_reg[0]_0\ : STD_LOGIC;
signal \^datatx_r_reg[0]_1\ : STD_LOGIC;
signal \^datatx_r_reg[0]_2\ : STD_LOGIC;
signal \^datatx_r_reg[0]_3\ : STD_LOGIC;
signal \^datatx_r_reg[0]_4\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ : STD_LOGIC;
signal S_AXI_ARREADY_INST_0_i_1_n_0 : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_4 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal s_axi_bvalid_i0 : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[10]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[11]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[12]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[13]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[14]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[15]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[16]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[17]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[18]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[19]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[20]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[21]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[22]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal start : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of S_AXI_ARREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of S_AXI_AWREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of data_rdy_bit_i_2 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_bvalid_i_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_rvalid_i_i_2 : label is "soft_lutpair0";
begin
\DataTx_R_reg[0]\ <= \^datatx_r_reg[0]\;
\DataTx_R_reg[0]_0\ <= \^datatx_r_reg[0]_0\;
\DataTx_R_reg[0]_1\ <= \^datatx_r_reg[0]_1\;
\DataTx_R_reg[0]_2\ <= \^datatx_r_reg[0]_2\;
\DataTx_R_reg[0]_3\ <= \^datatx_r_reg[0]_3\;
\DataTx_R_reg[0]_4\ <= \^datatx_r_reg[0]_4\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF02020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
I5 => \^datatx_r_reg[0]_4\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^datatx_r_reg[0]_4\,
R => '0'
);
\DataTx_L[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_0\,
I1 => \^datatx_r_reg[0]_1\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => \DataTx_L_reg[0]\(0)
);
\DataTx_R[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_1\,
I1 => \^datatx_r_reg[0]_0\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => E(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202020202FF02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_4
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_4,
Q => \^datatx_r_reg[0]_3\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_3,
Q => \^datatx_r_reg[0]_2\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(1),
I2 => S_AXI_ARADDR(0),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(1),
I5 => S_AXI_AWADDR(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_2,
Q => \^datatx_r_reg[0]_1\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_ARADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_WVALID,
I2 => S_AXI_AWVALID,
I3 => Q(1),
I4 => Q(0),
I5 => S_AXI_AWADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_1,
Q => \^datatx_r_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => S_AXI_ARESETN,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => S_AXI_ARREADY_INST_0_i_1_n_0,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
O => start
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\,
I2 => S_AXI_AWADDR(1),
I3 => S_AXI_AWADDR(2),
I4 => S_AXI_AWADDR(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => S_AXI_ARADDR(0),
I1 => S_AXI_ARADDR(2),
I2 => S_AXI_ARADDR(1),
I3 => S_AXI_ARVALID,
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_AWVALID,
I3 => S_AXI_WVALID,
I4 => S_AXI_ARVALID,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_0,
Q => \^datatx_r_reg[0]\,
R => cs_ce_clr
);
S_AXI_ARREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_ARREADY
);
S_AXI_ARREADY_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]_1\,
O => S_AXI_ARREADY_INST_0_i_1_n_0
);
S_AXI_AWREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_AWREADY
);
data_rdy_bit_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg_0
);
data_rdy_bit_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^datatx_r_reg[0]_3\,
I1 => \^datatx_r_reg[0]_2\,
I2 => \^datatx_r_reg[0]_1\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]\,
I5 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_bvalid_i0,
I1 => S_AXI_BREADY,
I2 => s_axi_bvalid_i_reg_1,
O => s_axi_bvalid_i_reg
);
s_axi_bvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(1),
I4 => Q(0),
O => s_axi_bvalid_i0
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAAEAAAEAAAEAAA"
)
port map (
I0 => \s_axi_rdata_i[0]_i_2_n_0\,
I1 => data_rdy_bit,
I2 => \^datatx_r_reg[0]\,
I3 => \s_axi_rdata_i[0]_i_3_n_0\,
I4 => \^datatx_r_reg[0]_0\,
I5 => \DataTx_R_reg[31]\(0),
O => \s_axi_rdata_i_reg[31]\(0)
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \s_axi_rdata_i[0]_i_4_n_0\,
I1 => \DataTx_L_reg[31]\(0),
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(0),
I4 => \DataRx_L_reg[23]\(0),
I5 => \s_axi_rdata_i[23]_i_2_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_1\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(10),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(10),
I4 => \s_axi_rdata_i[10]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(10)
);
\s_axi_rdata_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(10),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(10),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[10]_i_2_n_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(11),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(11),
I4 => \s_axi_rdata_i[11]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(11)
);
\s_axi_rdata_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(11),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(11),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[11]_i_2_n_0\
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(12),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(12),
I4 => \s_axi_rdata_i[12]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(12)
);
\s_axi_rdata_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(12),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(12),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[12]_i_2_n_0\
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(13),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(13),
I4 => \s_axi_rdata_i[13]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(13)
);
\s_axi_rdata_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(13),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(13),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[13]_i_2_n_0\
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(14),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(14),
I4 => \s_axi_rdata_i[14]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(14)
);
\s_axi_rdata_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(14),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(14),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[14]_i_2_n_0\
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(15),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(15),
I4 => \s_axi_rdata_i[15]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(15)
);
\s_axi_rdata_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(15),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(15),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[15]_i_2_n_0\
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(16),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(16),
I4 => \s_axi_rdata_i[16]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(16)
);
\s_axi_rdata_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(16),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(16),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[16]_i_2_n_0\
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(17),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(17),
I4 => \s_axi_rdata_i[17]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(17)
);
\s_axi_rdata_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(17),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(17),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[17]_i_2_n_0\
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(18),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(18),
I4 => \s_axi_rdata_i[18]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(18)
);
\s_axi_rdata_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(18),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(18),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[18]_i_2_n_0\
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(19),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(19),
I4 => \s_axi_rdata_i[19]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(19)
);
\s_axi_rdata_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(19),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(19),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[19]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(1),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(1),
I4 => \s_axi_rdata_i[1]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(1)
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(1),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(20),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(20),
I4 => \s_axi_rdata_i[20]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(20)
);
\s_axi_rdata_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(20),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(20),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[20]_i_2_n_0\
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(21),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(21),
I4 => \s_axi_rdata_i[21]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(21)
);
\s_axi_rdata_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(21),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(21),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[21]_i_2_n_0\
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(22),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(22),
I4 => \s_axi_rdata_i[22]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(22)
);
\s_axi_rdata_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(22),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(22),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[22]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(23),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(23),
I4 => \s_axi_rdata_i[23]_i_4_n_0\,
O => \s_axi_rdata_i_reg[31]\(23)
);
\s_axi_rdata_i[23]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_3\,
O => \s_axi_rdata_i[23]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_2\,
O => \s_axi_rdata_i[23]_i_3_n_0\
);
\s_axi_rdata_i[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(23),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(23),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[23]_i_4_n_0\
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(24),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(24),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(25),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(25),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(26),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(26),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(27),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(27),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(28),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(28),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(29),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(29),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(2),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(2),
I4 => \s_axi_rdata_i[2]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(2)
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(2),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(2),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(30),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(30),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(31),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(31),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(31)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(3),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(3),
I4 => \s_axi_rdata_i[3]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(3)
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(3),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(3),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(4),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(4),
I4 => \s_axi_rdata_i[4]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(4)
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(4),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(4),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(5),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(5),
I4 => \s_axi_rdata_i[5]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(5)
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(5),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(5),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(6),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(6),
I4 => \s_axi_rdata_i[6]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(6)
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(6),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(6),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(7),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(7),
I4 => \s_axi_rdata_i[7]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(7)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(7),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(7),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[7]_i_2_n_0\
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(8),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(8),
I4 => \s_axi_rdata_i[8]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(8)
);
\s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(8),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(8),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[8]_i_2_n_0\
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(9),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(9),
I4 => \s_axi_rdata_i[9]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(9)
);
\s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(9),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(9),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[9]_i_2_n_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => S_AXI_RREADY,
I2 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(0),
I4 => Q(1),
O => s_axi_rvalid_i0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARVALID,
I2 => s_axi_bvalid_i0,
I3 => s_axi_bvalid_i_reg_0,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4454"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_WVALID_0,
I3 => S_AXI_ARVALID,
I4 => \state_reg[1]\,
I5 => s_axi_rvalid_i0,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
port (
lrclk_d1 : out STD_LOGIC;
sclk_d1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\rdata_reg_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bit_cntr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sdata_reg_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]_0\ : out STD_LOGIC;
\DataRx_L_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_R_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
data_rdy_bit : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
SDATA_I : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
signal \^datarx_l_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^datarx_r_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_sequential_iis_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_4_n_0\ : STD_LOGIC;
signal \bit_cntr[4]_i_1_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal bit_rdy : STD_LOGIC;
signal data_rdy_bit_i_4_n_0 : STD_LOGIC;
signal eqOp : STD_LOGIC;
signal iis_state : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of iis_state : signal is "yes";
signal ldata_reg : STD_LOGIC;
signal ldata_reg0 : STD_LOGIC;
signal \^lrclk_d1\ : STD_LOGIC;
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rdata_reg0 : STD_LOGIC;
signal \^sclk_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DataRx_L[23]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \FSM_sequential_iis_state[2]_i_4\ : label is "soft_lutpair8";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[0]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[1]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[2]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_2__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of sdata_reg_i_2 : label is "soft_lutpair10";
begin
\DataRx_L_reg[23]\(23 downto 0) <= \^datarx_l_reg[23]\(23 downto 0);
\DataRx_R_reg[23]\(23 downto 0) <= \^datarx_r_reg[23]\(23 downto 0);
E(0) <= \^e\(0);
lrclk_d1 <= \^lrclk_d1\;
sclk_d1 <= \^sclk_d1\;
\DataRx_L[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => eqOp,
I1 => iis_state(2),
I2 => iis_state(1),
I3 => iis_state(0),
O => \^e\(0)
);
\DataRx_L[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(2),
O => eqOp
);
\FSM_onehot_iis_state[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(1),
O => \FSM_onehot_iis_state_reg[0]_0\
);
\FSM_onehot_iis_state[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(0),
O => \FSM_onehot_iis_state_reg[0]\
);
\FSM_sequential_iis_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75777F7745444044"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(0),
O => \FSM_sequential_iis_state[0]_i_1_n_0\
);
\FSM_sequential_iis_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3A7B3F7B0A480048"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(1),
O => \FSM_sequential_iis_state[1]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FB33FB30F800080"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(2),
O => \FSM_sequential_iis_state[2]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFA33FF000A330F"
)
port map (
I0 => bit_rdy,
I1 => \FSM_sequential_iis_state[2]_i_4_n_0\,
I2 => iis_state(2),
I3 => iis_state(0),
I4 => iis_state(1),
I5 => eqOp,
O => \FSM_sequential_iis_state[2]_i_2_n_0\
);
\FSM_sequential_iis_state[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22A222A2EEAE22A2"
)
port map (
I0 => bit_rdy,
I1 => iis_state(2),
I2 => iis_state(0),
I3 => iis_state(1),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_3_n_0\
);
\FSM_sequential_iis_state[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(1),
I1 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_4_n_0\
);
\FSM_sequential_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[0]_i_1_n_0\,
Q => iis_state(0),
R => '0'
);
\FSM_sequential_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[1]_i_1_n_0\,
Q => iis_state(1),
R => '0'
);
\FSM_sequential_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[2]_i_1_n_0\,
Q => iis_state(2),
R => '0'
);
\bit_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(0)
);
\bit_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__1\(1)
);
\bit_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(2)
);
\bit_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(3),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(3)
);
\bit_cntr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D7"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => bit_rdy
);
\bit_cntr[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^sclk_d1\,
I1 => Q(0),
O => \bit_cntr_reg[4]_0\(0)
);
\bit_cntr[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"78F0F0F0"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(2),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1_n_0\
);
data_rdy_bit_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC00EA0000000000"
)
port map (
I0 => data_rdy_bit,
I1 => \^e\(0),
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => data_rdy_bit_i_4_n_0,
I5 => S_AXI_ARESETN,
O => data_rdy_bit_reg
);
data_rdy_bit_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => eqOp,
I3 => iis_state(2),
I4 => iis_state(1),
I5 => iis_state(0),
O => data_rdy_bit_i_4_n_0
);
\ldata_reg[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => ldata_reg
);
\ldata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(2),
I1 => iis_state(0),
I2 => iis_state(1),
I3 => Q(0),
I4 => \^sclk_d1\,
O => ldata_reg0
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => SDATA_I,
Q => \^datarx_l_reg[23]\(0),
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(9),
Q => \^datarx_l_reg[23]\(10),
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(10),
Q => \^datarx_l_reg[23]\(11),
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(11),
Q => \^datarx_l_reg[23]\(12),
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(12),
Q => \^datarx_l_reg[23]\(13),
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(13),
Q => \^datarx_l_reg[23]\(14),
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(14),
Q => \^datarx_l_reg[23]\(15),
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(15),
Q => \^datarx_l_reg[23]\(16),
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(16),
Q => \^datarx_l_reg[23]\(17),
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(17),
Q => \^datarx_l_reg[23]\(18),
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(18),
Q => \^datarx_l_reg[23]\(19),
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(0),
Q => \^datarx_l_reg[23]\(1),
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(19),
Q => \^datarx_l_reg[23]\(20),
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(20),
Q => \^datarx_l_reg[23]\(21),
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(21),
Q => \^datarx_l_reg[23]\(22),
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(22),
Q => \^datarx_l_reg[23]\(23),
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(1),
Q => \^datarx_l_reg[23]\(2),
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(2),
Q => \^datarx_l_reg[23]\(3),
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(3),
Q => \^datarx_l_reg[23]\(4),
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(4),
Q => \^datarx_l_reg[23]\(5),
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(5),
Q => \^datarx_l_reg[23]\(6),
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(6),
Q => \^datarx_l_reg[23]\(7),
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(7),
Q => \^datarx_l_reg[23]\(8),
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(8),
Q => \^datarx_l_reg[23]\(9),
R => ldata_reg
);
lrclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(1),
Q => \^lrclk_d1\,
R => '0'
);
\rdata_reg[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(0),
I1 => iis_state(1),
I2 => iis_state(2),
I3 => Q(0),
I4 => \^sclk_d1\,
O => rdata_reg0
);
\rdata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
I2 => \out\(2),
I3 => \out\(0),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \rdata_reg_reg[23]_0\(0)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => SDATA_I,
Q => \^datarx_r_reg[23]\(0),
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(9),
Q => \^datarx_r_reg[23]\(10),
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(10),
Q => \^datarx_r_reg[23]\(11),
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(11),
Q => \^datarx_r_reg[23]\(12),
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(12),
Q => \^datarx_r_reg[23]\(13),
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(13),
Q => \^datarx_r_reg[23]\(14),
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(14),
Q => \^datarx_r_reg[23]\(15),
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(15),
Q => \^datarx_r_reg[23]\(16),
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(16),
Q => \^datarx_r_reg[23]\(17),
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(17),
Q => \^datarx_r_reg[23]\(18),
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(18),
Q => \^datarx_r_reg[23]\(19),
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(0),
Q => \^datarx_r_reg[23]\(1),
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(19),
Q => \^datarx_r_reg[23]\(20),
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(20),
Q => \^datarx_r_reg[23]\(21),
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(21),
Q => \^datarx_r_reg[23]\(22),
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(22),
Q => \^datarx_r_reg[23]\(23),
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(1),
Q => \^datarx_r_reg[23]\(2),
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(2),
Q => \^datarx_r_reg[23]\(3),
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(3),
Q => \^datarx_r_reg[23]\(4),
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(4),
Q => \^datarx_r_reg[23]\(5),
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(5),
Q => \^datarx_r_reg[23]\(6),
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(6),
Q => \^datarx_r_reg[23]\(7),
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(7),
Q => \^datarx_r_reg[23]\(8),
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(8),
Q => \^datarx_r_reg[23]\(9),
R => ldata_reg
);
sclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(0),
Q => \^sclk_d1\,
R => '0'
);
sdata_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => sdata_reg_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
port (
SDATA_O : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
sclk_d1 : in STD_LOGIC;
lrclk_d1 : in STD_LOGIC;
\DataTx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataTx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\clk_cntr_reg[4]\ : in STD_LOGIC;
lrclk_d1_reg : in STD_LOGIC;
lrclk_d1_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
sclk_d1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
signal \FSM_onehot_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_2_n_0\ : STD_LOGIC;
signal \^sdata_o\ : STD_LOGIC;
signal \bit_cntr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal eqOp : STD_LOGIC;
signal ldata_reg : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of ldata_reg : signal is "yes";
signal \ldata_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[17]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[18]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[21]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[22]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_2__0_n_0\ : STD_LOGIC;
signal \ldata_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_0_in2_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in2_in : signal is "yes";
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 0 );
signal p_2_in : STD_LOGIC;
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \rdata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[23]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal sdata_reg_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_4\ : label is "soft_lutpair11";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[0]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[1]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[2]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[3]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[4]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3__0\ : label is "soft_lutpair11";
begin
SDATA_O <= \^sdata_o\;
\out\(2 downto 0) <= \^out\(2 downto 0);
\FSM_onehot_iis_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAABA"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(2),
I3 => \^out\(1),
I4 => \^out\(0),
O => \FSM_onehot_iis_state[1]_i_1_n_0\
);
\FSM_onehot_iis_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0ACA"
)
port map (
I0 => p_0_in2_in,
I1 => \^out\(0),
I2 => \FSM_onehot_iis_state[4]_i_1_n_0\,
I3 => ldata_reg,
O => \FSM_onehot_iis_state[2]_i_1_n_0\
);
\FSM_onehot_iis_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_0_in2_in,
I1 => ldata_reg,
I2 => \^out\(0),
O => \FSM_onehot_iis_state[3]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFFFEEEFFFF"
)
port map (
I0 => ldata_reg,
I1 => lrclk_d1_reg,
I2 => \^out\(2),
I3 => eqOp,
I4 => lrclk_d1_reg_0,
I5 => p_0_in2_in,
O => \FSM_onehot_iis_state[4]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(1),
I3 => \^out\(0),
O => \FSM_onehot_iis_state[4]_i_2_n_0\
);
\FSM_onehot_iis_state[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(2),
I3 => \bit_cntr_reg__0\(4),
I4 => \bit_cntr_reg__0\(3),
O => eqOp
);
\FSM_onehot_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => '0',
Q => ldata_reg,
R => '0'
);
\FSM_onehot_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[1]_i_1_n_0\,
Q => \^out\(0),
R => '0'
);
\FSM_onehot_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_onehot_iis_state[2]_i_1_n_0\,
Q => p_0_in2_in,
R => '0'
);
\FSM_onehot_iis_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[3]_i_1_n_0\,
Q => \^out\(1),
R => '0'
);
\FSM_onehot_iis_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[4]_i_2_n_0\,
Q => \^out\(2),
R => '0'
);
\bit_cntr[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__2\(0)
);
\bit_cntr[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__2\(1)
);
\bit_cntr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__2\(2)
);
\bit_cntr[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \bit_cntr_reg__0\(2),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(1),
I3 => \bit_cntr_reg__0\(3),
O => \plusOp__2\(3)
);
\bit_cntr[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(2),
I1 => p_0_in2_in,
O => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr[4]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
I4 => \bit_cntr_reg__0\(4),
O => \plusOp__2\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1__0_n_0\
);
\ldata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_L_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => \ldata_reg[0]_i_1_n_0\
);
\ldata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(10),
O => \ldata_reg[10]_i_1_n_0\
);
\ldata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(11),
O => \ldata_reg[11]_i_1_n_0\
);
\ldata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(12),
O => \ldata_reg[12]_i_1_n_0\
);
\ldata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(13),
O => \ldata_reg[13]_i_1_n_0\
);
\ldata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(14),
O => \ldata_reg[14]_i_1_n_0\
);
\ldata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(15),
O => \ldata_reg[15]_i_1_n_0\
);
\ldata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(16),
O => \ldata_reg[16]_i_1_n_0\
);
\ldata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(17),
O => \ldata_reg[17]_i_1_n_0\
);
\ldata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(18),
O => \ldata_reg[18]_i_1_n_0\
);
\ldata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(19),
O => \ldata_reg[19]_i_1_n_0\
);
\ldata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(1),
O => \ldata_reg[1]_i_1_n_0\
);
\ldata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(20),
O => \ldata_reg[20]_i_1_n_0\
);
\ldata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(21),
O => \ldata_reg[21]_i_1_n_0\
);
\ldata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(22),
O => \ldata_reg[22]_i_1_n_0\
);
\ldata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => p_0_in2_in,
I1 => Q(0),
I2 => sclk_d1,
I3 => \^out\(0),
I4 => Q(1),
I5 => lrclk_d1,
O => \ldata_reg[23]_i_1__0_n_0\
);
\ldata_reg[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(23),
O => \ldata_reg[23]_i_2__0_n_0\
);
\ldata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(2),
O => \ldata_reg[2]_i_1_n_0\
);
\ldata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(3),
O => \ldata_reg[3]_i_1_n_0\
);
\ldata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(4),
O => \ldata_reg[4]_i_1_n_0\
);
\ldata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(5),
O => \ldata_reg[5]_i_1_n_0\
);
\ldata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(6),
O => \ldata_reg[6]_i_1_n_0\
);
\ldata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(7),
O => \ldata_reg[7]_i_1_n_0\
);
\ldata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(8),
O => \ldata_reg[8]_i_1_n_0\
);
\ldata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(9),
O => \ldata_reg[9]_i_1_n_0\
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[0]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[10]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[11]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[12]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[13]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[14]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[15]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[16]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[17]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[18]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[19]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[1]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[20]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[21]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[22]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[23]_i_2__0_n_0\,
Q => p_2_in,
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[2]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[3]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[4]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[5]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[6]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[7]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[8]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[9]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[9]\,
R => ldata_reg
);
\rdata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_R_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => p_1_in(0)
);
\rdata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(10),
O => p_1_in(10)
);
\rdata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(11),
O => p_1_in(11)
);
\rdata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(12),
O => p_1_in(12)
);
\rdata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(13),
O => p_1_in(13)
);
\rdata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(14),
O => p_1_in(14)
);
\rdata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(15),
O => p_1_in(15)
);
\rdata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(16),
O => p_1_in(16)
);
\rdata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(17),
O => p_1_in(17)
);
\rdata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(18),
O => p_1_in(18)
);
\rdata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(19),
O => p_1_in(19)
);
\rdata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(1),
O => p_1_in(1)
);
\rdata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(20),
O => p_1_in(20)
);
\rdata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(21),
O => p_1_in(21)
);
\rdata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(22),
O => p_1_in(22)
);
\rdata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(23),
O => p_1_in(23)
);
\rdata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(2),
O => p_1_in(2)
);
\rdata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(3),
O => p_1_in(3)
);
\rdata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(4),
O => p_1_in(4)
);
\rdata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(5),
O => p_1_in(5)
);
\rdata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(6),
O => p_1_in(6)
);
\rdata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(7),
O => p_1_in(7)
);
\rdata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(8),
O => p_1_in(8)
);
\rdata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(9),
O => p_1_in(9)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(0),
Q => \rdata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(10),
Q => \rdata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(11),
Q => \rdata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(12),
Q => \rdata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(13),
Q => \rdata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(14),
Q => \rdata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(15),
Q => \rdata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(16),
Q => \rdata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(17),
Q => \rdata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(18),
Q => \rdata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(19),
Q => \rdata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(1),
Q => \rdata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(20),
Q => \rdata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(21),
Q => \rdata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(22),
Q => \rdata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(23),
Q => \rdata_reg_reg_n_0_[23]\,
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(2),
Q => \rdata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(3),
Q => \rdata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(4),
Q => \rdata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(5),
Q => \rdata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(6),
Q => \rdata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(7),
Q => \rdata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(8),
Q => \rdata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(9),
Q => \rdata_reg_reg_n_0_[9]\,
R => ldata_reg
);
sdata_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCCAF0000CCA0"
)
port map (
I0 => \rdata_reg_reg_n_0_[23]\,
I1 => p_2_in,
I2 => \^out\(2),
I3 => p_0_in2_in,
I4 => \clk_cntr_reg[4]\,
I5 => \^sdata_o\,
O => sdata_reg_i_1_n_0
);
sdata_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => sdata_reg_i_1_n_0,
Q => \^sdata_o\,
R => ldata_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal I_DECODER_n_46 : STD_LOGIC;
signal I_DECODER_n_47 : STD_LOGIC;
signal I_DECODER_n_7 : STD_LOGIC;
signal I_DECODER_n_8 : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal timeout : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair4";
begin
S_AXI_BVALID <= \^s_axi_bvalid\;
S_AXI_RVALID <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => timeout,
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(3),
Q => timeout,
R => p_2_out
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(1) => I_DECODER_n_7,
D(0) => I_DECODER_n_8,
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \DataTx_R_reg[0]\,
\DataTx_R_reg[0]_0\ => \DataTx_R_reg[0]_0\,
\DataTx_R_reg[0]_1\ => \DataTx_R_reg[0]_1\,
\DataTx_R_reg[0]_2\ => \DataTx_R_reg[0]_2\,
\DataTx_R_reg[0]_3\ => \DataTx_R_reg[0]_3\,
\DataTx_R_reg[0]_4\ => \DataTx_R_reg[0]_4\,
\DataTx_R_reg[31]\(31 downto 0) => Q(31 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0) => timeout,
Q(1 downto 0) => state(1 downto 0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WVALID_0 => \state[1]_i_2_n_0\,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0,
s_axi_bvalid_i_reg => I_DECODER_n_47,
s_axi_bvalid_i_reg_0 => \state[0]_i_2_n_0\,
s_axi_bvalid_i_reg_1 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[31]\(31 downto 0) => IP2Bus_Data(31 downto 0),
s_axi_rvalid_i_reg => I_DECODER_n_46,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
\state_reg[1]\ => \state[1]_i_3_n_0\
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => SR(0),
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_47,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => S_AXI_RDATA(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => S_AXI_RDATA(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => S_AXI_RDATA(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => S_AXI_RDATA(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => S_AXI_RDATA(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => S_AXI_RDATA(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => S_AXI_RDATA(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => S_AXI_RDATA(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => S_AXI_RDATA(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => S_AXI_RDATA(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => S_AXI_RDATA(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => S_AXI_RDATA(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => S_AXI_RDATA(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => S_AXI_RDATA(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => S_AXI_RDATA(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => S_AXI_RDATA(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => S_AXI_RDATA(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => S_AXI_RDATA(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => S_AXI_RDATA(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => S_AXI_RDATA(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => S_AXI_RDATA(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => S_AXI_RDATA(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => S_AXI_RDATA(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => S_AXI_RDATA(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => S_AXI_RDATA(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => S_AXI_RDATA(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => S_AXI_RDATA(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => S_AXI_RDATA(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => S_AXI_RDATA(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => S_AXI_RDATA(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => S_AXI_RDATA(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => S_AXI_RDATA(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_46,
Q => \^s_axi_rvalid\,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07770000FFFF0000"
)
port map (
I0 => \^s_axi_bvalid\,
I1 => S_AXI_BREADY,
I2 => S_AXI_RREADY,
I3 => \^s_axi_rvalid\,
I4 => state(0),
I5 => state(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => S_AXI_RREADY,
I3 => S_AXI_BREADY,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_8,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_7,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
port (
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
data_rdy_bit : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
signal Inst_iis_deser_n_3 : STD_LOGIC;
signal Inst_iis_deser_n_33 : STD_LOGIC;
signal Inst_iis_deser_n_34 : STD_LOGIC;
signal Inst_iis_deser_n_35 : STD_LOGIC;
signal Inst_iis_deser_n_36 : STD_LOGIC;
signal Inst_iis_deser_n_37 : STD_LOGIC;
signal Inst_iis_deser_n_38 : STD_LOGIC;
signal Inst_iis_deser_n_39 : STD_LOGIC;
signal Inst_iis_deser_n_40 : STD_LOGIC;
signal Inst_iis_deser_n_41 : STD_LOGIC;
signal Inst_iis_deser_n_42 : STD_LOGIC;
signal Inst_iis_deser_n_43 : STD_LOGIC;
signal Inst_iis_deser_n_44 : STD_LOGIC;
signal Inst_iis_deser_n_45 : STD_LOGIC;
signal Inst_iis_deser_n_46 : STD_LOGIC;
signal Inst_iis_deser_n_47 : STD_LOGIC;
signal Inst_iis_deser_n_48 : STD_LOGIC;
signal Inst_iis_deser_n_49 : STD_LOGIC;
signal Inst_iis_deser_n_5 : STD_LOGIC;
signal Inst_iis_deser_n_50 : STD_LOGIC;
signal Inst_iis_deser_n_51 : STD_LOGIC;
signal Inst_iis_deser_n_52 : STD_LOGIC;
signal Inst_iis_deser_n_53 : STD_LOGIC;
signal Inst_iis_deser_n_54 : STD_LOGIC;
signal Inst_iis_deser_n_55 : STD_LOGIC;
signal Inst_iis_deser_n_56 : STD_LOGIC;
signal Inst_iis_deser_n_6 : STD_LOGIC;
signal Inst_iis_deser_n_7 : STD_LOGIC;
signal Inst_iis_deser_n_8 : STD_LOGIC;
signal Inst_iis_ser_n_1 : STD_LOGIC;
signal Inst_iis_ser_n_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \clk_cntr[10]_i_2_n_0\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[0]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[1]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[2]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[3]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[5]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[6]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[7]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[8]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[9]\ : STD_LOGIC;
signal data_rdy : STD_LOGIC;
signal \^data_rdy_bit\ : STD_LOGIC;
signal ldata_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal lrclk_d1 : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^s_axi_rdata_i_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rdata_i_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal sclk_d1 : STD_LOGIC;
signal write_bit : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \clk_cntr[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[7]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[8]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \clk_cntr[9]_i_1\ : label is "soft_lutpair15";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
SR(0) <= \^sr\(0);
data_rdy_bit <= \^data_rdy_bit\;
\s_axi_rdata_i_reg[31]\(31 downto 0) <= \^s_axi_rdata_i_reg[31]\(31 downto 0);
\s_axi_rdata_i_reg[31]_0\(31 downto 0) <= \^s_axi_rdata_i_reg[31]_0\(31 downto 0);
\DataRx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(0),
Q => \s_axi_rdata_i_reg[23]\(0),
R => '0'
);
\DataRx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(10),
Q => \s_axi_rdata_i_reg[23]\(10),
R => '0'
);
\DataRx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(11),
Q => \s_axi_rdata_i_reg[23]\(11),
R => '0'
);
\DataRx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(12),
Q => \s_axi_rdata_i_reg[23]\(12),
R => '0'
);
\DataRx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(13),
Q => \s_axi_rdata_i_reg[23]\(13),
R => '0'
);
\DataRx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(14),
Q => \s_axi_rdata_i_reg[23]\(14),
R => '0'
);
\DataRx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(15),
Q => \s_axi_rdata_i_reg[23]\(15),
R => '0'
);
\DataRx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(16),
Q => \s_axi_rdata_i_reg[23]\(16),
R => '0'
);
\DataRx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(17),
Q => \s_axi_rdata_i_reg[23]\(17),
R => '0'
);
\DataRx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(18),
Q => \s_axi_rdata_i_reg[23]\(18),
R => '0'
);
\DataRx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(19),
Q => \s_axi_rdata_i_reg[23]\(19),
R => '0'
);
\DataRx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(1),
Q => \s_axi_rdata_i_reg[23]\(1),
R => '0'
);
\DataRx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(20),
Q => \s_axi_rdata_i_reg[23]\(20),
R => '0'
);
\DataRx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(21),
Q => \s_axi_rdata_i_reg[23]\(21),
R => '0'
);
\DataRx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(22),
Q => \s_axi_rdata_i_reg[23]\(22),
R => '0'
);
\DataRx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(23),
Q => \s_axi_rdata_i_reg[23]\(23),
R => '0'
);
\DataRx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(2),
Q => \s_axi_rdata_i_reg[23]\(2),
R => '0'
);
\DataRx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(3),
Q => \s_axi_rdata_i_reg[23]\(3),
R => '0'
);
\DataRx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(4),
Q => \s_axi_rdata_i_reg[23]\(4),
R => '0'
);
\DataRx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(5),
Q => \s_axi_rdata_i_reg[23]\(5),
R => '0'
);
\DataRx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(6),
Q => \s_axi_rdata_i_reg[23]\(6),
R => '0'
);
\DataRx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(7),
Q => \s_axi_rdata_i_reg[23]\(7),
R => '0'
);
\DataRx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(8),
Q => \s_axi_rdata_i_reg[23]\(8),
R => '0'
);
\DataRx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(9),
Q => \s_axi_rdata_i_reg[23]\(9),
R => '0'
);
\DataRx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_56,
Q => \s_axi_rdata_i_reg[23]_0\(0),
R => '0'
);
\DataRx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_46,
Q => \s_axi_rdata_i_reg[23]_0\(10),
R => '0'
);
\DataRx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_45,
Q => \s_axi_rdata_i_reg[23]_0\(11),
R => '0'
);
\DataRx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_44,
Q => \s_axi_rdata_i_reg[23]_0\(12),
R => '0'
);
\DataRx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_43,
Q => \s_axi_rdata_i_reg[23]_0\(13),
R => '0'
);
\DataRx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_42,
Q => \s_axi_rdata_i_reg[23]_0\(14),
R => '0'
);
\DataRx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_41,
Q => \s_axi_rdata_i_reg[23]_0\(15),
R => '0'
);
\DataRx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_40,
Q => \s_axi_rdata_i_reg[23]_0\(16),
R => '0'
);
\DataRx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_39,
Q => \s_axi_rdata_i_reg[23]_0\(17),
R => '0'
);
\DataRx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_38,
Q => \s_axi_rdata_i_reg[23]_0\(18),
R => '0'
);
\DataRx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_37,
Q => \s_axi_rdata_i_reg[23]_0\(19),
R => '0'
);
\DataRx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_55,
Q => \s_axi_rdata_i_reg[23]_0\(1),
R => '0'
);
\DataRx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_36,
Q => \s_axi_rdata_i_reg[23]_0\(20),
R => '0'
);
\DataRx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_35,
Q => \s_axi_rdata_i_reg[23]_0\(21),
R => '0'
);
\DataRx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_34,
Q => \s_axi_rdata_i_reg[23]_0\(22),
R => '0'
);
\DataRx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_33,
Q => \s_axi_rdata_i_reg[23]_0\(23),
R => '0'
);
\DataRx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_54,
Q => \s_axi_rdata_i_reg[23]_0\(2),
R => '0'
);
\DataRx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_53,
Q => \s_axi_rdata_i_reg[23]_0\(3),
R => '0'
);
\DataRx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_52,
Q => \s_axi_rdata_i_reg[23]_0\(4),
R => '0'
);
\DataRx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_51,
Q => \s_axi_rdata_i_reg[23]_0\(5),
R => '0'
);
\DataRx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_50,
Q => \s_axi_rdata_i_reg[23]_0\(6),
R => '0'
);
\DataRx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_49,
Q => \s_axi_rdata_i_reg[23]_0\(7),
R => '0'
);
\DataRx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_48,
Q => \s_axi_rdata_i_reg[23]_0\(8),
R => '0'
);
\DataRx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_47,
Q => \s_axi_rdata_i_reg[23]_0\(9),
R => '0'
);
\DataTx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]\(0),
R => \^sr\(0)
);
\DataTx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]\(10),
R => \^sr\(0)
);
\DataTx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]\(11),
R => \^sr\(0)
);
\DataTx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]\(12),
R => \^sr\(0)
);
\DataTx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]\(13),
R => \^sr\(0)
);
\DataTx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]\(14),
R => \^sr\(0)
);
\DataTx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]\(15),
R => \^sr\(0)
);
\DataTx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]\(16),
R => \^sr\(0)
);
\DataTx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]\(17),
R => \^sr\(0)
);
\DataTx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]\(18),
R => \^sr\(0)
);
\DataTx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]\(19),
R => \^sr\(0)
);
\DataTx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]\(1),
R => \^sr\(0)
);
\DataTx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]\(20),
R => \^sr\(0)
);
\DataTx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]\(21),
R => \^sr\(0)
);
\DataTx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]\(22),
R => \^sr\(0)
);
\DataTx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]\(23),
R => \^sr\(0)
);
\DataTx_L_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]\(24),
R => \^sr\(0)
);
\DataTx_L_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]\(25),
R => \^sr\(0)
);
\DataTx_L_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]\(26),
R => \^sr\(0)
);
\DataTx_L_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]\(27),
R => \^sr\(0)
);
\DataTx_L_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]\(28),
R => \^sr\(0)
);
\DataTx_L_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]\(29),
R => \^sr\(0)
);
\DataTx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]\(2),
R => \^sr\(0)
);
\DataTx_L_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]\(30),
R => \^sr\(0)
);
\DataTx_L_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]\(31),
R => \^sr\(0)
);
\DataTx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]\(3),
R => \^sr\(0)
);
\DataTx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]\(4),
R => \^sr\(0)
);
\DataTx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]\(5),
R => \^sr\(0)
);
\DataTx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]\(6),
R => \^sr\(0)
);
\DataTx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]\(7),
R => \^sr\(0)
);
\DataTx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]\(8),
R => \^sr\(0)
);
\DataTx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]\(9),
R => \^sr\(0)
);
\DataTx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]_0\(0),
R => \^sr\(0)
);
\DataTx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]_0\(10),
R => \^sr\(0)
);
\DataTx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]_0\(11),
R => \^sr\(0)
);
\DataTx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]_0\(12),
R => \^sr\(0)
);
\DataTx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]_0\(13),
R => \^sr\(0)
);
\DataTx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]_0\(14),
R => \^sr\(0)
);
\DataTx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]_0\(15),
R => \^sr\(0)
);
\DataTx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]_0\(16),
R => \^sr\(0)
);
\DataTx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]_0\(17),
R => \^sr\(0)
);
\DataTx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]_0\(18),
R => \^sr\(0)
);
\DataTx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]_0\(19),
R => \^sr\(0)
);
\DataTx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]_0\(1),
R => \^sr\(0)
);
\DataTx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]_0\(20),
R => \^sr\(0)
);
\DataTx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]_0\(21),
R => \^sr\(0)
);
\DataTx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]_0\(22),
R => \^sr\(0)
);
\DataTx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]_0\(23),
R => \^sr\(0)
);
\DataTx_R_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]_0\(24),
R => \^sr\(0)
);
\DataTx_R_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]_0\(25),
R => \^sr\(0)
);
\DataTx_R_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]_0\(26),
R => \^sr\(0)
);
\DataTx_R_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]_0\(27),
R => \^sr\(0)
);
\DataTx_R_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]_0\(28),
R => \^sr\(0)
);
\DataTx_R_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]_0\(29),
R => \^sr\(0)
);
\DataTx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]_0\(2),
R => \^sr\(0)
);
\DataTx_R_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]_0\(30),
R => \^sr\(0)
);
\DataTx_R_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]_0\(31),
R => \^sr\(0)
);
\DataTx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]_0\(3),
R => \^sr\(0)
);
\DataTx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]_0\(4),
R => \^sr\(0)
);
\DataTx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]_0\(5),
R => \^sr\(0)
);
\DataTx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]_0\(6),
R => \^sr\(0)
);
\DataTx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]_0\(7),
R => \^sr\(0)
);
\DataTx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]_0\(8),
R => \^sr\(0)
);
\DataTx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]_0\(9),
R => \^sr\(0)
);
Inst_iis_deser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
port map (
\DataRx_L_reg[23]\(23 downto 0) => ldata_reg(23 downto 0),
\DataRx_R_reg[23]\(23) => Inst_iis_deser_n_33,
\DataRx_R_reg[23]\(22) => Inst_iis_deser_n_34,
\DataRx_R_reg[23]\(21) => Inst_iis_deser_n_35,
\DataRx_R_reg[23]\(20) => Inst_iis_deser_n_36,
\DataRx_R_reg[23]\(19) => Inst_iis_deser_n_37,
\DataRx_R_reg[23]\(18) => Inst_iis_deser_n_38,
\DataRx_R_reg[23]\(17) => Inst_iis_deser_n_39,
\DataRx_R_reg[23]\(16) => Inst_iis_deser_n_40,
\DataRx_R_reg[23]\(15) => Inst_iis_deser_n_41,
\DataRx_R_reg[23]\(14) => Inst_iis_deser_n_42,
\DataRx_R_reg[23]\(13) => Inst_iis_deser_n_43,
\DataRx_R_reg[23]\(12) => Inst_iis_deser_n_44,
\DataRx_R_reg[23]\(11) => Inst_iis_deser_n_45,
\DataRx_R_reg[23]\(10) => Inst_iis_deser_n_46,
\DataRx_R_reg[23]\(9) => Inst_iis_deser_n_47,
\DataRx_R_reg[23]\(8) => Inst_iis_deser_n_48,
\DataRx_R_reg[23]\(7) => Inst_iis_deser_n_49,
\DataRx_R_reg[23]\(6) => Inst_iis_deser_n_50,
\DataRx_R_reg[23]\(5) => Inst_iis_deser_n_51,
\DataRx_R_reg[23]\(4) => Inst_iis_deser_n_52,
\DataRx_R_reg[23]\(3) => Inst_iis_deser_n_53,
\DataRx_R_reg[23]\(2) => Inst_iis_deser_n_54,
\DataRx_R_reg[23]\(1) => Inst_iis_deser_n_55,
\DataRx_R_reg[23]\(0) => Inst_iis_deser_n_56,
E(0) => data_rdy,
\FSM_onehot_iis_state_reg[0]\ => Inst_iis_deser_n_6,
\FSM_onehot_iis_state_reg[0]_0\ => Inst_iis_deser_n_8,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_I => SDATA_I,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
\bit_cntr_reg[4]_0\(0) => write_bit,
data_rdy_bit => \^data_rdy_bit\,
data_rdy_bit_reg => Inst_iis_deser_n_7,
lrclk_d1 => lrclk_d1,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
\rdata_reg_reg[23]_0\(0) => Inst_iis_deser_n_3,
sclk_d1 => sclk_d1,
sdata_reg_reg => Inst_iis_deser_n_5
);
Inst_iis_ser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
port map (
\DataTx_L_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]\(23 downto 0),
\DataTx_R_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]_0\(23 downto 0),
E(0) => Inst_iis_deser_n_3,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
\clk_cntr_reg[4]\ => Inst_iis_deser_n_5,
lrclk_d1 => lrclk_d1,
lrclk_d1_reg => Inst_iis_deser_n_8,
lrclk_d1_reg_0 => Inst_iis_deser_n_6,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
sclk_d1 => sclk_d1,
sclk_d1_reg(0) => write_bit
);
\clk_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
O => \plusOp__0\(0)
);
\clk_cntr[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \clk_cntr_reg_n_0_[9]\,
I1 => \clk_cntr_reg_n_0_[7]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[6]\,
I4 => \clk_cntr_reg_n_0_[8]\,
I5 => \^q\(1),
O => \plusOp__0\(10)
);
\clk_cntr[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \clk_cntr[10]_i_2_n_0\
);
\clk_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
I1 => \clk_cntr_reg_n_0_[1]\,
O => \plusOp__0\(1)
);
\clk_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \clk_cntr_reg_n_0_[1]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[2]\,
O => \plusOp__0\(2)
);
\clk_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \clk_cntr_reg_n_0_[2]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[1]\,
I3 => \clk_cntr_reg_n_0_[3]\,
O => \plusOp__0\(3)
);
\clk_cntr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \clk_cntr_reg_n_0_[3]\,
I1 => \clk_cntr_reg_n_0_[1]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[2]\,
I4 => \^q\(0),
O => \plusOp__0\(4)
);
\clk_cntr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \plusOp__0\(5)
);
\clk_cntr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \clk_cntr[10]_i_2_n_0\,
I1 => \clk_cntr_reg_n_0_[6]\,
O => \plusOp__0\(6)
);
\clk_cntr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \clk_cntr_reg_n_0_[6]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[7]\,
O => \plusOp__0\(7)
);
\clk_cntr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \clk_cntr_reg_n_0_[7]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[6]\,
I3 => \clk_cntr_reg_n_0_[8]\,
O => \plusOp__0\(8)
);
\clk_cntr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \clk_cntr_reg_n_0_[8]\,
I1 => \clk_cntr_reg_n_0_[6]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[7]\,
I4 => \clk_cntr_reg_n_0_[9]\,
O => \plusOp__0\(9)
);
\clk_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(0),
Q => \clk_cntr_reg_n_0_[0]\,
R => '0'
);
\clk_cntr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(10),
Q => \^q\(1),
R => '0'
);
\clk_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(1),
Q => \clk_cntr_reg_n_0_[1]\,
R => '0'
);
\clk_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(2),
Q => \clk_cntr_reg_n_0_[2]\,
R => '0'
);
\clk_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(3),
Q => \clk_cntr_reg_n_0_[3]\,
R => '0'
);
\clk_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(4),
Q => \^q\(0),
R => '0'
);
\clk_cntr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(5),
Q => \clk_cntr_reg_n_0_[5]\,
R => '0'
);
\clk_cntr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(6),
Q => \clk_cntr_reg_n_0_[6]\,
R => '0'
);
\clk_cntr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(7),
Q => \clk_cntr_reg_n_0_[7]\,
R => '0'
);
\clk_cntr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(8),
Q => \clk_cntr_reg_n_0_[8]\,
R => '0'
);
\clk_cntr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(9),
Q => \clk_cntr_reg_n_0_[9]\,
R => '0'
);
data_rdy_bit_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Inst_iis_deser_n_7,
Q => \^data_rdy_bit\,
R => '0'
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXI_ARESETN,
O => \^sr\(0)
);
slv_ip2bus_data: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000400040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \s_axi_rdata_i_reg[24]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\DataTx_R_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\DataTx_R_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\DataTx_R_reg[0]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\DataTx_R_reg[0]_3\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\DataTx_R_reg[0]_4\ => Bus_RNW_reg,
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(31 downto 0) => Q(31 downto 0),
SR(0) => SR(0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal DataRx_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataRx_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataTx_L : STD_LOGIC_VECTOR ( 31 downto 0 );
signal DataTx_R : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal USER_LOGIC_I_n_0 : STD_LOGIC;
signal USER_LOGIC_I_n_69 : STD_LOGIC;
signal data_rdy_bit : STD_LOGIC;
begin
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\DataRx_L_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => DataRx_R(23 downto 0),
\DataTx_L_reg[0]\(0) => AXI_LITE_IPIF_I_n_12,
\DataTx_L_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
E(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => USER_LOGIC_I_n_0,
Q(31 downto 0) => DataTx_R(31 downto 0),
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => AXI_LITE_IPIF_I_n_8,
data_rdy_bit_reg_0 => AXI_LITE_IPIF_I_n_13
);
USER_LOGIC_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI_LITE_IPIF_I_n_13,
Q(1 downto 0) => \out\(1 downto 0),
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
data_rdy_bit => data_rdy_bit,
\s_axi_rdata_i_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\s_axi_rdata_i_reg[23]_0\(23 downto 0) => DataRx_R(23 downto 0),
\s_axi_rdata_i_reg[24]\ => USER_LOGIC_I_n_0,
\s_axi_rdata_i_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
\s_axi_rdata_i_reg[31]_0\(31 downto 0) => DataTx_R(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "i2s_ctrl,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
attribute max_fanout : string;
attribute max_fanout of S_AXI_ACLK : signal is "10000";
attribute sigis : string;
attribute sigis of S_AXI_ACLK : signal is "Clk";
attribute x_interface_info : string;
attribute x_interface_info of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of S_AXI_ACLK : signal is "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute max_fanout of S_AXI_ARESETN : signal is "10000";
attribute sigis of S_AXI_ARESETN : signal is "Rst";
attribute x_interface_info of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST";
attribute x_interface_parameter of S_AXI_ARESETN : signal is "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of S_AXI_AWADDR : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_WREADY <= \^s_axi_awready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
port map (
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(4 downto 2),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(4 downto 2),
S_AXI_AWREADY => \^s_axi_awready\,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
S_AXI_WVALID => S_AXI_WVALID,
\out\(1) => LRCLK,
\out\(0) => BCLK
);
end STRUCTURE;
| mit | 87b72cae38d4cb7ea5d69514b5123581 | 0.502873 | 2.611591 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/chip_8A_board.vhd | 1 | 13,436 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity chip_8A_board is
Port ( keyPad : in STD_LOGIC_VECTOR (15 downto 0);
gameSelect : in STD_LOGIC_VECTOR (3 downto 0);
clk, reset : in STD_LOGIC;
err_code : out STD_LOGIC_VECTOR( 2 downto 0 );
heart_beat, buzz : out STD_LOGIC;
cpu_active, mem_active, vga_active : out STD_LOGIC;
mapped_out : out STD_LOGIC_VECTOR( 7 downto 0 );
-- step : in STD_LOGIC; -- for debuging memory
VGA_HS_O : out STD_LOGIC;
VGA_VS_O : out STD_LOGIC;
VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0);
audioEn : out STD_LOGIC;
audioAMP: out STD_LOGIC
);
end chip_8A_board;
architecture Behavioral of chip_8A_board is
component core
port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
keyPad : in STD_LOGIC_VECTOR (15 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
cpu_state : out STD_LOGIC_VECTOR( 7 downto 0 );
t_PC : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_I : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_addr : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_n, t_x, t_y : out STD_LOGIC_VECTOR ( 3 downto 0 );
t_kk : out STD_LOGIC_VECTOR ( 7 downto 0 );
t_SP : out STD_LOGIC_VECTOR ( 7 downto 0 );
t_STACK_0, t_STACK_1, t_STACK_2, t_STACK_3,
t_STACK_4, t_STACK_5, t_STACK_6, t_STACK_7,
t_STACK_8, t_STACK_9, t_STACK_A, t_STACK_B,
t_STACK_C, t_STACK_D, t_STACK_E, t_STACK_F
: out STD_LOGIC_VECTOR (15 downto 0);
t_REG_0, t_REG_1, t_REG_2, t_REG_3,
t_REG_4, t_REG_5, t_REG_6, t_REG_7,
t_REG_8, t_REG_9, t_REG_A, t_REG_B,
t_REG_C, t_REG_D, t_REG_E, t_REG_F
: out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
active : out STD_LOGIC;
reset : in STD_LOGIC;
err_code : out STD_LOGIC_VECTOR( 2 downto 0 ));
end component;
component clock_div
port ( reset, clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC );
end component;
component mem_controller
port ( memAddress : in STD_LOGIC_VECTOR (35 downto 0);
dataIn : in STD_LOGIC_VECTOR (23 downto 0);
dataOut : out STD_LOGIC_VECTOR (23 downto 0);
valid : in STD_LOGIC_VECTOR (2 downto 0);
done : out STD_LOGIC_VECTOR (2 downto 0);
write : in STD_LOGIC_VECTOR (2 downto 0);
hold : in STD_LOGIC_VECTOR (2 downto 0);
gameSelect : in STD_LOGIC_VECTOR (3 downto 0);
gameSelected : out STD_LOGIC_VECTOR (3 downto 0);
mapped_out : out STD_LOGIC_VECTOR( 7 downto 0 );
debug_read_data : out STD_LOGIC_VECTOR( 7 downto 0 );
mem_state : out STD_LOGIC_VECTOR( 7 downto 0 );
sys_reset : out STD_LOGIC;
cpu_reset : out STD_LOGIC;
active : out STD_LOGIC;
step : in STD_LOGIC;
clk, reset : in STD_LOGIC);
end component;
component time_keeper
port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
heart_beat : out STD_LOGIC;
buzz : out STD_LOGIC);
end component;
component vga_controller
port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
active : out STD_LOGIC;
clk, sys_clk : in STD_LOGIC;
reset, sys_reset : in STD_LOGIC;
VGA_HS_O : out STD_LOGIC;
VGA_VS_O : out STD_LOGIC;
VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal s_CPU_memRead : STD_LOGIC_VECTOR (7 downto 0);
signal s_CPU_memWrite : STD_LOGIC_VECTOR (7 downto 0);
signal s_CPU_memAddress : STD_LOGIC_VECTOR (11 downto 0);
signal s_CPU_mem_valid : STD_LOGIC;
signal s_CPU_mem_write : STD_LOGIC;
signal s_CPU_mem_hold : STD_LOGIC;
signal s_CPU_mem_done : STD_LOGIC;
signal s_cpu_state : STD_LOGIC_VECTOR( 7 downto 0 );
signal s_TIME_memRead : STD_LOGIC_VECTOR (7 downto 0);
signal s_TIME_memWrite : STD_LOGIC_VECTOR (7 downto 0);
signal s_TIME_memAddress : STD_LOGIC_VECTOR (11 downto 0);
signal s_TIME_mem_valid : STD_LOGIC;
signal s_TIME_mem_write : STD_LOGIC;
signal s_TIME_mem_hold : STD_LOGIC;
signal s_TIME_mem_done : STD_LOGIC;
signal s_VGA_memRead : STD_LOGIC_VECTOR (7 downto 0);
signal s_VGA_memWrite : STD_LOGIC_VECTOR (7 downto 0);
signal s_VGA_memAddress : STD_LOGIC_VECTOR (11 downto 0);
signal s_VGA_mem_valid : STD_LOGIC;
signal s_VGA_mem_write : STD_LOGIC;
signal s_VGA_mem_hold : STD_LOGIC;
signal s_VGA_mem_done : STD_LOGIC;
signal s_gameSelected : STD_LOGIC_VECTOR (3 downto 0);
signal s_memAddress : STD_LOGIC_VECTOR (35 downto 0);
signal s_dataIn : STD_LOGIC_VECTOR (23 downto 0);
signal s_dataOut : STD_LOGIC_VECTOR (23 downto 0);
signal s_valid : STD_LOGIC_VECTOR (2 downto 0);
signal s_done : STD_LOGIC_VECTOR (2 downto 0);
signal s_write : STD_LOGIC_VECTOR (2 downto 0);
signal s_hold : STD_LOGIC_VECTOR (2 downto 0);
signal s_sys_reset : STD_LOGIC;
signal s_cpu_reset : STD_LOGIC;
signal s_mem_state : STD_LOGIC_VECTOR (7 downto 0);
signal s_debug_read_data : STD_LOGIC_VECTOR( 7 downto 0 );
signal s_step : STD_LOGIC;
signal s_clock : std_logic;
signal s_t_PC : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_t_I : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_t_addr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_t_n, s_t_x, s_t_y : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s_t_kk : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_t_SP : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_t_STACK_0, s_t_STACK_1, s_t_STACK_2, s_t_STACK_3,
s_t_STACK_4, s_t_STACK_5, s_t_STACK_6, s_t_STACK_7,
s_t_STACK_8, s_t_STACK_9, s_t_STACK_A, s_t_STACK_B,
s_t_STACK_C, s_t_STACK_D, s_t_STACK_E, s_t_STACK_F
: STD_LOGIC_VECTOR (15 downto 0);
signal s_t_REG_0, s_t_REG_1, s_t_REG_2, s_t_REG_3,
s_t_REG_4, s_t_REG_5, s_t_REG_6, s_t_REG_7,
s_t_REG_8, s_t_REG_9, s_t_REG_A, s_t_REG_B,
s_t_REG_C, s_t_REG_D, s_t_REG_E, s_t_REG_F
: STD_LOGIC_VECTOR (7 downto 0);
signal audioAMPsig : std_logic := '0';
signal counter: unsigned(15 DOWNTO 0) := x"0000";
signal s_buzz : STD_LOGIC;
begin
buzz <= s_buzz;
process(clk) begin
if rising_edge(clk) then
if(counter = 53628) then
audioAMPsig <= not(audioAMPsig);
counter <= x"0000";
else
counter <= counter + 1;
end if;
end if;
end process;
audioAMP <= audioAMPsig;
audioEn <= s_buzz;
s_step <= '0';
-- s_step <= step; -- for debugging memory
s_memAddress <= s_CPU_memAddress & s_TIME_memAddress & s_VGA_memAddress;
s_dataIn <= s_CPU_memWrite & s_TIME_memWrite & s_VGA_memWrite;
s_valid <= s_CPU_mem_valid & s_TIME_mem_valid & s_VGA_mem_valid;
s_write <= s_CPU_mem_write & s_TIME_mem_write & s_VGA_mem_write;
s_hold <= s_CPU_mem_hold & s_TIME_mem_hold & s_VGA_mem_hold;
s_CPU_memRead <= s_dataOut( 23 downto 16 );
s_TIME_memRead <= s_dataOut( 15 downto 8 );
s_VGA_memRead <= s_dataOut( 7 downto 0 );
s_CPU_mem_done <= s_done(2);
s_TIME_mem_done <= s_done(1);
s_VGA_mem_done <= s_done(0);
my_core : core
port map ( memRead => s_CPU_memRead,
memWrite => s_CPU_memWrite,
memAddress => s_CPU_memAddress,
keyPad => keyPad,
mem_valid => s_CPU_mem_valid,
mem_write => s_CPU_mem_write,
mem_hold => s_CPU_mem_hold,
mem_done => s_CPU_mem_done,
cpu_state => s_cpu_state,
t_PC => s_t_PC,
t_I => s_t_I,
t_addr => s_t_addr,
t_n => s_t_n, t_x => s_t_x, t_y => s_t_y,
t_kk => s_t_kk,
t_SP => s_t_SP,
t_STACK_0 => s_t_STACK_0, t_STACK_1 => s_t_STACK_1, t_STACK_2 => s_t_STACK_2, t_STACK_3 => s_t_STACK_3,
t_STACK_4 => s_t_STACK_4, t_STACK_5 => s_t_STACK_5, t_STACK_6 => s_t_STACK_6, t_STACK_7 => s_t_STACK_7,
t_STACK_8 => s_t_STACK_8, t_STACK_9 => s_t_STACK_9, t_STACK_A => s_t_STACK_A, t_STACK_B => s_t_STACK_B,
t_STACK_C => s_t_STACK_C, t_STACK_D => s_t_STACK_D, t_STACK_E => s_t_STACK_E, t_STACK_F => s_t_STACK_F,
t_REG_0 => s_t_REG_0, t_REG_1 => s_t_REG_1, t_REG_2 => s_t_REG_2, t_REG_3 => s_t_REG_3,
t_REG_4 => s_t_REG_4, t_REG_5 => s_t_REG_5, t_REG_6 => s_t_REG_6, t_REG_7 => s_t_REG_7,
t_REG_8 => s_t_REG_8, t_REG_9 => s_t_REG_9, t_REG_A => s_t_REG_A, t_REG_B => s_t_REG_B,
t_REG_C => s_t_REG_C, t_REG_D => s_t_REG_D, t_REG_E => s_t_REG_E, t_REG_F => s_t_REG_F,
clk => s_clock,
reset => s_cpu_reset,
active => cpu_active,
err_code => err_code);
my_clock_div : clock_div
port map ( reset => reset,
clk_in => clk,
clk_out => s_clock );
my_mem_controller : mem_controller
port map ( memAddress => s_memAddress,
dataIn => s_dataIn,
dataOut => s_dataOut,
valid => s_valid,
done => s_done,
write => s_write,
hold => s_hold,
gameSelect => gameSelect,
gameSelected => s_gameSelected,
mapped_out => mapped_out,
debug_read_data => s_debug_read_data,
mem_state => s_mem_state,
sys_reset => s_sys_reset,
cpu_reset => s_cpu_reset,
step => s_step,
clk => s_clock,
active => mem_active,
reset => reset );
my_time_keeper : time_keeper
port map ( memRead => s_TIME_memRead,
memWrite => s_TIME_memWrite,
memAddress => s_TIME_memAddress,
mem_valid => s_TIME_mem_valid,
mem_write => s_TIME_mem_write,
mem_hold => s_TIME_mem_hold,
mem_done => s_TIME_mem_done,
clk => s_clock,
reset => s_sys_reset,
heart_beat => heart_beat,
buzz => s_buzz );
my_vga_controller : vga_controller
port map ( memRead => s_VGA_memRead,
memWrite => s_VGA_memWrite,
memAddress => s_VGA_memAddress,
mem_valid => s_VGA_mem_valid,
mem_write => s_VGA_mem_write,
mem_hold => s_VGA_mem_hold,
mem_done => s_VGA_mem_done,
clk => clk,
sys_clk => s_clock,
active => vga_active,
reset => reset,
sys_reset => s_sys_reset,
VGA_HS_O => VGA_HS_O,
VGA_VS_O => VGA_VS_O,
VGA_RED_O => VGA_RED_O,
VGA_GREEN_O => VGA_GREEN_O,
VGA_BLUE_O => VGA_BLUE_O );
end Behavioral; | mit | 91845744889a63eb671137d4bfb4d551 | 0.481096 | 3.340627 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_0/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl | 1 | 856,369 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_0/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[18]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair2";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(0) <= \^q\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\,
I1 => \s_axi_arqos[3]\(25),
I2 => \s_axi_arqos[3]\(26),
I3 => \s_axi_arqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(32),
I1 => \s_axi_arqos[3]\(33),
I2 => \s_axi_arqos[3]\(34),
I3 => \s_axi_arqos[3]\(35),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(31),
I1 => \s_axi_arqos[3]\(30),
I2 => \s_axi_arqos[3]\(29),
I3 => \s_axi_arqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[24]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => S_AXI_ARREADY(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair14";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(0),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_awqos[3]\(29),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(31),
I4 => \s_axi_awqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_awqos[3]\(34),
I1 => \s_axi_awqos[3]\(35),
I2 => \s_axi_awqos[3]\(33),
I3 => \s_axi_awqos[3]\(32),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(34),
I2 => \s_axi_awqos[3]\(32),
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
I5 => \s_axi_awqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\,
I1 => \s_axi_awqos[3]\(25),
I2 => \s_axi_awqos[3]\(26),
I3 => \s_axi_awqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_awqos[3]\(32),
I1 => \s_axi_awqos[3]\(33),
I2 => \s_axi_awqos[3]\(34),
I3 => \s_axi_awqos[3]\(35),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_awqos[3]\(31),
I1 => \s_axi_awqos[3]\(30),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_awqos[3]\(40),
I1 => \s_axi_awqos[3]\(41),
I2 => \s_axi_awqos[3]\(38),
I3 => \s_axi_awqos[3]\(39),
I4 => \s_axi_awqos[3]\(43),
I5 => \s_axi_awqos[3]\(42),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[24]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_26_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_36_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_37_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_38_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_39_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair156";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid[0]\,
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8888888AAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \gen_multi_thread.accept_cnt_reg[0]\,
I2 => \^s_axi_bvalid[0]\,
I3 => p_0_out,
I4 => s_axi_bready(0),
I5 => Q(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\,
I1 => \s_axi_awaddr[30]\(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\,
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_2__0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(11),
I3 => w_issuing_cnt(9),
I4 => w_issuing_cnt(10),
O => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid[0]\
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[34]_4\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair123";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid[0]\,
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044444444"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => s_axi_arvalid(0),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \^s_axi_rvalid[0]\,
I4 => \m_payload_i_reg[34]_4\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(0),
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid[0]\
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair190";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair194";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal p_2_out : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_38__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I4 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
I2 => D(0),
I3 => D(1),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_37__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_2__1\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I4 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair62";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\,
I1 => D(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_35__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_36__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc : entity is "generic_baseblocks_v2_1_0_mux_enc";
end zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_34__0\ : label is "soft_lutpair128";
begin
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => \chosen_reg[0]\,
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_34__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \any_pop__1\ : STD_LOGIC;
signal \^p_0_out\ : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair162";
begin
p_0_out <= \^p_0_out\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => \^p_0_out\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^p_0_out\,
I2 => m_valid_i_reg,
O => \any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_araddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_27__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_29__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_32__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33__0\ : label is "soft_lutpair155";
begin
D(0) <= \^d\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_57\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_56\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.accept_cnt_reg__0\(3),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
\m_payload_i_reg[34]_4\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(0),
resp_select(0) => resp_select(2),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(0) => s_axi_rready(0),
\s_axi_rvalid[0]\ => \^s_axi_rvalid[0]\,
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(1),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
\chosen_reg[0]\ => \^s_axi_rvalid[0]\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_30__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_33__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_bvalid[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_15\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_29_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_32_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_35_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28__0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_30\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_35\ : label is "soft_lutpair189";
begin
D(2 downto 0) <= \^d\(2 downto 0);
SR(0) <= \^sr\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_0_out => p_0_out_0,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_bready(0) => s_axi_bready(0),
\s_axi_bvalid[0]\ => \^s_axi_bvalid[0]\,
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(2),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(2),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(2),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(2),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(2),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(2),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(2),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(1),
O => \^d\(1)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(2),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_15\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^s_axi_bvalid[0]\,
p_0_out => p_0_out_0,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(2)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_31__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair192";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1) => \s_axi_awaddr[30]\(2),
\s_axi_awaddr[30]\(0) => \s_axi_awaddr[30]\(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
D(0) => D(1),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(1),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1 downto 0) => \s_axi_awaddr[30]\(2 downto 1),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(2),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[23]\(13 downto 0) => \m_axi_bid[23]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
D(0) => D(0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[35]\(13 downto 0) => \m_axi_bid[35]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(2 downto 0) => D(2 downto 0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
\s_axi_rvalid[0]\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_79 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_99 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_12 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_10 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_3 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_5\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_11 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(2) => addr_arbiter_ar_n_79,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(1) => addr_arbiter_ar_n_80,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(0) => addr_arbiter_ar_n_81,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_82,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_83,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_88,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_89,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_90,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_85,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_86,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_87,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_99,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[24]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0
);
addr_arbiter_aw: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
E(0) => s_ready_i0_11,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_10,
match => match_3,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
\s_axi_awqos[3]\(68 downto 0) => D(68 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
ss_aa_awready => ss_aa_awready,
w_issuing_cnt(0) => w_issuing_cnt(32),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_12(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_80,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_79,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => \gen_master_slots[1].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_7\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\m_axi_bid[23]\(13 downto 2) => m_axi_bid(23 downto 12),
\m_axi_bid[23]\(1 downto 0) => m_axi_bresp(3 downto 2),
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
E(0) => \gen_master_slots[2].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_axi_bid[35]\(13 downto 2) => m_axi_bid(35 downto 24),
\m_axi_bid[35]\(1 downto 0) => m_axi_bresp(5 downto 4),
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_5\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => r_issuing_cnt(27 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_99,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_25,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_5\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(32),
\s_axi_araddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
\s_axi_araddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
\s_axi_araddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => \s_axi_rvalid[0]\,
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_11,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_10,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_3,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => \s_axi_bvalid[0]\,
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_3,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_xbar_0 : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
end zqynq_lab_1_design_xbar_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 002779553da5347625fda1a8d2599bf6 | 0.553516 | 2.621969 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/leon3sh.vhd | 1 | 6,522 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3sh
-- File: leon3sh.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3sh is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of leon3sh is
signal gnd, vcc : std_logic;
begin
gnd <= '0'; vcc <= '1';
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => fpui,
fpuo => fpuo,
clken => vcc);
end;
| gpl-2.0 | 64a09165ae2229208f91936aaec6a14d | 0.468261 | 3.976829 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/LIFO.vhd | 1 | 2,389 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity LIFO is
generic(
-- address bus
m: integer := 5;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- write/read operation type
WR: in std_logic;
-- read data bus
RB: out std_logic_vector(n-1 downto 0);
-- write data bus
WB: in std_logic_vector(n-1 downto 0)
);
end LIFO;
architecture Beh of LIFO is
-- word type
subtype word is std_logic_vector (n-1 downto 0);
-- storage
type tRam is array (0 to 2**m - 1) of word;
signal sRAM: tRam := (
(others => (others => '0'))
);
signal head: unsigned(m - 1 downto 0) := (others => '0');
signal data_rb: std_logic_vector(n-1 downto 0);
signal data_wb: std_logic_vector(n-1 downto 0);
constant Limit: unsigned(m - 1 downto 0) := to_unsigned(2 ** m -1, m);
Begin
SH: process (CLK)
begin
if (EN = '1') then
if rising_edge(CLK) then
if (WR = '0') then
if (head = Limit) then
head <= (others => '0');
else
head <= head + 1;
end if;
elsif (WR = '1') then
if (head = 0) then
head <= Limit;
else
head <= head - 1;
end if;
end if;
end if;
end if;
end process;
data_wb <= WB;
WRP: process (CLK, head, data_wb)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '0' then
sRAM(to_integer(head)) <= data_wb;
end if;
end if;
end if;
end process;
RDP: process(CLK, head)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '1' then
if (head = 0) then
data_rb <= sRAM (to_integer(Limit));
else
data_rb <= sRAM (to_integer(head - 1));
end if;
end if;
end if;
end if;
end process;
RB <= data_rb;
end Beh; | mit | 8cf10b4c763ae02482bc514ca9ea5019 | 0.434073 | 3.93575 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/synth/zynq_design_1_axi_gpio_0_0.vhd | 1 | 9,775 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zynq_design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zynq_design_1_axi_gpio_0_0;
ARCHITECTURE zynq_design_1_axi_gpio_0_0_arch OF zynq_design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_axi_gpio_0_0_arch : ARCHITECTURE IS "zynq_design_1_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "zynq_design_1_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_design_1_axi_gpio_0_0_arch;
| mit | be538a76940e20184c880ceab286000c | 0.68757 | 3.161384 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution4/syn/vhdl/matrix_mult.vhd | 1 | 43,612 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.402000,HLS_SYN_LAT=37,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=3,HLS_SYN_FF=1112,HLS_SYN_LUT=595}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal indvar_flatten_reg_104 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_115 : STD_LOGIC_VECTOR (2 downto 0);
signal j_reg_126 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond_flatten_fu_137_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_exitcond_flatten_reg_379 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next_fu_143_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal j_mid2_fu_161_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter1_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter2_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter3_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter4_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter5_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter6_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter7_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter8_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter9_j_mid2_reg_388 : STD_LOGIC_VECTOR (2 downto 0);
signal i_cast6_mid2_v_fu_169_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter1_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter2_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter3_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter4_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter5_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter6_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter7_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter8_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter9_i_cast6_mid2_v_reg_394 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_fu_177_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_17_fu_191_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_reg_417 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_fu_195_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_reg_422 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_6_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_6_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_6_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_reg_432 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_7_reg_432 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_7_reg_432 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_7_reg_432 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_reg_437 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_8_reg_437 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_8_reg_437 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_8_reg_437 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_8_reg_437 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_reg_442 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_9_reg_442 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_9_reg_442 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_9_reg_442 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_9_reg_442 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_reg_447 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_reg_452 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_reg_457 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_14_reg_457 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_14_reg_457 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_14_reg_457 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_reg_462 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_15_reg_462 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_15_reg_462 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_15_reg_462 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_285_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_reg_507 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_297_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_reg_522 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_358_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp1_reg_527 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_reg_pp0_iter9_tmp1_reg_527 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_365_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp4_reg_532 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_372_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp2_reg_537 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal tmp_5_fu_344_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_5_reg_542 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_4_fu_350_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_3_4_fu_350_p2 : signal is "no";
signal tmp_3_4_reg_547 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal i_phi_fu_119_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal i_cast6_mid2_fu_183_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal j_cast5_fu_187_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_cast_fu_354_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_fu_149_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_fu_324_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl_cast_fu_331_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal i_cast6_mid2_cast_fu_321_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast5_cast_fu_341_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_fu_335_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component matrix_mult_mul_8bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mul_8bkb_U0 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_18_reg_422,
din1 => tmp_17_reg_417,
ce => ap_const_logic_1,
dout => grp_fu_285_p2);
matrix_mult_mul_8bkb_U1 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_13_reg_452,
din1 => tmp_10_reg_447,
ce => ap_const_logic_1,
dout => grp_fu_297_p2);
matrix_mult_mac_mcud_U2 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_reg_pp0_iter5_tmp_7_reg_432,
din1 => ap_reg_pp0_iter5_tmp_6_reg_427,
din2 => tmp_16_reg_507,
ce => ap_const_logic_1,
dout => grp_fu_358_p3);
matrix_mult_mac_mcud_U3 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_reg_pp0_iter5_tmp_15_reg_462,
din1 => ap_reg_pp0_iter5_tmp_14_reg_457,
din2 => tmp_2_3_reg_522,
ce => ap_const_logic_1,
dout => grp_fu_365_p3);
matrix_mult_mac_mdEe_U4 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_reg_pp0_iter6_tmp_9_reg_442,
din1 => ap_reg_pp0_iter6_tmp_8_reg_437,
din2 => tmp4_reg_532,
ce => ap_const_logic_1,
dout => grp_fu_372_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
i_reg_115_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_379 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
i_reg_115 <= i_cast6_mid2_v_reg_394;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_115 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten_reg_104_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_0))) then
indvar_flatten_reg_104 <= indvar_flatten_next_fu_143_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_104 <= ap_const_lv5_0;
end if;
end if;
end process;
j_reg_126_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_0))) then
j_reg_126 <= j_1_fu_177_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_126 <= ap_const_lv3_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) then
ap_reg_pp0_iter10_exitcond_flatten_reg_379 <= ap_reg_pp0_iter9_exitcond_flatten_reg_379;
ap_reg_pp0_iter2_exitcond_flatten_reg_379 <= ap_reg_pp0_iter1_exitcond_flatten_reg_379;
ap_reg_pp0_iter2_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter1_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter2_j_mid2_reg_388 <= ap_reg_pp0_iter1_j_mid2_reg_388;
ap_reg_pp0_iter3_exitcond_flatten_reg_379 <= ap_reg_pp0_iter2_exitcond_flatten_reg_379;
ap_reg_pp0_iter3_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter2_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter3_j_mid2_reg_388 <= ap_reg_pp0_iter2_j_mid2_reg_388;
ap_reg_pp0_iter3_tmp_14_reg_457 <= tmp_14_reg_457;
ap_reg_pp0_iter3_tmp_15_reg_462 <= tmp_15_reg_462;
ap_reg_pp0_iter3_tmp_6_reg_427 <= tmp_6_reg_427;
ap_reg_pp0_iter3_tmp_7_reg_432 <= tmp_7_reg_432;
ap_reg_pp0_iter3_tmp_8_reg_437 <= tmp_8_reg_437;
ap_reg_pp0_iter3_tmp_9_reg_442 <= tmp_9_reg_442;
ap_reg_pp0_iter4_exitcond_flatten_reg_379 <= ap_reg_pp0_iter3_exitcond_flatten_reg_379;
ap_reg_pp0_iter4_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter3_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter4_j_mid2_reg_388 <= ap_reg_pp0_iter3_j_mid2_reg_388;
ap_reg_pp0_iter4_tmp_14_reg_457 <= ap_reg_pp0_iter3_tmp_14_reg_457;
ap_reg_pp0_iter4_tmp_15_reg_462 <= ap_reg_pp0_iter3_tmp_15_reg_462;
ap_reg_pp0_iter4_tmp_6_reg_427 <= ap_reg_pp0_iter3_tmp_6_reg_427;
ap_reg_pp0_iter4_tmp_7_reg_432 <= ap_reg_pp0_iter3_tmp_7_reg_432;
ap_reg_pp0_iter4_tmp_8_reg_437 <= ap_reg_pp0_iter3_tmp_8_reg_437;
ap_reg_pp0_iter4_tmp_9_reg_442 <= ap_reg_pp0_iter3_tmp_9_reg_442;
ap_reg_pp0_iter5_exitcond_flatten_reg_379 <= ap_reg_pp0_iter4_exitcond_flatten_reg_379;
ap_reg_pp0_iter5_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter4_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter5_j_mid2_reg_388 <= ap_reg_pp0_iter4_j_mid2_reg_388;
ap_reg_pp0_iter5_tmp_14_reg_457 <= ap_reg_pp0_iter4_tmp_14_reg_457;
ap_reg_pp0_iter5_tmp_15_reg_462 <= ap_reg_pp0_iter4_tmp_15_reg_462;
ap_reg_pp0_iter5_tmp_6_reg_427 <= ap_reg_pp0_iter4_tmp_6_reg_427;
ap_reg_pp0_iter5_tmp_7_reg_432 <= ap_reg_pp0_iter4_tmp_7_reg_432;
ap_reg_pp0_iter5_tmp_8_reg_437 <= ap_reg_pp0_iter4_tmp_8_reg_437;
ap_reg_pp0_iter5_tmp_9_reg_442 <= ap_reg_pp0_iter4_tmp_9_reg_442;
ap_reg_pp0_iter6_exitcond_flatten_reg_379 <= ap_reg_pp0_iter5_exitcond_flatten_reg_379;
ap_reg_pp0_iter6_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter5_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter6_j_mid2_reg_388 <= ap_reg_pp0_iter5_j_mid2_reg_388;
ap_reg_pp0_iter6_tmp_8_reg_437 <= ap_reg_pp0_iter5_tmp_8_reg_437;
ap_reg_pp0_iter6_tmp_9_reg_442 <= ap_reg_pp0_iter5_tmp_9_reg_442;
ap_reg_pp0_iter7_exitcond_flatten_reg_379 <= ap_reg_pp0_iter6_exitcond_flatten_reg_379;
ap_reg_pp0_iter7_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter6_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter7_j_mid2_reg_388 <= ap_reg_pp0_iter6_j_mid2_reg_388;
ap_reg_pp0_iter8_exitcond_flatten_reg_379 <= ap_reg_pp0_iter7_exitcond_flatten_reg_379;
ap_reg_pp0_iter8_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter7_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter8_j_mid2_reg_388 <= ap_reg_pp0_iter7_j_mid2_reg_388;
ap_reg_pp0_iter9_exitcond_flatten_reg_379 <= ap_reg_pp0_iter8_exitcond_flatten_reg_379;
ap_reg_pp0_iter9_i_cast6_mid2_v_reg_394 <= ap_reg_pp0_iter8_i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter9_j_mid2_reg_388 <= ap_reg_pp0_iter8_j_mid2_reg_388;
ap_reg_pp0_iter9_tmp1_reg_527 <= tmp1_reg_527;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_exitcond_flatten_reg_379 <= exitcond_flatten_reg_379;
ap_reg_pp0_iter1_i_cast6_mid2_v_reg_394 <= i_cast6_mid2_v_reg_394;
ap_reg_pp0_iter1_j_mid2_reg_388 <= j_mid2_reg_388;
exitcond_flatten_reg_379 <= exitcond_flatten_fu_137_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_0))) then
i_cast6_mid2_v_reg_394 <= i_cast6_mid2_v_fu_169_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_0))) then
j_mid2_reg_388 <= j_mid2_fu_161_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_reg_pp0_iter7_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
tmp1_reg_527 <= grp_fu_358_p3;
tmp4_reg_532 <= grp_fu_365_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9) and (ap_reg_pp0_iter8_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
tmp2_reg_537 <= grp_fu_372_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
tmp_10_reg_447 <= a_q0(31 downto 24);
tmp_13_reg_452 <= b_q0(31 downto 24);
tmp_14_reg_457 <= a_q0(39 downto 32);
tmp_15_reg_462 <= b_q0(39 downto 32);
tmp_17_reg_417 <= tmp_17_fu_191_p1;
tmp_18_reg_422 <= tmp_18_fu_195_p1;
tmp_6_reg_427 <= a_q0(15 downto 8);
tmp_7_reg_432 <= b_q0(15 downto 8);
tmp_8_reg_437 <= a_q0(23 downto 16);
tmp_9_reg_442 <= b_q0(23 downto 16);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter6_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
tmp_16_reg_507 <= grp_fu_285_p2;
tmp_2_3_reg_522 <= grp_fu_297_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
tmp_3_4_reg_547 <= tmp_3_4_fu_350_p2;
tmp_5_reg_542 <= tmp_5_fu_344_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten_fu_137_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011011, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0))) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_137_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
a_address0 <= i_cast6_mid2_fu_183_p1(3 - 1 downto 0);
a_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(2);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten_fu_137_p2)
begin
if ((exitcond_flatten_fu_137_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter10) and (ap_const_logic_0 = ap_enable_reg_pp0_iter11))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
b_address0 <= j_cast5_fu_187_p1(3 - 1 downto 0);
b_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
exitcond_flatten_fu_137_p2 <= "1" when (indvar_flatten_reg_104 = ap_const_lv5_19) else "0";
exitcond_fu_155_p2 <= "1" when (j_reg_126 = ap_const_lv3_5) else "0";
i_1_fu_149_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_phi_fu_119_p4));
i_cast6_mid2_cast_fu_321_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter9_i_cast6_mid2_v_reg_394),6));
i_cast6_mid2_fu_183_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast6_mid2_v_reg_394),32));
i_cast6_mid2_v_fu_169_p3 <=
i_1_fu_149_p2 when (exitcond_fu_155_p2(0) = '1') else
i_phi_fu_119_p4;
i_phi_fu_119_p4_assign_proc : process(i_reg_115, exitcond_flatten_reg_379, ap_CS_fsm_pp0_stage0, i_cast6_mid2_v_reg_394, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_379 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_phi_fu_119_p4 <= i_cast6_mid2_v_reg_394;
else
i_phi_fu_119_p4 <= i_reg_115;
end if;
end process;
indvar_flatten_next_fu_143_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_104) + unsigned(ap_const_lv5_1));
j_1_fu_177_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid2_fu_161_p3));
j_cast5_cast_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter9_j_mid2_reg_388),6));
j_cast5_fu_187_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_mid2_reg_388),32));
j_mid2_fu_161_p3 <=
ap_const_lv3_0 when (exitcond_fu_155_p2(0) = '1') else
j_reg_126;
p_shl_cast_fu_331_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_324_p3),6));
prod_address0 <= tmp_18_cast_fu_354_p1(5 - 1 downto 0);
prod_ce0_assign_proc : process(ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter11)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11))) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_d0 <= tmp_3_4_reg_547;
prod_we0_assign_proc : process(ap_block_pp0_stage0_flag00011001, ap_reg_pp0_iter10_exitcond_flatten_reg_379, ap_enable_reg_pp0_iter11)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_reg_pp0_iter10_exitcond_flatten_reg_379 = ap_const_lv1_0))) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
tmp_17_fu_191_p1 <= a_q0(8 - 1 downto 0);
tmp_18_cast_fu_354_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_reg_542),32));
tmp_18_fu_195_p1 <= b_q0(8 - 1 downto 0);
tmp_2_fu_335_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_331_p1) + unsigned(i_cast6_mid2_cast_fu_321_p1));
tmp_3_4_fu_350_p2 <= std_logic_vector(signed(tmp2_reg_537) + signed(ap_reg_pp0_iter9_tmp1_reg_527));
tmp_5_fu_344_p2 <= std_logic_vector(unsigned(j_cast5_cast_fu_341_p1) + unsigned(tmp_2_fu_335_p2));
tmp_fu_324_p3 <= (ap_reg_pp0_iter9_i_cast6_mid2_v_reg_394 & ap_const_lv2_0);
end behav;
| mit | 05a1b1edc157d810ae66a14bb19456b2 | 0.584449 | 2.847108 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-vc707/sgmii_vc707.vhd | 1 | 40,242 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_vc707 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
abits : integer := 8;
autonegotiation : integer := 1;
pirq : integer := 0;
debugmem : integer := 0;
tech : integer := 0;
simulation : integer := 0
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_vc707;
architecture top_level of sgmii_vc707 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii
port(
-- Transceiver Interface
------------------------
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
cplllock : out std_logic;
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
rxoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
rxuserclk : in std_logic; -- 125MHz clock.
rxuserclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
mmcm_locked : in std_logic; -- Locked signal from MMCM
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
--CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
--CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
--CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
--CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
--CLKOUT3_USE_FINE_PS : boolean := FALSE;
--CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
--CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
--CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
--CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
--SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component BUFHCE -----
component BUFHCE
generic (
CE_TYPE : string := "SYNC";
INIT_OUT : integer := 0
);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic
);
end component;
----- component BUFGMUX -----
component BUFGMUX
generic (
CLK_SEL_TYPE : string := "ASYNC"
);
port (
O : out std_ulogic := '0';
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic := '0'
);
end component;
----- component ODDR -----
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type sgmiiregs is record
irq : std_logic_vector(31 downto 0); -- interrupt
mask : std_logic_vector(31 downto 0); -- interrupt enable
configuration_vector : std_logic_vector( 4 downto 0);
an_adv_config_vector : std_logic_vector(15 downto 0);
end record;
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_configuration_vector : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(autonegotiation,1)) & "0000";
constant RES : sgmiiregs :=
( irq => (others => '0'), mask => (others => '0'),
configuration_vector => RES_configuration_vector, an_adv_config_vector => "0001100000000001");
type rxregs is record
gmii_rxd : std_logic_vector(7 downto 0);
gmii_rxd_int : std_logic_vector(7 downto 0);
gmii_rx_dv : std_logic;
gmii_rx_er : std_logic;
count : integer;
gmii_dv : std_logic;
keepalive : integer;
end record;
constant RESRX : rxregs :=
( gmii_rxd => (others => '0'), gmii_rxd_int => (others => '0'),
gmii_rx_dv => '0', gmii_rx_er => '0',
count => 0, gmii_dv => '0', keepalive => 0
);
type txregs is record
gmii_txd : std_logic_vector(7 downto 0);
gmii_txd_int : std_logic_vector(7 downto 0);
gmii_tx_en : std_logic;
gmii_tx_en_int : std_logic;
gmii_tx_er : std_logic;
count : integer;
cnt_en : std_logic;
keepalive : integer;
end record;
constant RESTX : txregs :=
( gmii_txd => (others => '0'), gmii_txd_int => (others => '0'),
gmii_tx_en => '0', gmii_tx_en_int => '0', gmii_tx_er => '0',
count => 0, cnt_en => '0', keepalive => 0
);
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal rxoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
signal rxuserclk : std_logic;
signal rxuserclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
-- Internal GMII signals from Xilinx SGMII block
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
signal status_vector_apb1 : std_logic_vector(31 downto 0);
signal status_vector_apb2 : std_logic_vector(31 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
-- Route gtrefclk through an IBUFG.
signal gtrefclk_buf_i : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
signal r, rin : sgmiiregs;
signal rrx,rinrx : rxregs;
signal rtx, rintx : txregs;
signal cnt_en : std_logic;
signal usr2rstn : std_logic;
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin
-----------------------------------------------------------------------------
-- Default for VC707
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
-- Configuration for Xilinx SGMII IP. See doc for SGMII IP for more information
an_adv_config_vector <= "0001100000000001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
gmiii.gtx_clk <= userclk2;
gmiii.tx_clk <= userclk2;
gmiii.rx_clk <= userclk2;
gmiii.rmii_clk <= userclk2;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.rx_en <= gmii_rx_dv or sgmii_clk_en;
--gmiii.tx_dv <= '1';
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
-- Not used
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
gmiii.tx_clk_90 <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
sgmii1 : if simulation = 1 generate
end generate;
sgmii0 : if simulation = 0 generate
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk_buf_i,
ODIV2 => open
);
bufhce_gtrefclk : BUFHCE
port map (
I => gtrefclk_buf_i,
CE => '1',
O => gtrefclk
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
--CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
--CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
--CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
--CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_rxuserclk: BUFG
port map (
I => rxoutclk,
O => rxuserclk
);
end generate;
-----------------------------------------------------------------------------
-- Sync Reset for user clock
-----------------------------------------------------------------------------
userclk2_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(apb_rstn, userclk2, '1', usr2rstn, open);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- GMII (Aeroflex Gaisler) to GMII (Xilinx) style
------------------------------------------------------------------------------
-- 10/100Mbit TX Loic
process (usr2rstn,rtx,gmiio)
variable v : txregs;
begin
v := rtx;
v.cnt_en := '0';
v.gmii_tx_en_int := gmiio.tx_en;
if (gmiio.tx_en = '1' and rtx.gmii_tx_en_int = '0') then
v.count := 0;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
else
v.count := rtx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_txd_int(3 downto 0) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
when 5 =>
if gmiio.speed = '1' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 50=>
if gmiio.speed = '0' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 9 =>
if gmiio.speed = '1' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when 99 =>
if gmiio.speed = '0' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when others =>
null;
end case;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '1') then
v.keepalive := 2;
end if;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '0' and rtx.keepalive = 0) then
v := RESTX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESTX;
end if;
-- update registers
rintx <= v;
end process;
txegs : process(userclk2)
begin
if rising_edge(userclk2) then
rtx <= rintx;
if RESET_ALL and usr2rstn = '0' then
rtx <= RESTX;
end if;
end if;
end process;
-- 1000Mbit TX Logic (Bypass)
-- n/a
-- TX Mux Select
cnt_en <= '1' when (gmiio.gbit = '1') else rtx.cnt_en;
gmii_txd <= gmiio.txd when (gmiio.gbit = '1') else rtx.gmii_txd;
gmii_tx_en <= gmiio.tx_en when (gmiio.gbit = '1') else rtx.gmii_tx_en;
gmii_tx_er <= gmiio.tx_er when (gmiio.gbit = '1') else rtx.gmii_tx_er;
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii
port map (
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
resetdone => resetdone,
cplllock => OPEN ,
txoutclk => txoutclk,
rxoutclk => rxoutclk ,
userclk => userclk,
userclk2 => userclk2,
rxuserclk => rxuserclk ,
rxuserclk2 => rxuserclk ,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
mmcm_locked => mmcm_locked,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect,
gt0_qplloutclk_in => '0',
gt0_qplloutrefclk_in => '0'
);
------------------------------------------------------------------------------
-- GMII (Xilinx) to GMII (Aeroflex Gailers) style
------------------------------------------------------------------------------
---- 10/100Mbit RX Loic
process (usr2rstn,rrx,gmii_rx_dv_int,gmii_rxd_int,gmii_rx_er_int,sgmii_clk_en)
variable v : rxregs;
begin
v := rrx;
if (gmii_rx_dv_int = '1' and sgmii_clk_en = '1') then
v.count := 0;
v.gmii_rxd_int := gmii_rxd_int;
v.gmii_dv := '1';
v.keepalive := 1;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
else
v.count := rrx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_rxd := v.gmii_rxd_int(3 downto 0) & v.gmii_rxd_int(3 downto 0);
v.gmii_rx_dv := v.gmii_dv;
when 5 =>
if gmiio.speed = '1' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when 50 =>
if gmiio.speed = '0' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when others =>
v.gmii_rxd := v.gmii_rxd;
v.gmii_rx_dv := '0';
end case;
v.gmii_rx_er := gmii_rx_er_int;
if (rrx.keepalive = 0 and gmii_rx_dv_int = '0') then
v := RESRX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESRX;
end if;
-- update registers
rinrx <= v;
end process;
rx100regs : process(userclk2)
begin
if rising_edge(userclk2) then
rrx <= rinrx;
if RESET_ALL and usr2rstn = '0' then
rrx <= RESRX;
end if;
end if;
end process;
---- 1000Mbit RX Logic (Bypass)
-- n/a
---- RX Mux Select
gmii_rxd <= gmii_rxd_int when (gmiio.gbit = '1') else rinrx.gmii_rxd;
gmii_rx_dv <= gmii_rx_dv_int when (gmiio.gbit = '1') else rinrx.gmii_rx_dv;
gmii_rx_er <= gmii_rx_er_int when (gmiio.gbit = '1') else rinrx.gmii_rx_er;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Extra registers to ease CDC placement
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb1 <= (others => '0');
status_vector_apb2 <= (others => '0');
if autonegotiation = 1 then status_vector_apb2(17) <= '1'; else status_vector_apb2(17) <= '0'; end if;
if debugmem = 1 then status_vector_apb2(16) <= '1'; else status_vector_apb2(16) <= '0'; end if;
-- Register to detect a speed change
status_vector_apb1(15 downto 0) <= status_vector_apb;
status_vector_apb2 <= status_vector_apb1;
end if;
end process;
rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : sgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(31 downto 0) := status_vector_apb2;
when "000001" =>
rdata(31 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(31 downto 0) := r.mask;
when "000011" =>
rdata(4 downto 0) := r.configuration_vector;
when "000100" =>
rdata(15 downto 0) := r.an_adv_config_vector;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(31 downto 0);
when "000011" =>
v.configuration_vector := apbi.pwdata(4 downto 0);
when "000100" =>
v.an_adv_config_vector := apbi.pwdata(15 downto 0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to status_vector_apb2'length-1 loop
if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
v := RES;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
r <= RES;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
WMemRgmiioData(15 downto 0) <= '0' & '0' & '0' & '0' & "00" & gmii_tx_er & gmii_tx_en & gmii_txd;
if (gmii_tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (gmii_tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
if usr2rstn = '0' then
WMemRgmiioAddr <= (others => '0');
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
userclk2, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
if (gmii_rx_dv = '1') then
WMemRgmiiiData(15 downto 0) <= '0' & sgmii_clk_en & '0' & '0' & "00" & gmii_rx_er & gmii_rx_dv & gmii_rxd;
elsif (gmii_rx_dv_int = '0') then
WMemRgmiiiData(15 downto 0) <= (others => '0');
else
WMemRgmiiiData <= WMemRgmiiiData;
end if;
if (gmii_rx_dv = '1') and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (gmii_rx_dv_int = '0') then
WMemRgmiiiAddr <= (others => '1');
WMemRgmiiiWrEn <= '0';
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
WMemRgmiiiWrEn <= '0';
end if;
end if;
if usr2rstn = '0' then
WMemRgmiiiAddr <= (others => '0');
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
userclk2, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sgmii" & tost(pindex) &
": SGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end top_level;
| gpl-2.0 | 113366b9c37efbc937ce874693c8362c | 0.483376 | 3.979235 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/grpci1/pci_mt.vhd | 1 | 28,846 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbreadword(ahbsi.hwdata)(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata(31 downto 0); v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= ahbdrivedata(r2.hrdata);
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbreadword(ahbsi.hwdata);
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
| gpl-2.0 | eae8001467d2b2fbe24feb7f5ee2e249 | 0.559003 | 2.923186 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/logan.vhd | 1 | 16,907 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
| gpl-2.0 | 15e454ef7803624d32bae5c1a0079fcb | 0.497368 | 3.864457 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/apbvga.vhd | 1 | 11,932 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbvga
-- File: vga.vhd
-- Author: Marcus Hellqvist
-- Description: VGA controller
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.charrom_package.all;
entity apbvga is
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port( rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end entity apbvga;
architecture rtl of apbvga is
type state_type is (s0,s1,s2);
constant RAM_DEPTH : integer := 12;
constant RAM_DATA_BITS : integer := 8;
constant MAX_FRAME : std_logic_vector((RAM_DEPTH-1) downto 0):= X"B90";
type ram_out_type is record
dataout2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
end record;
type vga_regs is record
video_out : std_logic_vector(23 downto 0);
hsync : std_ulogic;
vsync : std_ulogic;
csync : std_ulogic;
hcnt : std_logic_vector(9 downto 0);
vcnt : std_logic_vector(9 downto 0);
blank : std_ulogic;
linecnt : std_logic_vector(3 downto 0);
h_video_on : std_ulogic;
v_video_on : std_ulogic;
pixel : std_ulogic;
state : state_type;
rombit : std_logic_vector(2 downto 0);
romaddr : std_logic_vector(11 downto 0);
ramaddr2 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
raddr : std_logic_vector((RAM_DEPTH-1) downto 0);
tmp : std_logic_vector(RAM_DEPTH-1 downto 0);
end record;
type color_reg_type is record
bgcolor : std_logic_vector(23 downto 0);
txtcolor : std_logic_vector(23 downto 0);
end record;
type vmmu_reg_type is record
waddr : std_logic_vector((RAM_DEPTH-1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
ramaddr1 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain1 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
ramenable1 : std_ulogic;
ramwrite1 : std_ulogic;
color : color_reg_type;
end record;
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_VGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant hmax : integer:= 799;
constant vmax : integer:= 524;
constant hvideo : integer:= 639;
constant vvideo : integer:= 480;
constant hfporch : integer:= 19;
constant vfporch : integer:= 11;
constant hbporch : integer:= 45;
constant vbporch : integer:= 31;
constant hsyncpulse : integer:= 96;
constant vsyncpulse : integer:= 2;
constant char_height : std_logic_vector(3 downto 0):="1100";
signal p,pin : vmmu_reg_type;
signal ramo : ram_out_type;
signal r,rin : vga_regs;
signal romdata : std_logic_vector(7 downto 0);
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
comb1: process(rst,r,p,romdata,ramo)
variable v : vga_regs;
begin
v:=r;
v.wstartaddr := p.wstartaddr;
-- horizontal counter
if r.hcnt < conv_std_logic_vector(hmax,10) then
v.hcnt := r.hcnt +1;
else
v.hcnt := (others => '0');
end if;
-- vertical counter
if (r.vcnt >= conv_std_logic_vector(vmax,10)) and (r.hcnt >= conv_std_logic_vector(hmax,10)) then
v.vcnt := (others => '0');
elsif r.hcnt = conv_std_logic_vector(hmax,10) then
v.vcnt := r.vcnt +1;
end if;
-- horizontal pixel out
if r.hcnt <= conv_std_logic_vector(hvideo,10) then
v.h_video_on := '1';
else
v.h_video_on := '0';
end if;
-- vertical pixel out
if r.vcnt <= conv_std_logic_vector(vvideo,10) then
v.v_video_on := '1';
else
v.v_video_on := '0';
end if;
-- generate hsync
if (r.hcnt <= conv_std_logic_vector((hvideo+hfporch+hsyncpulse),10)) and
(r.hcnt >= conv_std_logic_vector((hvideo+hfporch),10)) then
v.hsync := '0';
else
v.hsync := '1';
end if;
-- generate vsync
if (r.vcnt <= conv_std_logic_vector((vvideo+vfporch+vsyncpulse),10)) and
(r.vcnt >= conv_std_logic_vector((vvideo+vfporch),10)) then
v.vsync := '0';
else
v.vsync := '1';
end if;
--generate csync & blank
v.csync := not (v.hsync xor v.vsync);
v.blank := v.h_video_on and v.v_video_on;
-- count line of character
if v.hcnt = conv_std_logic_vector(hvideo,10) then
if (r.linecnt = char_height) or (v.vcnt = conv_std_logic_vector(vmax,10)) then
v.linecnt := (others => '0');
else
v.linecnt := r.linecnt +1;
end if;
end if;
if v.blank = '1' then
case r.state is
when s0 => v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
v.state := s1;
when s1 => v.romaddr := v.linecnt & ramo.dataout2;
v.state := s2;
when s2 => if r.rombit = "011" then
v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
elsif r.rombit = "010" then
v.state := s1;
end if;
end case;
v.rombit := r.rombit - 1;
v.pixel := romdata(conv_integer(r.rombit));
end if;
-- read from same address char_height times
if v.raddr = (r.tmp + X"050") then
if (v.linecnt < char_height) then
v.raddr := r.tmp;
elsif v.raddr(11 downto 4) = X"FF" then --check for end of allowed memory(80x51)
v.raddr := (others => '0');
v.tmp := (others => '0');
else
v.tmp := r.tmp + X"050";
end if;
end if;
if v.v_video_on = '0' then
v.raddr := r.wstartaddr;
v.tmp := r.wstartaddr;
v.state := s0;
end if;
-- define pixel color
if v.pixel = '1'and v.blank = '1' then
v.video_out := p.color.txtcolor;
else
v.video_out := p.color.bgcolor;
end if;
if rst = '0' then
v.hcnt := conv_std_logic_Vector(hmax,10);
v.vcnt := conv_std_logic_Vector(vmax,10);
v.v_video_on := '0';
v.h_video_on := '0';
v.hsync := '0';
v.vsync := '0';
v.csync := '0';
v.blank := '0';
v.linecnt := (others => '0');
v.state := s0;
v.rombit := "111";
v.pixel := '0';
v.video_out := (others => '0');
v.raddr := (others => '0');
v.tmp := (others => '0');
v.ramaddr2 := (others => '0');
v.ramdatain2 := (others => '0');
end if;
-- update register
rin <= v;
-- drive outputs
vgao.hsync <= r.hsync;
vgao.vsync <= r.vsync;
vgao.comp_sync <= r.csync;
vgao.blank <= r.blank;
vgao.video_out_r <= r.video_out(23 downto 16);
vgao.video_out_g <= r.video_out(15 downto 8);
vgao.video_out_b <= r.video_out(7 downto 0);
vgao.bitdepth <= "11"; -- All data is valid
end process;
comb2: process(rst,r,p,apbi,ramo)
variable v : vmmu_reg_type;
variable rdata : std_logic_vector(31 downto 0);
begin
v := p;
v.ramenable1 := '0'; v.ramwrite1 := '0';
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.waddr := apbi.pwdata(19 downto 8);
v.ramdatain1 := apbi.pwdata(7 downto 0);
v.ramenable1 := '1';
v.ramwrite1 := '1';
v.ramaddr1 := apbi.pwdata(19 downto 8);
end if;
when "01" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.bgcolor := apbi.pwdata(23 downto 0);
end if;
when "10" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.txtcolor := apbi.pwdata(23 downto 0);
end if;
when others => null;
end case;
if (p.waddr - p.wstartaddr) >= MAX_FRAME then
if p.wstartaddr(11 downto 4) = X"FA" then --last position of allowed memory
v.wstartaddr := X"000";
else
v.wstartaddr := p.wstartaddr + X"050";
end if;
end if;
if rst = '0' then
v.waddr := (others => '0');
v.wstartaddr := (others => '0');
v.color.bgcolor := (others => '0');
v.color.txtcolor := (others => '1');
end if;
--update registers
pin <= v;
--drive outputs
apbo.prdata <= rdata;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end process;
apbo.pconfig <= pconfig;
reg : process(clk)
begin
if clk'event and clk = '1' then
p <= pin;
end if;
end process;
reg2 : process(vgaclk)
begin
if vgaclk'event and vgaclk = '1' then
r <= rin;
end if;
end process;
rom0 : charrom port map(clk=>vgaclk, addr=>r.romaddr, data=>romdata);
ram0 : syncram_2p generic map (tech => memtech, abits => RAM_DEPTH,
dbits => RAM_DATA_BITS, sepclk => 1)
port map (
rclk => vgaclk, raddress => r.ramaddr2, dataout => ramo.dataout2, renable => vcc,
wclk => clk, waddress => p.ramaddr1, datain => p.ramdatain1, write => p.ramwrite1
);
-- ram0 : syncram_dp generic map (tech => memtech, abits => RAM_DEPTH, dbits => RAM_DATA_BITS)
-- port map ( clk1 => clk, address1 => p.ramaddr1, datain1 => p.ramdatain1,
-- dataout1 => open, enable1 => p.ramenable1, write1 => p.ramwrite1,
-- clk2 => vgaclk, address2 => r.ramaddr2, datain2 => r.ramdatain2,
-- dataout2 => ramo.dataout2, enable2 => gnd, write2 => gnd);
-- pragma translate_off
bootmsg : report_version
generic map ("apbvga" & tost(pindex) & ": APB VGA module rev 0");
-- pragma translate_on
end architecture;
| gpl-2.0 | ba9ead9cdca69e8682da7d0698cb317c | 0.531009 | 3.504258 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/spw/wrapper/grspw_codec_gen.vhd | 1 | 7,725 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_codec_gen
-- File: grspw_codec_gen.vhd
-- Author: Marko Isomaki - Aeroflex Gaisler
-- Description: Generic wrapper for SpaceWire encoder-decoder
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 3 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end entity;
architecture rtl of grspw_codec_gen is
constant fabits : integer := log2(fifosize/4)+2;
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(9 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(9 downto 0);
signal rxerror : std_logic_vector(1 downto 0);
signal rxaccess : std_ulogic;
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(8 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(8 downto 0);
signal txerror : std_logic_vector(1 downto 0);
signal txaccess : std_ulogic;
signal testin : std_logic_vector(3 downto 0);
begin
testin <= testen & "000";
core : grspw_codec_core
generic map(
ports => ports,
input_type => input_type,
output_type => output_type,
rxtx_sameclk => rxtx_sameclk,
fifosize => fifosize,
tech => tech,
scantest => scantest
)
port map(
rst => rst,
clk => clk,
rxclk0 => rxclk0,
rxclk1 => rxclk1,
txclk => txclk,
txclkn => txclkn,
testen => testen,
testrst => testrst,
--spw in
d => d,
dv => dv,
dconnect => dconnect,
--spw out
do => do,
so => so,
--link fsm
linkdisabled => linkdisabled,
linkstart => linkstart,
autostart => autostart,
portsel => portsel,
noportforce => noportforce,
rdivisor => rdivisor,
idivisor => idivisor,
state => state,
actport => actport,
dconnecterr => dconnecterr,
crederr => crederr,
escerr => escerr,
parerr => parerr,
--rx fifo signals
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
rxaccess => rxaccess,
--rx iface
rxicharav => rxicharav,
rxicharcnt => rxicharcnt,
rxichar => rxichar,
rxiread => rxiread,
rxififorst => rxififorst,
--tx fifo signals
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
txaccess => txaccess,
--tx iface
txicharcnt => txicharcnt,
txifull => txifull,
txiempty => txiempty,
txiwrite => txiwrite,
txichar => txichar,
txififorst => txififorst,
txififorstact => txififorstact,
--time iface
tickin => tickin,
timein => timein,
tickin_done => tickin_done,
tickout => tickout,
timeout => timeout
);
ft0 : if ft = 0 generate
merror <= '0';
end generate;
ft1 : if ft /= 0 generate
merror <= (orv(rxerror) and rxaccess) or (orv(txerror) and txaccess);
end generate;
--receiver nchar FIFO
rx_ram : syncram_2pft generic map(tech*techfifo, fabits, 10, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk, rxwrite,
rxwaddress(fabits-1 downto 0), rxwdata, rxerror, testin);
--transmitter nchar FIFO
tx_ram : syncram_2pft generic map(tech*techfifo, fabits, 9, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk, txwrite,
txwaddress(fabits-1 downto 0), txwdata, txerror, testin);
end architecture;
| gpl-2.0 | 2b43ad3672228ba1359640c756f13b27 | 0.562977 | 3.929298 | false | true | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/util/util.vhd | 1 | 2,346 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_design is
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end;
architecture beh of report_design is
begin
x : report_version
generic map (
msg1 => msg1,
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & fabtech & ", memory library: " & memtech,
mdel => mdel);
end;
-- pragma translate_on
| gpl-2.0 | c30b446ef33dfd55d6c2a61178d8b7e2 | 0.606991 | 3.916528 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml403/testbench.vhd | 1 | 9,793 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | 78cb8f38e0a810784d3818403ddcb3b5 | 0.609313 | 3.003067 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/leon3mp.vhd | 1 | 35,477 | -----------------------------------------------------------------------------
-- LEON3 Xilinx SP605 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.ODDR2;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.pcie.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk27 : in std_ulogic; -- 27 MHz clock
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
clk33 : in std_ulogic; -- 32 MHz clock from sysace
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_reset_n : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqs_n : inout std_logic_vector (1 downto 0); -- ddr dqs_n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
button : inout std_logic_vector(3 downto 0); -- I/O port
switch : inout std_logic_vector(3 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_mii_int_n : in std_ulogic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
--pcie
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
--attribute syn_netlist_hierarchy : boolean;
--attribute syn_netlist_hierarchy of rtl : architecture is false;
component ODDR2
generic (
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 33000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_GRACECTRL;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
signal video_clk : std_ulogic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
ethclk <= lclk;
clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open);
reset_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= button(3);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp605 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 4, paddr => 4,
vgamst => CFG_SVGA_ENABLE, vgaburst => 64)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_reset_n=> ddr_reset_n,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n=> ddr_dqs_n(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqs_n(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_p => clk200p,
clk_mem_n => clk200n,
clk_125 => egtx_clk,
clk_50 => video_clk
);
end generate;
led(2) <= calib_done;
led(3) <= lock;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP:pcie_master_target_sp605
generic map (
master => CFG_PCIE_SIM_MAS,
hmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
hslvndx => 7,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG)
);
end generate;
----------------------------------------------------------------------
-----------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf_dma : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
dapbndx => 7, dapbaddr => 7,dapbmask => 16#FFF#, dapbirq => 4, blength => 12,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
slvndx => 7, apbndx => 5, apbaddr => 5, apbmask =>16#FFF#, haddr => 16#A00#, hmask => 16#FFF#,
nsync => 2, pcie_bar_mask => 16#FFE#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(7),
dahbmo =>ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG),
apbi =>apbi,
apbo =>apbo(5),
ahbmi =>ahbmi,
ahbsi =>ahbsi,
ahbso =>ahbso(7)
);
end generate;
pcie_mf: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_sp605
generic map (
memtech => memtech,
hslvndx => 7,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#A00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#)
port map(
rst => rstn,
clk => clkm,
-- System In
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Expre
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 5, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(16);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 8, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT, mode => 2)
port map (rstn, clkm, lclk, ahbsi, ahbso(8), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 8)
port map (sysace_d, aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
-- b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 6 generate
pio_pad : iopad generic map (tech => padtech)
port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
negtx_clk <= not egtx_clk;
x0 : ODDR2 port map ( Q => phy_gtx_clk, C0 => egtx_clk,
C1 => negtx_clk, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14),
ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_mii_int_n, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx SP605 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 3a2c21e46ae363137218b55ec3c0e78f | 0.548496 | 3.498373 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl | 1 | 29,735 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_1 : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_1;
architecture STRUCTURE of zynq_design_1_auto_pc_1 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 001034e2d24d7b29a5ddaa6a9ee16f98 | 0.640995 | 2.884653 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3mp/config.vhd | 1 | 7,707 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 4c66cec22ecff892aa30895af583184d | 0.64928 | 3.609836 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/system_monitor.vhd | 1 | 13,140 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: system_monitor
-- File: system_monitor.vhd
-- Author: Jan Andersson, Jiri Gaisler - Gaisler Research
-- Description: System monitor wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity system_monitor is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end system_monitor;
architecture struct of system_monitor is
component sysmon_virtex5
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component sysmon
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_DEVICE : string := "VIRTEX5";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
begin -- struct
gen: if not ((tech = virtex5) or (tech = virtex6) or (tech = virtex7) or (tech = kintex7)) generate
alm <= (others => '0');
busy <= '0';
channel <= (others => '0');
do <= (others => '0');
drdy <= '0';
eoc <= '0';
eos <= '0';
jtagbusy <= '0';
jtaglocked <= '0';
jtagmodified <= '0';
ot <= '0';
end generate gen;
v5: if tech = virtex5 generate
v50 : sysmon_virtex5
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v5;
v6: if tech = virtex6 generate
v60 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v6;
v7: if tech = virtex7 generate
v70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v7;
k7: if tech = kintex7 generate
k70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "KINTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate k7;
end struct;
| gpl-2.0 | 7d07215f86f7434be605064b1b880864 | 0.504033 | 3.499334 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-kc705/sgmii_kc705.vhd | 2 | 25,153 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.net.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_kc705 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
autonegotiation : integer := 1
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_kc705;
architecture top_level of sgmii_kc705 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii_block
port(
-- Transceiver Interface
------------------------
drpaddr_in : in std_logic_vector(8 downto 0);
drpclk_in : in std_logic;
drpdi_in : in std_logic_vector(15 downto 0);
drpdo_out : out std_logic_vector(15 downto 0);
drpen_in : in std_logic;
drprdy_out : out std_logic;
drpwe_in : in std_logic;
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
mmcm_locked : in std_logic; -- Locked signal from MMCM
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : boolean := FALSE;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
CLKSWING_CFG : bit_vector := "11"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
signal gmii_txd_int : std_logic_vector(7 downto 0);
signal gmii_tx_en_int : std_logic;
signal gmii_tx_er_int : std_logic;
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
begin
-----------------------------------------------------------------------------
-- Default for KC705
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
--an_adv_config_vector <= x"4001";
an_adv_config_vector <= "0000000000100001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= status_vector_apb;
gmiii.gtx_clk <= sgmii_clk;
gmiii.tx_clk <= sgmii_clk;
gmiii.rx_clk <= sgmii_clk;
gmii_txd <= gmiio.txd;
gmii_tx_en <= gmiio.tx_en;
gmii_tx_er <= gmiio.tx_er;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
gmiii.rmii_clk <= sgmii_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk,
ODIV2 => open
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii_block
port map (
drpaddr_in => "000000000",
drpclk_in => '0',
drpdi_in => "0000000000000000",
drpdo_out => OPEN,
drpen_in => '0',
drprdy_out => OPEN,
drpwe_in => '0',
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
txoutclk => txoutclk,
resetdone => resetdone,
mmcm_locked => mmcm_locked,
userclk => userclk,
userclk2 => userclk2,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
link_timer_value => link_timer_value,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect
);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd;
gmii_tx_en_int <= gmii_tx_en;
gmii_tx_er_int <= gmii_tx_er;
end if;
end process;
-----------------------------------------------------------------------------
-- SGMII clock logic
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
sgmii_clk_int <= sgmii_clk_r;
end if;
end process;
sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int;
-----------------------------------------------------------------------------
-- GMII receiver data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd <= gmii_rxd_int;
gmii_rx_dv <= gmii_rx_dv_int;
gmii_rx_er <= gmii_rx_er_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease IOB placement
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
status_vector <= status_vector_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
end top_level;
| gpl-2.0 | ea22bbbcd56bb2e75c1c8081f6c2d2f2 | 0.459746 | 4.286469 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/mul_inferred.vhd | 1 | 4,244 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
| gpl-2.0 | f984b5fb096caf13f825191d3b48d332 | 0.56951 | 3.566387 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution1/syn/vhdl/array_io_acc.vhd | 1 | 3,187 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity array_io_acc_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 32;
awidth : integer := 3;
mem_size : integer := 8
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of array_io_acc_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity array_io_acc is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 8;
AddressWidth : INTEGER := 3);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of array_io_acc is
component array_io_acc_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
array_io_acc_ram_U : component array_io_acc_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| mit | 8b26c32997f7c7173c8c94315113bdeb | 0.518983 | 3.633979 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-111/leon3mp.vhd | 1 | 16,594 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.11",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 9ef163625031c9cc61210ff79a1d5d46 | 0.533687 | 3.778233 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/GPR/src/Constants.vhd | 1 | 550 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package OneHotGPR is
subtype operation is std_logic_vector(2 downto 0);
subtype command is std_logic_vector(17 downto 0);
subtype mem_addr is std_logic_vector(4 downto 0);
subtype operand is std_logic_vector(15 downto 0);
constant ADD: operation := "001";
constant SUBT: operation := "010";
constant SHIFT: operation := "011";
constant JNZ: operation := "100";
constant COPY: operation := "101";
constant HALT: operation := "111";
end OneHotGPR; | mit | badc001cab049d4f03e6ed121a7dd525 | 0.658182 | 3.216374 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/8d6f9c45e1ea3378/zynq_design_1_auto_pc_1_sim_netlist.vhdl | 1 | 30,151 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | b9f2bac33f6f0c69a9e8a864cd367a44 | 0.645352 | 2.910609 | false | false | false | false |
Subsets and Splits