repo_name
stringlengths 6
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stringlengths 6
236
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int64 1
472
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
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class | config_or_test
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classes | has_no_keywords
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bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
freecores/mdct | source/xilinx/romo_xil.vhd | 1 | 4,350 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2005 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file romo_xil.vhd when simulating
-- the core, romo_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY romo_xil IS
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
END romo_xil;
ARCHITECTURE romo_xil_a OF romo_xil IS
-- synopsys translate_off
component wrapped_romo_xil
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
end component;
-- Configuration specification
for all : wrapped_romo_xil use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
generic map(
c_qualify_we => 0,
c_mem_type => 0,
c_has_qdpo_rst => 0,
c_has_qspo => 1,
c_has_qspo_rst => 0,
c_has_dpo => 0,
c_has_qdpo_clk => 0,
c_has_d => 0,
c_qce_joined => 0,
c_width => 14,
c_reg_a_d_inputs => 0,
c_latency => 1,
c_has_spo => 0,
c_has_we => 0,
c_depth => 64,
c_has_i_ce => 0,
c_default_data_radix => 2,
c_default_data => "0",
c_has_dpra => 0,
c_has_clk => 1,
c_enable_rlocs => 0,
c_generate_mif => 1,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qdpo_srst => 0,
c_mux_type => 0,
c_has_spra => 0,
c_has_qdpo => 0,
c_mem_init_file => "c:/elektronika/dct/mdct/source/xilinx/romo_xil.mif",
c_reg_dpra_input => 0,
c_has_qspo_srst => 0,
c_has_rd_en => 0,
c_read_mif => 1,
c_sync_enable => 0,
c_has_qdpo_ce => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_romo_xil
port map (
A => A,
CLK => CLK,
QSPO => QSPO);
-- synopsys translate_on
END romo_xil_a;
| lgpl-3.0 | 9a815584a1a4b7a81c5c237f0ffd4484 | 0.544368 | 3.947368 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/synth/convolve_kernel_ap_fadd_7_full_dsp_32.vhd | 1 | 14,033 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
| mit | 9745c0de98517f463bcdd48e155b78a9 | 0.661298 | 3.032851 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml501/testbench.vhd | 1 | 12,016 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.ml50x.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int : std_ulogic := '1';
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal sysace_clk_in : std_ulogic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_dvi <= 'H'; iic_sda_dvi <= 'H';
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, clk_200_p, clk_200_n, sysace_clk_in,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_oen,
sram_flash_we_n, flash_cen, flash_oen, flash_adv_n,sram_clk,
sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_dvi, iic_sda_dvi,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
-- ddr2mem : for i in 0 to 3 generate
-- u1 : ddr2
-- PORT MAP(
-- ck => ddr_clk(0), ck_n => ddr_clkb(0), cke => ddr_cke(0), cs_n => ddr_csb(0),
-- ras_n => ddr_rasb, cas_n => ddr_casb, we_n => ddr_web,
-- dm_rdqs => ddr_dm(i*2+1 downto i*2), ba => ddr_ba,
-- addr => ddr_ad(12 downto 0), dq => ddr_dq(i*16+15 downto i*16),
-- dqs => ddr_dqsp(i*2+1 downto i*2), dqs_n => ddr_dqsn(i*2+1 downto i*2),
-- rdqs_n => ddr_rdqs(i*2+1 downto i*2), odt => ddr_odt(0));
-- end generate;
ddr2ranks: for j in 0 to CS_NUM-1 generate
-- ddr2chips: for i in 0 to 3 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2),
-- LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1),
-- UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2),
-- WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(j),
-- BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(j),
-- CLK => ddr_clk(j), CLKB => ddr_clkb(j), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>0, density => 2,
lddelay => 100 us * CFG_MIG_DDR2)
port map (ck => ddr_clk(j), ckn => ddr_clkb(j), cke => ddr_cke(j), csn => ddr_csb(j),
odt => ddr_odt(j), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqsp, dqsn =>ddr_dqsn);
end generate;
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 4.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
-- p0: phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | dbdbb250d4eb915636752c637e27bbf1 | 0.608272 | 2.961065 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/synth/ip_design_axi_gpio_1_0.vhd | 1 | 11,081 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 16
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_16;
USE axi_gpio_v2_0_16.axi_gpio;
ENTITY ip_design_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ip_design_axi_gpio_1_0;
ARCHITECTURE ip_design_axi_gpio_1_0_arch OF ip_design_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_design_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ip_design_axi_gpio_1_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ip_design_axi_gpio_1_0_arch : ARCHITECTURE IS "ip_design_axi_gpio_1_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ip_design_axi_gpio_1_0_arch: ARCHITECTURE IS "ip_design_axi_gpio_1_0,axi_gpio,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=16,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=8,C_ALL_INPUTS=1,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 8,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END ip_design_axi_gpio_1_0_arch;
| mit | 970b5f70d858430b0d4b787bbdc3b1f8 | 0.6975 | 3.173253 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc7z020/config.vhd | 1 | 5,097 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 955e5dd1b145eabe60114d3979225674 | 0.639788 | 3.669546 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_adEe.vhd | 1 | 2,143 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_DSP48_0 is
port (
in0: in std_logic_vector(5 - 1 downto 0);
in1: in std_logic_vector(2 - 1 downto 0);
in2: in std_logic_vector(6 - 1 downto 0);
dout: out std_logic_vector(9 - 1 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_DSP48_0 is
signal b : signed(18-1 downto 0);
signal a : signed(25-1 downto 0);
signal d : signed(25-1 downto 0);
signal m : signed(43-1 downto 0);
signal ad : signed(25-1 downto 0);
begin
a <= signed(resize(signed(in0), 25));
d <= signed(resize(unsigned(in1), 25));
b <= signed(resize(unsigned(in2), 18));
ad <= a + d;
m <= ad * b;
dout <= std_logic_vector(resize(unsigned(m), 9));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_DSP48_0 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_DSP48_0_U : component convolve_kernel_adEe_DSP48_0
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
| mit | 4c81cdf49a85231fab219eb097e38e76 | 0.571162 | 3.296923 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-6/src/TB/RAM_T.vhd | 1 | 1,285 | library ieee;
use ieee.std_logic_1164.all;
entity RAM_T is
end RAM_T;
architecture Beh of RAM_T is
component RAM is
generic(
-- øèíà äàííûé
m: integer := 2;
-- øèíà àäðåñà
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- øèíà àäðåñà
AB: in std_logic_vector (m-1 downto 0);
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0)
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal AB: std_logic_vector (1 downto 0);
signal DB: std_logic_vector (1 downto 0);
constant CLK_period: time := 10 ns;
begin
URAM: RAM port map(
CLK => CLK,
WR => WR,
AB => AB,
DB => DB
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for CLK_Period;
AB <= "01";
DB <= "10";
wait for CLK_Period;
AB <= "10";
DB <= "01";
wait for CLK_Period;
WR <= '1';
DB <= "ZZ";
AB <= "01";
wait for CLK_Period;
DB <= "ZZ";
AB <= "10";
wait for CLK_Period;
wait;
end process;
end Beh;
configuration config of RAM_T is
for Beh
for URAM : RAM
use entity work.RAM(Beh);
end for;
end for;
end config; | mit | 8ddf96d3281a6ab175db5559d8526169 | 0.602335 | 2.514677 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/devices.vhd | 1 | 44,723 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Vendor and devices IDs for AMBA plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_DTU : amba_vendor_type := 16#0D#;
constant VENDOR_BSC : amba_vendor_type := 16#0E#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_C3E : amba_vendor_type := 16#C3#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
-- Aeroflex Gaisler device ids
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_SERIES7 : amba_device_type := 16#090#;
constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- European Space Agency device ids
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip IDs
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device ids
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- DTU device ids
constant DTU_IV : amba_device_type := 16#001#;
constant DTU_RBMMTRANS : amba_device_type := 16#002#;
constant DTU_FTMCTRL : amba_device_type := 16#054#;
-- BSC device ids
constant BSC_CORE1 : amba_device_type := 16#001#;
constant BSC_CORE2 : amba_device_type := 16#002#;
-- Orbita device ids
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library IDs
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device ids
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_NEXTREME1 : system_device_type := 16#0101#;
constant LEON4_NEXTREME1 : system_device_type := 16#0102#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID6RSNETH: system_device_type := 16#0196#;
constant LEON3_RTAX_KARI : system_device_type := 16#0197#;
constant LEON3_RTAX_IAA : system_device_type := 16#0198#;
constant LEON3_RTAX_TECNOBIT : system_device_type := 16#0199#;
constant LEON3_RTAX_TDP8 : system_device_type := 16#0200#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_IHP25RH1 : system_device_type := 16#0251#;
constant LEON3_PROXIMA : system_device_type := 16#0252#;
constant NGMP_PROTOTYPE : system_device_type := 16#0281#;
constant NGMP_PROTOTYPE2 : system_device_type := 16#0282#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant ALTERA_DE4 : system_device_type := 16#0303#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
constant ORBITA_1 : system_device_type := 16#0631#;
constant ORBITA_OBTMP : system_device_type := 16#0632#;
constant AEROFLEX_UT699 : system_device_type := 16#0699#;
constant AEROFLEX_UT700 : system_device_type := 16#0700#;
constant GAISLER_GR701 : system_device_type := 16#0701#;
constant GAISLER_GR702 : system_device_type := 16#0702#;
constant GAISLER_GR703 : system_device_type := 16#0703#;
constant GAISLER_DARE1 : system_device_type := 16#0704#;
constant GAISLER_GR712RC : system_device_type := 16#0712#;
constant GAISLER_SPWRTRASIC : system_device_type := 16#0718#;
constant AEROFLEX_UT840 : system_device_type := 16#0840#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Aeroflex Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_SERIES7 => "Xilinx MIG DDR3 Controller ",
GAISLER_GRSPW2_SIST => "GRSPW Router SIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "DMA Controller with APB bridge ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant bsc_device_table : device_table_type := (
BSC_CORE1 => "Core 1 ",
BSC_CORE2 => "Core 2 ",
others => "Unknown Device ");
constant BSC_DESC : vendor_description := "BSC ";
constant bsc_lib : vendor_library_type := (
vendorid => VENDOR_BSC,
vendordesc => BSC_DESC,
device_table => bsc_device_table
);
constant dtu_device_table : device_table_type := (
DTU_IV => "Instrument Virtualizer ",
DTU_RBMMTRANS => "RB/MM Transfer ",
DTU_FTMCTRL => "Memory controller with 8CS ",
others => "Unknown Device ");
constant DTU_DESC : vendor_description := "DTU Space ";
constant dtu_lib : vendor_library_type := (
vendorid => VENDOR_DTU,
vendordesc => DTU_DESC,
device_table => dtu_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant C3E_DESC : vendor_description := "TU Braunschweig C3E ";
constant c3e_device_table : device_table_type := (
others => "Unknown Device ");
constant c3e_lib : vendor_library_type := (
vendorid => VENDOR_C3E,
vendordesc => C3E_DESC,
device_table => c3e_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_NEXTREME1 => "LEON3 eASIC Nextreme controller",
LEON4_NEXTREME1 => "LEON4 eASIC Nextreme SoC ",
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ",
ALTERA_DE2 => "Altera DE2 Development board ",
ALTERA_DE4 => "TerASIC DE4 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
AEROFLEX_UT699 => "Aeroflex UT699 Rad-Hard CPU ",
AEROFLEX_UT700 => "Aeroflex UT700 Rad-Hard CPU ",
GAISLER_DARE1 => "Gaisler DARE1 Rad-Hard CPU ",
GAISLER_GR712RC => "Gaisler GR712RC Rad-Hard CPU ",
NGMP_PROTOTYPE => "NGMP Prototype System-on-Chip ",
NGMP_PROTOTYPE2 => "NGMP Prototype System-on-Chip ",
ORBITA_OBTMP => "Orbita LEON4 prototype system ",
GAISLER_SPWRTRASIC => "Gaisler SpaceWire Router ASIC ",
others => "Unknown system ");
-- pragma translate_on
end;
| gpl-2.0 | f229943883d38b6402fcf1f62b55dbc3 | 0.595108 | 3.685759 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/b9c82e235214f825/zynq_design_1_auto_pc_0_sim_netlist.vhdl | 1 | 533,310 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | cbd1ce72c71b7ac96d3045206ca76267 | 0.532034 | 2.542986 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pci_master.vhd | 1 | 19,230 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
v.grant := to_x01(pciin.ifc.frame) and to_x01(pciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(pciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := pciin.ad.ad; v.perr_cbe := pciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(pciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(pciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(pciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(pciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0' and to_x01(pciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(pciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(pciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(pciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
| gpl-2.0 | dec3329fd49916cefb7ca758a1a6771e | 0.528133 | 3.344348 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pci_monitor.vhd | 1 | 14,767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author:
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
entity pt_pci_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pt_pci_monitor;
architecture tb of pt_pci_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | 7efa353521ce228174293f4fdacbf665 | 0.529153 | 3.755595 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd | 1 | 15,265 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
| gpl-2.0 | 9fc8c4775675cb64a7697d415dc41194 | 0.507304 | 3.04569 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/greth/greth.vhd | 1 | 12,400 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1518;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed);
etho.txd(7 downto 4) <= "0000";
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
etho.gbit <= '0';
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 | c0abeb650fac7818453d4dbc43df2c22 | 0.521048 | 4.168067 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/libleon3.vhd | 1 | 7,842 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libleon3
-- File: libleon3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 internal components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libfpu.all;
use gaisler.mmuiface.all;
package libleon3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (
fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
rfft : integer range 0 to 2 := 0); -- 0 - no protection, 1 - parity
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component regfile_3p_l3
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
wrfst : integer := 0;
numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
end;
| gpl-2.0 | d3876748417ef8210e7d454ab9a0f724 | 0.475771 | 3.832845 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/synth/convolve_kernel_ap_fmul_3_max_dsp_32.vhd | 1 | 14,022 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_3_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_3_max_dsp_32_arch OF convolve_kernel_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=" &
"0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_" &
"THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_3_max_dsp_32_arch;
| mit | efc930bde3d2746efecd1c5196183366 | 0.661033 | 3.030473 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/pads_unisim.vhd | 1 | 40,266 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity unisim_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
cmos_15 : if voltage = x15v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS15") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity unisim_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad is
component IOBUF generic (
DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_15 : if voltage = x15v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity unisim_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_3: if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_25: if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_18: if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_15: if voltage = x15v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity unisim_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of unisim_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFT : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity unisim_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of unisim_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity unisim_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0;
tech : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of unisim_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFR port (O : out std_logic; I, CE, CLR : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
component DCM_SP
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFG : component is true;
attribute syn_noprune of IBUF : component is true;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
lock <= '1';
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
lock <= '1';
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
lock <= '1';
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
sp6 : if tech = spartan6 generate
dll: DCM_SP
generic map (CLK_FEEDBACK => "1X")
port map (
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => lock,
PSDONE => open,
STATUS => open,
CLKFB => ol3,
CLKIN => ol,
DSSEN => gnd,
PSCLK => gnd,
PSEN => gnd,
PSINCDEC => gnd,
RST => rst);
end generate;
nsp6 : if tech /= spartan6 generate
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
g4 : if arch = 4 generate
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
end generate;
gen0 : if (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
lock <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity unisim_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity unisim_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS_LVDS_25 : component is true;
attribute syn_noprune of IBUFGDS_LVDS_33 : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
xsstl : if level = sstl generate
sstl_18 : if voltage = x18v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL18")
port map (O => o, I => padp, IB => padn);
end generate;
sstl_15 : if voltage = x15v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL15")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if ((level /= lvds) and (level /= sstl)) generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity unisim_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_33")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
lvds_25 : if voltage /= x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_25")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_I")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
xsstl18_ii : if level = sstl18_ii generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_II")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
default : if (level /= lvds) and (level /= sstl18_i) and (level /= sstl18_ii) generate
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity unisim_outpad_ds is
generic (level : integer := lvds; slew : integer := 0; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad_ds is
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFDS : component is true;
begin
slow : if slew = 0 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
fast : if slew = 1 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
| gpl-2.0 | 46719fa2d71bc1e6f5d1b5e5bac5b0d3 | 0.582328 | 3.571897 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/b9c82e235214f825/zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl | 1 | 533,330 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:12:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | df74b67fe418f9b220dd7c58b41134b8 | 0.532046 | 2.542948 | false | false | false | false |
JimLewis/OSVVM | MemoryPkg.vhd | 1 | 27,689 | --
-- File Name: MemoryPkg.vhd
-- Design Unit Name: MemoryPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description
-- Package defines a protected type, MemoryPType, and methods
-- for efficiently implementing memory data structures
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 05/2005 0.1 Initial revision
-- 06/2015 2015.06 Updated for Alerts, ...
-- Numerous revisions for VHDL Testbenches and Verification
-- 01/2016 2016.01 Update for buf.all(buf'left)
-- 11/2016 2016.11 Refinement to MemRead to return value, X (if X), U (if not initialized)
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.numeric_std.all ;
use IEEE.numeric_std_unsigned.all ;
use IEEE.math_real.all ;
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
package MemoryPkg is
type MemoryPType is protected
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : in integer ) ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) ;
------------------------------------------------------------
procedure MemRead (
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase ;
procedure deallocate ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadH (FileName : string) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadB (FileName : string) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteH (FileName : string) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteB (FileName : string) ;
end protected MemoryPType ;
end MemoryPkg ;
package body MemoryPkg is
constant BLOCK_WIDTH : integer := 10 ;
type MemoryPType is protected body
type MemBlockType is array (integer range <>) of integer ;
type MemBlockPtrType is access MemBlockType ;
type MemArrayType is array (integer range <>) of MemBlockPtrType ;
type ArrayPtrVarType is access MemArrayType ;
variable ArrayPtrVar : ArrayPtrVarType := NULL ;
variable AddrWidthVar : integer := -1 ; -- set by MemInit - merges addr length and initialized checks.
variable DataWidthVar : natural := 1 ; -- set by MemInit
variable BlockkWidthVar : natural := 0 ; -- set by MemInit
variable AlertLogIDVar : AlertLogIDType := OSVVM_ALERTLOG_ID ;
type FileFormatType is (BINARY, HEX) ;
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : In integer ) is
------------------------------------------------------------
begin
if AddrWidth <= 0 then
Alert(AlertLogIDVar, "MemoryPType.MemInit. AddrWidth = " & to_string(AddrWidth) & " must be > 0.", FAILURE) ;
return ;
end if ;
if DataWidth <= 0 then
Alert(AlertLogIDVar, "MemoryPType.MemInit. DataWidth = " & to_string(DataWidth) & " must be > 0.", FAILURE) ;
return ;
end if ;
AddrWidthVar := AddrWidth ;
DataWidthVar := DataWidth ;
BlockkWidthVar := minimum(BLOCK_WIDTH, AddrWidth) ;
ArrayPtrVar := new MemArrayType(0 to 2**(AddrWidth-BlockkWidthVar)-1) ;
end procedure MemInit ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) is
------------------------------------------------------------
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
-- Check Bounds of Address and if memory is initialized
if Addr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Memory not initialized, Write Ignored.", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= DataWidthVar then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(DataWidthVar), FAILURE) ;
return ;
end if ;
if is_X( Addr ) then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Address X, Write Ignored.") ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockkWidthVar then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockkWidthVar)) ;
else
BlockAddr := 0 ;
end if ;
-- If empty, allocate a memory block
if (ArrayPtrVar(BlockAddr) = NULL) then
ArrayPtrVar(BlockAddr) := new MemBlockType(0 to 2**BlockkWidthVar-1) ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockkWidthVar -1 downto 0)) ;
-- Write to BlockAddr, WordAddr
if (Is_X(Data)) then
ArrayPtrVar(BlockAddr)(WordAddr) := -1 ;
else
ArrayPtrVar(BlockAddr)(WordAddr) := to_integer( Data ) ;
end if ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
Addr : In std_logic_vector ;
Data : Out std_logic_vector
) is
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
-- Check Bounds of Address and if memory is initialized
if Addr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.MemRead: Memory not initialized. Returning U", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.MemRead: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= DataWidthVar then
Alert(AlertLogIDVar, "MemoryPType.MemRead: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(DataWidthVar), FAILURE) ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- If Addr X, data = X
if is_X( aAddr ) then
Data := (Data'range => 'X') ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockkWidthVar then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockkWidthVar)) ;
else
BlockAddr := 0 ;
end if ;
-- Empty Block, return all U
if (ArrayPtrVar(BlockAddr) = NULL) then
Data := (Data'range => 'U') ;
return ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockkWidthVar -1 downto 0)) ;
if ArrayPtrVar(BlockAddr)(WordAddr) >= 0 then
-- Get the Word from the Array
Data := to_slv(ArrayPtrVar(BlockAddr)(WordAddr), Data'length) ;
elsif ArrayPtrVar(BlockAddr)(WordAddr) = -1 then
-- X in Word, return all X
Data := (Data'range => 'X') ;
else
-- Location Uninitialized, return all X
Data := (Data'range => 'U') ;
end if ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector is
------------------------------------------------------------
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
variable Data : std_logic_vector(DataWidthVar-1 downto 0) ;
begin
MemRead(Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase is
-- Deallocate the memory, but not the array of pointers
------------------------------------------------------------
begin
for BlockAddr in ArrayPtrVar'range loop
if (ArrayPtrVar(BlockAddr) /= NULL) then
deallocate (ArrayPtrVar(BlockAddr)) ;
end if ;
end loop ;
end procedure ;
------------------------------------------------------------
procedure deallocate is
-- Deallocate all allocated memory
------------------------------------------------------------
begin
MemErase ;
deallocate(ArrayPtrVar) ;
AddrWidthVar := -1 ;
DataWidthVar := 1 ;
BlockkWidthVar := 0 ;
end procedure ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar ;
end function GetAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure FileReadX (
-- Hexadecimal or Binary File Read
------------------------------------------------------------
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
-- Format:
-- @hh..h -- Address in hex
-- hhh_XX_ZZ -- data values in hex - space delimited
-- "--" or "//" -- comments
file MemFile : text open READ_MODE is FileName ;
variable Addr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable SmallAddr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable BigAddr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable Data : std_logic_vector(DataWidthVar - 1 downto 0) ;
variable LineNum : natural ;
variable ItemNum : natural ;
variable AddrInc : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean ;
variable NextChar : character ;
variable StrLen : integer ;
begin
MultiLineComment := FALSE ;
if StartAddr'length /= AddrWidthVar and EndAddr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.FileReadX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.FileReadX: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
Addr := StartAddr ;
LineNum := 0 ;
if StartAddr <= EndAddr then
SmallAddr := StartAddr ;
BigAddr := EndAddr ;
AddrInc := (AddrWidthVar -1 downto 0 => '0') + 1 ;
else
SmallAddr := EndAddr ;
BigAddr := StartAddr ;
AddrInc := (others => '1') ; -- -1
end if;
ReadLineLoop : while not EndFile(MemFile) loop
ReadLine(MemFile, buf) ;
LineNum := LineNum + 1 ;
ItemNum := 0 ;
ItemLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ItemLoop when Empty ;
ItemNum := ItemNum + 1 ;
NextChar := buf.all(buf'left) ;
if (NextChar = '@') then
-- Get Address
read(buf, NextChar) ;
ReadHexToken(buf, Addr, StrLen) ;
exit ReadLineLoop when AlertIf(AlertLogIDVar, StrLen = 0, "MemoryPType.FileReadX: Address length 0 on line: " & to_string(LineNum), FAILURE) ;
exit ItemLoop when AlertIf(AlertLogIDVar, Addr < SmallAddr,
"MemoryPType.FileReadX: Address in file: " & to_hstring(Addr) &
" < StartAddr: " & to_hstring(StartAddr) & " on line: " & to_string(LineNum)) ;
exit ItemLoop when AlertIf(AlertLogIDVar, Addr > BigAddr,
"MemoryPType.FileReadX: Address in file: " & to_hstring(Addr) &
" > EndAddr: " & to_hstring(BigAddr) & " on line: " & to_string(LineNum)) ;
elsif DataFormat = HEX and ishex(NextChar) then
-- Get Hex Data
ReadHexToken(buf, data, StrLen) ;
exit ReadLineLoop when AlertIfNot(AlertLogIDVar, StrLen > 0,
"MemoryPType.FileReadH: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log("MemoryPType.FileReadX: MemWrite(Addr => " & to_hstring(Addr) & ", Data => " & to_hstring(Data) & ")", DEBUG) ;
MemWrite(Addr, data) ;
Addr := Addr + AddrInc ;
elsif DataFormat = BINARY and isstd_logic(NextChar) then
-- Get Binary Data
-- read(buf, data, ReadValid) ;
ReadBinaryToken(buf, data, StrLen) ;
-- exit ReadLineLoop when AlertIfNot(AlertLogIDVar, ReadValid,
exit ReadLineLoop when AlertIfNot(AlertLogIDVar, StrLen > 0,
"MemoryPType.FileReadB: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log("MemoryPType.FileReadX: MemWrite(Addr => " & to_hstring(Addr) & ", Data => " & to_string(Data) & ")", DEBUG) ;
MemWrite(Addr, data) ;
Addr := Addr + AddrInc ;
else
-- Invalid Text, Issue Warning and skip it
Alert(AlertLogIDVar,
"MemoryPType.FileReadX: Invalid text on line: " & to_string(LineNum) &
" Item: " & to_string(ItemNum) & ". Skipping text: " & buf.all) ;
exit ItemLoop ;
end if ;
end loop ItemLoop ;
end loop ReadLineLoop ;
-- -- must read EndAddr-StartAddr number of words if both start and end specified
-- if (StartAddr /= 0 or (not EndAddr) /= 0) and (Addr /= EndAddr) then
-- Alert("MemoryPType.FileReadH: insufficient data values", WARNING) ;
-- end if ;
file_close(MemFile) ;
end FileReadX ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Read
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string) is
-- Hexadecimal File Read
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadB (
-- Binary File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Read
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string) is
-- Binary File Read
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- PT Local
procedure FileWriteX (
-- Hexadecimal or Binary File Write
------------------------------------------------------------
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
-- Format:
-- @hh..h -- Address in hex
-- hhhhh -- data one per line in either hex or binary as specified
file MemFile : text open WRITE_MODE is FileName ;
alias normStartAddr : std_logic_vector(StartAddr'length-1 downto 0) is StartAddr ;
alias normEndAddr : std_logic_vector(EndAddr'length-1 downto 0) is EndAddr ;
variable StartBlockAddr : natural ;
variable EndBlockAddr : natural ;
variable StartWordAddr : natural ;
variable EndWordAddr : natural ;
variable Data : std_logic_vector(DataWidthVar - 1 downto 0) ;
variable FoundData : boolean ;
variable buf : line ;
begin
if StartAddr'length /= AddrWidthVar and EndAddr'length /= AddrWidthVar then
-- Check StartAddr and EndAddr Widths and Memory not initialized
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.FileWriteX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
AlertIf(AlertLogIDVar, StartAddr'length /= AddrWidthVar, "MemoryPType.FileWriteX: StartAddr'length: "
& to_string(StartAddr'length) &
" /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
AlertIf(AlertLogIDVar, EndAddr'length /= AddrWidthVar, "MemoryPType.FileWriteX: EndAddr'length: "
& to_string(EndAddr'length) &
" /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
if StartAddr > EndAddr then
-- Only support ascending addresses
Alert(AlertLogIDVar, "MemoryPType.FileWriteX: StartAddr: " & to_hstring(StartAddr) &
" > EndAddr: " & to_hstring(EndAddr), FAILURE) ;
return ;
end if ;
-- Slice out upper address to form block address
if AddrWidthVar >= BlockkWidthVar then
StartBlockAddr := to_integer(normStartAddr(AddrWidthVar-1 downto BlockkWidthVar)) ;
EndBlockAddr := to_integer( normEndAddr(AddrWidthVar-1 downto BlockkWidthVar)) ;
else
StartBlockAddr := 0 ;
EndBlockAddr := 0 ;
end if ;
BlockAddrLoop : for BlockAddr in StartBlockAddr to EndBlockAddr loop
next BlockAddrLoop when ArrayPtrVar(BlockAddr) = NULL ;
if BlockAddr = StartBlockAddr then
StartWordAddr := to_integer(normStartAddr(BlockkWidthVar-1 downto 0)) ;
else
StartWordAddr := 0 ;
end if ;
if BlockAddr = EndBlockAddr then
EndWordAddr := to_integer(normEndAddr(BlockkWidthVar-1 downto 0)) ;
else
EndWordAddr := 2**BlockkWidthVar-1 ;
end if ;
FoundData := FALSE ;
WordAddrLoop : for WordAddr in StartWordAddr to EndWordAddr loop
if (ArrayPtrVar(BlockAddr)(WordAddr) < 0) then
-- X in Word, return all X
Data := (Data'range => 'X') ;
FoundData := FALSE ;
else
-- Get the Word from the Array
Data := to_slv(ArrayPtrVar(BlockAddr)(WordAddr), Data'length) ;
if not FoundData then
-- Write Address
write(buf, '@') ;
hwrite(buf, to_slv(BlockAddr, AddrWidthVar-BlockkWidthVar) & to_slv(WordAddr, BlockkWidthVar)) ;
writeline(MemFile, buf) ;
end if ;
FoundData := TRUE ;
end if ;
if FoundData then -- Write Data
if DataFormat = HEX then
hwrite(buf, Data) ;
writeline(MemFile, buf) ;
else
write(buf, Data) ;
writeline(MemFile, buf) ;
end if;
end if ;
end loop WordAddrLoop ;
end loop BlockAddrLoop ;
file_close(MemFile) ;
end FileWriteX ;
------------------------------------------------------------
procedure FileWriteH (
-- Hexadecimal File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Write
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string) is
-- Hexadecimal File Write
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteB (
-- Binary File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Write
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string) is
-- Binary File Write
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
end protected body MemoryPType ;
end MemoryPkg ; | artistic-2.0 | 2351ab160a1d9817708d39fb50aebb89 | 0.514681 | 4.688283 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-c5ekit/leon3mp.vhd | 1 | 28,025 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic; -- Driven const low by MAXV CPLD?
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : inout std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- This has been commented out as some pins have been placed in
-- violation with the Altera diff pad keep-out rules.
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic; -- changed due to placement rule
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic; -- in due to placement rule
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_greth1 : integer := hmi_cpu + CFG_NCPU;
constant hmi_greth2 : integer := hmi_greth1 + CFG_GRETH;
constant hmi_ahbuart : integer := hmi_greth2 + CFG_GRETH2;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant nahbm : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant hsi_ssrctrl : integer := 0;
constant hsi_apbctrl : integer := hsi_ssrctrl + (CFG_SSCTRL + CFG_AHBROMEN + 1)/2;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_lpddr2 : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_lpddr2 + 1;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_irqmp : integer := 0;
constant pi_apbuart : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_gpt : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant pi_ssrctrl : integer := pi_ahbuart + CFG_AHB_UART;
constant pi_greth1 : integer := pi_ssrctrl + CFG_SSCTRL;
constant pi_greth2 : integer := pi_greth1 + CFG_GRETH;
constant pi_i2cmst : integer := pi_greth2 + CFG_GRETH2;
constant napbs : integer := pi_i2cmst + CFG_I2C_ENABLE;
constant CPU_FREQ : integer := 75000;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal ui_serial, ui_usb, ui, dui: uart_in_type;
signal uo_serial, uo_usb, uo, duo: uart_out_type;
signal ethi1,ethi2: eth_in_type;
signal etho1,etho2: eth_out_type;
signal i2ci: i2c_in_type;
signal i2co: i2c_out_type;
signal vcc, gnd: std_ulogic;
-- signal logsig: std_logic_vector(31 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
user_led(0) <= not clklock;
clkgen0: entity work.clkgen_c5ekit
port map (clkin_50_fpga_right, clkm, open, clklock);
rstgen0: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (cpu_resetn, clkm, clklock, rstn);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU, timer and IRQ controller
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (user_led(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (user_pb(3), dsui.break);
user_led(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
irqi(i).rst <= '1';
irqi(i).run <= '1';
irqi(i).rstvec <= (others => '0');
irqi(i).iact <= '0';
irqi(i).index <= (others => '0');
irqi(i).hrdrst <= '1';
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; gpti.wdogen <= '0';
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-- EDCL included in Ethernet below
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
fm_a <= del_addr; -- sro.address(26 downto 1);
-- fm_d_pad: iopadvv
-- generic map (tech => padtech, width => 16)
-- port map (pad => fm_d, i => sro.data(31 downto 16),
-- en => sro.vbdrive(31 downto 16), o => sri.data(31 downto 16));
sri.data(31 downto 16) <= fm_d;
flash_clk <= '0';
flash_resetn <= '1';
flash_cen <= '0'; -- sro.romsn(0);
flash_advn <= '0';
flash_wen <= sro.writen or sro.romsn(0);
flash_oen <= sro.oen or sro.romsn(0);
ssram_clk <= clkm;
ssram_oen <= sro.oen;
sram_cen <= del_ce; -- sro.ramsn(0);
ssram_bwen <= del_bwe(1); -- sro.writen;
ssram_bwan <= del_bwa(1); -- sro.wrn(0);
ssram_bwbn <= del_bwb(1); -- sro.wrn(1);
ssram_adscn <= '1';
ssram_adspn <= '0';
ssram_zzn <= '0';
ssram_advn <= '1';
sri.data(15 downto 0) <= sri.data(31 downto 16);
sri.brdyn <= '1';
sri.bexcn <= '1';
sri.writen <= '1';
sri.wrn <= (others => '1');
sri.bwidth <= "01";
sri.sd <= (others => '0');
sri.cb <= (others => '0');
sri.scb <= (others => '0');
sri.edac <= '0';
delproc: process(clkm)
begin
if rising_edge(clkm) then
del_addr <= sro.address(26 downto 1);
del_ce <= sro.ramsn(0);
del_bwe <= del_bwe(0) & sro.writen;
del_bwa <= del_bwa(0) & sro.wrn(0);
del_bwb <= del_bwb(0) & sro.wrn(1);
end if;
end process;
ssrctrl: if CFG_SSCTRL = 1 generate
ssrctrl0: gaisler.memctrl.ssrctrl
generic map (hindex => hsi_ssrctrl, pindex => pi_ssrctrl,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
bus16 => CFG_SSCTRLP16
)
port map (rstn, clkm, ahbsi, ahbso(hsi_ssrctrl), apbi, apbo(pi_ssrctrl), sri, sro);
end generate;
nossrctrl: if CFG_SSCTRL = 0 generate
sro <= memory_out_none;
end generate;
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SSCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ssrctrl, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ssrctrl));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#E00#
) port map (
pll_ref_clk => diff_clkin_top_125_p,
global_reset_n => cpu_resetn,
mem_a => ddr3_a,
mem_ba => ddr3_ba,
mem_ck => ddr3_ck_p,
mem_ck_n => ddr3_ck_n,
mem_cke => ddr3_cke,
mem_reset_n => ddr3_rstn,
mem_cs_n => ddr3_csn,
mem_dm => ddr3_dm,
mem_ras_n => ddr3_rasn,
mem_cas_n => ddr3_casn,
mem_we_n => ddr3_wen,
mem_dq => ddr3_dq,
mem_dqs => ddr3_dqs_p,
mem_dqs_n => ddr3_dqs_n,
mem_odt => ddr3_odt,
oct_rzqin => ddr3_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
lpddr2if0: entity work.lpddr2if
generic map (
hindex => hsi_lpddr2,
haddr => 16#600#, hmask => 16#F00#
) port map (
pll_ref_clk => diff_clkin_bot_125_p,
global_reset_n => cpu_resetn,
mem_ca => lpddr2_a,
mem_ck => lpddr2_ck_p,
mem_ck_n => lpddr2_ck_n,
mem_cke => lpddr2_cke,
mem_cs_n => lpddr2_csn,
mem_dm => lpddr2_dm,
mem_dq => lpddr2_dq,
mem_dqs => lpddr2_dqs_p,
mem_dqs_n => lpddr2_dqs_n,
oct_rzqin => lpddr2_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_lpddr2)
);
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
srx_pad : inpad generic map (tech => padtech) port map (uart_rxd, ui_serial.rxd);
srts_pad : inpad generic map (tech => padtech) port map (uart_rts, ui_serial.ctsn);
stx_pad : outpad generic map (tech => padtech) port map (uart_txd, uo_serial.txd);
scts_pad : outpad generic map (tech => padtech) port map (uart_cts, uo_serial.rtsn);
urx_pad : inpad generic map (tech => padtech) port map (usb_uart_rxd, ui_usb.rxd);
urts_pad : inpad generic map (tech => padtech) port map (usb_uart_rts, ui_usb.ctsn);
utx_pad : outpad generic map (tech => padtech) port map (usb_uart_txd, uo_usb.txd);
ucts_pad : outpad generic map (tech => padtech) port map (usb_uart_cts, uo_usb.rtsn);
usb_uart_dtr <= '0';
ui_serial.extclk <= '0'; ui_usb.extclk <= '0';
-- UART switch
ui <= ui_serial when user_dipsw(0)='0' else ui_usb;
dui <= ui_usb when user_dipsw(0)='0' else ui_serial;
uo_serial <= uo when user_dipsw(0)='0' else duo;
uo_usb <= duo when user_dipsw(0)='0' else uo;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate
uo.rtsn <= '0'; uo.txd <= '0'; uo.scaler <= (others => '0');
uo.txen <= '0'; uo.flow <= '0'; uo.rxen <= '0';
end generate;
-- AHBUART, see under Debug links above
-----------------------------------------------------------------------------
-- Ethernet
-----------------------------------------------------------------------------
emdio_pad : iopad generic map (tech => padtech)
port map (eneta_mdio, etho1.mdio_o, etho1.mdio_oe, ethi1.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_tx_clk, ethi1.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_rx_clk, ethi1.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (eneta_rx_d, ethi1.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (eneta_rx_dv, ethi1.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (eneta_rx_er, ethi1.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eneta_rx_col, ethi1.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eneta_rx_crs, ethi1.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (eneta_intn, ethi1.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (eneta_tx_d, etho1.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eneta_tx_en, etho1.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (eneta_tx_er, etho1.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (eneta_mdc, etho1.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eneta_resetn, rstn);
ethi1.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi1.gtx_clk <= '0'; ethi1.rmii_clk <= '0';
emdio_pad2 : iopad generic map (tech => padtech)
port map (enetb_mdio, etho2.mdio_o, etho2.mdio_oe, ethi2.mdio_i);
etxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_tx_clk, ethi2.tx_clk);
erxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_rx_clk, ethi2.rx_clk);
erxd_pad2 : inpadv generic map (tech => padtech, width => 4)
port map (enetb_rx_d, ethi2.rxd(3 downto 0));
erxdv_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_dv, ethi2.rx_dv);
erxer_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_er, ethi2.rx_er);
erxco_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_col, ethi2.rx_col);
erxcr_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_crs, ethi2.rx_crs);
emdint_pad2 : inpad generic map (tech => padtech)
port map (enetb_intn, ethi2.mdint);
etxd_pad2 : outpadv generic map (tech => padtech, width => 4)
port map (enetb_tx_d, etho2.txd(3 downto 0));
etxen_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_en, etho2.tx_en);
etxer_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_er, etho2.tx_er);
emdc_pad2 : outpad generic map (tech => padtech)
port map (enetb_mdc, etho2.mdc);
erst_pad2 : outpad generic map (tech => padtech)
port map (enetb_resetn, rstn);
ethi2.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi2.gtx_clk <= '0'; ethi2.rmii_clk <= '0';
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => hmi_greth1,
pindex => pi_greth1, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 0,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth1),
apbi => apbi, apbo => apbo(pi_greth1), ethi => ethi1, etho => etho1);
end generate;
noeth1 : if CFG_GRETH = 0 generate
etho1 <= eth_out_none;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Secondary ethernet MAC
e2 : grethm generic map(hindex => hmi_greth2,
pindex => pi_greth2, paddr => 12, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth2),
apbi => apbi, apbo => apbo(pi_greth2), ethi => ethi2, etho => etho2);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
etho2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------------
-- GPIO
-----------------------------------------------------------------------------
-- TO DO
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
max5_csn <= '1';
sclpad: iopad generic map (tech => padtech) port map (eeprom_scl, i2co.scl, i2co.scloen, i2ci.scl);
sdapad: iopad generic map (tech => padtech) port map (eeprom_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
i2c: if CFG_I2C_ENABLE=1 generate
i2cmst0: i2cmst
generic map (pindex => pi_i2cmst, paddr => 4, pmask => 16#FFF#, pirq => 4)
port map (rstn,clkm,apbi,apbo(pi_i2cmst),i2ci,i2co);
end generate;
noi2c: if CFG_I2C_ENABLE=0 generate
i2co <= (others => '1');
end generate;
-- logan0: logan
-- generic map (pindex => napbs-1, paddr => 16#100#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(napbs-1), logsig);
--
-- logsig(31 downto 6) <= (others => '0');
-- logsig(5 downto 0) <= i2co.scl & i2co.scloen & i2ci.scl & i2co.sda & i2co.sdaoen & i2ci.sda;
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera CycloneV E Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 880d8fb0c76a69c65e098d67b22a1e62 | 0.571882 | 3.329571 | false | false | false | false |
luizesramos/project-utils | decoder-py/testpack/dec-12-full-cplx/decoder.vhdl | 1 | 139,410 | ------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------
entity DECODER is
port(OP1,OP2,OP3,OP4,OP5,OP6: in integer range 0 to 255;
CLOCK: std_logic;
OUTS: out integer range 0 to 2048);
end DECODER;
------------------------------------------
architecture behv of DECODER is
signal NEXT_OUTS: integer;
begin
process(CLOCK)
begin
if(rising_edge(CLOCK)) then
OUTS <= NEXT_OUTS;
end if;
end process;
process(OP1,OP2,OP3,OP4,OP5,OP6)
begin
case OP1 is
when 0 => NEXT_OUTS <= 809; -- addb_Eb_Gb SANITY
when 1 =>
case OP2 is
when 0 => NEXT_OUTS <= 1579; -- addl_Ed_Gd SANITY
when 1 => NEXT_OUTS <= 1598; -- decl_ERX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 2 => NEXT_OUTS <= 1045; -- addb_Gb_Eb SANITY
when 3 => NEXT_OUTS <= 360; -- addl_Gd_Ed SANITY
when 4 => NEXT_OUTS <= 1394; -- addb_AL_Ib SANITY
when 5 => NEXT_OUTS <= 727; -- addl_EAX_Id SANITY
when 6 => NEXT_OUTS <= 77; -- pushl_ES SANITY
when 7 => NEXT_OUTS <= 1032; -- popl_ES SANITY
when 8 => NEXT_OUTS <= 397; -- orb_Eb_Gb SANITY
when 9 => NEXT_OUTS <= 513; -- orl_Ed_Gd SANITY
when 10 => NEXT_OUTS <= 1378; -- orb_Gb_Eb SANITY
when 11 => NEXT_OUTS <= 263; -- orl_Gd_Ed SANITY
when 12 => NEXT_OUTS <= 557; -- orb_AL_Ib SANITY
when 13 => NEXT_OUTS <= 93; -- orl_EAX_Id SANITY
when 14 => NEXT_OUTS <= 730; -- pushl_CS SANITY
when 15 =>
case OP2 is
when 0 =>
case OP3 is
when 0 => NEXT_OUTS <= 1423; -- sldt SANITY
when 8 => NEXT_OUTS <= 1289; -- str SANITY
when 16 => NEXT_OUTS <= 1312; -- lldt SANITY
when 24 => NEXT_OUTS <= 383; -- ltr SANITY
when 32 => NEXT_OUTS <= 420; -- verr SANITY
when 40 => NEXT_OUTS <= 1447; -- verw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 1 =>
case OP3 is
when 0 => NEXT_OUTS <= 811; -- sgdt SANITY
when 8 => NEXT_OUTS <= 1446; -- sidt SANITY
when 16 => NEXT_OUTS <= 1652; -- lgdt SANITY
when 24 => NEXT_OUTS <= 1236; -- lidt SANITY
when 32 => NEXT_OUTS <= 841; -- smsw_Ew SANITY
when 48 => NEXT_OUTS <= 9; -- lmsw_Ew SANITY
when 56 => NEXT_OUTS <= 700; -- invlpg SANITY
when 193 => NEXT_OUTS <= 1483; -- vmcall SANITY
when 194 => NEXT_OUTS <= 553; -- vmlaunch SANITY
when 195 => NEXT_OUTS <= 205; -- vmresume SANITY
when 196 => NEXT_OUTS <= 939; -- vmxoff SANITY
when 200 => NEXT_OUTS <= 1497; -- monitor SANITY
when 201 => NEXT_OUTS <= 489; -- mwait SANITY
when 208 => NEXT_OUTS <= 1348; -- xgetbv SANITY
when 209 => NEXT_OUTS <= 141; -- xsetbv SANITY
when 248 => NEXT_OUTS <= 712; -- swapgs SANITY
when 249 => NEXT_OUTS <= 262; -- rdtscp SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 2 =>
case OP3 is
when 0 => NEXT_OUTS <= 1586; -- larl_Gd_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP3 is
when 0 => NEXT_OUTS <= 975; -- lsll_Gd_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 5 => NEXT_OUTS <= 628; -- syscall SANITY
when 6 => NEXT_OUTS <= 100; -- clts SANITY
when 7 => NEXT_OUTS <= 1049; -- sysret SANITY
when 8 => NEXT_OUTS <= 367; -- invd SANITY
when 9 => NEXT_OUTS <= 735; -- wbinvd SANITY
when 11 => NEXT_OUTS <= 878; -- ud2a SANITY
when 16 => NEXT_OUTS <= 155; -- movups_Vps_Wps SANITY
when 17 => NEXT_OUTS <= 826; -- movups_Wps_Vps SANITY
when 18 =>
case OP3 is
when 0 => NEXT_OUTS <= 1114; -- movlps_Vps_Mq SANITY
when 192 => NEXT_OUTS <= 693; -- movhlps_Vps_Udq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 19 => NEXT_OUTS <= 1574; -- movlps_Mq_Vps SANITY
when 20 => NEXT_OUTS <= 1511; -- unpcklps_Vps_Wps SANITY
when 21 => NEXT_OUTS <= 1028; -- unpckhps_Vps_Wps SANITY
when 22 =>
case OP3 is
when 0 => NEXT_OUTS <= 625; -- movhps_Vps_Mq SANITY
when 192 => NEXT_OUTS <= 1016; -- movlhps_Vps_Udq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 23 => NEXT_OUTS <= 74; -- movhps_Mq_Vps SANITY
when 24 =>
case OP3 is
when 0 => NEXT_OUTS <= 1328; -- prefetchnta SANITY
when 8 => NEXT_OUTS <= 886; -- prefetcht0 SANITY
when 16 => NEXT_OUTS <= 7; -- prefetcht1 SANITY
when 24 => NEXT_OUTS <= 522; -- prefetcht2 SANITY
when 32 => NEXT_OUTS <= 412; -- prefetch_hint SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 25 => NEXT_OUTS <= 623; -- multibyte_nop SANITY
when 32 =>
case OP3 is
when 0 => NEXT_OUTS <= 881; -- movl_Rd_Cd SANITY
when 1 => NEXT_OUTS <= 526; -- movq_Rq_Cq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 33 =>
case OP3 is
when 0 => NEXT_OUTS <= 1178; -- movl_Rd_Dd SANITY
when 1 => NEXT_OUTS <= 596; -- movq_Rq_Dq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 34 =>
case OP3 is
when 0 => NEXT_OUTS <= 722; -- movl_Cd_Rd SANITY
when 1 => NEXT_OUTS <= 1375; -- movq_Cq_Rq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 35 =>
case OP3 is
when 0 => NEXT_OUTS <= 1354; -- movl_Dd_Rd SANITY
when 1 => NEXT_OUTS <= 797; -- movq_Dq_Rq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 36 =>
case OP3 is
when 0 => NEXT_OUTS <= 956; -- movl_Rd_Td SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 38 => NEXT_OUTS <= 919; -- movl_Td_Rd SANITY
when 40 => NEXT_OUTS <= 457; -- movaps_Vps_Wps SANITY
when 41 => NEXT_OUTS <= 1102; -- movaps_Wps_Vps SANITY
when 42 => NEXT_OUTS <= 1098; -- cvtpi2ps_Vps_Qq SANITY
when 43 => NEXT_OUTS <= 414; -- movntps_Mps_Vps SANITY
when 44 => NEXT_OUTS <= 1105; -- cvttps2pi_Pq_Wps SANITY
when 45 => NEXT_OUTS <= 6; -- cvtps2pi_Pq_Wps SANITY
when 46 => NEXT_OUTS <= 4; -- ucomiss_Vss_Wss SANITY
when 47 => NEXT_OUTS <= 877; -- comiss_Vss_Wss SANITY
when 48 => NEXT_OUTS <= 923; -- wrmsr SANITY
when 49 => NEXT_OUTS <= 1234; -- rdtsc SANITY
when 50 => NEXT_OUTS <= 388; -- rdmsr SANITY
when 51 => NEXT_OUTS <= 1416; -- rdpmc SANITY
when 52 => NEXT_OUTS <= 1047; -- sysenter SANITY
when 53 => NEXT_OUTS <= 45; -- sysexit SANITY
when 55 => NEXT_OUTS <= 951; -- getsec SANITY
when 56 =>
case OP3 is
when 0 => NEXT_OUTS <= 1435; -- pshufb_Pq_Qq SANITY
when 1 => NEXT_OUTS <= 413; -- phaddw_Pq_Qq SANITY
when 2 => NEXT_OUTS <= 1564; -- phaddd_Pq_Qq SANITY
when 3 => NEXT_OUTS <= 19; -- phaddsw_Pq_Qq SANITY
when 4 => NEXT_OUTS <= 245; -- pmaddubsw_Pq_Qq SANITY
when 5 => NEXT_OUTS <= 470; -- phsubw_Pq_Qq SANITY
when 6 => NEXT_OUTS <= 637; -- phsubd_Pq_Qq SANITY
when 7 => NEXT_OUTS <= 11; -- phsubsw_Pq_Qq SANITY
when 8 => NEXT_OUTS <= 753; -- psignb_Pq_Qq SANITY
when 9 => NEXT_OUTS <= 997; -- psignw_Pq_Qq SANITY
when 10 => NEXT_OUTS <= 458; -- psignd_Pq_Qq SANITY
when 11 => NEXT_OUTS <= 984; -- pmulhrsw_Pq_Qq SANITY
when 28 => NEXT_OUTS <= 1644; -- pabsb_Pq_Qq SANITY
when 29 => NEXT_OUTS <= 1103; -- pabsw_Pq_Qq SANITY
when 30 => NEXT_OUTS <= 752; -- pabsd_Pq_Qq SANITY
when 240 => NEXT_OUTS <= 1090; -- movbe_Gd_Md SANITY
when 241 =>
case OP4 is
when 195 => NEXT_OUTS <= 105; -- movbe_Md_Gd SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 58 =>
case OP3 is
when 15 => NEXT_OUTS <= 1304; -- palignr_Pq_Qq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 64 => NEXT_OUTS <= 1544; -- cmovol_Gd_Ed SANITY
when 65 => NEXT_OUTS <= 867; -- cmovnol_Gd_Ed SANITY
when 66 => NEXT_OUTS <= 1247; -- cmovcl_Gd_Ed SANITY
when 67 => NEXT_OUTS <= 403; -- cmovncl_Gd_Ed SANITY
when 68 => NEXT_OUTS <= 1638; -- cmovzl_Gd_Ed SANITY
when 69 => NEXT_OUTS <= 1132; -- cmovnzl_Gd_Ed SANITY
when 70 => NEXT_OUTS <= 766; -- cmovnal_Gd_Ed SANITY
when 71 => NEXT_OUTS <= 1566; -- cmoval_Gd_Ed SANITY
when 72 => NEXT_OUTS <= 104; -- cmovsl_Gd_Ed SANITY
when 73 => NEXT_OUTS <= 139; -- cmovnsl_Gd_Ed SANITY
when 74 => NEXT_OUTS <= 486; -- cmovpl_Gd_Ed SANITY
when 75 => NEXT_OUTS <= 1365; -- cmovnpl_Gd_Ed SANITY
when 76 => NEXT_OUTS <= 902; -- cmovll_Gd_Ed SANITY
when 77 => NEXT_OUTS <= 1557; -- cmovnll_Gd_Ed SANITY
when 78 => NEXT_OUTS <= 942; -- cmovngl_Gd_Ed SANITY
when 79 => NEXT_OUTS <= 1535; -- cmovgl_Gd_Ed SANITY
when 80 => NEXT_OUTS <= 988; -- movmskps_Gd_Ups SANITY
when 81 => NEXT_OUTS <= 990; -- sqrtps_Vps_Wps SANITY
when 82 => NEXT_OUTS <= 502; -- rsqrtps_Vps_Wps SANITY
when 83 => NEXT_OUTS <= 493; -- rcpps_Vps_Wps SANITY
when 84 => NEXT_OUTS <= 801; -- andps_Vps_Wps SANITY
when 85 => NEXT_OUTS <= 1431; -- andnps_Vps_Wps SANITY
when 86 => NEXT_OUTS <= 103; -- orps_Vps_Wps SANITY
when 87 => NEXT_OUTS <= 1642; -- xorps_Vps_Wps SANITY
when 88 => NEXT_OUTS <= 1546; -- addps_Vps_Wps SANITY
when 89 => NEXT_OUTS <= 943; -- mulps_Vps_Wps SANITY
when 90 => NEXT_OUTS <= 40; -- cvtps2pd_Vpd_Wps SANITY
when 91 => NEXT_OUTS <= 341; -- cvtdq2ps_Vps_Wdq SANITY
when 92 => NEXT_OUTS <= 1223; -- subps_Vps_Wps SANITY
when 93 => NEXT_OUTS <= 828; -- minps_Vps_Wps SANITY
when 94 => NEXT_OUTS <= 1141; -- divps_Vps_Wps SANITY
when 95 => NEXT_OUTS <= 1376; -- maxps_Vps_Wps SANITY
when 96 => NEXT_OUTS <= 1571; -- punpcklbw_Pq_Qd SANITY
when 97 => NEXT_OUTS <= 322; -- punpcklwd_Pq_Qd SANITY
when 98 => NEXT_OUTS <= 1384; -- punpckldq_Pq_Qd SANITY
when 99 => NEXT_OUTS <= 714; -- packsswb_Pq_Qq SANITY
when 100 => NEXT_OUTS <= 352; -- pcmpgtb_Pq_Qq SANITY
when 101 => NEXT_OUTS <= 789; -- pcmpgtw_Pq_Qq SANITY
when 102 => NEXT_OUTS <= 439; -- pcmpgtd_Pq_Qq SANITY
when 103 => NEXT_OUTS <= 657; -- packuswb_Pq_Qq SANITY
when 104 => NEXT_OUTS <= 1241; -- punpckhbw_Pq_Qq SANITY
when 105 => NEXT_OUTS <= 1285; -- punpckhwd_Pq_Qq SANITY
when 106 => NEXT_OUTS <= 1367; -- punpckhdq_Pq_Qq SANITY
when 107 => NEXT_OUTS <= 167; -- packssdw_Pq_Qq SANITY
when 110 => NEXT_OUTS <= 1379; -- movd_Pq_Ed SANITY
when 111 => NEXT_OUTS <= 948; -- movq_Pq_Qq SANITY
when 112 => NEXT_OUTS <= 65; -- pshufw_Pq_Qq_Ib SANITY
when 113 =>
case OP3 is
when 16 => NEXT_OUTS <= 537; -- psrlw_Nq_Ib SANITY
when 32 => NEXT_OUTS <= 1044; -- psraw_Nq_Ib SANITY
when 48 => NEXT_OUTS <= 1388; -- psllw_Nq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 114 =>
case OP3 is
when 16 => NEXT_OUTS <= 516; -- psrld_Nq_Ib SANITY
when 32 => NEXT_OUTS <= 187; -- psrad_Nq_Ib SANITY
when 48 => NEXT_OUTS <= 615; -- pslld_Nq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 115 =>
case OP3 is
when 16 => NEXT_OUTS <= 1317; -- psrlq_Nq_Ib SANITY
when 48 => NEXT_OUTS <= 849; -- psllq_Nq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 116 => NEXT_OUTS <= 434; -- pcmpeqb_Pq_Qq SANITY
when 117 => NEXT_OUTS <= 981; -- pcmpeqw_Pq_Qq SANITY
when 118 => NEXT_OUTS <= 295; -- pcmpeqd_Pq_Qq SANITY
when 119 => NEXT_OUTS <= 663; -- emms SANITY
when 126 =>
case OP3 is
when 0 => NEXT_OUTS <= 1166; -- movd_Ed_Pq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 127 => NEXT_OUTS <= 1029; -- movq_Qq_Pq SANITY
when 128 => NEXT_OUTS <= 1081; -- jo_Jd SANITY
when 129 => NEXT_OUTS <= 291; -- jno_Jd SANITY
when 130 => NEXT_OUTS <= 950; -- jb_Jd SANITY
when 131 => NEXT_OUTS <= 1601; -- jnb_Jd SANITY
when 132 => NEXT_OUTS <= 364; -- jz_Jd SANITY
when 133 => NEXT_OUTS <= 1655; -- jnz_Jd SANITY
when 134 => NEXT_OUTS <= 1179; -- jbe_Jd SANITY
when 135 => NEXT_OUTS <= 1588; -- jnbe_Jd SANITY
when 136 => NEXT_OUTS <= 1073; -- js_Jd SANITY
when 137 => NEXT_OUTS <= 257; -- jns_Jd SANITY
when 138 => NEXT_OUTS <= 256; -- jp_Jd SANITY
when 139 => NEXT_OUTS <= 1538; -- jnp_Jd SANITY
when 140 => NEXT_OUTS <= 759; -- jl_Jd SANITY
when 141 => NEXT_OUTS <= 58; -- jnl_Jd SANITY
when 142 => NEXT_OUTS <= 983; -- jle_Jd SANITY
when 143 => NEXT_OUTS <= 821; -- jnle_Jd SANITY
when 144 => NEXT_OUTS <= 349; -- seto_Eb SANITY
when 145 => NEXT_OUTS <= 455; -- setno_Eb SANITY
when 146 => NEXT_OUTS <= 565; -- setb_Eb SANITY
when 147 => NEXT_OUTS <= 1211; -- setnb_Eb SANITY
when 148 => NEXT_OUTS <= 337; -- setz_Eb SANITY
when 149 => NEXT_OUTS <= 231; -- setnz_Eb SANITY
when 150 => NEXT_OUTS <= 1612; -- setbe_Eb SANITY
when 151 => NEXT_OUTS <= 192; -- setnbe_Eb SANITY
when 152 => NEXT_OUTS <= 239; -- sets_Eb SANITY
when 153 => NEXT_OUTS <= 1235; -- setns_Eb SANITY
when 154 => NEXT_OUTS <= 1640; -- setp_Eb SANITY
when 155 => NEXT_OUTS <= 1116; -- setnp_Eb SANITY
when 156 => NEXT_OUTS <= 445; -- setl_Eb SANITY
when 157 => NEXT_OUTS <= 1474; -- setnl_Eb SANITY
when 158 => NEXT_OUTS <= 332; -- setle_Eb SANITY
when 159 => NEXT_OUTS <= 776; -- setnle_Eb SANITY
when 160 =>
case OP3 is
when 0 => NEXT_OUTS <= 133; -- pushl_FS SANITY
when 1 => NEXT_OUTS <= 822; -- pushq_FS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 161 =>
case OP3 is
when 0 => NEXT_OUTS <= 1463; -- popl_FS SANITY
when 1 => NEXT_OUTS <= 1515; -- popq_FS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 162 => NEXT_OUTS <= 354; -- cpuid SANITY
when 163 => NEXT_OUTS <= 1433; -- btl_Ed_Gd SANITY
when 164 => NEXT_OUTS <= 1504; -- shldl_Ed_Gd_Ib SANITY
when 165 => NEXT_OUTS <= 118; -- shldl_Ed_Gd_CL SANITY
when 168 =>
case OP3 is
when 0 => NEXT_OUTS <= 1065; -- pushl_GS SANITY
when 1 => NEXT_OUTS <= 1634; -- pushq_GS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 169 =>
case OP3 is
when 0 => NEXT_OUTS <= 292; -- popl_GS SANITY
when 1 => NEXT_OUTS <= 1437; -- popq_GS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 170 => NEXT_OUTS <= 499; -- rsm SANITY
when 171 => NEXT_OUTS <= 1554; -- btsl_Ed_Gd SANITY
when 172 => NEXT_OUTS <= 961; -- shrdl_Ed_Gd_Ib SANITY
when 173 => NEXT_OUTS <= 889; -- shrdl_Ed_Gd_CL SANITY
when 174 =>
case OP3 is
when 0 => NEXT_OUTS <= 416; -- fxsave SANITY
when 8 => NEXT_OUTS <= 895; -- fxrstor SANITY
when 16 => NEXT_OUTS <= 175; -- ldmxcsr SANITY
when 24 => NEXT_OUTS <= 123; -- stmxcsr SANITY
when 48 => NEXT_OUTS <= 1281; -- xsaveopt SANITY
when 56 => NEXT_OUTS <= 87; -- cflush SANITY
when 232 => NEXT_OUTS <= 195; -- lfence SANITY
when 240 => NEXT_OUTS <= 582; -- mfence SANITY
when 248 => NEXT_OUTS <= 370; -- sfence SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 175 => NEXT_OUTS <= 508; -- imull_Gd_Ed SANITY
when 176 => NEXT_OUTS <= 400; -- cmpxchgb_Eb_Gb SANITY
when 177 => NEXT_OUTS <= 467; -- cmpxchgl_Ed_Gd SANITY
when 178 => NEXT_OUTS <= 504; -- lssl_Gd_Mp SANITY
when 179 => NEXT_OUTS <= 1273; -- btrl_Ed_Gd SANITY
when 180 => NEXT_OUTS <= 191; -- lfsl_Gd_Mp SANITY
when 181 => NEXT_OUTS <= 122; -- lgsl_Gd_Mp SANITY
when 182 => NEXT_OUTS <= 1140; -- movzbl_Gd_Eb SANITY
when 183 => NEXT_OUTS <= 851; -- movzwl_Gd_Ew SANITY
when 185 =>
case OP3 is
when 0 => NEXT_OUTS <= 1358; -- ud2b SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 186 =>
case OP3 is
when 32 => NEXT_OUTS <= 401; -- btl_Ed_Ib SANITY
when 40 => NEXT_OUTS <= 1562; -- btsl_Ed_Ib SANITY
when 48 => NEXT_OUTS <= 430; -- btrl_Ed_Ib SANITY
when 56 => NEXT_OUTS <= 674; -- btcl_Ed_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 771; -- btcl_Ed_Gd SANITY
when 188 => NEXT_OUTS <= 540; -- bsfl_Gd_Ed SANITY
when 189 => NEXT_OUTS <= 1399; -- bsrl_Gd_Ed SANITY
when 190 => NEXT_OUTS <= 1150; -- movsbl_Gd_Eb SANITY
when 191 => NEXT_OUTS <= 1413; -- movswl_Gd_Ew SANITY
when 192 => NEXT_OUTS <= 524; -- xaddb_Eb_Gb SANITY
when 193 => NEXT_OUTS <= 717; -- xaddl_Ed_Gd SANITY
when 194 =>
case OP3 is
when 0 =>
case OP4 is
when 0 => NEXT_OUTS <= 447; -- cmpps_Vps_Wps_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 195 => NEXT_OUTS <= 243; -- movnti_Md_Gd SANITY
when 196 =>
case OP3 is
when 0 => NEXT_OUTS <= 21; -- pinsrw_Pq_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 197 => NEXT_OUTS <= 769; -- pextrw_Gd_Nq_Ib SANITY
when 198 => NEXT_OUTS <= 246; -- shufps_Vps_Wps_Ib SANITY
when 199 =>
case OP3 is
when 8 => NEXT_OUTS <= 41; -- cmpxchg8b_Mq SANITY
when 48 => NEXT_OUTS <= 884; -- vmptrld_Mq SANITY
when 56 => NEXT_OUTS <= 407; -- vmptrst_Mq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 200 => NEXT_OUTS <= 1417; -- bswapl_ERX SANITY
when 209 => NEXT_OUTS <= 1545; -- psrlw_Pq_Qq SANITY
when 210 => NEXT_OUTS <= 311; -- psrld_Pq_Qq SANITY
when 211 => NEXT_OUTS <= 810; -- psrlq_Pq_Qq SANITY
when 212 => NEXT_OUTS <= 1118; -- paddq_Pq_Qq SANITY
when 213 => NEXT_OUTS <= 699; -- pmullw_Pq_Qq SANITY
when 215 => NEXT_OUTS <= 1126; -- pmovmskb_Gd_Nq SANITY
when 216 => NEXT_OUTS <= 169; -- psubusb_Pq_Qq SANITY
when 217 => NEXT_OUTS <= 151; -- psubusw_Pq_Qq SANITY
when 218 => NEXT_OUTS <= 150; -- pminub_Pq_Qq SANITY
when 219 => NEXT_OUTS <= 974; -- pand_Pq_Qq SANITY
when 220 => NEXT_OUTS <= 831; -- paddusb_Pq_Qq SANITY
when 221 => NEXT_OUTS <= 1430; -- paddusw_Pq_Qq SANITY
when 222 => NEXT_OUTS <= 496; -- pmaxub_Pq_Qq SANITY
when 223 => NEXT_OUTS <= 1660; -- pandn_Pq_Qq SANITY
when 224 => NEXT_OUTS <= 258; -- pavgb_Pq_Qq SANITY
when 225 => NEXT_OUTS <= 1266; -- psraw_Pq_Qq SANITY
when 226 => NEXT_OUTS <= 1560; -- psrad_Pq_Qq SANITY
when 227 => NEXT_OUTS <= 1659; -- pavgw_Pq_Qq SANITY
when 228 => NEXT_OUTS <= 1019; -- pmulhuw_Pq_Qq SANITY
when 229 => NEXT_OUTS <= 448; -- pmulhw_Pq_Qq SANITY
when 231 => NEXT_OUTS <= 186; -- movntq_Mq_Pq SANITY
when 232 => NEXT_OUTS <= 16; -- psubsb_Pq_Qq SANITY
when 233 => NEXT_OUTS <= 1080; -- psubsw_Pq_Qq SANITY
when 234 => NEXT_OUTS <= 588; -- pminsw_Pq_Qq SANITY
when 235 => NEXT_OUTS <= 638; -- por_Pq_Qq SANITY
when 236 => NEXT_OUTS <= 738; -- paddsb_Pq_Qq SANITY
when 237 => NEXT_OUTS <= 531; -- paddsw_Pq_Qq SANITY
when 238 => NEXT_OUTS <= 1480; -- pmaxsw_Pq_Qq SANITY
when 239 => NEXT_OUTS <= 91; -- pxor_Pq_Qq SANITY
when 241 => NEXT_OUTS <= 1615; -- psllw_Pq_Qq SANITY
when 242 => NEXT_OUTS <= 1482; -- pslld_Pq_Qq SANITY
when 243 => NEXT_OUTS <= 1532; -- psllq_Pq_Qq SANITY
when 244 => NEXT_OUTS <= 228; -- pmuludq_Pq_Qq SANITY
when 245 => NEXT_OUTS <= 1593; -- pmaddwd_Pq_Qq SANITY
when 246 => NEXT_OUTS <= 957; -- psadbw_Pq_Qq SANITY
when 247 => NEXT_OUTS <= 269; -- maskmovq_Pq_Nq SANITY
when 248 => NEXT_OUTS <= 1085; -- psubb_Pq_Qq SANITY
when 249 => NEXT_OUTS <= 1189; -- psubw_Pq_Qq SANITY
when 250 => NEXT_OUTS <= 211; -- psubd_Pq_Qq SANITY
when 251 => NEXT_OUTS <= 535; -- psubq_Pq_Qq SANITY
when 252 => NEXT_OUTS <= 428; -- paddb_Pq_Qq SANITY
when 253 => NEXT_OUTS <= 554; -- paddw_Pq_Qq SANITY
when 254 => NEXT_OUTS <= 617; -- paddd_Pq_Qq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 16 => NEXT_OUTS <= 546; -- adcb_Eb_Gb SANITY
when 17 => NEXT_OUTS <= 611; -- adcl_Ed_Gd SANITY
when 18 => NEXT_OUTS <= 384; -- adcb_Gb_Eb SANITY
when 19 => NEXT_OUTS <= 1484; -- adcl_Gd_Ed SANITY
when 20 => NEXT_OUTS <= 541; -- adcb_AL_Ib SANITY
when 21 => NEXT_OUTS <= 1256; -- adcl_EAX_Id SANITY
when 22 => NEXT_OUTS <= 115; -- pushl_SS SANITY
when 23 => NEXT_OUTS <= 1563; -- popl_SS SANITY
when 24 => NEXT_OUTS <= 1345; -- sbbb_Eb_Gb SANITY
when 25 => NEXT_OUTS <= 1530; -- sbbl_Ed_Gd SANITY
when 26 => NEXT_OUTS <= 1200; -- sbbb_Gb_Eb SANITY
when 27 => NEXT_OUTS <= 61; -- sbbl_Gd_Ed SANITY
when 28 => NEXT_OUTS <= 684; -- sbbb_AL_Ib SANITY
when 29 => NEXT_OUTS <= 340; -- sbbl_EAX_Id SANITY
when 30 => NEXT_OUTS <= 1663; -- pushl_DS SANITY
when 31 => NEXT_OUTS <= 1385; -- popl_DS SANITY
when 32 => NEXT_OUTS <= 1274; -- andb_Eb_Gb SANITY
when 33 => NEXT_OUTS <= 1454; -- andl_Ed_Gd SANITY
when 34 => NEXT_OUTS <= 1503; -- andb_Gb_Eb SANITY
when 35 => NEXT_OUTS <= 1260; -- andl_Gd_Ed SANITY
when 36 => NEXT_OUTS <= 982; -- andb_AL_Ib SANITY
when 37 => NEXT_OUTS <= 527; -- andl_EAX_Id SANITY
when 39 => NEXT_OUTS <= 345; -- daa SANITY
when 40 => NEXT_OUTS <= 1186; -- subb_Eb_Gb SANITY
when 41 => NEXT_OUTS <= 399; -- subl_Ed_Gd SANITY
when 42 => NEXT_OUTS <= 835; -- subb_Gb_Eb SANITY
when 43 => NEXT_OUTS <= 98; -- subl_Gd_Ed SANITY
when 44 => NEXT_OUTS <= 834; -- subb_AL_Ib SANITY
when 45 => NEXT_OUTS <= 394; -- subl_EAX_Id SANITY
when 47 => NEXT_OUTS <= 1169; -- das SANITY
when 48 => NEXT_OUTS <= 1027; -- xorb_Eb_Gb SANITY
when 49 => NEXT_OUTS <= 630; -- xorl_Ed_Gd SANITY
when 50 => NEXT_OUTS <= 817; -- xorb_Gb_Eb SANITY
when 51 => NEXT_OUTS <= 1297; -- xorl_Gd_Ed SANITY
when 52 => NEXT_OUTS <= 408; -- xorb_AL_Ib SANITY
when 53 => NEXT_OUTS <= 1306; -- xorl_EAX_Id SANITY
when 55 => NEXT_OUTS <= 377; -- aaa SANITY
when 56 => NEXT_OUTS <= 1227; -- cmpb_Eb_Gb SANITY
when 57 => NEXT_OUTS <= 179; -- cmpl_Ed_Gd SANITY
when 58 => NEXT_OUTS <= 946; -- cmpb_Gb_Eb SANITY
when 59 => NEXT_OUTS <= 242; -- cmpl_Gd_Ed SANITY
when 60 => NEXT_OUTS <= 81; -- cmpb_AL_Ib SANITY
when 61 => NEXT_OUTS <= 507; -- cmpl_EAX_Id SANITY
when 63 => NEXT_OUTS <= 1005; -- aas SANITY
when 64 => NEXT_OUTS <= 758; -- incl_ERX SANITY
when 72 =>
case OP2 is
when 1 => NEXT_OUTS <= 459; -- addq_Eq_Gq SANITY
when 3 => NEXT_OUTS <= 249; -- addq_Gq_Eq SANITY
when 5 => NEXT_OUTS <= 166; -- addq_RAX_sId SANITY
when 9 => NEXT_OUTS <= 1442; -- orq_Eq_Gq SANITY
when 11 => NEXT_OUTS <= 307; -- orq_Gq_Eq SANITY
when 13 => NEXT_OUTS <= 805; -- orq_RAX_sId SANITY
when 15 =>
case OP3 is
when 2 =>
case OP4 is
when 0 => NEXT_OUTS <= 276; -- larq_Gq_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP4 is
when 0 => NEXT_OUTS <= 784; -- lslq_Gq_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 56 =>
case OP4 is
when 240 => NEXT_OUTS <= 1389; -- movbe_Gq_Mq SANITY
when 241 =>
case OP5 is
when 195 => NEXT_OUTS <= 381; -- movbe_Mq_Gq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 64 => NEXT_OUTS <= 1314; -- cmovoq_Gq_Eq SANITY
when 65 => NEXT_OUTS <= 765; -- cmovnoq_Gq_Eq SANITY
when 66 => NEXT_OUTS <= 900; -- cmovcq_Gq_Eq SANITY
when 67 => NEXT_OUTS <= 658; -- cmovncq_Gq_Eq SANITY
when 68 => NEXT_OUTS <= 1002; -- cmovzq_Gq_Eq SANITY
when 69 => NEXT_OUTS <= 1380; -- cmovnzq_Gq_Eq SANITY
when 70 => NEXT_OUTS <= 1343; -- cmovnaq_Gq_Eq SANITY
when 71 => NEXT_OUTS <= 1138; -- cmovaq_Gq_Eq SANITY
when 72 => NEXT_OUTS <= 1404; -- cmovsq_Gq_Eq SANITY
when 73 => NEXT_OUTS <= 1292; -- cmovnsq_Gq_Eq SANITY
when 74 => NEXT_OUTS <= 742; -- cmovpq_Gq_Eq SANITY
when 75 => NEXT_OUTS <= 335; -- cmovnpq_Gq_Eq SANITY
when 76 => NEXT_OUTS <= 1344; -- cmovlq_Gq_Eq SANITY
when 77 => NEXT_OUTS <= 1522; -- cmovnlq_Gq_Eq SANITY
when 78 => NEXT_OUTS <= 358; -- cmovngq_Gq_Eq SANITY
when 79 => NEXT_OUTS <= 995; -- cmovgq_Gq_Eq SANITY
when 110 => NEXT_OUTS <= 1228; -- movq_Pq_Eq SANITY
when 126 =>
case OP4 is
when 0 => NEXT_OUTS <= 168; -- movq_Eq_Pq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 163 => NEXT_OUTS <= 548; -- btq_Eq_Gq SANITY
when 164 => NEXT_OUTS <= 780; -- shldq_Eq_Gq_Ib SANITY
when 165 => NEXT_OUTS <= 819; -- shldq_Eq_Gq_CL SANITY
when 171 => NEXT_OUTS <= 597; -- btsq_Eq_Gq SANITY
when 172 => NEXT_OUTS <= 813; -- shrdq_Eq_Gq_Ib SANITY
when 173 => NEXT_OUTS <= 1371; -- shrdq_Eq_Gq_CL SANITY
when 175 => NEXT_OUTS <= 1024; -- imulq_Gq_Eq SANITY
when 177 => NEXT_OUTS <= 1415; -- cmpxchgq_Eq_Gq SANITY
when 178 => NEXT_OUTS <= 806; -- lssq_Gq_Mp SANITY
when 179 => NEXT_OUTS <= 1205; -- btrq_Eq_Gq SANITY
when 180 => NEXT_OUTS <= 474; -- lfsq_Gq_Mp SANITY
when 181 => NEXT_OUTS <= 281; -- lgsq_Gq_Mp SANITY
when 182 => NEXT_OUTS <= 453; -- movzbq_Gq_Eb SANITY
when 183 => NEXT_OUTS <= 386; -- movzwq_Gq_Ew SANITY
when 186 =>
case OP4 is
when 32 => NEXT_OUTS <= 740; -- btq_Eq_Ib SANITY
when 40 => NEXT_OUTS <= 171; -- btsq_Eq_Ib SANITY
when 48 => NEXT_OUTS <= 301; -- btrq_Eq_Ib SANITY
when 56 => NEXT_OUTS <= 1207; -- btcq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 96; -- btcq_Eq_Gq SANITY
when 188 => NEXT_OUTS <= 334; -- bsfq_Gq_Eq SANITY
when 189 => NEXT_OUTS <= 1386; -- bsrq_Gq_Eq SANITY
when 190 => NEXT_OUTS <= 1035; -- movsbq_Gq_Eb SANITY
when 191 => NEXT_OUTS <= 711; -- movswq_Gq_Ew SANITY
when 193 => NEXT_OUTS <= 1396; -- xaddq_Eq_Gq SANITY
when 195 => NEXT_OUTS <= 1059; -- movntiq_Mq_Gq SANITY
when 199 =>
case OP4 is
when 8 => NEXT_OUTS <= 665; -- cmpxchg16b_Mdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 200 => NEXT_OUTS <= 1584; -- bswapq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 17 => NEXT_OUTS <= 1133; -- adcq_Eq_Gq SANITY
when 19 => NEXT_OUTS <= 1068; -- adcq_Gq_Eq SANITY
when 21 => NEXT_OUTS <= 479; -- adcq_RAX_sId SANITY
when 25 => NEXT_OUTS <= 503; -- sbbq_Eq_Gq SANITY
when 27 => NEXT_OUTS <= 226; -- sbbq_Gq_Eq SANITY
when 29 => NEXT_OUTS <= 1624; -- sbbq_RAX_sId SANITY
when 33 => NEXT_OUTS <= 1397; -- andq_Eq_Gq SANITY
when 35 => NEXT_OUTS <= 1267; -- andq_Gq_Eq SANITY
when 37 => NEXT_OUTS <= 1323; -- andq_RAX_sId SANITY
when 41 => NEXT_OUTS <= 1518; -- subq_Eq_Gq SANITY
when 43 => NEXT_OUTS <= 1100; -- subq_Gq_Eq SANITY
when 45 => NEXT_OUTS <= 224; -- subq_RAX_sId SANITY
when 49 => NEXT_OUTS <= 929; -- xorq_Eq_Gq SANITY
when 51 => NEXT_OUTS <= 1494; -- xorq_Gq_Eq SANITY
when 53 => NEXT_OUTS <= 994; -- xorq_RAX_sId SANITY
when 57 => NEXT_OUTS <= 1231; -- cmpq_Eq_Gq SANITY
when 59 => NEXT_OUTS <= 59; -- cmpq_Gq_Eq SANITY
when 61 => NEXT_OUTS <= 687; -- cmpq_RAX_sId SANITY
when 99 => NEXT_OUTS <= 1136; -- movslq_Gq_Ed SANITY
when 105 => NEXT_OUTS <= 1409; -- imulq_Gq_Eq_sId SANITY
when 107 => NEXT_OUTS <= 409; -- imulq_Gq_Eq_sIb SANITY
when 129 =>
case OP3 is
when 0 => NEXT_OUTS <= 1270; -- addq_Eq_sId SANITY
when 8 => NEXT_OUTS <= 645; -- orq_Eq_sId SANITY
when 16 => NEXT_OUTS <= 248; -- adcq_Eq_sId SANITY
when 24 => NEXT_OUTS <= 512; -- sbbq_Eq_sId SANITY
when 32 => NEXT_OUTS <= 1296; -- andq_Eq_sId SANITY
when 40 => NEXT_OUTS <= 1630; -- subq_Eq_sId SANITY
when 48 => NEXT_OUTS <= 288; -- xorq_Eq_sId SANITY
when 56 => NEXT_OUTS <= 1020; -- cmpq_Eq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP3 is
when 0 => NEXT_OUTS <= 484; -- addq_Eq_sIb SANITY
when 8 => NEXT_OUTS <= 794; -- orq_Eq_sIb SANITY
when 16 => NEXT_OUTS <= 1664; -- adcq_Eq_sIb SANITY
when 24 => NEXT_OUTS <= 737; -- sbbq_Eq_sIb SANITY
when 32 => NEXT_OUTS <= 1581; -- andq_Eq_sIb SANITY
when 40 => NEXT_OUTS <= 183; -- subq_Eq_sIb SANITY
when 48 => NEXT_OUTS <= 278; -- xorq_Eq_sIb SANITY
when 56 => NEXT_OUTS <= 1594; -- cmpq_Eq_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 133 => NEXT_OUTS <= 472; -- testq_Eq_Gq SANITY
when 135 => NEXT_OUTS <= 595; -- xchgq_Eq_Gq SANITY
when 137 => NEXT_OUTS <= 102; -- movq_Eq_Gq SANITY
when 139 => NEXT_OUTS <= 1632; -- movq_Gq_Eq SANITY
when 141 => NEXT_OUTS <= 181; -- leaq_Gq_Mq SANITY
when 145 => NEXT_OUTS <= 906; -- xchgq_RRX_RAX SANITY
when 152 => NEXT_OUTS <= 47; -- cdqe SANITY
when 153 => NEXT_OUTS <= 147; -- cqo SANITY
when 161 => NEXT_OUTS <= 888; -- movq_RAX_Oq SANITY
when 163 => NEXT_OUTS <= 1578; -- movq_Oq_RAX SANITY
when 165 => NEXT_OUTS <= 1046; -- movsq_Yq_Xq SANITY
when 167 => NEXT_OUTS <= 154; -- cmpsq_Yq_Xq SANITY
when 169 => NEXT_OUTS <= 931; -- testq_RAX_sId SANITY
when 171 => NEXT_OUTS <= 610; -- stosq_Yq_RAX SANITY
when 173 => NEXT_OUTS <= 1613; -- lodsq_RAX_Xq SANITY
when 175 => NEXT_OUTS <= 539; -- scasq_Yq_RAX SANITY
when 184 => NEXT_OUTS <= 1255; -- movq_RRX_Iq SANITY
when 193 =>
case OP3 is
when 0 => NEXT_OUTS <= 327; -- rolq_Eq_Ib SANITY
when 8 => NEXT_OUTS <= 816; -- rorq_Eq_Ib SANITY
when 16 => NEXT_OUTS <= 402; -- rclq_Eq_Ib SANITY
when 24 => NEXT_OUTS <= 261; -- rcrq_Eq_Ib SANITY
when 32 => NEXT_OUTS <= 346; -- shlq_Eq_Ib SANITY
when 40 => NEXT_OUTS <= 1147; -- shrq_Eq_Ib SANITY
when 56 => NEXT_OUTS <= 463; -- sarq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 199 =>
case OP3 is
when 0 => NEXT_OUTS <= 446; -- movq_Eq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 207 => NEXT_OUTS <= 799; -- iretq SANITY
when 209 =>
case OP3 is
when 0 => NEXT_OUTS <= 1075; -- rolq_Eq_I1 SANITY
when 8 => NEXT_OUTS <= 783; -- rorq_Eq_I1 SANITY
when 16 => NEXT_OUTS <= 273; -- rclq_Eq_I1 SANITY
when 24 => NEXT_OUTS <= 649; -- rcrq_Eq_I1 SANITY
when 32 => NEXT_OUTS <= 1582; -- shlq_Eq_I1 SANITY
when 40 => NEXT_OUTS <= 236; -- shrq_Eq_I1 SANITY
when 56 => NEXT_OUTS <= 406; -- sarq_Eq_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP3 is
when 0 => NEXT_OUTS <= 1137; -- rolq_Eq_CL SANITY
when 8 => NEXT_OUTS <= 308; -- rorq_Eq_CL SANITY
when 16 => NEXT_OUTS <= 55; -- rclq_Eq_CL SANITY
when 24 => NEXT_OUTS <= 1123; -- rcrq_Eq_CL SANITY
when 32 => NEXT_OUTS <= 355; -- shlq_Eq_CL SANITY
when 40 => NEXT_OUTS <= 1359; -- shrq_Eq_CL SANITY
when 56 => NEXT_OUTS <= 1194; -- sarq_Eq_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 247 =>
case OP3 is
when 0 => NEXT_OUTS <= 1453; -- testq_Eq_sId SANITY
when 16 => NEXT_OUTS <= 635; -- notq_Eq SANITY
when 24 => NEXT_OUTS <= 27; -- negq_Eq SANITY
when 32 => NEXT_OUTS <= 1326; -- mulq_RAX_Eq SANITY
when 40 => NEXT_OUTS <= 221; -- imulq_RAX_Eq SANITY
when 48 => NEXT_OUTS <= 418; -- divq_RAX_Eq SANITY
when 56 => NEXT_OUTS <= 1067; -- idivq_RAX_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP3 is
when 0 => NEXT_OUTS <= 731; -- incq_Eq SANITY
when 8 => NEXT_OUTS <= 1164; -- decq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 80 =>
case OP2 is
when 0 => NEXT_OUTS <= 879; -- pushl_ERX SANITY
when 1 => NEXT_OUTS <= 798; -- pushq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 88 =>
case OP2 is
when 0 => NEXT_OUTS <= 937; -- popl_ERX SANITY
when 1 => NEXT_OUTS <= 128; -- popq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 96 => NEXT_OUTS <= 1512; -- pushal SANITY
when 97 => NEXT_OUTS <= 76; -- popal SANITY
when 98 => NEXT_OUTS <= 897; -- boundl_Gd_Ma SANITY
when 99 => NEXT_OUTS <= 36; -- arpl_Ew_Gw SANITY
when 102 =>
case OP2 is
when 1 =>
case OP3 is
when 0 => NEXT_OUTS <= 356; -- addw_Ew_Gw SANITY
when 1 => NEXT_OUTS <= 581; -- decw_RX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 => NEXT_OUTS <= 777; -- addw_Gw_Ew SANITY
when 5 => NEXT_OUTS <= 444; -- addw_AX_Iw SANITY
when 6 => NEXT_OUTS <= 197; -- pushw_ES SANITY
when 7 => NEXT_OUTS <= 1364; -- popw_ES SANITY
when 9 => NEXT_OUTS <= 587; -- orw_Ew_Gw SANITY
when 11 => NEXT_OUTS <= 315; -- orw_Gw_Ew SANITY
when 13 => NEXT_OUTS <= 1293; -- orw_AX_Iw SANITY
when 14 => NEXT_OUTS <= 1224; -- pushw_CS SANITY
when 15 =>
case OP3 is
when 2 =>
case OP4 is
when 0 => NEXT_OUTS <= 142; -- larw_Gw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP4 is
when 0 => NEXT_OUTS <= 174; -- lslw_Gw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 16 => NEXT_OUTS <= 490; -- movupd_Vpd_Wpd SANITY
when 17 => NEXT_OUTS <= 124; -- movupd_Wpd_Vpd SANITY
when 18 => NEXT_OUTS <= 788; -- movlpd_Vpd_Mq SANITY
when 19 => NEXT_OUTS <= 86; -- movlpd_Mq_Vpd SANITY
when 20 => NEXT_OUTS <= 120; -- unpcklpd_Vpd_Wpd SANITY
when 21 => NEXT_OUTS <= 585; -- unpckhpd_Vpd_Wpd SANITY
when 22 => NEXT_OUTS <= 854; -- movhpd_Vpd_Mq SANITY
when 23 => NEXT_OUTS <= 8; -- movhpd_Mq_Vpd SANITY
when 40 => NEXT_OUTS <= 622; -- movapd_Vpd_Wpd SANITY
when 41 => NEXT_OUTS <= 662; -- movapd_Wpd_Vpd SANITY
when 42 => NEXT_OUTS <= 624; -- cvtpi2pd_Vpd_Qq SANITY
when 44 => NEXT_OUTS <= 146; -- cvttpd2pi_Pq_Wpd SANITY
when 45 => NEXT_OUTS <= 1124; -- cvtpd2pi_Pq_Wpd SANITY
when 46 => NEXT_OUTS <= 1606; -- ucomisd_Vsd_Wsd SANITY
when 47 => NEXT_OUTS <= 339; -- comisd_Vsd_Wsd SANITY
when 56 =>
case OP4 is
when 0 => NEXT_OUTS <= 739; -- pshufb_Vdq_Wdq SANITY
when 1 => NEXT_OUTS <= 1160; -- phaddw_Vdq_Wdq SANITY
when 2 => NEXT_OUTS <= 485; -- phaddd_Vdq_Wdq SANITY
when 3 => NEXT_OUTS <= 330; -- phaddsw_Vdq_Wdq SANITY
when 4 => NEXT_OUTS <= 1042; -- pmaddubsw_Vdq_Wdq SANITY
when 5 => NEXT_OUTS <= 909; -- phsubw_Vdq_Wdq SANITY
when 6 => NEXT_OUTS <= 578; -- phsubd_Vdq_Wdq SANITY
when 7 => NEXT_OUTS <= 677; -- phsubsw_Vdq_Wdq SANITY
when 8 => NEXT_OUTS <= 574; -- psignb_Vdq_Wdq SANITY
when 9 => NEXT_OUTS <= 1190; -- psignw_Vdq_Wdq SANITY
when 10 => NEXT_OUTS <= 971; -- psignd_Vdq_Wdq SANITY
when 11 => NEXT_OUTS <= 1144; -- pmulhrsw_Vdq_Wdq SANITY
when 16 => NEXT_OUTS <= 223; -- pblendvb_Vdq_Wdq SANITY
when 20 => NEXT_OUTS <= 395; -- blendvps_Vps_Wps SANITY
when 21 => NEXT_OUTS <= 1239; -- blendvpd_Vpd_Wpd SANITY
when 23 => NEXT_OUTS <= 1641; -- ptest_Vdq_Wdq SANITY
when 28 => NEXT_OUTS <= 836; -- pabsb_Vdq_Wdq SANITY
when 29 => NEXT_OUTS <= 60; -- pabsw_Vdq_Wdq SANITY
when 30 => NEXT_OUTS <= 696; -- pabsd_Vdq_Wdq SANITY
when 32 =>
case OP5 is
when 1 => NEXT_OUTS <= 1496; -- pmovsxbw_Vdq_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 33 => NEXT_OUTS <= 1004; -- pmovsxbd_Vdq_Wd SANITY
when 34 => NEXT_OUTS <= 721; -- pmovsxbq_Vdq_Ww SANITY
when 35 => NEXT_OUTS <= 1514; -- pmovsxwd_Vdq_Wq SANITY
when 36 => NEXT_OUTS <= 49; -- pmovsxwq_Vdq_Wd SANITY
when 37 => NEXT_OUTS <= 134; -- pmovsxdq_Vdq_Wq SANITY
when 40 => NEXT_OUTS <= 1555; -- pmuldq_Vdq_Wdq SANITY
when 41 => NEXT_OUTS <= 451; -- pcmpeqq_Vdq_Wdq SANITY
when 42 => NEXT_OUTS <= 848; -- movntdqa_Vdq_Mdq SANITY
when 43 => NEXT_OUTS <= 564; -- packusdw_Vdq_Wdq SANITY
when 48 => NEXT_OUTS <= 697; -- pmovzxbw_Vdq_Wq SANITY
when 49 => NEXT_OUTS <= 353; -- pmovzxbd_Vdq_Wd SANITY
when 50 => NEXT_OUTS <= 1524; -- pmovzxbq_Vdq_Ww SANITY
when 51 => NEXT_OUTS <= 491; -- pmovzxwd_Vdq_Wq SANITY
when 52 => NEXT_OUTS <= 1307; -- pmovzxwq_Vdq_Wd SANITY
when 53 => NEXT_OUTS <= 389; -- pmovzxdq_Vdq_Wq SANITY
when 55 => NEXT_OUTS <= 144; -- pcmpgtq_Vdq_Wdq SANITY
when 56 => NEXT_OUTS <= 189; -- pminsb_Vdq_Wdq SANITY
when 57 => NEXT_OUTS <= 452; -- pminsd_Vdq_Wdq SANITY
when 58 => NEXT_OUTS <= 907; -- pminuw_Vdq_Wdq SANITY
when 59 => NEXT_OUTS <= 1115; -- pminud_Vdq_Wdq SANITY
when 60 => NEXT_OUTS <= 551; -- pmaxsb_Vdq_Wdq SANITY
when 61 => NEXT_OUTS <= 1471; -- pmaxsd_Vdq_Wdq SANITY
when 62 => NEXT_OUTS <= 1499; -- pmaxuw_Vdq_Wdq SANITY
when 63 => NEXT_OUTS <= 991; -- pmaxud_Vdq_Wdq SANITY
when 64 => NEXT_OUTS <= 20; -- pmulld_Vdq_Wdq SANITY
when 65 => NEXT_OUTS <= 914; -- phminposuw_Vdq_Wdq SANITY
when 130 => NEXT_OUTS <= 1418; -- invpcid_Gy_Mdq SANITY
when 219 => NEXT_OUTS <= 935; -- aesimc_Vdq_Wdq SANITY
when 220 => NEXT_OUTS <= 1639; -- aesenc_Vdq_Wdq SANITY
when 221 => NEXT_OUTS <= 807; -- aesenclast_Vdq_Wdq SANITY
when 222 => NEXT_OUTS <= 1438; -- aesdec_Vdq_Wdq SANITY
when 223 => NEXT_OUTS <= 534; -- aesdeclast_Vdq_Wdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 58 =>
case OP4 is
when 8 => NEXT_OUTS <= 1347; -- roundps_Vps_Wps_Ib SANITY
when 9 => NEXT_OUTS <= 1268; -- roundpd_Vpd_Wpd_Ib SANITY
when 10 => NEXT_OUTS <= 655; -- roundss_Vss_Wss_Ib SANITY
when 11 => NEXT_OUTS <= 56; -- roundsd_Vsd_Wsd_Ib SANITY
when 12 => NEXT_OUTS <= 90; -- blendps_Vps_Wps_Ib SANITY
when 13 => NEXT_OUTS <= 1182; -- blendpd_Vpd_Wpd_Ib SANITY
when 14 => NEXT_OUTS <= 1324; -- pblendw_Vdq_Wdq_Ib SANITY
when 15 => NEXT_OUTS <= 1349; -- palignr_Vdq_Wdq_Ib SANITY
when 20 =>
case OP5 is
when 0 => NEXT_OUTS <= 424; -- pextrb_Ebd_Vdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 21 =>
case OP5 is
when 0 => NEXT_OUTS <= 561; -- pextrw_Ewd_Vdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 22 => NEXT_OUTS <= 1620; -- pextrd_Ed_Vdq_Ib SANITY
when 23 => NEXT_OUTS <= 220; -- extractps_Ed_Vdq_Ib SANITY
when 32 => NEXT_OUTS <= 300; -- pinsrb_Vdq_Ed_Ib SANITY
when 33 => NEXT_OUTS <= 482; -- insertps_Vps_Wss_Ib SANITY
when 34 => NEXT_OUTS <= 1391; -- pinsrd_Vdq_Ed_Ib SANITY
when 64 => NEXT_OUTS <= 992; -- dpps_Vps_Wps_Ib SANITY
when 65 => NEXT_OUTS <= 1142; -- dppd_Vpd_Wpd_Ib SANITY
when 66 => NEXT_OUTS <= 1526; -- mpsadbw_Vdq_Wdq_Ib SANITY
when 68 => NEXT_OUTS <= 1608; -- pclmulqdq_Vdq_Wdq_Ib SANITY
when 96 => NEXT_OUTS <= 755; -- pcmpestrm_Vdq_Wdq_Ib SANITY
when 97 => NEXT_OUTS <= 609; -- pcmpestri_Vdq_Wdq_Ib SANITY
when 98 => NEXT_OUTS <= 1148; -- pcmpistrm_Vdq_Wdq_Ib SANITY
when 99 => NEXT_OUTS <= 589; -- pcmpistri_Vdq_Wdq_Ib SANITY
when 223 => NEXT_OUTS <= 473; -- aeskeygenassist_Vdq_Wdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 64 => NEXT_OUTS <= 1012; -- cmovow_Gw_Ew SANITY
when 65 => NEXT_OUTS <= 1074; -- cmovnow_Gw_Ew SANITY
when 66 => NEXT_OUTS <= 1643; -- cmovcw_Gw_Ew SANITY
when 67 => NEXT_OUTS <= 1095; -- cmovncw_Gw_Ew SANITY
when 68 => NEXT_OUTS <= 264; -- cmovzw_Gw_Ew SANITY
when 69 => NEXT_OUTS <= 1548; -- cmovnzw_Gw_Ew SANITY
when 70 => NEXT_OUTS <= 558; -- cmovnaw_Gw_Ew SANITY
when 71 => NEXT_OUTS <= 511; -- cmovaw_Gw_Ew SANITY
when 72 => NEXT_OUTS <= 823; -- cmovsw_Gw_Ew SANITY
when 73 => NEXT_OUTS <= 350; -- cmovnsw_Gw_Ew SANITY
when 74 => NEXT_OUTS <= 918; -- cmovpw_Gw_Ew SANITY
when 75 => NEXT_OUTS <= 698; -- cmovnpw_Gw_Ew SANITY
when 76 => NEXT_OUTS <= 1125; -- cmovlw_Gw_Ew SANITY
when 77 => NEXT_OUTS <= 1305; -- cmovnlw_Gw_Ew SANITY
when 78 => NEXT_OUTS <= 1071; -- cmovngw_Gw_Ew SANITY
when 79 => NEXT_OUTS <= 342; -- cmovgw_Gw_Ew SANITY
when 80 => NEXT_OUTS <= 235; -- movmskpd_Gd_Upd SANITY
when 81 => NEXT_OUTS <= 1651; -- sqrtpd_Vpd_Wpd SANITY
when 84 => NEXT_OUTS <= 17; -- andpd_Vpd_Wpd SANITY
when 85 => NEXT_OUTS <= 492; -- andnpd_Vpd_Wpd SANITY
when 86 => NEXT_OUTS <= 646; -- orpd_Vpd_Wpd SANITY
when 87 => NEXT_OUTS <= 1206; -- xorpd_Vpd_Wpd SANITY
when 88 => NEXT_OUTS <= 460; -- addpd_Vpd_Wpd SANITY
when 89 => NEXT_OUTS <= 1264; -- mulpd_Vpd_Wpd SANITY
when 90 => NEXT_OUTS <= 1243; -- cvtpd2ps_Vps_Wpd SANITY
when 91 => NEXT_OUTS <= 348; -- cvtps2dq_Vdq_Wps SANITY
when 92 => NEXT_OUTS <= 1218; -- subpd_Vpd_Wpd SANITY
when 93 => NEXT_OUTS <= 691; -- minpd_Vpd_Wpd SANITY
when 94 => NEXT_OUTS <= 284; -- divpd_Vpd_Wpd SANITY
when 95 => NEXT_OUTS <= 688; -- maxpd_Vpd_Wpd SANITY
when 96 => NEXT_OUTS <= 10; -- punpcklbw_Vdq_Wdq SANITY
when 97 => NEXT_OUTS <= 285; -- punpcklwd_Vdq_Wdq SANITY
when 98 => NEXT_OUTS <= 1238; -- punpckldq_Vdq_Wdq SANITY
when 99 => NEXT_OUTS <= 68; -- packsswb_Vdq_Wdq SANITY
when 100 => NEXT_OUTS <= 1040; -- pcmpgtb_Vdq_Wdq SANITY
when 101 => NEXT_OUTS <= 659; -- pcmpgtw_Vdq_Wdq SANITY
when 102 => NEXT_OUTS <= 22; -- pcmpgtd_Vdq_Wdq SANITY
when 103 => NEXT_OUTS <= 1440; -- packuswb_Vdq_Wdq SANITY
when 104 => NEXT_OUTS <= 973; -- punpckhbw_Vdq_Wdq SANITY
when 105 => NEXT_OUTS <= 433; -- punpckhwd_Vdq_Wdq SANITY
when 106 => NEXT_OUTS <= 435; -- punpckhdq_Vdq_Wdq SANITY
when 107 => NEXT_OUTS <= 1331; -- packssdw_Vdq_Wdq SANITY
when 108 => NEXT_OUTS <= 1291; -- punpcklqdq_Vdq_Wdq SANITY
when 109 => NEXT_OUTS <= 125; -- punpckhqdq_Vdq_Wdq SANITY
when 110 => NEXT_OUTS <= 1428; -- movd_Vdq_Ed SANITY
when 111 => NEXT_OUTS <= 80; -- movdqa_Vdq_Wdq SANITY
when 112 => NEXT_OUTS <= 1097; -- pshufd_Vdq_Wdq_Ib SANITY
when 113 =>
case OP4 is
when 16 => NEXT_OUTS <= 1491; -- psrlw_Udq_Ib SANITY
when 32 => NEXT_OUTS <= 1485; -- psraw_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 483; -- psllw_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 114 =>
case OP4 is
when 16 => NEXT_OUTS <= 989; -- psrld_Udq_Ib SANITY
when 32 => NEXT_OUTS <= 1106; -- psrad_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 1311; -- pslld_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 115 =>
case OP4 is
when 16 => NEXT_OUTS <= 1202; -- psrlq_Udq_Ib SANITY
when 24 => NEXT_OUTS <= 456; -- psrldq_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 1572; -- psllq_Udq_Ib SANITY
when 56 => NEXT_OUTS <= 832; -- pslldq_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 116 => NEXT_OUTS <= 305; -- pcmpeqb_Vdq_Wdq SANITY
when 117 => NEXT_OUTS <= 319; -- pcmpeqw_Vdq_Wdq SANITY
when 118 => NEXT_OUTS <= 542; -- pcmpeqd_Vdq_Wdq SANITY
when 124 => NEXT_OUTS <= 1271; -- haddpd_Vpd_Wpd SANITY
when 125 => NEXT_OUTS <= 838; -- hsubpd_Vpd_Wpd SANITY
when 126 =>
case OP4 is
when 0 => NEXT_OUTS <= 694; -- movd_Ed_Vd SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 127 => NEXT_OUTS <= 1023; -- movdqa_Wdq_Vdq SANITY
when 128 => NEXT_OUTS <= 847; -- jo_Jw SANITY
when 129 => NEXT_OUTS <= 1308; -- jno_Jw SANITY
when 130 => NEXT_OUTS <= 1284; -- jb_Jw SANITY
when 131 => NEXT_OUTS <= 952; -- jnb_Jw SANITY
when 132 => NEXT_OUTS <= 12; -- jz_Jw SANITY
when 133 => NEXT_OUTS <= 1066; -- jnz_Jw SANITY
when 134 => NEXT_OUTS <= 679; -- jbe_Jw SANITY
when 135 => NEXT_OUTS <= 1498; -- jnbe_Jw SANITY
when 136 => NEXT_OUTS <= 1048; -- js_Jw SANITY
when 137 => NEXT_OUTS <= 1226; -- jns_Jw SANITY
when 138 => NEXT_OUTS <= 1403; -- jp_Jw SANITY
when 139 => NEXT_OUTS <= 1534; -- jnp_Jw SANITY
when 140 => NEXT_OUTS <= 1445; -- jl_Jw SANITY
when 141 => NEXT_OUTS <= 1531; -- jnl_Jw SANITY
when 142 => NEXT_OUTS <= 333; -- jle_Jw SANITY
when 143 => NEXT_OUTS <= 678; -- jnle_Jw SANITY
when 160 => NEXT_OUTS <= 1605; -- pushw_FS SANITY
when 161 => NEXT_OUTS <= 1151; -- popw_FS SANITY
when 163 => NEXT_OUTS <= 855; -- btw_Ew_Gw SANITY
when 164 => NEXT_OUTS <= 443; -- shldw_Ew_Gw_Ib SANITY
when 165 => NEXT_OUTS <= 1018; -- shldw_Ew_Gw_CL SANITY
when 168 => NEXT_OUTS <= 1061; -- pushw_GS SANITY
when 169 => NEXT_OUTS <= 1551; -- popw_GS SANITY
when 171 => NEXT_OUTS <= 1187; -- btsw_Ew_Gw SANITY
when 172 => NEXT_OUTS <= 1222; -- shrdw_Ew_Gw_Ib SANITY
when 173 => NEXT_OUTS <= 268; -- shrdw_Ew_Gw_CL SANITY
when 175 => NEXT_OUTS <= 306; -- imulw_Gw_Ew SANITY
when 177 => NEXT_OUTS <= 874; -- cmpxchgw_Ew_Gw SANITY
when 178 => NEXT_OUTS <= 1215; -- lssw_Gw_Mp SANITY
when 179 => NEXT_OUTS <= 1070; -- btrw_Ew_Gw SANITY
when 180 => NEXT_OUTS <= 1461; -- lfsw_Gw_Mp SANITY
when 181 => NEXT_OUTS <= 1139; -- lgsw_Gw_Mp SANITY
when 182 => NEXT_OUTS <= 153; -- movzbw_Gw_Eb SANITY
when 186 =>
case OP4 is
when 32 => NEXT_OUTS <= 497; -- btw_Ew_Ib SANITY
when 40 => NEXT_OUTS <= 796; -- btsw_Ew_Ib SANITY
when 48 => NEXT_OUTS <= 872; -- btrw_Ew_Ib SANITY
when 56 => NEXT_OUTS <= 157; -- btcw_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 232; -- btcw_Ew_Gw SANITY
when 188 => NEXT_OUTS <= 575; -- bsfw_Gw_Ew SANITY
when 189 => NEXT_OUTS <= 1341; -- bsrw_Gw_Ew SANITY
when 190 => NEXT_OUTS <= 1577; -- movsbw_Gw_Eb SANITY
when 193 => NEXT_OUTS <= 1568; -- xaddw_Ew_Gw SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 550; -- cmppd_Vpd_Wpd_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 196 =>
case OP4 is
when 0 => NEXT_OUTS <= 1470; -- pinsrw_Vdq_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 197 => NEXT_OUTS <= 1585; -- pextrw_Gd_Udq_Ib SANITY
when 198 => NEXT_OUTS <= 79; -- shufpd_Vpd_Wpd_Ib SANITY
when 199 =>
case OP4 is
when 48 => NEXT_OUTS <= 647; -- vmclear_Mq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 208 => NEXT_OUTS <= 510; -- addsubpd_Vpd_Wpd SANITY
when 209 => NEXT_OUTS <= 633; -- psrlw_Vdq_Wdq SANITY
when 210 => NEXT_OUTS <= 567; -- psrld_Vdq_Wdq SANITY
when 211 => NEXT_OUTS <= 666; -- psrlq_Vdq_Wdq SANITY
when 212 => NEXT_OUTS <= 627; -- paddq_Vdq_Wdq SANITY
when 213 => NEXT_OUTS <= 136; -- pmullw_Vdq_Wdq SANITY
when 214 => NEXT_OUTS <= 532; -- movq_Wq_Vq SANITY
when 215 => NEXT_OUTS <= 559; -- pmovmskb_Gd_Udq SANITY
when 216 => NEXT_OUTS <= 1422; -- psubusb_Vdq_Wdq SANITY
when 217 => NEXT_OUTS <= 724; -- psubusw_Vdq_Wdq SANITY
when 218 => NEXT_OUTS <= 1370; -- pminub_Vdq_Wdq SANITY
when 219 => NEXT_OUTS <= 110; -- pand_Vdq_Wdq SANITY
when 220 => NEXT_OUTS <= 385; -- paddusb_Vdq_Wdq SANITY
when 221 => NEXT_OUTS <= 967; -- paddusw_Vdq_Wdq SANITY
when 222 => NEXT_OUTS <= 964; -- pmaxub_Vdq_Wdq SANITY
when 223 => NEXT_OUTS <= 50; -- pandn_Vdq_Wdq SANITY
when 224 => NEXT_OUTS <= 786; -- pavgb_Vdq_Wdq SANITY
when 225 => NEXT_OUTS <= 1310; -- psraw_Vdq_Wdq SANITY
when 226 => NEXT_OUTS <= 1580; -- psrad_Vdq_Wdq SANITY
when 227 => NEXT_OUTS <= 216; -- pavgw_Vdq_Wdq SANITY
when 228 => NEXT_OUTS <= 790; -- pmulhuw_Vdq_Wdq SANITY
when 229 => NEXT_OUTS <= 26; -- pmulhw_Vdq_Wdq SANITY
when 230 => NEXT_OUTS <= 101; -- cvttpd2dq_Vq_Wpd SANITY
when 231 => NEXT_OUTS <= 1519; -- movntdq_Mdq_Vdq SANITY
when 232 => NEXT_OUTS <= 117; -- psubsb_Vdq_Wdq SANITY
when 233 => NEXT_OUTS <= 1279; -- psubsw_Vdq_Wdq SANITY
when 234 => NEXT_OUTS <= 941; -- pminsw_Vdq_Wdq SANITY
when 235 => NEXT_OUTS <= 573; -- por_Vdq_Wdq SANITY
when 236 => NEXT_OUTS <= 880; -- paddsb_Vdq_Wdq SANITY
when 237 => NEXT_OUTS <= 1569; -- paddsw_Vdq_Wdq SANITY
when 238 => NEXT_OUTS <= 1038; -- pmaxsw_Vdq_Wdq SANITY
when 239 => NEXT_OUTS <= 1313; -- pxor_Vdq_Wdq SANITY
when 241 => NEXT_OUTS <= 270; -- psllw_Vdq_Wdq SANITY
when 242 => NEXT_OUTS <= 190; -- pslld_Vdq_Wdq SANITY
when 243 => NEXT_OUTS <= 910; -- psllq_Vdq_Wdq SANITY
when 244 => NEXT_OUTS <= 673; -- pmuludq_Vdq_Wdq SANITY
when 245 => NEXT_OUTS <= 145; -- pmaddwd_Vdq_Wdq SANITY
when 246 => NEXT_OUTS <= 1254; -- psadbw_Vdq_Wdq SANITY
when 247 => NEXT_OUTS <= 1175; -- maskmovdqu_Vdq_Udq SANITY
when 248 => NEXT_OUTS <= 199; -- psubb_Vdq_Wdq SANITY
when 249 => NEXT_OUTS <= 1469; -- psubw_Vdq_Wdq SANITY
when 250 => NEXT_OUTS <= 481; -- psubd_Vdq_Wdq SANITY
when 251 => NEXT_OUTS <= 682; -- psubq_Vdq_Wdq SANITY
when 252 => NEXT_OUTS <= 1393; -- paddb_Vdq_Wdq SANITY
when 253 => NEXT_OUTS <= 1007; -- paddw_Vdq_Wdq SANITY
when 254 => NEXT_OUTS <= 505; -- paddd_Vdq_Wdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 17 => NEXT_OUTS <= 1556; -- adcw_Ew_Gw SANITY
when 19 => NEXT_OUTS <= 741; -- adcw_Gw_Ew SANITY
when 21 => NEXT_OUTS <= 896; -- adcw_AX_Iw SANITY
when 22 => NEXT_OUTS <= 876; -- pushw_SS SANITY
when 23 => NEXT_OUTS <= 1214; -- popw_SS SANITY
when 25 => NEXT_OUTS <= 1330; -- sbbw_Ew_Gw SANITY
when 27 => NEXT_OUTS <= 1014; -- sbbw_Gw_Ew SANITY
when 29 => NEXT_OUTS <= 92; -- sbbw_AX_Iw SANITY
when 30 => NEXT_OUTS <= 1352; -- pushw_DS SANITY
when 31 => NEXT_OUTS <= 760; -- popw_DS SANITY
when 33 => NEXT_OUTS <= 1650; -- andw_Ew_Gw SANITY
when 35 => NEXT_OUTS <= 375; -- andw_Gw_Ew SANITY
when 37 => NEXT_OUTS <= 1055; -- andw_AX_Iw SANITY
when 41 => NEXT_OUTS <= 781; -- subw_Ew_Gw SANITY
when 43 => NEXT_OUTS <= 225; -- subw_Gw_Ew SANITY
when 45 => NEXT_OUTS <= 556; -- subw_AX_Iw SANITY
when 49 => NEXT_OUTS <= 518; -- xorw_Ew_Gw SANITY
when 51 => NEXT_OUTS <= 845; -- xorw_Gw_Ew SANITY
when 53 => NEXT_OUTS <= 1265; -- xorw_AX_Iw SANITY
when 57 => NEXT_OUTS <= 1539; -- cmpw_Ew_Gw SANITY
when 59 => NEXT_OUTS <= 1487; -- cmpw_Gw_Ew SANITY
when 61 => NEXT_OUTS <= 303; -- cmpw_AX_Iw SANITY
when 64 => NEXT_OUTS <= 1278; -- incw_RX SANITY
when 72 =>
case OP3 is
when 15 =>
case OP4 is
when 58 =>
case OP5 is
when 22 => NEXT_OUTS <= 680; -- pextrq_Eq_Vdq_Ib SANITY
when 34 => NEXT_OUTS <= 475; -- pinsrq_Vdq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 110 => NEXT_OUTS <= 751; -- movq_Vdq_Eq SANITY
when 126 =>
case OP5 is
when 0 => NEXT_OUTS <= 382; -- movq_Eq_Vq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 80 => NEXT_OUTS <= 138; -- pushw_RX SANITY
when 88 => NEXT_OUTS <= 1654; -- popw_RX SANITY
when 96 => NEXT_OUTS <= 1441; -- pushaw SANITY
when 97 => NEXT_OUTS <= 336; -- popaw SANITY
when 98 => NEXT_OUTS <= 1252; -- boundw_Gw_Ma SANITY
when 104 => NEXT_OUTS <= 1172; -- pushw_Iw SANITY
when 105 => NEXT_OUTS <= 770; -- imulw_Gw_Ew_Iw SANITY
when 106 => NEXT_OUTS <= 1050; -- pushw_sIb SANITY
when 107 => NEXT_OUTS <= 440; -- imulw_Gw_Ew_sIb SANITY
when 109 => NEXT_OUTS <= 338; -- insw_Yw_DX SANITY
when 111 => NEXT_OUTS <= 745; -- outsw_DX_Xw SANITY
when 129 =>
case OP3 is
when 0 => NEXT_OUTS <= 203; -- addw_Ew_Iw SANITY
when 8 => NEXT_OUTS <= 1618; -- orw_Ew_Iw SANITY
when 16 => NEXT_OUTS <= 1025; -- adcw_Ew_Iw SANITY
when 24 => NEXT_OUTS <= 48; -- sbbw_Ew_Iw SANITY
when 32 => NEXT_OUTS <= 371; -- andw_Ew_Iw SANITY
when 40 => NEXT_OUTS <= 422; -- subw_Ew_Iw SANITY
when 48 => NEXT_OUTS <= 1395; -- xorw_Ew_Iw SANITY
when 56 => NEXT_OUTS <= 215; -- cmpw_Ew_Iw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP3 is
when 0 => NEXT_OUTS <= 1477; -- addw_Ew_sIb SANITY
when 8 => NEXT_OUTS <= 1244; -- orw_Ew_sIb SANITY
when 16 => NEXT_OUTS <= 1021; -- adcw_Ew_sIb SANITY
when 24 => NEXT_OUTS <= 1083; -- sbbw_Ew_sIb SANITY
when 32 => NEXT_OUTS <= 450; -- andw_Ew_sIb SANITY
when 40 => NEXT_OUTS <= 1277; -- subw_Ew_sIb SANITY
when 48 => NEXT_OUTS <= 672; -- xorw_Ew_sIb SANITY
when 56 => NEXT_OUTS <= 1479; -- cmpw_Ew_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 133 => NEXT_OUTS <= 1184; -- testw_Ew_Gw SANITY
when 135 => NEXT_OUTS <= 1030; -- xchgw_Ew_Gw SANITY
when 137 => NEXT_OUTS <= 1299; -- movw_Ew_Gw SANITY
when 139 => NEXT_OUTS <= 1537; -- movw_Gw_Ew SANITY
when 141 => NEXT_OUTS <= 1561; -- leaw_Gw_Mw SANITY
when 143 =>
case OP3 is
when 0 => NEXT_OUTS <= 312; -- popw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 145 => NEXT_OUTS <= 1468; -- xchgw_RX_AX SANITY
when 152 => NEXT_OUTS <= 71; -- cbw SANITY
when 153 => NEXT_OUTS <= 1204; -- cwd SANITY
when 154 => NEXT_OUTS <= 1107; -- lcall_Apw SANITY
when 156 => NEXT_OUTS <= 172; -- pushfw SANITY
when 157 => NEXT_OUTS <= 129; -- popfw SANITY
when 161 => NEXT_OUTS <= 1649; -- movw_AX_Ow SANITY
when 163 => NEXT_OUTS <= 1495; -- movw_Ow_AX SANITY
when 165 => NEXT_OUTS <= 1346; -- movsw_Yw_Xw SANITY
when 167 => NEXT_OUTS <= 1661; -- cmpsw_Yw_Xw SANITY
when 169 => NEXT_OUTS <= 359; -- testw_AX_Iw SANITY
when 171 => NEXT_OUTS <= 294; -- stosw_Yw_AX SANITY
when 173 => NEXT_OUTS <= 1451; -- lodsw_AX_Xw SANITY
when 175 => NEXT_OUTS <= 114; -- scasw_Yw_AX SANITY
when 184 => NEXT_OUTS <= 868; -- movw_RX_Iw SANITY
when 193 =>
case OP3 is
when 0 => NEXT_OUTS <= 208; -- rolw_Ew_Ib SANITY
when 8 => NEXT_OUTS <= 1590; -- rorw_Ew_Ib SANITY
when 16 => NEXT_OUTS <= 361; -- rclw_Ew_Ib SANITY
when 24 => NEXT_OUTS <= 1121; -- rcrw_Ew_Ib SANITY
when 32 => NEXT_OUTS <= 689; -- shlw_Ew_Ib SANITY
when 40 => NEXT_OUTS <= 1489; -- shrw_Ew_Ib SANITY
when 56 => NEXT_OUTS <= 636; -- sarw_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 196 => NEXT_OUTS <= 728; -- lesw_Gw_Mp SANITY
when 197 => NEXT_OUTS <= 1249; -- ldsw_Gw_Mp SANITY
when 199 =>
case OP3 is
when 0 => NEXT_OUTS <= 915; -- movw_Ew_Iw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 207 => NEXT_OUTS <= 1619; -- iretw SANITY
when 209 =>
case OP3 is
when 0 => NEXT_OUTS <= 1188; -- rolw_Ew_I1 SANITY
when 8 => NEXT_OUTS <= 1406; -- rorw_Ew_I1 SANITY
when 16 => NEXT_OUTS <= 890; -- rclw_Ew_I1 SANITY
when 24 => NEXT_OUTS <= 1529; -- rcrw_Ew_I1 SANITY
when 32 => NEXT_OUTS <= 1464; -- shlw_Ew_I1 SANITY
when 40 => NEXT_OUTS <= 648; -- shrw_Ew_I1 SANITY
when 56 => NEXT_OUTS <= 2; -- sarw_Ew_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP3 is
when 0 => NEXT_OUTS <= 1390; -- rolw_Ew_CL SANITY
when 8 => NEXT_OUTS <= 857; -- rorw_Ew_CL SANITY
when 16 => NEXT_OUTS <= 1163; -- rclw_Ew_CL SANITY
when 24 => NEXT_OUTS <= 471; -- rcrw_Ew_CL SANITY
when 32 => NEXT_OUTS <= 323; -- shlw_Ew_CL SANITY
when 40 => NEXT_OUTS <= 865; -- shrw_Ew_CL SANITY
when 56 => NEXT_OUTS <= 514; -- sarw_Ew_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 229 => NEXT_OUTS <= 927; -- inw_AX_Ib SANITY
when 231 => NEXT_OUTS <= 148; -- outw_Ib_AX SANITY
when 232 => NEXT_OUTS <= 1467; -- call_Jw SANITY
when 233 => NEXT_OUTS <= 1053; -- jmp_Jw SANITY
when 234 => NEXT_OUTS <= 1633; -- ljmp_Apw SANITY
when 237 => NEXT_OUTS <= 920; -- inw_AX_DX SANITY
when 239 => NEXT_OUTS <= 1626; -- outw_DX_AX SANITY
when 242 =>
case OP3 is
when 15 =>
case OP4 is
when 56 =>
case OP5 is
when 241 =>
case OP6 is
when 195 => NEXT_OUTS <= 1146; -- crc32_Gd_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 243 =>
case OP3 is
when 15 =>
case OP4 is
when 184 => NEXT_OUTS <= 95; -- popcnt_Gw_Ew SANITY
when 188 => NEXT_OUTS <= 536; -- tzcntw_Gw_Ew SANITY
when 189 => NEXT_OUTS <= 140; -- lzcntw_Gw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 247 =>
case OP3 is
when 0 => NEXT_OUTS <= 1427; -- testw_Ew_Iw SANITY
when 16 => NEXT_OUTS <= 380; -- notw_Ew SANITY
when 24 => NEXT_OUTS <= 1230; -- negw_Ew SANITY
when 32 => NEXT_OUTS <= 1033; -- mulw_AX_Ew SANITY
when 40 => NEXT_OUTS <= 1043; -- imulw_AX_Ew SANITY
when 48 => NEXT_OUTS <= 814; -- divw_AX_Ew SANITY
when 56 => NEXT_OUTS <= 1173; -- idivw_AX_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP3 is
when 0 => NEXT_OUTS <= 1282; -- incw_Ew SANITY
when 8 => NEXT_OUTS <= 462; -- decw_Ew SANITY
when 16 => NEXT_OUTS <= 1609; -- call_Ew SANITY
when 32 => NEXT_OUTS <= 1300; -- jmp_Ew SANITY
when 48 => NEXT_OUTS <= 1490; -- pushw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 103 =>
case OP2 is
when 227 => NEXT_OUTS <= 465; -- jcxz_Jb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 104 =>
case OP2 is
when 0 => NEXT_OUTS <= 591; -- pushl_Id SANITY
when 1 => NEXT_OUTS <= 1658; -- pushq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 105 => NEXT_OUTS <= 438; -- imull_Gd_Ed_Id SANITY
when 106 =>
case OP2 is
when 0 => NEXT_OUTS <= 392; -- pushl_sIb SANITY
when 1 => NEXT_OUTS <= 314; -- pushq_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 107 => NEXT_OUTS <= 579; -- imull_Gd_Ed_sIb SANITY
when 108 => NEXT_OUTS <= 1177; -- insb_Yb_DX SANITY
when 109 => NEXT_OUTS <= 709; -- insl_Yd_DX SANITY
when 110 => NEXT_OUTS <= 1225; -- outsb_DX_Xb SANITY
when 111 => NEXT_OUTS <= 461; -- outsl_DX_Xd SANITY
when 112 => NEXT_OUTS <= 921; -- jo_Jb SANITY
when 113 => NEXT_OUTS <= 229; -- jno_Jb SANITY
when 114 => NEXT_OUTS <= 82; -- jb_Jb SANITY
when 115 => NEXT_OUTS <= 241; -- jnb_Jb SANITY
when 116 => NEXT_OUTS <= 1506; -- jz_Jb SANITY
when 117 => NEXT_OUTS <= 621; -- jnz_Jb SANITY
when 118 => NEXT_OUTS <= 1143; -- jbe_Jb SANITY
when 119 => NEXT_OUTS <= 642; -- jnbe_Jb SANITY
when 120 => NEXT_OUTS <= 787; -- js_Jb SANITY
when 121 => NEXT_OUTS <= 668; -- jns_Jb SANITY
when 122 => NEXT_OUTS <= 108; -- jp_Jb SANITY
when 123 => NEXT_OUTS <= 1104; -- jnp_Jb SANITY
when 124 => NEXT_OUTS <= 1336; -- jl_Jb SANITY
when 125 => NEXT_OUTS <= 875; -- jnl_Jb SANITY
when 126 => NEXT_OUTS <= 976; -- jle_Jb SANITY
when 127 => NEXT_OUTS <= 1149; -- jnle_Jb SANITY
when 128 =>
case OP2 is
when 0 => NEXT_OUTS <= 237; -- addb_Eb_Ib SANITY
when 8 => NEXT_OUTS <= 1665; -- orb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 652; -- adcb_Eb_Ib SANITY
when 24 => NEXT_OUTS <= 32; -- sbbb_Eb_Ib SANITY
when 32 => NEXT_OUTS <= 654; -- andb_Eb_Ib SANITY
when 40 => NEXT_OUTS <= 1135; -- subb_Eb_Ib SANITY
when 48 => NEXT_OUTS <= 917; -- xorb_Eb_Ib SANITY
when 56 => NEXT_OUTS <= 1315; -- cmpb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 129 =>
case OP2 is
when 0 => NEXT_OUTS <= 825; -- addl_Ed_Id SANITY
when 8 => NEXT_OUTS <= 1656; -- orl_Ed_Id SANITY
when 16 => NEXT_OUTS <= 644; -- adcl_Ed_Id SANITY
when 24 => NEXT_OUTS <= 164; -- sbbl_Ed_Id SANITY
when 32 => NEXT_OUTS <= 1316; -- andl_Ed_Id SANITY
when 40 => NEXT_OUTS <= 634; -- subl_Ed_Id SANITY
when 48 => NEXT_OUTS <= 107; -- xorl_Ed_Id SANITY
when 56 => NEXT_OUTS <= 421; -- cmpl_Ed_Id SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP2 is
when 0 => NEXT_OUTS <= 1552; -- addl_Ed_sIb SANITY
when 8 => NEXT_OUTS <= 1363; -- orl_Ed_sIb SANITY
when 16 => NEXT_OUTS <= 1062; -- adcl_Ed_sIb SANITY
when 24 => NEXT_OUTS <= 193; -- sbbl_Ed_sIb SANITY
when 32 => NEXT_OUTS <= 521; -- andl_Ed_sIb SANITY
when 40 => NEXT_OUTS <= 544; -- subl_Ed_sIb SANITY
when 48 => NEXT_OUTS <= 85; -- xorl_Ed_sIb SANITY
when 56 => NEXT_OUTS <= 1096; -- cmpl_Ed_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 132 => NEXT_OUTS <= 686; -- testb_Eb_Gb SANITY
when 133 => NEXT_OUTS <= 23; -- testl_Ed_Gd SANITY
when 134 => NEXT_OUTS <= 500; -- xchgb_Eb_Gb SANITY
when 135 => NEXT_OUTS <= 1501; -- xchgl_Ed_Gd SANITY
when 136 => NEXT_OUTS <= 373; -- movb_Eb_Gb SANITY
when 137 => NEXT_OUTS <= 1092; -- movl_Ed_Gd SANITY
when 138 => NEXT_OUTS <= 213; -- movb_Gb_Eb SANITY
when 139 => NEXT_OUTS <= 160; -- movl_Gd_Ed SANITY
when 140 => NEXT_OUTS <= 1113; -- movw_Ew_Sw SANITY
when 141 => NEXT_OUTS <= 53; -- leal_Gd_Md SANITY
when 142 => NEXT_OUTS <= 159; -- movw_Sw_Ew SANITY
when 143 =>
case OP2 is
when 0 =>
case OP3 is
when 0 => NEXT_OUTS <= 1475; -- popl_Ed SANITY
when 1 => NEXT_OUTS <= 351; -- popq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 144 => NEXT_OUTS <= 607; -- nop SANITY
when 145 => NEXT_OUTS <= 608; -- xchgl_ERX_EAX SANITY
when 152 => NEXT_OUTS <= 1573; -- cwde SANITY
when 153 => NEXT_OUTS <= 1060; -- cdq SANITY
when 154 => NEXT_OUTS <= 112; -- lcall_Apd SANITY
when 155 => NEXT_OUTS <= 63; -- fwait SANITY
when 156 =>
case OP2 is
when 0 => NEXT_OUTS <= 280; -- pushfl SANITY
when 1 => NEXT_OUTS <= 1117; -- pushfq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 157 =>
case OP2 is
when 0 => NEXT_OUTS <= 42; -- popfl SANITY
when 1 => NEXT_OUTS <= 692; -- popfq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 158 => NEXT_OUTS <= 1625; -- sahf SANITY
when 159 => NEXT_OUTS <= 344; -- lahf SANITY
when 160 => NEXT_OUTS <= 1301; -- movb_AL_Ob SANITY
when 161 => NEXT_OUTS <= 432; -- movl_EAX_Od SANITY
when 162 => NEXT_OUTS <= 1181; -- movb_Ob_AL SANITY
when 163 => NEXT_OUTS <= 121; -- movl_Od_EAX SANITY
when 164 => NEXT_OUTS <= 113; -- movsb_Yb_Xb SANITY
when 165 => NEXT_OUTS <= 1196; -- movsl_Yd_Xd SANITY
when 166 => NEXT_OUTS <= 260; -- cmpsb_Yb_Xb SANITY
when 167 => NEXT_OUTS <= 1493; -- cmpsl_Yd_Xd SANITY
when 168 => NEXT_OUTS <= 1250; -- testb_AL_Ib SANITY
when 169 => NEXT_OUTS <= 1069; -- testl_EAX_Id SANITY
when 170 => NEXT_OUTS <= 695; -- stosb_Yb_AL SANITY
when 171 => NEXT_OUTS <= 196; -- stosl_Yd_EAX SANITY
when 172 => NEXT_OUTS <= 1513; -- lodsb_AL_Xb SANITY
when 173 => NEXT_OUTS <= 1246; -- lodsl_EAX_Xd SANITY
when 174 => NEXT_OUTS <= 374; -- scasb_Yb_AL SANITY
when 175 => NEXT_OUTS <= 1421; -- scasl_Yd_EAX SANITY
when 176 => NEXT_OUTS <= 130; -- movb_R8_Ib SANITY
when 184 => NEXT_OUTS <= 576; -- movl_ERX_Id SANITY
when 192 =>
case OP2 is
when 0 => NEXT_OUTS <= 702; -- rolb_Eb_Ib SANITY
when 8 => NEXT_OUTS <= 639; -- rorb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 1039; -- rclb_Eb_Ib SANITY
when 24 => NEXT_OUTS <= 1000; -- rcrb_Eb_Ib SANITY
when 32 => NEXT_OUTS <= 43; -- shlb_Eb_Ib SANITY
when 40 => NEXT_OUTS <= 729; -- shrb_Eb_Ib SANITY
when 56 => NEXT_OUTS <= 1076; -- sarb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 193 =>
case OP2 is
when 0 => NEXT_OUTS <= 1195; -- roll_Ed_Ib SANITY
when 8 => NEXT_OUTS <= 366; -- rorl_Ed_Ib SANITY
when 16 => NEXT_OUTS <= 899; -- rcll_Ed_Ib SANITY
when 24 => NEXT_OUTS <= 1500; -- rcrl_Ed_Ib SANITY
when 32 => NEXT_OUTS <= 369; -- shll_Ed_Ib SANITY
when 40 => NEXT_OUTS <= 1540; -- shrl_Ed_Ib SANITY
when 56 => NEXT_OUTS <= 547; -- sarl_Ed_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 194 => NEXT_OUTS <= 109; -- ret_Iw SANITY
when 195 => NEXT_OUTS <= 198; -- ret SANITY
when 196 =>
case OP2 is
when 0 => NEXT_OUTS <= 791; -- lesl_Gd_Mp SANITY
when 225 =>
case OP3 is
when 249 =>
case OP4 is
when 110 => NEXT_OUTS <= 987; -- vmovq_Vdq_Eq SANITY
when 126 =>
case OP5 is
when 0 => NEXT_OUTS <= 1110; -- vmovq_Eq_Vq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 226 =>
case OP3 is
when 80 =>
case OP4 is
when 242 => NEXT_OUTS <= 67; -- andn_Gy_By_Ey SANITY
when 243 =>
case OP5 is
when 8 => NEXT_OUTS <= 1356; -- blsr_By_Ey SANITY
when 16 => NEXT_OUTS <= 1082; -- blsmsk_By_Ey SANITY
when 24 => NEXT_OUTS <= 715; -- blsi_By_Ey SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 245 => NEXT_OUTS <= 1439; -- bzhi_Gy_Ey_By SANITY
when 247 => NEXT_OUTS <= 31; -- bextr_Gy_Ey_By SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 81 =>
case OP4 is
when 0 => NEXT_OUTS <= 3; -- vpshufb_Vdq_Hdq_Wdq SANITY
when 1 => NEXT_OUTS <= 552; -- vphaddw_Vdq_Hdq_Wdq SANITY
when 2 => NEXT_OUTS <= 13; -- vphaddd_Vdq_Hdq_Wdq SANITY
when 3 => NEXT_OUTS <= 613; -- vphaddsw_Vdq_Hdq_Wdq SANITY
when 4 => NEXT_OUTS <= 309; -- vpmaddubsw_Vdq_Hdq_Wdq SANITY
when 5 => NEXT_OUTS <= 764; -- vphsubw_Vdq_Hdq_Wdq SANITY
when 6 => NEXT_OUTS <= 1015; -- vphsubd_Vdq_Hdq_Wdq SANITY
when 7 => NEXT_OUTS <= 266; -- vphsubsw_Vdq_Hdq_Wdq SANITY
when 8 => NEXT_OUTS <= 774; -- vpsignb_Vdq_Hdq_Wdq SANITY
when 9 => NEXT_OUTS <= 1342; -- vpsignw_Vdq_Hdq_Wdq SANITY
when 10 => NEXT_OUTS <= 1156; -- vpsignd_Vdq_Hdq_Wdq SANITY
when 11 => NEXT_OUTS <= 15; -- vpmulhrsw_Vdq_Hdq_Wdq SANITY
when 12 => NEXT_OUTS <= 538; -- vpermilps_Vps_Hps_Wps SANITY
when 13 => NEXT_OUTS <= 650; -- vpermilpd_Vpd_Hpd_Wpd SANITY
when 22 => NEXT_OUTS <= 1237; -- vpermps_Vps_Hps_Wps SANITY
when 40 => NEXT_OUTS <= 419; -- vpmuldq_Vdq_Hdq_Wdq SANITY
when 41 => NEXT_OUTS <= 1414; -- vpcmpeqq_Vdq_Hdq_Wdq SANITY
when 43 => NEXT_OUTS <= 1472; -- vpackusdw_Vdq_Hdq_Wdq SANITY
when 44 => NEXT_OUTS <= 376; -- vmaskmovps_Vps_Hps_Mps SANITY
when 45 => NEXT_OUTS <= 704; -- vmaskmovpd_Vpd_Hpd_Mpd SANITY
when 46 => NEXT_OUTS <= 706; -- vmaskmovps_Mps_Hps_Vps SANITY
when 47 => NEXT_OUTS <= 568; -- vmaskmovpd_Mpd_Hpd_Vpd SANITY
when 54 => NEXT_OUTS <= 944; -- vpermd_Vdq_Hdq_Wdq SANITY
when 55 => NEXT_OUTS <= 632; -- vpcmpgtq_Vdq_Hdq_Wdq SANITY
when 56 => NEXT_OUTS <= 1507; -- vpminsb_Vdq_Hdq_Wdq SANITY
when 57 => NEXT_OUTS <= 763; -- vpminsd_Vdq_Hdq_Wdq SANITY
when 58 => NEXT_OUTS <= 1209; -- vpminuw_Vdq_Hdq_Wdq SANITY
when 59 => NEXT_OUTS <= 545; -- vpminud_Vdq_Hdq_Wdq SANITY
when 60 => NEXT_OUTS <= 379; -- vpmaxsb_Vdq_Hdq_Wdq SANITY
when 61 => NEXT_OUTS <= 1221; -- vpmaxsd_Vdq_Hdq_Wdq SANITY
when 62 => NEXT_OUTS <= 149; -- vpmaxuw_Vdq_Hdq_Wdq SANITY
when 63 => NEXT_OUTS <= 1176; -- vpmaxud_Vdq_Hdq_Wdq SANITY
when 64 => NEXT_OUTS <= 274; -- vpmulld_Vdq_Hdq_Wdq SANITY
when 69 => NEXT_OUTS <= 861; -- vpsrlvd_Vdq_Hdq_Wdq SANITY
when 70 => NEXT_OUTS <= 176; -- vpsravd_Vdq_Hdq_Wdq SANITY
when 71 => NEXT_OUTS <= 1486; -- vpsllvd_Vdq_Hdq_Wdq SANITY
when 140 => NEXT_OUTS <= 713; -- vmaskmovd_Vdq_Hdq_Mdq SANITY
when 142 => NEXT_OUTS <= 1517; -- vmaskmovq_Mdq_Hdq_Vdq SANITY
when 144 => NEXT_OUTS <= 1647; -- vgatherdd_Vdq_VSib_Hdq SANITY
when 145 => NEXT_OUTS <= 1212; -- vgatherqd_Vdq_VSib_Hdq SANITY
when 146 => NEXT_OUTS <= 1283; -- vgatherdps_Vps_VSib_Hps SANITY
when 147 => NEXT_OUTS <= 1168; -- vgatherqps_Vps_VSib_Hps SANITY
when 150 => NEXT_OUTS <= 222; -- vfmaddsub132ps_Vps_Hps_Wps SANITY
when 151 => NEXT_OUTS <= 830; -- vfmsubadd132ps_Vps_Hps_Wps SANITY
when 152 => NEXT_OUTS <= 954; -- vfmadd132ps_Vps_Hps_Wps SANITY
when 153 => NEXT_OUTS <= 924; -- vfmadd132ss_Vps_Hss_Wss SANITY
when 154 => NEXT_OUTS <= 1516; -- vfmsub132ps_Vps_Hps_Wps SANITY
when 155 => NEXT_OUTS <= 795; -- vfmsub132ss_Vps_Hss_Wss SANITY
when 156 => NEXT_OUTS <= 1455; -- vfnmadd132ps_Vps_Hps_Wps SANITY
when 157 => NEXT_OUTS <= 1084; -- vfnmadd132ss_Vps_Hss_Wss SANITY
when 158 => NEXT_OUTS <= 1351; -- vfnmsub132ps_Vps_Hps_Wps SANITY
when 159 => NEXT_OUTS <= 1635; -- vfnmsub132ss_Vps_Hss_Wss SANITY
when 166 => NEXT_OUTS <= 853; -- vfmaddsub213ps_Vps_Hps_Wps SANITY
when 167 => NEXT_OUTS <= 779; -- vfmsubadd213ps_Vps_Hps_Wps SANITY
when 168 => NEXT_OUTS <= 963; -- vfmadd213ps_Vps_Hps_Wps SANITY
when 169 => NEXT_OUTS <= 643; -- vfmadd213ss_Vps_Hss_Wss SANITY
when 170 => NEXT_OUTS <= 842; -- vfmsub213ps_Vps_Hps_Wps SANITY
when 171 => NEXT_OUTS <= 761; -- vfmsub213ss_Vps_Hss_Wss SANITY
when 172 => NEXT_OUTS <= 1600; -- vfnmadd213ps_Vps_Hps_Wps SANITY
when 173 => NEXT_OUTS <= 846; -- vfnmadd213ss_Vps_Hss_Wss SANITY
when 174 => NEXT_OUTS <= 116; -- vfnmsub213ps_Vps_Hps_Wps SANITY
when 175 => NEXT_OUTS <= 977; -- vfnmsub213ss_Vps_Hss_Wss SANITY
when 182 => NEXT_OUTS <= 204; -- vfmaddsub231ps_Vps_Hps_Wps SANITY
when 183 => NEXT_OUTS <= 1629; -- vfmsubadd231ps_Vps_Hps_Wps SANITY
when 184 => NEXT_OUTS <= 298; -- vfmadd231ps_Vps_Hps_Wps SANITY
when 185 => NEXT_OUTS <= 945; -- vfmadd231ss_Vps_Hss_Wss SANITY
when 186 => NEXT_OUTS <= 844; -- vfmsub231ps_Vps_Hps_Wps SANITY
when 187 => NEXT_OUTS <= 782; -- vfmsub231ss_Vps_Hss_Wss SANITY
when 188 => NEXT_OUTS <= 619; -- vfnmadd231ps_Vps_Hps_Wps SANITY
when 189 => NEXT_OUTS <= 1340; -- vfnmadd231ss_Vps_Hss_Wss SANITY
when 190 => NEXT_OUTS <= 562; -- vfnmsub231ps_Vps_Hps_Wps SANITY
when 191 => NEXT_OUTS <= 720; -- vfnmsub231ss_Vps_Hss_Wss SANITY
when 219 => NEXT_OUTS <= 302; -- vaesimc_Vdq_Wdq SANITY
when 220 => NEXT_OUTS <= 477; -- vaesenc_Vdq_Hdq_Wdq SANITY
when 221 => NEXT_OUTS <= 1167; -- vaesenclast_Vdq_Hdq_Wdq SANITY
when 222 => NEXT_OUTS <= 1575; -- vaesdec_Vdq_Hdq_Wdq SANITY
when 223 => NEXT_OUTS <= 170; -- vaesdeclast_Vdq_Hdq_Wdq SANITY
when 247 => NEXT_OUTS <= 1327; -- shlx_Gy_Ey_By SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 82 =>
case OP4 is
when 245 => NEXT_OUTS <= 1622; -- pext_Gy_By_Ey SANITY
when 247 => NEXT_OUTS <= 1217; -- sarx_Gy_Ey_By SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 83 =>
case OP4 is
when 245 => NEXT_OUTS <= 1372; -- pdep_Gy_By_Ey SANITY
when 247 => NEXT_OUTS <= 1368; -- shrx_Gy_Ey_By SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 121 =>
case OP4 is
when 14 => NEXT_OUTS <= 802; -- vtestps_Vps_Wps SANITY
when 15 => NEXT_OUTS <= 744; -- vtestpd_Vpd_Wpd SANITY
when 19 => NEXT_OUTS <= 1481; -- vcvtph2ps_Vps_Wq SANITY
when 23 => NEXT_OUTS <= 1201; -- vptest_Vdq_Wdq SANITY
when 24 => NEXT_OUTS <= 1565; -- vbroadcastss_Vps_Wss SANITY
when 25 => NEXT_OUTS <= 1637; -- vbroadcastsd_Vpd_Wsd SANITY
when 26 => NEXT_OUTS <= 44; -- vbroadcastf128_Vdq_Mdq SANITY
when 28 => NEXT_OUTS <= 656; -- vpabsb_Vdq_Hdq_Wdq SANITY
when 29 => NEXT_OUTS <= 1191; -- vpabsw_Vdq_Hdq_Wdq SANITY
when 30 => NEXT_OUTS <= 1350; -- vpabsd_Vdq_Hdq_Wdq SANITY
when 32 =>
case OP5 is
when 1 => NEXT_OUTS <= 387; -- vpmovsxbw_Vdq_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 33 => NEXT_OUTS <= 1091; -- vpmovsxbd_Vdq_Wd SANITY
when 34 => NEXT_OUTS <= 586; -- vpmovsxbq_Vdq_Ww SANITY
when 35 => NEXT_OUTS <= 238; -- vpmovsxwd_Vdq_Wq SANITY
when 36 => NEXT_OUTS <= 600; -- vpmovsxwq_Vdq_Wd SANITY
when 37 => NEXT_OUTS <= 119; -- vpmovsxdq_Vdq_Wq SANITY
when 42 => NEXT_OUTS <= 898; -- vmovntdqa_Vdq_Mdq SANITY
when 48 => NEXT_OUTS <= 749; -- vpmovzxbw_Vdq_Wq SANITY
when 49 => NEXT_OUTS <= 593; -- vpmovzxbd_Vdq_Wd SANITY
when 50 => NEXT_OUTS <= 716; -- vpmovzxbq_Vdq_Ww SANITY
when 51 => NEXT_OUTS <= 1322; -- vpmovzxwd_Vdq_Wq SANITY
when 52 => NEXT_OUTS <= 882; -- vpmovzxwq_Vdq_Wd SANITY
when 53 => NEXT_OUTS <= 247; -- vpmovzxdq_Vdq_Wq SANITY
when 65 => NEXT_OUTS <= 34; -- vphminposuw_Vdq_Wdq SANITY
when 88 => NEXT_OUTS <= 1318; -- vpbroadcastd_Vdq_Wd SANITY
when 89 => NEXT_OUTS <= 723; -- vpbroadcastq_Vdq_Wq SANITY
when 90 => NEXT_OUTS <= 1377; -- vbroadcasti128_Vdq_Mdq SANITY
when 120 => NEXT_OUTS <= 670; -- vpbroadcastb_Vdq_Wb SANITY
when 121 => NEXT_OUTS <= 1420; -- vpbroadcastw_Vdq_Ww SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 209 =>
case OP4 is
when 69 => NEXT_OUTS <= 454; -- vpsrlvq_Vdq_Hdq_Wdq SANITY
when 71 => NEXT_OUTS <= 1155; -- vpsllvq_Vdq_Hdq_Wdq SANITY
when 140 => NEXT_OUTS <= 173; -- vmaskmovq_Vdq_Hdq_Mdq SANITY
when 144 => NEXT_OUTS <= 577; -- vgatherdq_Vdq_VSib_Hdq SANITY
when 145 => NEXT_OUTS <= 1158; -- vgatherqq_Vdq_VSib_Hdq SANITY
when 146 => NEXT_OUTS <= 411; -- vgatherdpd_Vpd_VSib_Hpd SANITY
when 147 => NEXT_OUTS <= 1570; -- vgatherqpd_Vpd_VSib_Hpd SANITY
when 150 => NEXT_OUTS <= 343; -- vfmaddsub132pd_Vpd_Hpd_Wpd SANITY
when 151 => NEXT_OUTS <= 1198; -- vfmsubadd132pd_Vpd_Hpd_Wpd SANITY
when 152 => NEXT_OUTS <= 885; -- vfmadd132pd_Vpd_Hpd_Wpd SANITY
when 153 => NEXT_OUTS <= 671; -- vfmadd132sd_Vpd_Hsd_Wsd SANITY
when 154 => NEXT_OUTS <= 476; -- vfmsub132pd_Vpd_Hpd_Wpd SANITY
when 155 => NEXT_OUTS <= 88; -- vfmsub132sd_Vpd_Hsd_Wsd SANITY
when 156 => NEXT_OUTS <= 62; -- vfnmadd132pd_Vpd_Hpd_Wpd SANITY
when 157 => NEXT_OUTS <= 324; -- vfnmadd132sd_Vpd_Hsd_Wsd SANITY
when 158 => NEXT_OUTS <= 244; -- vfnmsub132pd_Vpd_Hpd_Wpd SANITY
when 159 => NEXT_OUTS <= 405; -- vfnmsub132sd_Vpd_Hsd_Wsd SANITY
when 166 => NEXT_OUTS <= 1429; -- vfmaddsub213pd_Vpd_Hpd_Wpd SANITY
when 167 => NEXT_OUTS <= 1154; -- vfmsubadd213pd_Vpd_Hpd_Wpd SANITY
when 168 => NEXT_OUTS <= 1591; -- vfmadd213pd_Vpd_Hpd_Wpd SANITY
when 169 => NEXT_OUTS <= 425; -- vfmadd213sd_Vpd_Hsd_Wsd SANITY
when 170 => NEXT_OUTS <= 1458; -- vfmsub213pd_Vpd_Hpd_Wpd SANITY
when 171 => NEXT_OUTS <= 972; -- vfmsub213sd_Vpd_Hsd_Wsd SANITY
when 172 => NEXT_OUTS <= 1369; -- vfnmadd213pd_Vpd_Hpd_Wpd SANITY
when 173 => NEXT_OUTS <= 601; -- vfnmadd213sd_Vpd_Hsd_Wsd SANITY
when 174 => NEXT_OUTS <= 1596; -- vfnmsub213pd_Vpd_Hpd_Wpd SANITY
when 175 => NEXT_OUTS <= 1197; -- vfnmsub213sd_Vpd_Hsd_Wsd SANITY
when 182 => NEXT_OUTS <= 1041; -- vfmaddsub231pd_Vpd_Hpd_Wpd SANITY
when 183 => NEXT_OUTS <= 660; -- vfmsubadd231pd_Vpd_Hpd_Wpd SANITY
when 184 => NEXT_OUTS <= 495; -- vfmadd231pd_Vpd_Hpd_Wpd SANITY
when 185 => NEXT_OUTS <= 1607; -- vfmadd231sd_Vpd_Hsd_Wsd SANITY
when 186 => NEXT_OUTS <= 111; -- vfmsub231pd_Vpd_Hpd_Wpd SANITY
when 187 => NEXT_OUTS <= 1261; -- vfmsub231sd_Vpd_Hsd_Wsd SANITY
when 188 => NEXT_OUTS <= 1120; -- vfnmadd231pd_Vpd_Hpd_Wpd SANITY
when 189 => NEXT_OUTS <= 1157; -- vfnmadd231sd_Vpd_Hsd_Wsd SANITY
when 190 => NEXT_OUTS <= 1646; -- vfnmsub231pd_Vpd_Hpd_Wpd SANITY
when 191 => NEXT_OUTS <= 1171; -- vfnmsub231sd_Vpd_Hsd_Wsd SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 227 =>
case OP3 is
when 81 =>
case OP4 is
when 2 => NEXT_OUTS <= 1269; -- vpblendd_Vdq_Hdq_Wdq_Ib SANITY
when 6 => NEXT_OUTS <= 158; -- vperm2f128_Vdq_Hdq_Wdq_Ib SANITY
when 10 => NEXT_OUTS <= 773; -- vroundss_Vss_Hps_Wss_Ib SANITY
when 11 => NEXT_OUTS <= 932; -- vroundsd_Vsd_Hpd_Wsd_Ib SANITY
when 12 => NEXT_OUTS <= 953; -- vblendps_Vps_Hps_Wps_Ib SANITY
when 13 => NEXT_OUTS <= 1152; -- vblendpd_Vpd_Hpd_Wpd_Ib SANITY
when 14 => NEXT_OUTS <= 54; -- vpblendw_Vdq_Hdq_Wdq_Ib SANITY
when 15 => NEXT_OUTS <= 33; -- vpalignr_Vdq_Hdq_Wdq_Ib SANITY
when 24 => NEXT_OUTS <= 426; -- vinsertf128_Vdq_Hdq_Wdq_Ib SANITY
when 32 => NEXT_OUTS <= 1419; -- vpinsrb_Vdq_Hdq_Ed_Ib SANITY
when 33 => NEXT_OUTS <= 1332; -- vinsertps_Vps_Hps_Wss_Ib SANITY
when 34 => NEXT_OUTS <= 640; -- vpinsrd_Vdq_Hdq_Ed_Ib SANITY
when 56 => NEXT_OUTS <= 1401; -- vinserti128_Vdq_Hdq_Wdq_Ib SANITY
when 64 => NEXT_OUTS <= 436; -- vdpps_Vps_Hps_Wps_Ib SANITY
when 65 => NEXT_OUTS <= 940; -- vdppd_Vpd_Hpd_Wpd_Ib SANITY
when 66 => NEXT_OUTS <= 1093; -- vmpsadbw_Vdq_Hdq_Wdq_Ib SANITY
when 68 => NEXT_OUTS <= 965; -- vpclmulqdq_Vdq_Hdq_Wdq_Ib SANITY
when 70 => NEXT_OUTS <= 519; -- vperm2i128_Vdq_Hdq_Wdq_Ib SANITY
when 74 => NEXT_OUTS <= 1063; -- vblendvps_Vps_Hps_Wps_Ib SANITY
when 75 => NEXT_OUTS <= 277; -- vblendvpd_Vpd_Hpd_Wpd_Ib SANITY
when 76 => NEXT_OUTS <= 960; -- vpblendvb_Vdq_Hdq_Wdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 120 =>
case OP4 is
when 240 => NEXT_OUTS <= 200; -- rorx_Gy_Ey_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 121 =>
case OP4 is
when 4 => NEXT_OUTS <= 676; -- vpermilps_Vps_Wps_Ib SANITY
when 5 => NEXT_OUTS <= 1449; -- vpermilpd_Vpd_Wpd_Ib SANITY
when 8 => NEXT_OUTS <= 83; -- vroundps_Vps_Wps_Ib SANITY
when 9 => NEXT_OUTS <= 1589; -- vroundpd_Vpd_Wpd_Ib SANITY
when 20 =>
case OP5 is
when 0 => NEXT_OUTS <= 1193; -- vpextrb_Ebd_Vdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 21 =>
case OP5 is
when 0 => NEXT_OUTS <= 529; -- vpextrw_Ewd_Vdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 22 => NEXT_OUTS <= 603; -- vpextrd_Ed_Vdq_Ib SANITY
when 23 => NEXT_OUTS <= 1543; -- vextractps_Ed_Vdq_Ib SANITY
when 25 => NEXT_OUTS <= 887; -- vextractf128_Wdq_Vdq_Ib SANITY
when 29 => NEXT_OUTS <= 410; -- vcvtps2ph_Wq_Vps_Ib SANITY
when 57 => NEXT_OUTS <= 705; -- vextracti128_Wdq_Vdq_Ib SANITY
when 96 => NEXT_OUTS <= 768; -- vpcmpestrm_Vdq_Wdq_Ib SANITY
when 97 => NEXT_OUTS <= 856; -- vpcmpestri_Vdq_Wdq_Ib SANITY
when 98 => NEXT_OUTS <= 1465; -- vpcmpistrm_Vdq_Wdq_Ib SANITY
when 99 => NEXT_OUTS <= 1444; -- vpcmpistri_Vdq_Wdq_Ib SANITY
when 223 => NEXT_OUTS <= 653; -- vaeskeygenassist_Vdq_Wdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 209 =>
case OP4 is
when 34 => NEXT_OUTS <= 326; -- vpinsrq_Vdq_Hdq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 249 =>
case OP4 is
when 0 => NEXT_OUTS <= 959; -- vpermq_Vdq_Wdq_Ib SANITY
when 1 => NEXT_OUTS <= 132; -- vpermpd_Vpd_Wpd_Ib SANITY
when 22 => NEXT_OUTS <= 135; -- vpextrq_Eq_Vdq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 197 =>
case OP2 is
when 0 => NEXT_OUTS <= 52; -- ldsl_Gd_Mp SANITY
when 208 =>
case OP3 is
when 18 =>
case OP4 is
when 0 => NEXT_OUTS <= 1174; -- vmovlps_Vps_Hdq_Mq SANITY
when 192 => NEXT_OUTS <= 57; -- vmovhlps_Vps_Hdq_Udq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 20 => NEXT_OUTS <= 824; -- vunpcklps_Vps_Hps_Wps SANITY
when 21 => NEXT_OUTS <= 1295; -- vunpckhps_Vps_Hps_Wps SANITY
when 22 =>
case OP4 is
when 0 => NEXT_OUTS <= 1130; -- vmovhps_Vps_Hdq_Mq SANITY
when 192 => NEXT_OUTS <= 1627; -- vmovlhps_Vps_Hdq_Udq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 84 => NEXT_OUTS <= 864; -- vandps_Vps_Hps_Wps SANITY
when 85 => NEXT_OUTS <= 661; -- vandnps_Vps_Hps_Wps SANITY
when 86 => NEXT_OUTS <= 926; -- vorps_Vps_Hps_Wps SANITY
when 87 => NEXT_OUTS <= 515; -- vxorps_Vps_Hps_Wps SANITY
when 88 => NEXT_OUTS <= 1064; -- vaddps_Vps_Hps_Wps SANITY
when 89 => NEXT_OUTS <= 829; -- vmulps_Vps_Hps_Wps SANITY
when 92 => NEXT_OUTS <= 772; -- vsubps_Vps_Hps_Wps SANITY
when 93 => NEXT_OUTS <= 1242; -- vminps_Vps_Hps_Wps SANITY
when 94 => NEXT_OUTS <= 618; -- vdivps_Vps_Hps_Wps SANITY
when 95 => NEXT_OUTS <= 934; -- vmaxps_Vps_Hps_Wps SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 1398; -- vcmpps_Vps_Hps_Wps_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 198 => NEXT_OUTS <= 488; -- vshufps_Vps_Hps_Wps_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 209 =>
case OP3 is
when 18 => NEXT_OUTS <= 1129; -- vmovlpd_Vpd_Hdq_Mq SANITY
when 20 => NEXT_OUTS <= 980; -- vunpcklpd_Vpd_Hpd_Wpd SANITY
when 21 => NEXT_OUTS <= 70; -- vunpckhpd_Vpd_Hpd_Wpd SANITY
when 22 => NEXT_OUTS <= 1199; -- vmovhpd_Vpd_Hdq_Mq SANITY
when 84 => NEXT_OUTS <= 185; -- vandpd_Vpd_Hpd_Wpd SANITY
when 85 => NEXT_OUTS <= 265; -- vandnpd_Vpd_Hpd_Wpd SANITY
when 86 => NEXT_OUTS <= 1248; -- vorpd_Vpd_Hpd_Wpd SANITY
when 87 => NEXT_OUTS <= 938; -- vxorpd_Vpd_Hpd_Wpd SANITY
when 88 => NEXT_OUTS <= 37; -- vaddpd_Vpd_Hpd_Wpd SANITY
when 89 => NEXT_OUTS <= 862; -- vmulpd_Vpd_Hpd_Wpd SANITY
when 92 => NEXT_OUTS <= 1426; -- vsubpd_Vpd_Hpd_Wpd SANITY
when 93 => NEXT_OUTS <= 127; -- vminpd_Vpd_Hpd_Wpd SANITY
when 94 => NEXT_OUTS <= 707; -- vdivpd_Vpd_Hpd_Wpd SANITY
when 95 => NEXT_OUTS <= 733; -- vmaxpd_Vpd_Hpd_Wpd SANITY
when 96 => NEXT_OUTS <= 1302; -- vpunpcklbw_Vdq_Hdq_Wdq SANITY
when 97 => NEXT_OUTS <= 583; -- vpunpcklwd_Vdq_Hdq_Wdq SANITY
when 98 => NEXT_OUTS <= 282; -- vpunpckldq_Vdq_Hdq_Wdq SANITY
when 99 => NEXT_OUTS <= 1320; -- vpacksswb_Vdq_Hdq_Wdq SANITY
when 100 => NEXT_OUTS <= 1011; -- vpcmpgtb_Vdq_Hdq_Wdq SANITY
when 101 => NEXT_OUTS <= 1374; -- vpcmpgtw_Vdq_Hdq_Wdq SANITY
when 102 => NEXT_OUTS <= 1536; -- vpcmpgtd_Vdq_Hdq_Wdq SANITY
when 103 => NEXT_OUTS <= 1450; -- vpackuswb_Vdq_Hdq_Wdq SANITY
when 104 => NEXT_OUTS <= 606; -- vpunpckhbw_Vdq_Hdq_Wdq SANITY
when 105 => NEXT_OUTS <= 286; -- vpunpckhwd_Vdq_Hdq_Wdq SANITY
when 106 => NEXT_OUTS <= 137; -- vpunpckhdq_Vdq_Hdq_Wdq SANITY
when 107 => NEXT_OUTS <= 1232; -- vpackssdw_Vdq_Hdq_Wdq SANITY
when 108 => NEXT_OUTS <= 1112; -- vpunpcklqdq_Vdq_Hdq_Wdq SANITY
when 109 => NEXT_OUTS <= 1333; -- vpunpckhqdq_Vdq_Hdq_Wdq SANITY
when 113 =>
case OP4 is
when 16 => NEXT_OUTS <= 1462; -- vpsrlw_Hdq_Udq_Ib SANITY
when 32 => NEXT_OUTS <= 970; -- vpsraw_Hdq_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 480; -- vpsllw_Hdq_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 114 =>
case OP4 is
when 16 => NEXT_OUTS <= 903; -- vpsrld_Hdq_Udq_Ib SANITY
when 32 => NEXT_OUTS <= 1008; -- vpsrad_Hdq_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 1183; -- vpslld_Hdq_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 115 =>
case OP4 is
when 16 => NEXT_OUTS <= 894; -- vpsrlq_Hdq_Udq_Ib SANITY
when 24 => NEXT_OUTS <= 201; -- vpsrldq_Hdq_Udq_Ib SANITY
when 48 => NEXT_OUTS <= 398; -- vpsllq_Hdq_Udq_Ib SANITY
when 56 => NEXT_OUTS <= 599; -- vpslldq_Hdq_Udq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 116 => NEXT_OUTS <= 732; -- vpcmpeqb_Vdq_Hdq_Wdq SANITY
when 117 => NEXT_OUTS <= 1488; -- vpcmpeqw_Vdq_Hdq_Wdq SANITY
when 118 => NEXT_OUTS <= 703; -- vpcmpeqd_Vdq_Hdq_Wdq SANITY
when 124 => NEXT_OUTS <= 1366; -- vhaddpd_Vpd_Hpd_Wpd SANITY
when 125 => NEXT_OUTS <= 966; -- vhsubpd_Vpd_Hpd_Wpd SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 996; -- vcmppd_Vpd_Hpd_Wpd_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 196 =>
case OP4 is
when 0 => NEXT_OUTS <= 212; -- vpinsrw_Vdq_Hdq_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 198 => NEXT_OUTS <= 254; -- vshufpd_Vpd_Hpd_Wpd_Ib SANITY
when 208 => NEXT_OUTS <= 1457; -- vaddsubpd_Vpd_Hpd_Wpd SANITY
when 209 => NEXT_OUTS <= 1131; -- vpsrlw_Vdq_Hdq_Wdq SANITY
when 210 => NEXT_OUTS <= 1287; -- vpsrld_Vdq_Hdq_Wdq SANITY
when 211 => NEXT_OUTS <= 1353; -- vpsrlq_Vdq_Hdq_Wdq SANITY
when 212 => NEXT_OUTS <= 1233; -- vpaddq_Vdq_Hdq_Wdq SANITY
when 213 => NEXT_OUTS <= 1119; -- vpmullw_Vdq_Hdq_Wdq SANITY
when 216 => NEXT_OUTS <= 669; -- vpsubusb_Vdq_Hdq_Wdq SANITY
when 217 => NEXT_OUTS <= 94; -- vpsubusw_Vdq_Hdq_Wdq SANITY
when 218 => NEXT_OUTS <= 64; -- vpminub_Vdq_Hdq_Wdq SANITY
when 219 => NEXT_OUTS <= 1329; -- vpand_Vdq_Hdq_Wdq SANITY
when 220 => NEXT_OUTS <= 1411; -- vpaddusb_Vdq_Hdq_Wdq SANITY
when 221 => NEXT_OUTS <= 469; -- vpaddusw_Vdq_Hdq_Wdq SANITY
when 222 => NEXT_OUTS <= 1476; -- vpmaxub_Vdq_Hdq_Wdq SANITY
when 223 => NEXT_OUTS <= 1180; -- vpandn_Vdq_Hdq_Wdq SANITY
when 224 => NEXT_OUTS <= 1010; -- vpavgb_Vdq_Hdq_Wdq SANITY
when 225 => NEXT_OUTS <= 743; -- vpsraw_Vdq_Hdq_Wdq SANITY
when 226 => NEXT_OUTS <= 210; -- vpsrad_Vdq_Hdq_Wdq SANITY
when 227 => NEXT_OUTS <= 427; -- vpavgw_Vdq_Hdq_Wdq SANITY
when 228 => NEXT_OUTS <= 1134; -- vpmulhuw_Vdq_Hdq_Wdq SANITY
when 229 => NEXT_OUTS <= 1587; -- vpmulhw_Vdq_Hdq_Wdq SANITY
when 232 => NEXT_OUTS <= 194; -- vpsubsb_Vdq_Hdq_Wdq SANITY
when 233 => NEXT_OUTS <= 1410; -- vpsubsw_Vdq_Hdq_Wdq SANITY
when 234 => NEXT_OUTS <= 1339; -- vpminsw_Vdq_Hdq_Wdq SANITY
when 235 => NEXT_OUTS <= 1623; -- vpor_Vdq_Hdq_Wdq SANITY
when 236 => NEXT_OUTS <= 762; -- vpaddsb_Vdq_Hdq_Wdq SANITY
when 237 => NEXT_OUTS <= 417; -- vpaddsw_Vdq_Hdq_Wdq SANITY
when 238 => NEXT_OUTS <= 1003; -- vpmaxsw_Vdq_Hdq_Wdq SANITY
when 239 => NEXT_OUTS <= 1361; -- vpxor_Vdq_Hdq_Wdq SANITY
when 241 => NEXT_OUTS <= 1022; -- vpsllw_Vdq_Hdq_Wdq SANITY
when 242 => NEXT_OUTS <= 163; -- vpslld_Vdq_Hdq_Wdq SANITY
when 243 => NEXT_OUTS <= 916; -- vpsllq_Vdq_Hdq_Wdq SANITY
when 244 => NEXT_OUTS <= 468; -- vpmuludq_Vdq_Hdq_Wdq SANITY
when 245 => NEXT_OUTS <= 866; -- vpmaddwd_Vdq_Hdq_Wdq SANITY
when 246 => NEXT_OUTS <= 1528; -- vpsadbw_Vdq_Hdq_Wdq SANITY
when 248 => NEXT_OUTS <= 891; -- vpsubb_Vdq_Hdq_Wdq SANITY
when 249 => NEXT_OUTS <= 275; -- vpsubw_Vdq_Hdq_Wdq SANITY
when 250 => NEXT_OUTS <= 631; -- vpsubd_Vdq_Hdq_Wdq SANITY
when 251 => NEXT_OUTS <= 152; -- vpsubq_Vdq_Hdq_Wdq SANITY
when 252 => NEXT_OUTS <= 5; -- vpaddb_Vdq_Hdq_Wdq SANITY
when 253 => NEXT_OUTS <= 1109; -- vpaddw_Vdq_Hdq_Wdq SANITY
when 254 => NEXT_OUTS <= 66; -- vpaddd_Vdq_Hdq_Wdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 210 =>
case OP3 is
when 18 => NEXT_OUTS <= 602; -- vmovsldup_Vdq_Wdq SANITY
when 22 => NEXT_OUTS <= 928; -- vmovshdup_Vdq_Wdq SANITY
when 42 => NEXT_OUTS <= 1360; -- vcvtsi2ss_Vss_Hps_Ey SANITY
when 88 => NEXT_OUTS <= 1258; -- vaddss_Vss_Hps_Wss SANITY
when 89 => NEXT_OUTS <= 1072; -- vmulss_Vss_Hps_Wss SANITY
when 92 => NEXT_OUTS <= 1657; -- vsubss_Vss_Hps_Wss SANITY
when 93 => NEXT_OUTS <= 870; -- vminss_Vss_Hps_Wss SANITY
when 94 => NEXT_OUTS <= 1550; -- vdivss_Vss_Hps_Wss SANITY
when 95 => NEXT_OUTS <= 1402; -- vmaxss_Vss_Hps_Wss SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 1412; -- vcmpss_Vss_Hps_Wss_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP3 is
when 18 => NEXT_OUTS <= 908; -- vmovddup_Vdq_Wq SANITY
when 42 => NEXT_OUTS <= 1257; -- vcvtsi2sd_Vsd_Hpd_Ey SANITY
when 88 => NEXT_OUTS <= 1210; -- vaddsd_Vsd_Hpd_Wsd SANITY
when 89 => NEXT_OUTS <= 1355; -- vmulsd_Vsd_Hpd_Wsd SANITY
when 92 => NEXT_OUTS <= 317; -- vsubsd_Vsd_Hpd_Wsd SANITY
when 93 => NEXT_OUTS <= 901; -- vminsd_Vsd_Hpd_Wsd SANITY
when 94 => NEXT_OUTS <= 1597; -- vdivsd_Vsd_Hpd_Wsd SANITY
when 95 => NEXT_OUTS <= 131; -- vmaxsd_Vsd_Hpd_Wsd SANITY
when 124 => NEXT_OUTS <= 442; -- vhaddps_Vps_Hps_Wps SANITY
when 125 => NEXT_OUTS <= 240; -- vhsubps_Vps_Hps_Wps SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 1473; -- vcmpsd_Vsd_Hpd_Wsd_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 208 => NEXT_OUTS <= 1263; -- vaddsubps_Vps_Hps_Wps SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 248 =>
case OP3 is
when 16 => NEXT_OUTS <= 1219; -- vmovups_Vps_Wps SANITY
when 17 => NEXT_OUTS <= 28; -- vmovups_Wps_Vps SANITY
when 19 => NEXT_OUTS <= 757; -- vmovlps_Mq_Vps SANITY
when 23 => NEXT_OUTS <= 1459; -- vmovhps_Mq_Vps SANITY
when 40 => NEXT_OUTS <= 710; -- vmovaps_Vps_Wps SANITY
when 41 => NEXT_OUTS <= 1335; -- vmovaps_Wps_Vps SANITY
when 43 => NEXT_OUTS <= 99; -- vmovntps_Mps_Vps SANITY
when 46 => NEXT_OUTS <= 528; -- vucomiss_Vss_Wss SANITY
when 47 => NEXT_OUTS <= 509; -- vcomiss_Vss_Wss SANITY
when 80 => NEXT_OUTS <= 523; -- vmovmskps_Gd_Vps SANITY
when 81 => NEXT_OUTS <= 1185; -- vsqrtps_Vps_Wps SANITY
when 82 => NEXT_OUTS <= 316; -- vrsqrtps_Vps_Wps SANITY
when 83 => NEXT_OUTS <= 850; -- vrcpps_Vps_Wps SANITY
when 90 => NEXT_OUTS <= 1443; -- vcvtps2pd_Vpd_Wps SANITY
when 91 => NEXT_OUTS <= 1280; -- vcvtdq2ps_Vps_Wdq SANITY
when 119 => NEXT_OUTS <= 1031; -- vzeroupper SANITY
when 174 =>
case OP4 is
when 16 => NEXT_OUTS <= 38; -- vldmxcsr SANITY
when 24 => NEXT_OUTS <= 818; -- vstmxcsr SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 249 =>
case OP3 is
when 16 => NEXT_OUTS <= 1408; -- vmovupd_Vpd_Wpd SANITY
when 17 => NEXT_OUTS <= 1432; -- vmovupd_Wpd_Vpd SANITY
when 19 => NEXT_OUTS <= 217; -- vmovlpd_Mq_Vpd SANITY
when 23 => NEXT_OUTS <= 1309; -- vmovhpd_Mq_Vpd SANITY
when 40 => NEXT_OUTS <= 598; -- vmovapd_Vpd_Wpd SANITY
when 41 => NEXT_OUTS <= 393; -- vmovapd_Wpd_Vpd SANITY
when 43 => NEXT_OUTS <= 97; -- vmovntpd_Mpd_Vpd SANITY
when 46 => NEXT_OUTS <= 1272; -- vucomisd_Vsd_Wsd SANITY
when 47 => NEXT_OUTS <= 1290; -- vcomisd_Vsd_Wsd SANITY
when 80 => NEXT_OUTS <= 580; -- vmovmskpd_Gd_Vpd SANITY
when 81 => NEXT_OUTS <= 404; -- vsqrtpd_Vpd_Wpd SANITY
when 90 => NEXT_OUTS <= 955; -- vcvtpd2ps_Vps_Wpd SANITY
when 91 => NEXT_OUTS <= 29; -- vcvtps2dq_Vdq_Wps SANITY
when 110 => NEXT_OUTS <= 391; -- vmovd_Vdq_Ed SANITY
when 111 => NEXT_OUTS <= 1521; -- vmovdqa_Vdq_Wdq SANITY
when 112 => NEXT_OUTS <= 283; -- vpshufd_Vdq_Hdq_Wdq_Ib SANITY
when 126 =>
case OP4 is
when 0 => NEXT_OUTS <= 827; -- vmovd_Ed_Vd SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 127 => NEXT_OUTS <= 478; -- vmovdqa_Wdq_Vdq SANITY
when 197 => NEXT_OUTS <= 962; -- vpextrw_Gd_Udq_Ib SANITY
when 214 =>
case OP4 is
when 0 => NEXT_OUTS <= 1549; -- vmovq_Wq_Vq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 215 => NEXT_OUTS <= 30; -- vpmovmskb_Gd_Udq SANITY
when 230 => NEXT_OUTS <= 754; -- vcvttpd2dq_Vq_Wpd SANITY
when 231 => NEXT_OUTS <= 1592; -- vmovntdq_Mdq_Vdq SANITY
when 247 => NEXT_OUTS <= 180; -- vmaskmovdqu_Vdq_Udq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 250 =>
case OP3 is
when 16 => NEXT_OUTS <= 594; -- vmovss_Vss_Wss SANITY
when 17 => NEXT_OUTS <= 331; -- vmovss_Wss_Vss SANITY
when 44 => NEXT_OUTS <= 1382; -- vcvttss2si_Gy_Wss SANITY
when 45 => NEXT_OUTS <= 612; -- vcvtss2si_Gy_Wss SANITY
when 81 => NEXT_OUTS <= 683; -- vsqrtss_Vss_Hps_Wss SANITY
when 82 => NEXT_OUTS <= 641; -- vrsqrtss_Vss_Hps_Wss SANITY
when 83 => NEXT_OUTS <= 681; -- vrcpss_Vss_Hps_Wss SANITY
when 90 => NEXT_OUTS <= 162; -- vcvtss2sd_Vsd_Hpd_Wss SANITY
when 91 => NEXT_OUTS <= 1541; -- vcvttps2dq_Vdq_Wps SANITY
when 111 => NEXT_OUTS <= 1108; -- vmovdqu_Vdq_Wdq SANITY
when 112 => NEXT_OUTS <= 251; -- vpshufhw_Vdq_Hdq_Wdq_Ib SANITY
when 126 =>
case OP4 is
when 0 => NEXT_OUTS <= 572; -- vmovq_Vq_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 127 => NEXT_OUTS <= 202; -- vmovdqu_Wdq_Vdq SANITY
when 230 => NEXT_OUTS <= 1162; -- vcvtdq2pd_Vpd_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 251 =>
case OP3 is
when 16 => NEXT_OUTS <= 1567; -- vmovsd_Vsd_Wsd SANITY
when 17 => NEXT_OUTS <= 390; -- vmovsd_Wsd_Vsd SANITY
when 44 => NEXT_OUTS <= 1275; -- vcvttsd2si_Gy_Wsd SANITY
when 45 => NEXT_OUTS <= 570; -- vcvtsd2si_Gy_Wsd SANITY
when 81 => NEXT_OUTS <= 1337; -- vsqrtsd_Vsd_Hpd_Wsd SANITY
when 90 => NEXT_OUTS <= 863; -- vcvtsd2ss_Vss_Hps_Wsd SANITY
when 112 => NEXT_OUTS <= 207; -- vpshuflw_Vdq_Hdq_Wdq_Ib SANITY
when 230 => NEXT_OUTS <= 1127; -- vcvtpd2dq_Vq_Wpd SANITY
when 240 => NEXT_OUTS <= 1262; -- vlddqu_Vdq_Mdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 198 =>
case OP2 is
when 0 => NEXT_OUTS <= 1392; -- movb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 199 =>
case OP2 is
when 0 => NEXT_OUTS <= 1599; -- movl_Ed_Id SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 200 => NEXT_OUTS <= 555; -- enter SANITY
when 201 => NEXT_OUTS <= 517; -- leave SANITY
when 202 => NEXT_OUTS <= 35; -- lret_Iw SANITY
when 203 => NEXT_OUTS <= 1460; -- lret SANITY
when 204 => NEXT_OUTS <= 1086; -- int3 SANITY
when 205 => NEXT_OUTS <= 72; -- int_Ib SANITY
when 206 => NEXT_OUTS <= 287; -- into SANITY
when 207 => NEXT_OUTS <= 498; -- iretl SANITY
when 208 =>
case OP2 is
when 0 => NEXT_OUTS <= 1452; -- rolb_Eb_I1 SANITY
when 8 => NEXT_OUTS <= 106; -- rorb_Eb_I1 SANITY
when 16 => NEXT_OUTS <= 1520; -- rclb_Eb_I1 SANITY
when 24 => NEXT_OUTS <= 626; -- rcrb_Eb_I1 SANITY
when 32 => NEXT_OUTS <= 1362; -- shlb_Eb_I1 SANITY
when 40 => NEXT_OUTS <= 1523; -- shrb_Eb_I1 SANITY
when 56 => NEXT_OUTS <= 873; -- sarb_Eb_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 209 =>
case OP2 is
when 0 => NEXT_OUTS <= 1213; -- roll_Ed_I1 SANITY
when 8 => NEXT_OUTS <= 1251; -- rorl_Ed_I1 SANITY
when 16 => NEXT_OUTS <= 1648; -- rcll_Ed_I1 SANITY
when 24 => NEXT_OUTS <= 1387; -- rcrl_Ed_I1 SANITY
when 32 => NEXT_OUTS <= 1089; -- shll_Ed_I1 SANITY
when 40 => NEXT_OUTS <= 685; -- shrl_Ed_I1 SANITY
when 56 => NEXT_OUTS <= 1165; -- sarl_Ed_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 210 =>
case OP2 is
when 0 => NEXT_OUTS <= 1298; -- rolb_Eb_CL SANITY
when 8 => NEXT_OUTS <= 206; -- rorb_Eb_CL SANITY
when 16 => NEXT_OUTS <= 1088; -- rclb_Eb_CL SANITY
when 24 => NEXT_OUTS <= 750; -- rcrb_Eb_CL SANITY
when 32 => NEXT_OUTS <= 820; -- shlb_Eb_CL SANITY
when 40 => NEXT_OUTS <= 675; -- shrb_Eb_CL SANITY
when 56 => NEXT_OUTS <= 800; -- sarb_Eb_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP2 is
when 0 => NEXT_OUTS <= 859; -- roll_Ed_CL SANITY
when 8 => NEXT_OUTS <= 734; -- rorl_Ed_CL SANITY
when 16 => NEXT_OUTS <= 1604; -- rcll_Ed_CL SANITY
when 24 => NEXT_OUTS <= 321; -- rcrl_Ed_CL SANITY
when 32 => NEXT_OUTS <= 1628; -- shll_Ed_CL SANITY
when 40 => NEXT_OUTS <= 560; -- shrl_Ed_CL SANITY
when 56 => NEXT_OUTS <= 161; -- sarl_Ed_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 212 => NEXT_OUTS <= 1603; -- aam SANITY
when 213 => NEXT_OUTS <= 1407; -- aad SANITY
when 214 => NEXT_OUTS <= 156; -- salc SANITY
when 215 => NEXT_OUTS <= 719; -- xlat SANITY
when 216 =>
case OP2 is
when 0 => NEXT_OUTS <= 51; -- fadds_Md SANITY
when 8 => NEXT_OUTS <= 785; -- fmuls_Md SANITY
when 16 => NEXT_OUTS <= 604; -- fcoms_Md SANITY
when 24 => NEXT_OUTS <= 690; -- fcomps_Md SANITY
when 32 => NEXT_OUTS <= 1525; -- fsubs_Md SANITY
when 40 => NEXT_OUTS <= 778; -- fsubrs_Md SANITY
when 48 => NEXT_OUTS <= 843; -- fdivs_Md SANITY
when 56 => NEXT_OUTS <= 431; -- fdivrs_Md SANITY
when 192 => NEXT_OUTS <= 584; -- fadd_ST0_STi SANITY
when 200 => NEXT_OUTS <= 143; -- fmul_ST0_STi SANITY
when 208 => NEXT_OUTS <= 1338; -- fcom_STi SANITY
when 216 => NEXT_OUTS <= 299; -- fcomp_STi SANITY
when 224 => NEXT_OUTS <= 869; -- fsub_ST0_STi SANITY
when 232 => NEXT_OUTS <= 840; -- fsubr_ST0_STi SANITY
when 240 => NEXT_OUTS <= 69; -- fdiv_ST0_STi SANITY
when 248 => NEXT_OUTS <= 78; -- fdivr_ST0_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 217 =>
case OP2 is
when 0 => NEXT_OUTS <= 73; -- flds_Md SANITY
when 16 => NEXT_OUTS <= 804; -- fsts_Md SANITY
when 24 => NEXT_OUTS <= 1436; -- fstps_Md SANITY
when 32 => NEXT_OUTS <= 1621; -- fldenv SANITY
when 40 => NEXT_OUTS <= 1036; -- fldcw SANITY
when 48 => NEXT_OUTS <= 913; -- fnstenv SANITY
when 56 => NEXT_OUTS <= 1614; -- fnstcw SANITY
when 192 => NEXT_OUTS <= 252; -- fld_STi SANITY
when 200 => NEXT_OUTS <= 949; -- fxch SANITY
when 208 => NEXT_OUTS <= 667; -- fnop SANITY
when 224 => NEXT_OUTS <= 1259; -- fchs SANITY
when 225 => NEXT_OUTS <= 233; -- fabs SANITY
when 228 => NEXT_OUTS <= 1616; -- ftst SANITY
when 229 => NEXT_OUTS <= 182; -- fxam SANITY
when 232 => NEXT_OUTS <= 1502; -- fld1 SANITY
when 233 => NEXT_OUTS <= 289; -- fldl2t SANITY
when 234 => NEXT_OUTS <= 39; -- fldl2e SANITY
when 235 => NEXT_OUTS <= 1400; -- fldpi SANITY
when 236 => NEXT_OUTS <= 979; -- fldlg2 SANITY
when 237 => NEXT_OUTS <= 218; -- fldln2 SANITY
when 238 => NEXT_OUTS <= 839; -- fldz SANITY
when 240 => NEXT_OUTS <= 1602; -- f2xm1 SANITY
when 241 => NEXT_OUTS <= 1161; -- fyl2x SANITY
when 242 => NEXT_OUTS <= 415; -- fptan SANITY
when 243 => NEXT_OUTS <= 520; -- fpatan SANITY
when 244 => NEXT_OUTS <= 925; -- fxtract SANITY
when 245 => NEXT_OUTS <= 75; -- fprem1 SANITY
when 246 => NEXT_OUTS <= 1128; -- fdecstp SANITY
when 247 => NEXT_OUTS <= 279; -- fincstp SANITY
when 248 => NEXT_OUTS <= 1245; -- fprem SANITY
when 249 => NEXT_OUTS <= 178; -- fyl2xp1 SANITY
when 250 => NEXT_OUTS <= 815; -- fsqrt SANITY
when 251 => NEXT_OUTS <= 234; -- fsincos SANITY
when 252 => NEXT_OUTS <= 253; -- frndint SANITY
when 253 => NEXT_OUTS <= 1026; -- fscale SANITY
when 254 => NEXT_OUTS <= 255; -- fsin SANITY
when 255 => NEXT_OUTS <= 775; -- fcos SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 218 =>
case OP2 is
when 0 => NEXT_OUTS <= 84; -- fiaddl_Md SANITY
when 8 => NEXT_OUTS <= 188; -- fimull_Md SANITY
when 16 => NEXT_OUTS <= 756; -- ficoml_Md SANITY
when 24 => NEXT_OUTS <= 464; -- ficompl_Md SANITY
when 32 => NEXT_OUTS <= 290; -- fisubl_Md SANITY
when 40 => NEXT_OUTS <= 1079; -- fisubrl_Md SANITY
when 48 => NEXT_OUTS <= 423; -- fidivl_Md SANITY
when 56 => NEXT_OUTS <= 357; -- fidivrl_Md SANITY
when 192 => NEXT_OUTS <= 318; -- fcmovb_ST0_STi SANITY
when 200 => NEXT_OUTS <= 1170; -- fcmove_ST0_STi SANITY
when 208 => NEXT_OUTS <= 297; -- fcmovbe_ST0_STi SANITY
when 216 => NEXT_OUTS <= 1576; -- fcmovu_ST0_STi SANITY
when 233 => NEXT_OUTS <= 24; -- fucompp SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 219 =>
case OP2 is
when 0 => NEXT_OUTS <= 968; -- fildl_Md SANITY
when 8 => NEXT_OUTS <= 372; -- fisttpl_Md SANITY
when 16 => NEXT_OUTS <= 1425; -- fistl_Md SANITY
when 24 => NEXT_OUTS <= 1509; -- fistpl_Md SANITY
when 40 => NEXT_OUTS <= 592; -- fldt_Mt SANITY
when 56 => NEXT_OUTS <= 219; -- fstpt_Mt SANITY
when 192 => NEXT_OUTS <= 1448; -- fcmovnb_ST0_STi SANITY
when 200 => NEXT_OUTS <= 543; -- fcmovne_ST0_STi SANITY
when 208 => NEXT_OUTS <= 1122; -- fcmovnbe_ST0_STi SANITY
when 216 => NEXT_OUTS <= 89; -- fcmovnu_ST0_STi SANITY
when 226 => NEXT_OUTS <= 1334; -- fnclex SANITY
when 227 => NEXT_OUTS <= 304; -- fninit SANITY
when 232 => NEXT_OUTS <= 998; -- fucomi_ST0_STi SANITY
when 240 => NEXT_OUTS <= 793; -- fcomi_ST0_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 220 =>
case OP2 is
when 0 => NEXT_OUTS <= 701; -- faddl_Mq SANITY
when 8 => NEXT_OUTS <= 1253; -- fmull_Mq SANITY
when 16 => NEXT_OUTS <= 1610; -- fcoml_Mq SANITY
when 24 => NEXT_OUTS <= 871; -- fcompl_Mq SANITY
when 32 => NEXT_OUTS <= 1492; -- fsubl_Mq SANITY
when 40 => NEXT_OUTS <= 812; -- fsubrl_Mq SANITY
when 48 => NEXT_OUTS <= 1220; -- fdivl_Mq SANITY
when 56 => NEXT_OUTS <= 1052; -- fdivrl_Mq SANITY
when 192 => NEXT_OUTS <= 852; -- fadd_STi_ST0 SANITY
when 200 => NEXT_OUTS <= 320; -- fmul_STi_ST0 SANITY
when 224 => NEXT_OUTS <= 1037; -- fsubr_STi_ST0 SANITY
when 232 => NEXT_OUTS <= 227; -- fsub_STi_ST0 SANITY
when 240 => NEXT_OUTS <= 368; -- fdivr_STi_ST0 SANITY
when 248 => NEXT_OUTS <= 328; -- fdiv_STi_ST0 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 221 =>
case OP2 is
when 0 => NEXT_OUTS <= 651; -- fldl_Mq SANITY
when 8 => NEXT_OUTS <= 296; -- fisttpq_Mq SANITY
when 16 => NEXT_OUTS <= 230; -- fstl_Mq SANITY
when 24 => NEXT_OUTS <= 1583; -- fstpl_Mq SANITY
when 32 => NEXT_OUTS <= 272; -- frstor SANITY
when 48 => NEXT_OUTS <= 1636; -- fnsave SANITY
when 56 => NEXT_OUTS <= 858; -- fnstsw SANITY
when 192 => NEXT_OUTS <= 912; -- ffree_STi SANITY
when 208 => NEXT_OUTS <= 1405; -- fst_STi SANITY
when 216 => NEXT_OUTS <= 860; -- fstp_STi SANITY
when 224 => NEXT_OUTS <= 833; -- fucom_STi SANITY
when 232 => NEXT_OUTS <= 566; -- fucomp_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 222 =>
case OP2 is
when 0 => NEXT_OUTS <= 1288; -- fiadds_Mw SANITY
when 8 => NEXT_OUTS <= 1662; -- fimuls_Mw SANITY
when 16 => NEXT_OUTS <= 310; -- ficoms_Mw SANITY
when 24 => NEXT_OUTS <= 363; -- ficomps_Mw SANITY
when 32 => NEXT_OUTS <= 1229; -- fisubs_Mw SANITY
when 40 => NEXT_OUTS <= 1645; -- fisubrs_Mw SANITY
when 48 => NEXT_OUTS <= 487; -- fidivs_Mw SANITY
when 56 => NEXT_OUTS <= 1357; -- fidivrs_Mw SANITY
when 192 => NEXT_OUTS <= 569; -- faddp_STi_ST0 SANITY
when 200 => NEXT_OUTS <= 725; -- fmulp_STi_ST0 SANITY
when 217 => NEXT_OUTS <= 441; -- fcompp SANITY
when 224 => NEXT_OUTS <= 14; -- fsubrp_STi_ST0 SANITY
when 232 => NEXT_OUTS <= 549; -- fsubp_STi_ST0 SANITY
when 240 => NEXT_OUTS <= 905; -- fdivrp_STi_ST0 SANITY
when 248 => NEXT_OUTS <= 563; -- fdivp_STi_ST0 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 223 =>
case OP2 is
when 0 => NEXT_OUTS <= 506; -- filds_Mw SANITY
when 8 => NEXT_OUTS <= 259; -- fisttps_Mw SANITY
when 16 => NEXT_OUTS <= 893; -- fists_Mw SANITY
when 24 => NEXT_OUTS <= 936; -- fistps_Mw SANITY
when 32 => NEXT_OUTS <= 1527; -- fbldt_Mt SANITY
when 40 => NEXT_OUTS <= 293; -- fildq_Mq SANITY
when 48 => NEXT_OUTS <= 986; -- fbstpt_Mt SANITY
when 56 => NEXT_OUTS <= 1558; -- fistpq_Mq SANITY
when 224 => NEXT_OUTS <= 1553; -- fnstsw_AX SANITY
when 232 => NEXT_OUTS <= 1456; -- fucomip_ST0_STi SANITY
when 240 => NEXT_OUTS <= 325; -- fcomip_ST0_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 224 => NEXT_OUTS <= 177; -- loopne_Jb SANITY
when 225 => NEXT_OUTS <= 209; -- loope_Jb SANITY
when 226 => NEXT_OUTS <= 616; -- loop_Jb SANITY
when 227 =>
case OP2 is
when 0 => NEXT_OUTS <= 1077; -- jecxz_Jb SANITY
when 1 => NEXT_OUTS <= 803; -- jrcxz_Jb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 228 => NEXT_OUTS <= 347; -- inb_AL_Ib SANITY
when 229 => NEXT_OUTS <= 1510; -- inl_EAX_Ib SANITY
when 230 => NEXT_OUTS <= 571; -- outb_Ib_AL SANITY
when 231 => NEXT_OUTS <= 1611; -- outl_Ib_EAX SANITY
when 232 => NEXT_OUTS <= 1542; -- call_Jd SANITY
when 233 => NEXT_OUTS <= 1424; -- jmp_Jd SANITY
when 234 => NEXT_OUTS <= 1631; -- ljmp_Apd SANITY
when 235 => NEXT_OUTS <= 605; -- jmp_Jb SANITY
when 236 => NEXT_OUTS <= 365; -- inb_AL_DX SANITY
when 237 => NEXT_OUTS <= 184; -- inl_EAX_DX SANITY
when 238 => NEXT_OUTS <= 718; -- outb_DX_AL SANITY
when 239 => NEXT_OUTS <= 1547; -- outl_DX_EAX SANITY
when 241 => NEXT_OUTS <= 1595; -- int1 SANITY
when 242 =>
case OP2 is
when 15 =>
case OP3 is
when 16 => NEXT_OUTS <= 18; -- movsd_Vsd_Wsd SANITY
when 17 => NEXT_OUTS <= 437; -- movsd_Wsd_Vsd SANITY
when 18 => NEXT_OUTS <= 1034; -- movddup_Vdq_Wq SANITY
when 42 => NEXT_OUTS <= 1325; -- cvtsi2sd_Vsd_Ey SANITY
when 44 => NEXT_OUTS <= 892; -- cvttsd2si_Gy_Wsd SANITY
when 45 => NEXT_OUTS <= 590; -- cvtsd2si_Gy_Wsd SANITY
when 56 =>
case OP4 is
when 240 => NEXT_OUTS <= 1006; -- crc32_Gd_Eb SANITY
when 241 =>
case OP5 is
when 195 => NEXT_OUTS <= 1653; -- crc32_Gd_Ed SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 81 => NEXT_OUTS <= 1058; -- sqrtsd_Vsd_Wsd SANITY
when 88 => NEXT_OUTS <= 1087; -- addsd_Vsd_Wsd SANITY
when 89 => NEXT_OUTS <= 792; -- mulsd_Vsd_Wsd SANITY
when 90 => NEXT_OUTS <= 1303; -- cvtsd2ss_Vss_Wsd SANITY
when 92 => NEXT_OUTS <= 329; -- subsd_Vsd_Wsd SANITY
when 93 => NEXT_OUTS <= 533; -- minsd_Vsd_Wsd SANITY
when 94 => NEXT_OUTS <= 1054; -- divsd_Vsd_Wsd SANITY
when 95 => NEXT_OUTS <= 214; -- maxsd_Vsd_Wsd SANITY
when 112 => NEXT_OUTS <= 396; -- pshuflw_Vdq_Wdq_Ib SANITY
when 124 => NEXT_OUTS <= 271; -- haddps_Vps_Wps SANITY
when 125 => NEXT_OUTS <= 969; -- hsubps_Vps_Wps SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 165; -- cmpsd_Vsd_Wsd_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 208 => NEXT_OUTS <= 1319; -- addsubps_Vps_Wps SANITY
when 214 => NEXT_OUTS <= 501; -- movdq2q_Pq_Udq SANITY
when 230 => NEXT_OUTS <= 1145; -- cvtpd2dq_Vq_Wpd SANITY
when 240 => NEXT_OUTS <= 46; -- lddqu_Vdq_Mdq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 72 =>
case OP3 is
when 15 =>
case OP4 is
when 56 =>
case OP5 is
when 241 =>
case OP6 is
when 195 => NEXT_OUTS <= 904; -- crc32_Gd_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 243 =>
case OP2 is
when 15 =>
case OP3 is
when 16 => NEXT_OUTS <= 837; -- movss_Vss_Wss SANITY
when 17 => NEXT_OUTS <= 726; -- movss_Wss_Vss SANITY
when 18 => NEXT_OUTS <= 999; -- movsldup_Vdq_Wdq SANITY
when 22 => NEXT_OUTS <= 1478; -- movshdup_Vdq_Wdq SANITY
when 42 => NEXT_OUTS <= 620; -- cvtsi2ss_Vss_Ey SANITY
when 44 => NEXT_OUTS <= 1276; -- cvttss2si_Gy_Wss SANITY
when 45 => NEXT_OUTS <= 614; -- cvtss2si_Gy_Wss SANITY
when 81 => NEXT_OUTS <= 1216; -- sqrtss_Vss_Wss SANITY
when 82 => NEXT_OUTS <= 1153; -- rsqrtss_Vss_Wss SANITY
when 83 => NEXT_OUTS <= 1559; -- rcpss_Vss_Wss SANITY
when 88 => NEXT_OUTS <= 1208; -- addss_Vss_Wss SANITY
when 89 => NEXT_OUTS <= 808; -- mulss_Vss_Wss SANITY
when 90 => NEXT_OUTS <= 1009; -- cvtss2sd_Vsd_Wss SANITY
when 91 => NEXT_OUTS <= 1321; -- cvttps2dq_Vdq_Wps SANITY
when 92 => NEXT_OUTS <= 466; -- subss_Vss_Wss SANITY
when 93 => NEXT_OUTS <= 494; -- minss_Vss_Wss SANITY
when 94 => NEXT_OUTS <= 1383; -- divss_Vss_Wss SANITY
when 95 => NEXT_OUTS <= 736; -- maxss_Vss_Wss SANITY
when 111 => NEXT_OUTS <= 429; -- movdqu_Vdq_Wdq SANITY
when 112 => NEXT_OUTS <= 1373; -- pshufhw_Vdq_Wdq_Ib SANITY
when 126 =>
case OP4 is
when 0 => NEXT_OUTS <= 449; -- movq_Vq_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 127 => NEXT_OUTS <= 1013; -- movdqu_Wdq_Vdq SANITY
when 174 =>
case OP4 is
when 192 => NEXT_OUTS <= 1111; -- rdfsbase_Ry SANITY
when 200 => NEXT_OUTS <= 1159; -- rdgsbase_Ry SANITY
when 208 => NEXT_OUTS <= 126; -- wrfsbase_Ry SANITY
when 216 => NEXT_OUTS <= 525; -- wrgsbase_Ry SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 184 => NEXT_OUTS <= 911; -- popcnt_Gd_Ed SANITY
when 188 => NEXT_OUTS <= 747; -- tzcntl_Gd_Ed SANITY
when 189 => NEXT_OUTS <= 1078; -- lzcntl_Gd_Ed SANITY
when 194 =>
case OP4 is
when 0 =>
case OP5 is
when 0 => NEXT_OUTS <= 1508; -- cmpss_Vss_Wss_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 199 =>
case OP4 is
when 48 => NEXT_OUTS <= 1101; -- vmxon_Mq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 214 => NEXT_OUTS <= 1294; -- movq2dq_Vdq_Qq SANITY
when 230 => NEXT_OUTS <= 767; -- cvtdq2pd_Vpd_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 72 =>
case OP3 is
when 15 =>
case OP4 is
when 184 => NEXT_OUTS <= 1017; -- popcnt_Gq_Eq SANITY
when 188 => NEXT_OUTS <= 1192; -- tzcntq_Gq_Eq SANITY
when 189 => NEXT_OUTS <= 708; -- lzcntq_Gq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 144 => NEXT_OUTS <= 933; -- pause SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 244 => NEXT_OUTS <= 1286; -- hlt SANITY
when 245 => NEXT_OUTS <= 25; -- cmc SANITY
when 246 =>
case OP2 is
when 0 => NEXT_OUTS <= 378; -- testb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 1505; -- notb_Eb SANITY
when 24 => NEXT_OUTS <= 664; -- negb_Eb SANITY
when 32 => NEXT_OUTS <= 993; -- mulb_AL_Eb SANITY
when 40 => NEXT_OUTS <= 1001; -- imulb_AL_Eb SANITY
when 48 => NEXT_OUTS <= 629; -- divb_AL_Eb SANITY
when 56 => NEXT_OUTS <= 267; -- idivb_AL_Eb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 247 =>
case OP2 is
when 0 => NEXT_OUTS <= 530; -- testl_Ed_Id SANITY
when 16 => NEXT_OUTS <= 978; -- notl_Ed SANITY
when 24 => NEXT_OUTS <= 1617; -- negl_Ed SANITY
when 32 => NEXT_OUTS <= 250; -- mull_EAX_Ed SANITY
when 40 => NEXT_OUTS <= 1381; -- imull_EAX_Ed SANITY
when 48 => NEXT_OUTS <= 1051; -- divl_EAX_Ed SANITY
when 56 => NEXT_OUTS <= 1056; -- idivl_EAX_Ed SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 248 => NEXT_OUTS <= 1094; -- clc SANITY
when 249 => NEXT_OUTS <= 1203; -- stc SANITY
when 250 => NEXT_OUTS <= 1466; -- cli SANITY
when 251 => NEXT_OUTS <= 1057; -- sti SANITY
when 252 => NEXT_OUTS <= 883; -- cld SANITY
when 253 => NEXT_OUTS <= 947; -- std SANITY
when 254 =>
case OP2 is
when 0 => NEXT_OUTS <= 958; -- incb_Eb SANITY
when 8 => NEXT_OUTS <= 930; -- decb_Eb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP2 is
when 0 => NEXT_OUTS <= 1240; -- incl_Ed SANITY
when 8 => NEXT_OUTS <= 985; -- decl_Ed SANITY
when 16 =>
case OP3 is
when 0 => NEXT_OUTS <= 1099; -- call_Ed SANITY
when 1 => NEXT_OUTS <= 746; -- call_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 24 => NEXT_OUTS <= 1533; -- lcall_Mp SANITY
when 32 =>
case OP3 is
when 0 => NEXT_OUTS <= 748; -- jmp_Ed SANITY
when 1 => NEXT_OUTS <= 1434; -- jmp_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 40 => NEXT_OUTS <= 362; -- ljmp_Mp SANITY
when 48 =>
case OP3 is
when 0 => NEXT_OUTS <= 922; -- pushl_Ed SANITY
when 1 => NEXT_OUTS <= 313; -- pushq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
end process;
end behv;
| mit | 725a6928cc41277aca1c51ece5939609 | 0.47828 | 3.363086 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2cmst_gen.vhd | 1 | 3,384 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst_gen
-- File: i2cmst_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Generic I2CMST, see i2cmst.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
entity i2cmst_gen is
generic (
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2cmst_gen;
architecture rtl of i2cmst_gen is
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
apbi.psel(0) <= psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= penable;
apbi.paddr <= paddr;
apbi.pwrite <= pwrite;
apbi.pwdata <= pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
prdata <= apbo.prdata;
irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2cmst
generic map (pindex => 0, paddr => 0, pmask => 0, pirq => 0,
oepol => oepol, filter => filter, dynfilt => dynfilt)
port map (rstn, clk, apbi, apbo, i2ci, i2co);
end architecture rtl;
| gpl-2.0 | 57608f22980e288813c7e9fed119ee79 | 0.594563 | 3.291829 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de0-nano/config.vhd | 1 | 6,251 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 0f27c7f410ac75f9d6b12f8e5e6c7114 | 0.649656 | 3.692262 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/841f5df448bf42bc/zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl | 1 | 533,334 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | c486881244b1c47a7c7cfe14faaf7992 | 0.532044 | 2.542907 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-de2-ep2c35/config.vhd | 1 | 5,550 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 615bfec37940e2a80dcc015533d880ee | 0.644865 | 3.656126 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/hdl/ip_design_wrapper.vhd | 1 | 6,744 | --Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
--Date : Wed Oct 18 15:14:15 2017
--Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
--Command : generate_target ip_design_wrapper.bd
--Design : ip_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_wrapper is
port (
BCLK : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 );
IIC_0_scl_io : inout STD_LOGIC;
IIC_0_sda_io : inout STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ip_design_wrapper;
architecture STRUCTURE of ip_design_wrapper is
component ip_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
SDATA_I : in STD_LOGIC;
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC
);
end component ip_design;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal GPIO_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal GPIO_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal GPIO_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal IIC_0_scl_i : STD_LOGIC;
signal IIC_0_scl_o : STD_LOGIC;
signal IIC_0_scl_t : STD_LOGIC;
signal IIC_0_sda_i : STD_LOGIC;
signal IIC_0_sda_o : STD_LOGIC;
signal IIC_0_sda_t : STD_LOGIC;
begin
GPIO_tri_iobuf_0: component IOBUF
port map (
I => GPIO_tri_o_0(0),
IO => GPIO_tri_io(0),
O => GPIO_tri_i_0(0),
T => GPIO_tri_t_0(0)
);
GPIO_tri_iobuf_1: component IOBUF
port map (
I => GPIO_tri_o_1(1),
IO => GPIO_tri_io(1),
O => GPIO_tri_i_1(1),
T => GPIO_tri_t_1(1)
);
IIC_0_scl_iobuf: component IOBUF
port map (
I => IIC_0_scl_o,
IO => IIC_0_scl_io,
O => IIC_0_scl_i,
T => IIC_0_scl_t
);
IIC_0_sda_iobuf: component IOBUF
port map (
I => IIC_0_sda_o,
IO => IIC_0_sda_io,
O => IIC_0_sda_i,
T => IIC_0_sda_t
);
ip_design_i: component ip_design
port map (
BCLK => BCLK,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FCLK_CLK1 => FCLK_CLK1,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
GPIO_tri_i(1) => GPIO_tri_i_1(1),
GPIO_tri_i(0) => GPIO_tri_i_0(0),
GPIO_tri_o(1) => GPIO_tri_o_1(1),
GPIO_tri_o(0) => GPIO_tri_o_0(0),
GPIO_tri_t(1) => GPIO_tri_t_1(1),
GPIO_tri_t(0) => GPIO_tri_t_0(0),
IIC_0_scl_i => IIC_0_scl_i,
IIC_0_scl_o => IIC_0_scl_o,
IIC_0_scl_t => IIC_0_scl_t,
IIC_0_sda_i => IIC_0_sda_i,
IIC_0_sda_o => IIC_0_sda_o,
IIC_0_sda_t => IIC_0_sda_t,
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
LRCLK => LRCLK,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
btns_5bits_tri_i(4 downto 0) => btns_5bits_tri_i(4 downto 0),
sws_8bits_tri_i(7 downto 0) => sws_8bits_tri_i(7 downto 0)
);
end STRUCTURE;
| mit | bd07f443e9523635e6d79525e10b5aef | 0.573992 | 2.806492 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/ea58857b9a21c64b/zqynq_lab_1_design_xbar_1_sim_netlist.vhdl | 1 | 210,508 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:25 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd is
port (
aa_grant_any : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
f_hot2enc_return0 : out STD_LOGIC;
\m_atarget_hot_reg[4]\ : out STD_LOGIC;
\m_atarget_hot_reg[3]\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_axi.s_axi_wready_i_reg_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
s_axi_rid_i : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rlast_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_hot_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
write_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\gen_axi.s_axi_awready_i_reg_0\ : in STD_LOGIC;
mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d0_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_rready : in STD_LOGIC;
\gen_axi.read_cs_reg[0]\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aa_grant_any\ : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \^f_hot2enc_return0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[1]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_4_n_0\ : STD_LOGIC;
signal \^m_atarget_hot_reg[3]\ : STD_LOGIC;
signal \^m_atarget_hot_reg[4]\ : STD_LOGIC;
signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_6_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_bready[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair13";
begin
E(0) <= \^e\(0);
SR(0) <= \^sr\(0);
aa_grant_any <= \^aa_grant_any\;
aa_grant_rnw <= \^aa_grant_rnw\;
f_hot2enc_return0 <= \^f_hot2enc_return0\;
\m_atarget_hot_reg[3]\ <= \^m_atarget_hot_reg[3]\;
\m_atarget_hot_reg[4]\ <= \^m_atarget_hot_reg[4]\;
\m_axi_arqos[3]\(68 downto 0) <= \^m_axi_arqos[3]\(68 downto 0);
m_ready_d0(0) <= \^m_ready_d0\(0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
m_valid_i <= \^m_valid_i\;
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
O => \gen_axi.s_axi_arready_i_reg\
);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => m_ready_d_0(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \gen_axi.s_axi_awready_i_reg\
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I1 => \^m_axi_arqos[3]\(50),
I2 => \^m_axi_arqos[3]\(51),
I3 => \^m_axi_arqos[3]\(48),
I4 => \^m_axi_arqos[3]\(49),
I5 => mi_rvalid(0),
O => \gen_axi.s_axi_rlast_i_reg\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_rnw\,
I2 => m_ready_d(1),
I3 => \m_atarget_hot_reg[4]_0\(4),
I4 => mi_arready(0),
I5 => mi_rvalid(0),
O => s_axi_rid_i
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^m_axi_arqos[3]\(44),
I1 => \^m_axi_arqos[3]\(45),
I2 => \^m_axi_arqos[3]\(46),
I3 => \^m_axi_arqos[3]\(47),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^m_ready_d_reg[1]_0\,
I1 => s_axi_wlast(0),
I2 => \m_atarget_hot_reg[4]_0\(4),
I3 => write_cs(0),
O => \gen_axi.s_axi_wready_i_reg_0\
);
\gen_axi.s_axi_wready_i_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFFFF"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d_0(2),
I3 => mi_awready(0),
I4 => \m_atarget_hot_reg[4]_0\(4),
O => \gen_axi.s_axi_wready_i_reg\
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(0),
O => \m_ready_d_reg[0]_0\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF4700000044"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => s_axi_awvalid(0),
I3 => \^aa_grant_any\,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(0),
O => s_amesg(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(10),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_grant_any\,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(11),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(1),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(2),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(33)
);
\gen_no_arbiter.m_amesg_i[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(34)
);
\gen_no_arbiter.m_amesg_i[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(35)
);
\gen_no_arbiter.m_amesg_i[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(36)
);
\gen_no_arbiter.m_amesg_i[37]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(37)
);
\gen_no_arbiter.m_amesg_i[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(38)
);
\gen_no_arbiter.m_amesg_i[39]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(39)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(3),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[40]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(40)
);
\gen_no_arbiter.m_amesg_i[41]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(41)
);
\gen_no_arbiter.m_amesg_i[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(42)
);
\gen_no_arbiter.m_amesg_i[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(43)
);
\gen_no_arbiter.m_amesg_i[44]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(0),
O => s_amesg(44)
);
\gen_no_arbiter.m_amesg_i[45]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(1),
O => s_amesg(45)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(2),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(3),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(4),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[49]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(5),
O => s_amesg(49)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(4),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(6),
O => s_amesg(50)
);
\gen_no_arbiter.m_amesg_i[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlen(7),
O => s_amesg(51)
);
\gen_no_arbiter.m_amesg_i[52]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(0),
O => s_amesg(52)
);
\gen_no_arbiter.m_amesg_i[53]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(1),
O => s_amesg(53)
);
\gen_no_arbiter.m_amesg_i[54]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awsize(2),
O => s_amesg(54)
);
\gen_no_arbiter.m_amesg_i[55]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arlock(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awlock(0),
O => s_amesg(55)
);
\gen_no_arbiter.m_amesg_i[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(57)
);
\gen_no_arbiter.m_amesg_i[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(58)
);
\gen_no_arbiter.m_amesg_i[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(59)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(5),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[60]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arburst(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awburst(0),
O => s_amesg(60)
);
\gen_no_arbiter.m_amesg_i[61]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awburst(1),
O => s_amesg(61)
);
\gen_no_arbiter.m_amesg_i[62]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(0),
O => s_amesg(62)
);
\gen_no_arbiter.m_amesg_i[63]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(1),
O => s_amesg(63)
);
\gen_no_arbiter.m_amesg_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(2),
O => s_amesg(64)
);
\gen_no_arbiter.m_amesg_i[65]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arcache(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awcache(3),
O => s_amesg(65)
);
\gen_no_arbiter.m_amesg_i[66]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(0),
O => s_amesg(66)
);
\gen_no_arbiter.m_amesg_i[67]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(1),
O => s_amesg(67)
);
\gen_no_arbiter.m_amesg_i[68]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(2),
O => s_amesg(68)
);
\gen_no_arbiter.m_amesg_i[69]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arqos(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awqos(3),
O => s_amesg(69)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(6),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(7),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(8),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arid(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awid(9),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(0),
Q => \^m_axi_arqos[3]\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^m_axi_arqos[3]\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^m_axi_arqos[3]\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^m_axi_arqos[3]\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^m_axi_arqos[3]\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^m_axi_arqos[3]\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^m_axi_arqos[3]\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^m_axi_arqos[3]\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^m_axi_arqos[3]\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^m_axi_arqos[3]\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^m_axi_arqos[3]\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^m_axi_arqos[3]\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^m_axi_arqos[3]\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^m_axi_arqos[3]\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^m_axi_arqos[3]\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^m_axi_arqos[3]\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^m_axi_arqos[3]\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^m_axi_arqos[3]\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^m_axi_arqos[3]\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^m_axi_arqos[3]\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^m_axi_arqos[3]\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^m_axi_arqos[3]\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^m_axi_arqos[3]\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^m_axi_arqos[3]\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^m_axi_arqos[3]\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^m_axi_arqos[3]\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(33),
Q => \^m_axi_arqos[3]\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(34),
Q => \^m_axi_arqos[3]\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(35),
Q => \^m_axi_arqos[3]\(35),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(36),
Q => \^m_axi_arqos[3]\(36),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(37),
Q => \^m_axi_arqos[3]\(37),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(38),
Q => \^m_axi_arqos[3]\(38),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(39),
Q => \^m_axi_arqos[3]\(39),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^m_axi_arqos[3]\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(40),
Q => \^m_axi_arqos[3]\(40),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(41),
Q => \^m_axi_arqos[3]\(41),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(42),
Q => \^m_axi_arqos[3]\(42),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(43),
Q => \^m_axi_arqos[3]\(43),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(44),
Q => \^m_axi_arqos[3]\(44),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(45),
Q => \^m_axi_arqos[3]\(45),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^m_axi_arqos[3]\(46),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^m_axi_arqos[3]\(47),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^m_axi_arqos[3]\(48),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(49),
Q => \^m_axi_arqos[3]\(49),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^m_axi_arqos[3]\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(50),
Q => \^m_axi_arqos[3]\(50),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(51),
Q => \^m_axi_arqos[3]\(51),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(52),
Q => \^m_axi_arqos[3]\(52),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(53),
Q => \^m_axi_arqos[3]\(53),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(54),
Q => \^m_axi_arqos[3]\(54),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(55),
Q => \^m_axi_arqos[3]\(55),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(57),
Q => \^m_axi_arqos[3]\(56),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(58),
Q => \^m_axi_arqos[3]\(57),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(59),
Q => \^m_axi_arqos[3]\(58),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^m_axi_arqos[3]\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(60),
Q => \^m_axi_arqos[3]\(59),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(61),
Q => \^m_axi_arqos[3]\(60),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(62),
Q => \^m_axi_arqos[3]\(61),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(63),
Q => \^m_axi_arqos[3]\(62),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(64),
Q => \^m_axi_arqos[3]\(63),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(65),
Q => \^m_axi_arqos[3]\(64),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(66),
Q => \^m_axi_arqos[3]\(65),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(67),
Q => \^m_axi_arqos[3]\(66),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(68),
Q => \^m_axi_arqos[3]\(67),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(69),
Q => \^m_axi_arqos[3]\(68),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^m_axi_arqos[3]\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^m_axi_arqos[3]\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^m_axi_arqos[3]\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^m_axi_arqos[3]\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DDDC0000"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_any\,
I2 => s_axi_awvalid(0),
I3 => s_axi_arvalid(0),
I4 => aresetn_d,
I5 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808080808080B080"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => \^m_ready_d0\(0),
I4 => \m_ready_d[2]_i_6_n_0\,
I5 => \m_ready_d_reg[1]_1\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => \^aa_grant_any\,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => \^m_valid_i\,
I2 => \^aa_grant_any\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_any\,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_atarget_hot_reg[4]\,
I1 => \^f_hot2enc_return0\,
O => \m_atarget_enc_reg[2]\(0)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_atarget_hot[1]_i_2_n_0\,
I1 => \^aa_grant_any\,
I2 => \^m_axi_arqos[3]\(28),
I3 => \^m_axi_arqos[3]\(31),
I4 => \^m_axi_arqos[3]\(30),
I5 => \^m_axi_arqos[3]\(29),
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \^m_axi_arqos[3]\(31),
I1 => \^m_axi_arqos[3]\(30),
I2 => \^m_axi_arqos[3]\(29),
I3 => \m_atarget_hot[1]_i_2_n_0\,
I4 => \^m_axi_arqos[3]\(28),
I5 => \^aa_grant_any\,
O => D(1)
);
\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \m_atarget_hot[2]_i_3_n_0\,
I1 => \^m_axi_arqos[3]\(33),
I2 => \^m_axi_arqos[3]\(34),
I3 => \^m_axi_arqos[3]\(36),
I4 => \m_atarget_hot[1]_i_3_n_0\,
O => \m_atarget_hot[1]_i_2_n_0\
);
\m_atarget_hot[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^m_axi_arqos[3]\(32),
I1 => \^m_axi_arqos[3]\(37),
I2 => \^m_axi_arqos[3]\(35),
O => \m_atarget_hot[1]_i_3_n_0\
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \^m_axi_arqos[3]\(37),
I1 => \^m_axi_arqos[3]\(32),
I2 => \^m_axi_arqos[3]\(35),
I3 => \m_atarget_hot[2]_i_2_n_0\,
I4 => \^aa_grant_any\,
O => D(2)
);
\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \m_atarget_hot[2]_i_3_n_0\,
I1 => \^m_axi_arqos[3]\(33),
I2 => \^m_axi_arqos[3]\(34),
I3 => \^m_axi_arqos[3]\(36),
I4 => \m_atarget_hot[2]_i_4_n_0\,
O => \m_atarget_hot[2]_i_2_n_0\
);
\m_atarget_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \^m_axi_arqos[3]\(43),
I1 => \^m_axi_arqos[3]\(39),
I2 => \^m_axi_arqos[3]\(41),
I3 => \^m_axi_arqos[3]\(40),
I4 => \^m_axi_arqos[3]\(38),
I5 => \^m_axi_arqos[3]\(42),
O => \m_atarget_hot[2]_i_3_n_0\
);
\m_atarget_hot[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^m_axi_arqos[3]\(28),
I1 => \^m_axi_arqos[3]\(31),
I2 => \^m_axi_arqos[3]\(30),
I3 => \^m_axi_arqos[3]\(29),
O => \m_atarget_hot[2]_i_4_n_0\
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_atarget_hot_reg[3]\,
I1 => \^aa_grant_any\,
O => D(3)
);
\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^m_axi_arqos[3]\(35),
I1 => \^m_axi_arqos[3]\(37),
I2 => \^m_axi_arqos[3]\(32),
I3 => \m_atarget_hot[2]_i_2_n_0\,
O => \^m_atarget_hot_reg[3]\
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^f_hot2enc_return0\,
I1 => \^m_atarget_hot_reg[4]\,
I2 => \^aa_grant_any\,
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"1001"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => \^m_axi_arqos[3]\(32),
I2 => \^m_axi_arqos[3]\(37),
I3 => \^m_axi_arqos[3]\(35),
O => \^f_hot2enc_return0\
);
\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \^m_axi_arqos[3]\(31),
I1 => \^m_axi_arqos[3]\(30),
I2 => \^m_axi_arqos[3]\(29),
I3 => \m_atarget_hot[1]_i_2_n_0\,
O => \^m_atarget_hot_reg[4]\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
O => m_axi_arvalid(3)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(2),
O => m_axi_awvalid(3)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(0),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(1),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(2),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[4]_0\(3),
I1 => s_axi_wvalid(0),
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(3)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000FFFF"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => s_axi_rready(0),
I4 => sr_rvalid,
O => \^e\(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^m_valid_i\,
I1 => \^aa_grant_rnw\,
O => \m_ready_d_reg[0]_1\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA80AA00AA80AA80"
)
port map (
I0 => m_ready_d0_1(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => m_ready_d(1),
I4 => \m_atarget_enc_reg[0]\,
I5 => \m_atarget_enc_reg[2]_0\,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d_0(1),
I3 => s_axi_wvalid(0),
O => \^m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"020F0F0F"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[0]\,
I2 => m_ready_d(1),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
O => \m_ready_d_reg[1]\
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0FDF0"
)
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \gen_axi.s_axi_awready_i_reg_0\,
I2 => m_ready_d_0(2),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => \^m_ready_d0\(0)
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020202020222020"
)
port map (
I0 => \^m_ready_d0\(0),
I1 => \m_ready_d[2]_i_6_n_0\,
I2 => m_ready_d_0(1),
I3 => \m_atarget_enc_reg[1]\,
I4 => s_axi_wlast(0),
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d_reg[2]\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF2FFFFF"
)
port map (
I0 => \m_atarget_enc_reg[1]_0\,
I1 => \gen_axi.s_axi_bvalid_i_reg\,
I2 => s_axi_bready(0),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => m_ready_d_0(0),
O => \m_ready_d[2]_i_6_n_0\
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => Q(1),
I1 => \^e\(0),
I2 => m_valid_i_i_2_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAA8AAA8AAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d(0),
I2 => \^aa_grant_rnw\,
I3 => \^m_valid_i\,
I4 => \gen_axi.read_cs_reg[0]\,
I5 => \m_atarget_enc_reg[1]_1\,
O => m_valid_i_i_2_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => s_ready_i,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d_0(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => \^aa_grant_any\,
I4 => \m_atarget_enc_reg[0]_0\,
O => s_axi_bvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d_0(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => \^aa_grant_any\,
I4 => \m_atarget_enc_reg[1]\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => Q(0),
I1 => \^e\(0),
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
\skid_buffer_reg[0]\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\m_atarget_hot_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[2]_0\ : in STD_LOGIC;
aa_rready : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_no_arbiter.m_amesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\gen_no_arbiter.m_amesg_i_reg[50]\ : in STD_LOGIC;
s_axi_rid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_bvalid : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_rmesg : STD_LOGIC_VECTOR ( 144 to 144 );
signal \^mi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_wready : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \skid_buffer[0]_i_2_n_0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair17";
begin
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
mi_arready(0) <= \^mi_arready\(0);
mi_awready(0) <= \^mi_awready\(0);
mi_rvalid(0) <= \^mi_rvalid\(0);
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__1\(0),
I1 => \^mi_rvalid\(0),
I2 => \gen_no_arbiter.m_amesg_i_reg[51]\(0),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01FFFFFE010000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__1\(0),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \^mi_rvalid\(0),
I5 => \gen_no_arbiter.m_amesg_i_reg[51]\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(4),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B4FFB400"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(4),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(3),
I2 => \gen_axi.read_cnt_reg__1\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_4_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \^mi_rvalid\(0),
I3 => \gen_no_arbiter.m_amesg_i_reg[51]\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080F0008080"
)
port map (
I0 => \^mi_arready\(0),
I1 => \m_ready_d_reg[1]_1\,
I2 => Q(0),
I3 => aa_rready,
I4 => \^mi_rvalid\(0),
I5 => \gen_axi.read_cnt[7]_i_3_n_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(6),
I1 => \gen_axi.read_cnt[7]_i_4_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(7),
I3 => \^mi_rvalid\(0),
I4 => \gen_no_arbiter.m_amesg_i_reg[51]\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt[7]_i_4_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(6),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(5),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(3),
I3 => \gen_axi.read_cnt_reg__1\(0),
I4 => \gen_axi.read_cnt_reg__0\(1),
I5 => \gen_axi.read_cnt_reg__0\(4),
O => \gen_axi.read_cnt[7]_i_4_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__1\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFFFFF88008800"
)
port map (
I0 => \^mi_arready\(0),
I1 => \m_ready_d_reg[1]_1\,
I2 => aa_rready,
I3 => Q(0),
I4 => \gen_axi.read_cnt[7]_i_3_n_0\,
I5 => \^mi_rvalid\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^mi_rvalid\(0),
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC888808888888"
)
port map (
I0 => \gen_axi.s_axi_arready_i_i_2_n_0\,
I1 => aresetn_d,
I2 => \m_ready_d_reg[1]_1\,
I3 => Q(0),
I4 => \^mi_arready\(0),
I5 => \^mi_rvalid\(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5557555555555555"
)
port map (
I0 => \^mi_rvalid\(0),
I1 => \gen_axi.read_cnt_reg__0\(7),
I2 => \gen_axi.read_cnt[7]_i_4_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(6),
I4 => Q(0),
I5 => aa_rready,
O => \gen_axi.s_axi_arready_i_i_2_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready\(0),
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDFDF30003333"
)
port map (
I0 => \m_ready_d_reg[2]_0\,
I1 => write_cs(0),
I2 => Q(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready\(0),
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready\(0),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7FFF800000"
)
port map (
I0 => \gen_no_arbiter.grant_rnw_reg\,
I1 => Q(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \m_atarget_hot_reg[4]\,
I5 => mi_bvalid(4),
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => mi_bvalid(4),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4FFF4F4F400"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \^mi_rvalid\(0),
I2 => \gen_no_arbiter.m_amesg_i_reg[50]\,
I3 => s_axi_rid_i,
I4 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I5 => mi_rmesg(144),
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \^mi_rvalid\(0),
I2 => \gen_axi.read_cnt_reg__0\(4),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt_reg__0\(2),
I5 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF7"
)
port map (
I0 => aa_rready,
I1 => Q(0),
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \gen_axi.read_cnt_reg__0\(7),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => mi_rmesg(144),
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77770003"
)
port map (
I0 => \m_atarget_hot_reg[4]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => \gen_no_arbiter.grant_rnw_reg_0\,
I4 => mi_wready(4),
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => mi_wready(4),
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1A"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \gen_axi.write_cs[1]_i_3_n_0\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABF00"
)
port map (
I0 => write_cs(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => Q(0),
I3 => \^gen_axi.write_cs_reg[1]_0\(0),
I4 => \gen_axi.write_cs[1]_i_3_n_0\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B88888888888888"
)
port map (
I0 => \m_atarget_hot_reg[4]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => Q(0),
I4 => \^mi_awready\(0),
I5 => \m_ready_d_reg[2]_0\,
O => \gen_axi.write_cs[1]_i_3_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCF7FFF7"
)
port map (
I0 => mi_wready(4),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_wready(0),
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A00F0C00A0000C"
)
port map (
I0 => m_axi_arready(1),
I1 => m_axi_arready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => \^mi_arready\(0),
O => \m_ready_d_reg[1]\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000AFC00000A0C"
)
port map (
I0 => \^mi_awready\(0),
I1 => m_axi_awready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_awready(1),
O => \m_ready_d_reg[2]\
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF0A0000C00A00"
)
port map (
I0 => \^mi_rvalid\(0),
I1 => m_axi_rvalid(1),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_axi_rvalid(0),
O => m_valid_i_reg
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FCFDFFFD"
)
port map (
I0 => m_axi_bvalid(0),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_bvalid(2),
I5 => \^m_ready_d_reg[0]_0\,
O => \m_ready_d_reg[0]\
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A00C0000A00C0"
)
port map (
I0 => m_axi_bvalid(1),
I1 => mi_bvalid(4),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bvalid(3),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FCF7FFF7"
)
port map (
I0 => m_axi_wready(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => mi_wready(4),
I5 => \m_atarget_enc_reg[0]_0\,
O => \m_ready_d_reg[1]_0\
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF1000"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(1),
I3 => m_axi_rlast(1),
I4 => \skid_buffer[0]_i_2_n_0\,
I5 => \m_atarget_enc_reg[0]\,
O => \skid_buffer_reg[0]\
);
\skid_buffer[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => mi_rmesg(144),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rlast(0),
O => \skid_buffer[0]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
port (
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55550455"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \gen_axi.s_axi_wready_i_reg\,
I2 => \^m_ready_d_reg[1]_0\,
I3 => s_axi_wlast(0),
I4 => \gen_no_arbiter.grant_rnw_reg\,
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000BA00"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_atarget_enc_reg[0]\,
I2 => \gen_no_arbiter.grant_rnw_reg_0\,
I3 => aresetn_d,
I4 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AABA0000"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_atarget_enc_reg[1]\,
I2 => s_axi_wlast(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => aresetn_d,
I5 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => m_ready_d0(0),
I1 => aresetn_d,
I2 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DCFFDFFF"
)
port map (
I0 => m_axi_awready(1),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_awready(0),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4FFF7"
)
port map (
I0 => m_axi_bvalid(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_bvalid(0),
O => \m_ready_d_reg[2]_1\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000AC000000AC"
)
port map (
I0 => m_axi_wready(1),
I1 => m_axi_wready(0),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_wready(2),
O => \^m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_14_splitter";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAAAAAA"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \gen_no_arbiter.m_valid_i_reg\,
I2 => s_axi_rready(0),
I3 => sr_rvalid,
I4 => \m_payload_i_reg[0]\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCDFFFDF"
)
port map (
I0 => m_axi_arready(0),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_arready(1),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aa_grant_rnw : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_grant_any : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rdata[31]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \skid_buffer[24]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \skid_buffer[29]_i_2\ : label is "soft_lutpair20";
begin
aa_rready <= \^aa_rready\;
m_valid_i_reg_1(1 downto 0) <= \^m_valid_i_reg_1\(1 downto 0);
\s_axi_rdata[31]\(34 downto 0) <= \^s_axi_rdata[31]\(34 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_1\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_1\(0),
Q => \^m_valid_i_reg_1\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => Q(3),
O => m_axi_rready(3)
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_atarget_enc_reg[2]\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[10]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[11]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[12]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[13]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[14]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[15]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[16]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[17]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[18]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[19]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFAFAFACAFACAFA"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \m_payload_i[1]_i_2_n_0\,
I2 => \^aa_rready\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
I5 => m_axi_rresp(2),
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A0CF0000A0C0"
)
port map (
I0 => m_axi_rresp(6),
I1 => m_axi_rresp(4),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(2),
I5 => m_axi_rresp(0),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => m_atarget_enc(1),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[20]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[21]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[22]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[23]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[24]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[25]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[26]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[27]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[28]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[29]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E0EE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"030E0302FFFFFFFF"
)
port map (
I0 => m_axi_rresp(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rresp(5),
I5 => \^aa_rready\,
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F3F7FFF7"
)
port map (
I0 => m_axi_rresp(3),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rresp(7),
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[30]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[31]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[32]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[33]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[34]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[3]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[4]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[5]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[6]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[7]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[8]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[9]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^s_axi_rdata[31]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^s_axi_rdata[31]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^s_axi_rdata[31]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^s_axi_rdata[31]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^s_axi_rdata[31]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^s_axi_rdata[31]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^s_axi_rdata[31]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^s_axi_rdata[31]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^s_axi_rdata[31]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^s_axi_rdata[31]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^s_axi_rdata[31]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^s_axi_rdata[31]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^s_axi_rdata[31]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^s_axi_rdata[31]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^s_axi_rdata[31]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^s_axi_rdata[31]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^s_axi_rdata[31]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^s_axi_rdata[31]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^s_axi_rdata[31]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^s_axi_rdata[31]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^s_axi_rdata[31]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^s_axi_rdata[31]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^s_axi_rdata[31]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^s_axi_rdata[31]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^s_axi_rdata[31]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^s_axi_rdata[31]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^s_axi_rdata[31]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^s_axi_rdata[31]\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^s_axi_rdata[31]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^s_axi_rdata[31]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^s_axi_rdata[31]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^s_axi_rdata[31]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^s_axi_rdata[31]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^s_axi_rdata[31]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^s_axi_rdata[31]\(9),
R => '0'
);
\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF80000000"
)
port map (
I0 => \^s_axi_rdata[31]\(0),
I1 => \^sr_rvalid\,
I2 => s_axi_rready(0),
I3 => m_valid_i,
I4 => aa_grant_rnw,
I5 => m_ready_d(0),
O => m_ready_d0(0)
);
m_valid_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4FFF7"
)
port map (
I0 => m_axi_rvalid(1),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rvalid(0),
O => m_valid_i_reg_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^sr_rvalid\,
I1 => aa_grant_any,
O => s_axi_rvalid(0)
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C080008"
)
port map (
I0 => m_axi_rlast(0),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rlast(1),
O => \skid_buffer_reg[0]_0\
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(39),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(71),
I5 => \skid_buffer[10]_i_2_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(103),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(7),
O => \skid_buffer[10]_i_2_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(40),
I5 => \skid_buffer[11]_i_2_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(104),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(8),
O => \skid_buffer[11]_i_2_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(41),
I5 => \skid_buffer[12]_i_2_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(105),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(9),
O => \skid_buffer[12]_i_2_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(42),
I5 => \skid_buffer[13]_i_2_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(106),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(10),
O => \skid_buffer[13]_i_2_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(43),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(75),
I5 => \skid_buffer[14]_i_2_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(107),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(11),
O => \skid_buffer[14]_i_2_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(44),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(76),
I5 => \skid_buffer[15]_i_2_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(108),
O => \skid_buffer[15]_i_2_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(45),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(77),
I5 => \skid_buffer[16]_i_2_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[16]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(109),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(13),
O => \skid_buffer[16]_i_2_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(46),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(78),
I5 => \skid_buffer[17]_i_2_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[17]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(110),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(14),
O => \skid_buffer[17]_i_2_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(47),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(79),
I5 => \skid_buffer[18]_i_2_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[18]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(111),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(15),
O => \skid_buffer[18]_i_2_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(48),
I5 => \skid_buffer[19]_i_2_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(112),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(16),
O => \skid_buffer[19]_i_2_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(49),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(81),
I5 => \skid_buffer[20]_i_2_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[20]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(113),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(17),
O => \skid_buffer[20]_i_2_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(50),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(82),
I5 => \skid_buffer[21]_i_2_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[21]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(114),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(18),
O => \skid_buffer[21]_i_2_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(51),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(83),
I5 => \skid_buffer[22]_i_2_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[22]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(115),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(19),
O => \skid_buffer[22]_i_2_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(52),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(84),
I5 => \skid_buffer[23]_i_2_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(116),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(20),
O => \skid_buffer[23]_i_2_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(53),
I5 => \skid_buffer[24]_i_2_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[24]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(117),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(21),
O => \skid_buffer[24]_i_2_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(54),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(86),
I5 => \skid_buffer[25]_i_2_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[25]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(118),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(22),
O => \skid_buffer[25]_i_2_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(55),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(87),
I5 => \skid_buffer[26]_i_2_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[26]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(119),
O => \skid_buffer[26]_i_2_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(56),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(88),
I5 => \skid_buffer[27]_i_2_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(120),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(24),
O => \skid_buffer[27]_i_2_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(57),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(89),
I5 => \skid_buffer[28]_i_2_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(121),
O => \skid_buffer[28]_i_2_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(90),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(58),
I5 => \skid_buffer[29]_i_2_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(122),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(26),
O => \skid_buffer[29]_i_2_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(59),
I5 => \skid_buffer[30]_i_2_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[30]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(123),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(27),
O => \skid_buffer[30]_i_2_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(60),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(92),
I5 => \skid_buffer[31]_i_2_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(124),
O => \skid_buffer[31]_i_2_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(93),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(61),
I5 => \skid_buffer[32]_i_2_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[32]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(125),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(29),
O => \skid_buffer[32]_i_2_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(62),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(94),
I5 => \skid_buffer[33]_i_2_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[33]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(126),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(30),
O => \skid_buffer[33]_i_2_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(63),
I5 => \skid_buffer[34]_i_2_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[34]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(127),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(31),
O => \skid_buffer[34]_i_2_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(32),
I5 => \skid_buffer[3]_i_2_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(96),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(0),
O => \skid_buffer[3]_i_2_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(33),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(65),
I5 => \skid_buffer[4]_i_2_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(97),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(1),
O => \skid_buffer[4]_i_2_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(34),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(66),
I5 => \skid_buffer[5]_i_2_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(98),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(2),
O => \skid_buffer[5]_i_2_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(35),
I5 => \skid_buffer[6]_i_2_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C020002"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_atarget_enc(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(99),
O => \skid_buffer[6]_i_2_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(36),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(68),
I5 => \skid_buffer[7]_i_2_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(100),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(4),
O => \skid_buffer[7]_i_2_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00380008"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_axi_rdata(37),
I5 => \skid_buffer[8]_i_2_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(101),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(5),
O => \skid_buffer[8]_i_2_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF03200020"
)
port map (
I0 => m_axi_rdata(38),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => m_axi_rdata(70),
I5 => \skid_buffer[9]_i_2_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08030800"
)
port map (
I0 => m_axi_rdata(102),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_axi_rdata(6),
O => \skid_buffer[9]_i_2_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \m_atarget_enc_reg[2]\,
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal aa_grant_any : STD_LOGIC;
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_10 : STD_LOGIC;
signal addr_arbiter_inst_n_102 : STD_LOGIC;
signal addr_arbiter_inst_n_107 : STD_LOGIC;
signal addr_arbiter_inst_n_11 : STD_LOGIC;
signal addr_arbiter_inst_n_113 : STD_LOGIC;
signal addr_arbiter_inst_n_117 : STD_LOGIC;
signal addr_arbiter_inst_n_12 : STD_LOGIC;
signal addr_arbiter_inst_n_13 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_5 : STD_LOGIC;
signal addr_arbiter_inst_n_6 : STD_LOGIC;
signal addr_arbiter_inst_n_7 : STD_LOGIC;
signal addr_arbiter_inst_n_85 : STD_LOGIC;
signal addr_arbiter_inst_n_86 : STD_LOGIC;
signal addr_arbiter_inst_n_87 : STD_LOGIC;
signal addr_arbiter_inst_n_9 : STD_LOGIC;
signal addr_arbiter_inst_n_94 : STD_LOGIC;
signal addr_arbiter_inst_n_95 : STD_LOGIC;
signal addr_arbiter_inst_n_96 : STD_LOGIC;
signal any_error : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal f_hot2enc_return0 : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_10\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_11\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_9\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_atarget_enc[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_enc[1]_i_1_n_0\ : STD_LOGIC;
signal m_atarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 2 to 2 );
signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_awready : STD_LOGIC_VECTOR ( 4 to 4 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_39 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rdata[31]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal s_axi_rid_i : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair41";
begin
Q(68 downto 0) <= \^q\(68 downto 0);
\s_axi_rdata[31]\(34 downto 0) <= \^s_axi_rdata[31]\(34 downto 0);
addr_arbiter_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd
port map (
D(4) => addr_arbiter_inst_n_10,
D(3) => addr_arbiter_inst_n_11,
D(2) => addr_arbiter_inst_n_12,
D(1) => addr_arbiter_inst_n_13,
D(0) => m_atarget_hot0(0),
E(0) => p_1_in,
Q(1) => reg_slice_r_n_45,
Q(0) => reg_slice_r_n_46,
SR(0) => reset,
aa_grant_any => aa_grant_any,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
f_hot2enc_return0 => f_hot2enc_return0,
\gen_axi.read_cs_reg[0]\ => \gen_decerr.decerr_slave_inst_n_5\,
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_inst_n_6,
\gen_axi.s_axi_awready_i_reg\ => addr_arbiter_inst_n_107,
\gen_axi.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_7\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_11\,
\gen_axi.s_axi_rlast_i_reg\ => addr_arbiter_inst_n_117,
\gen_axi.s_axi_wready_i_reg\ => addr_arbiter_inst_n_87,
\gen_axi.s_axi_wready_i_reg_0\ => addr_arbiter_inst_n_94,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_atarget_enc_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_6,
\m_atarget_enc_reg[1]_1\ => reg_slice_r_n_39,
\m_atarget_enc_reg[2]\(0) => any_error,
\m_atarget_enc_reg[2]_0\ => splitter_ar_n_0,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_5,
\m_atarget_hot_reg[3]\ => addr_arbiter_inst_n_86,
\m_atarget_hot_reg[4]\ => addr_arbiter_inst_n_85,
\m_atarget_hot_reg[4]_0\(4 downto 0) => m_atarget_hot(4 downto 0),
\m_axi_arqos[3]\(68 downto 0) => \^q\(68 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0(2),
m_ready_d0_1(0) => m_ready_d0_0(0),
m_ready_d_0(2 downto 0) => m_ready_d_1(2 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_4,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_102,
\m_ready_d_reg[0]_1\ => addr_arbiter_inst_n_113,
\m_ready_d_reg[1]\ => addr_arbiter_inst_n_5,
\m_ready_d_reg[1]_0\ => addr_arbiter_inst_n_95,
\m_ready_d_reg[1]_1\ => splitter_aw_n_0,
\m_ready_d_reg[2]\ => addr_arbiter_inst_n_96,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_9,
mi_arready(0) => mi_arready(4),
mi_awready(0) => mi_awready(4),
mi_rvalid(0) => mi_rvalid(4),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rid_i => s_axi_rid_i,
s_axi_rready(0) => s_axi_rready(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_7,
sr_rvalid => sr_rvalid,
write_cs(0) => write_cs(1)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
port map (
Q(0) => m_atarget_hot(4),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_102,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_87,
\gen_no_arbiter.m_amesg_i_reg[50]\ => addr_arbiter_inst_n_117,
\gen_no_arbiter.m_amesg_i_reg[51]\(7 downto 0) => \^q\(51 downto 44),
\gen_no_arbiter.m_valid_i_reg\ => \gen_decerr.decerr_slave_inst_n_9\,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[0]\ => reg_slice_r_n_38,
\m_atarget_enc_reg[0]_0\ => splitter_aw_n_4,
\m_atarget_hot_reg[4]\ => addr_arbiter_inst_n_94,
m_axi_arready(1) => m_axi_arready(3),
m_axi_arready(0) => m_axi_arready(0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rlast(1) => m_axi_rlast(2),
m_axi_rlast(0) => m_axi_rlast(0),
m_axi_rvalid(1) => m_axi_rvalid(3),
m_axi_rvalid(0) => m_axi_rvalid(1),
m_axi_wready(0) => m_axi_wready(2),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_11\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_6,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_107,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_5\,
mi_arready(0) => mi_arready(4),
mi_awready(0) => mi_awready(4),
mi_rvalid(0) => mi_rvalid(4),
s_axi_rid_i => s_axi_rid_i,
\skid_buffer_reg[0]\ => \gen_decerr.decerr_slave_inst_n_4\
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C0E000E0"
)
port map (
I0 => \^q\(28),
I1 => addr_arbiter_inst_n_86,
I2 => aresetn_d,
I3 => addr_arbiter_inst_n_85,
I4 => f_hot2enc_return0,
O => \m_atarget_enc[0]_i_1_n_0\
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aresetn_d,
I1 => f_hot2enc_return0,
O => \m_atarget_enc[1]_i_1_n_0\
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[0]_i_1_n_0\,
Q => m_atarget_enc(0),
R => '0'
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[1]_i_1_n_0\,
Q => m_atarget_enc(1),
R => '0'
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => any_error,
Q => m_atarget_enc(2),
R => reset
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(0),
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_13,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_12,
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_11,
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_10,
Q => m_atarget_hot(4),
R => reset
);
reg_slice_r: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
E(0) => p_1_in,
Q(3 downto 0) => m_atarget_hot(3 downto 0),
SR(0) => reset,
aa_grant_any => aa_grant_any,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_7,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_9,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_4\,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast(1) => m_axi_rlast(3),
m_axi_rlast(0) => m_axi_rlast(1),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(1) => m_axi_rvalid(2),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_ready_d(0) => m_ready_d(0),
m_ready_d0(0) => m_ready_d0_0(0),
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_39,
m_valid_i_reg_1(1) => reg_slice_r_n_45,
m_valid_i_reg_1(0) => reg_slice_r_n_46,
\s_axi_rdata[31]\(34 downto 0) => \^s_axi_rdata[31]\(34 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
\skid_buffer_reg[0]_0\ => reg_slice_r_n_38,
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1410"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_axi_bresp(4),
I4 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CA000F00CA0000"
)
port map (
I0 => m_axi_bresp(2),
I1 => m_axi_bresp(6),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(0),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1410"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_axi_bresp(5),
I4 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A000C0F0A000C00"
)
port map (
I0 => m_axi_bresp(7),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(1),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
splitter_ar: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\
port map (
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_4,
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_inst_n_113,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(2 downto 1),
\m_payload_i_reg[0]\(0) => \^s_axi_rdata[31]\(0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0_0(0),
\m_ready_d_reg[1]_0\ => splitter_ar_n_0,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_5,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_wready_i_reg\ => \gen_decerr.decerr_slave_inst_n_9\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_95,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_102,
\gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_0,
m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_10\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_8\,
m_axi_awready(1 downto 0) => m_axi_awready(3 downto 2),
m_axi_bvalid(1) => m_axi_bvalid(2),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_wready(2) => m_axi_wready(3),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0(2),
\m_ready_d_reg[1]_0\ => splitter_aw_n_4,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_96,
\m_ready_d_reg[2]_0\ => splitter_aw_n_5,
\m_ready_d_reg[2]_1\ => splitter_aw_n_6,
s_axi_wlast(0) => s_axi_wlast(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 112 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 112) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(127 downto 112);
m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_arlock(3) <= \^m_axi_arlock\(0);
m_axi_arlock(2) <= \^m_axi_arlock\(0);
m_axi_arlock(1) <= \^m_axi_arlock\(0);
m_axi_arlock(0) <= \^m_axi_arlock\(0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 112) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(127 downto 112);
m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_awburst(7 downto 6) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
m_axi_awburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
m_axi_awcache(15 downto 12) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
m_axi_awcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
m_axi_awid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_arlock\(0);
m_axi_awlock(2) <= \^m_axi_arlock\(0);
m_axi_awlock(1) <= \^m_axi_arlock\(0);
m_axi_awlock(0) <= \^m_axi_arlock\(0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(15 downto 12) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
m_axi_awqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
m_axi_awsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
s_axi_buser(0) <= \<const0>\;
s_axi_rid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd
port map (
Q(68 downto 65) => \^m_axi_arqos\(3 downto 0),
Q(64 downto 61) => \^m_axi_arcache\(3 downto 0),
Q(60 downto 59) => \^m_axi_arburst\(1 downto 0),
Q(58 downto 56) => \^m_axi_arprot\(2 downto 0),
Q(55) => \^m_axi_arlock\(0),
Q(54 downto 52) => \^m_axi_arsize\(2 downto 0),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 28) => \^m_axi_awaddr\(127 downto 112),
Q(27 downto 12) => \^m_axi_araddr\(15 downto 0),
Q(11 downto 0) => \^m_axi_arid\(11 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(34 downto 3) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rdata[31]\(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_xbar_1,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => B"000000000000000000000000000000000000000000000000",
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => B"000000000000000000000000000000000000000000000000",
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 963d5c531546bb1782e38ae4448b76b6 | 0.545438 | 2.678866 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35,728 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end ip_design_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end ip_design_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end ip_design_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_lpf : entity is "lpf";
end ip_design_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.ip_design_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.ip_design_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end ip_design_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.ip_design_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end ip_design_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.ip_design_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.ip_design_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_rst_ps7_0_100M_0 : entity is "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ip_design_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ip_design_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2017.3";
end ip_design_rst_ps7_0_100M_0;
architecture STRUCTURE of ip_design_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.ip_design_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | f9cace11a21707af2d8c19070cd7e28c | 0.586403 | 2.857326 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel.vhd | 1 | 135,294 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.319800,HLS_SYN_LAT=10783,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=6,HLS_SYN_FF=3102,HLS_SYN_LUT=2726}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state56 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state57 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state58 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state59 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state60 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state61 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state62 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state63 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state64 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state65 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state66 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state67 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state68 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state69 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state70 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state71 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state72 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state73 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state74 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state75 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state77 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state78 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state79 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state80 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state81 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state82 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state83 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state84 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state85 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state86 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state87 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state88 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state89 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state90 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state91 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state92 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state93 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state94 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state95 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state96 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state97 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state98 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state99 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state100 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state101 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state102 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state103 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state104 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state105 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state106 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state107 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state108 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state109 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state110 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state111 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state112 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state113 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state114 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state115 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state116 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state117 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state118 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state119 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state120 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state121 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state122 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state123 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state124 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state125 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state126 : STD_LOGIC_VECTOR (136 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state127 : STD_LOGIC_VECTOR (136 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state128 : STD_LOGIC_VECTOR (136 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state129 : STD_LOGIC_VECTOR (136 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state130 : STD_LOGIC_VECTOR (136 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state131 : STD_LOGIC_VECTOR (136 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state132 : STD_LOGIC_VECTOR (136 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state133 : STD_LOGIC_VECTOR (136 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state134 : STD_LOGIC_VECTOR (136 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state135 : STD_LOGIC_VECTOR (136 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state136 : STD_LOGIC_VECTOR (136 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state137 : STD_LOGIC_VECTOR (136 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_65 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100101";
constant ap_const_lv32_6A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101010";
constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_7E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001";
constant ap_const_lv32_46 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000110";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_64 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100100";
constant ap_const_lv32_69 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101001";
constant ap_const_lv32_6E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101110";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_7D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111101";
constant ap_const_lv32_82 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000010";
constant ap_const_lv32_87 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_83 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_66 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100110";
constant ap_const_lv32_6B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101011";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv9_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_const_lv9_3 : STD_LOGIC_VECTOR (8 downto 0) := "000000011";
constant ap_const_lv9_4 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_const_lv9_5 : STD_LOGIC_VECTOR (8 downto 0) := "000000101";
constant ap_const_lv9_6 : STD_LOGIC_VECTOR (8 downto 0) := "000000110";
constant ap_const_lv9_7 : STD_LOGIC_VECTOR (8 downto 0) := "000000111";
constant ap_const_lv9_8 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
constant ap_const_lv9_A : STD_LOGIC_VECTOR (8 downto 0) := "000001010";
constant ap_const_lv9_B : STD_LOGIC_VECTOR (8 downto 0) := "000001011";
constant ap_const_lv9_C : STD_LOGIC_VECTOR (8 downto 0) := "000001100";
constant ap_const_lv9_D : STD_LOGIC_VECTOR (8 downto 0) := "000001101";
constant ap_const_lv9_E : STD_LOGIC_VECTOR (8 downto 0) := "000001110";
constant ap_const_lv9_F : STD_LOGIC_VECTOR (8 downto 0) := "000001111";
constant ap_const_lv9_10 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_const_lv9_11 : STD_LOGIC_VECTOR (8 downto 0) := "000010001";
constant ap_const_lv9_12 : STD_LOGIC_VECTOR (8 downto 0) := "000010010";
constant ap_const_lv9_13 : STD_LOGIC_VECTOR (8 downto 0) := "000010011";
constant ap_const_lv9_14 : STD_LOGIC_VECTOR (8 downto 0) := "000010100";
constant ap_const_lv9_15 : STD_LOGIC_VECTOR (8 downto 0) := "000010101";
constant ap_const_lv9_16 : STD_LOGIC_VECTOR (8 downto 0) := "000010110";
constant ap_const_lv9_17 : STD_LOGIC_VECTOR (8 downto 0) := "000010111";
constant ap_const_lv9_18 : STD_LOGIC_VECTOR (8 downto 0) := "000011000";
constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv9_19 : STD_LOGIC_VECTOR (8 downto 0) := "000011001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (136 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal reg_543 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal ap_CS_fsm_state32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
signal ap_CS_fsm_state37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
signal ap_CS_fsm_state42 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state42 : signal is "none";
signal ap_CS_fsm_state47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state47 : signal is "none";
signal ap_CS_fsm_state52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state52 : signal is "none";
signal ap_CS_fsm_state57 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state57 : signal is "none";
signal ap_CS_fsm_state62 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state62 : signal is "none";
signal ap_CS_fsm_state67 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state67 : signal is "none";
signal ap_CS_fsm_state72 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state72 : signal is "none";
signal ap_CS_fsm_state77 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state77 : signal is "none";
signal ap_CS_fsm_state82 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state82 : signal is "none";
signal ap_CS_fsm_state87 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state87 : signal is "none";
signal ap_CS_fsm_state92 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state92 : signal is "none";
signal ap_CS_fsm_state97 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state97 : signal is "none";
signal ap_CS_fsm_state102 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state102 : signal is "none";
signal ap_CS_fsm_state107 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state107 : signal is "none";
signal ap_CS_fsm_state112 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state112 : signal is "none";
signal ap_CS_fsm_state117 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state117 : signal is "none";
signal ap_CS_fsm_state122 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state122 : signal is "none";
signal ap_CS_fsm_state127 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state127 : signal is "none";
signal reg_548 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_539_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_553 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal ap_CS_fsm_state21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal ap_CS_fsm_state31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
signal ap_CS_fsm_state36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal ap_CS_fsm_state41 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state41 : signal is "none";
signal ap_CS_fsm_state46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state46 : signal is "none";
signal ap_CS_fsm_state51 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state51 : signal is "none";
signal ap_CS_fsm_state56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state56 : signal is "none";
signal ap_CS_fsm_state61 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state61 : signal is "none";
signal ap_CS_fsm_state66 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state66 : signal is "none";
signal ap_CS_fsm_state71 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state71 : signal is "none";
signal ap_CS_fsm_state76 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
signal ap_CS_fsm_state81 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state81 : signal is "none";
signal ap_CS_fsm_state86 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state86 : signal is "none";
signal ap_CS_fsm_state91 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state91 : signal is "none";
signal ap_CS_fsm_state96 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state96 : signal is "none";
signal ap_CS_fsm_state101 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state101 : signal is "none";
signal ap_CS_fsm_state106 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state106 : signal is "none";
signal ap_CS_fsm_state111 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state111 : signal is "none";
signal ap_CS_fsm_state116 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state116 : signal is "none";
signal ap_CS_fsm_state121 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state121 : signal is "none";
signal ap_CS_fsm_state126 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state126 : signal is "none";
signal ap_CS_fsm_state131 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state131 : signal is "none";
signal grp_fu_535_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_558 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state136 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state136 : signal is "none";
signal tmp_7_cast_fu_586_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_cast_reg_1394 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal to_b_1_fu_596_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal to_b_1_reg_1403 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_1387_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_reg_1408 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_34_fu_618_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_34_reg_1437 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_fu_624_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1443 : STD_LOGIC_VECTOR (0 downto 0);
signal ti_b_1_fu_630_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal ti_b_1_reg_1447 : STD_LOGIC_VECTOR (1 downto 0);
signal bufw_addr_reg_1452 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal bufw_addr_1_reg_1457 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_2_reg_1462 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_3_reg_1467 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_4_reg_1472 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_5_reg_1477 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_6_reg_1482 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_7_reg_1487 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_8_reg_1492 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_9_reg_1497 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_10_reg_1502 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_11_reg_1507 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_12_reg_1512 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_13_reg_1517 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_14_reg_1522 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_15_reg_1527 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_16_reg_1532 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_17_reg_1537 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_18_reg_1542 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_19_reg_1547 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_20_reg_1552 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_21_reg_1557 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_22_reg_1562 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_23_reg_1567 : STD_LOGIC_VECTOR (7 downto 0);
signal bufw_addr_24_reg_1572 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_35_cast_fu_880_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_35_cast_reg_1577 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_37_fu_912_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_reg_1585 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_40_fu_929_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_40_reg_1594 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_1_fu_945_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal row_b_1_reg_1602 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_43_fu_976_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_43_reg_1607 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_fu_939_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_46_fu_1013_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_reg_1616 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_48_fu_1046_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_48_reg_1625 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_1085_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_reg_1634 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal bufi_addr_5_reg_1648 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_addr_10_reg_1653 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_addr_15_reg_1658 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_addr_20_reg_1663 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_reg_1668 : STD_LOGIC_VECTOR (4 downto 0);
signal col_b_cast_fu_1159_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_cast_reg_1673 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_1_fu_1169_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_1_reg_1682 : STD_LOGIC_VECTOR (1 downto 0);
signal bufo_load_reg_1688 : STD_LOGIC_VECTOR (31 downto 0);
signal col_b_1_cast_cast_fu_1175_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal col_b_1_cast_cast_reg_1693 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_2_cast_cast_fu_1193_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_2_cast_cast_reg_1706 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_3_cast_cast_fu_1212_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_3_cast_cast_reg_1719 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_4_cast_cast_fu_1234_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_4_cast_cast_reg_1732 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_62_fu_1338_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_62_reg_1795 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_67_fu_1342_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_67_reg_1800 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_72_fu_1355_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_72_reg_1810 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_fu_1359_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_reg_1815 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1363_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_reg_1820 : STD_LOGIC_VECTOR (8 downto 0);
signal to_b_reg_490 : STD_LOGIC_VECTOR (1 downto 0);
signal ti_b_reg_501 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_fu_590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_b_reg_512 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_5_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_b_reg_523 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state137 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state137 : signal is "none";
signal tmp_9_cast_fu_636_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_10_cast_fu_645_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_11_cast_fu_655_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_cast_fu_665_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_cast_fu_675_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_cast_fu_685_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_15_cast_fu_695_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_16_cast_fu_705_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_17_cast_fu_715_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_cast_fu_725_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_19_cast_fu_735_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_20_cast_fu_745_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_cast_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_22_cast_fu_765_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_23_cast_fu_775_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_cast_fu_785_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_25_cast_fu_795_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_cast_fu_805_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_27_cast_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_28_cast_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_29_cast_fu_835_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_30_cast_fu_845_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_cast_fu_855_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_32_cast_fu_865_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_cast_fu_875_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_54_cast_fu_1104_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_55_cast_fu_1114_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_56_cast_fu_1124_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_57_cast_fu_1134_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_58_cast_fu_1144_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_59_cast_fu_1154_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_cast_fu_1183_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_65_cast_fu_1202_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_70_cast_fu_1221_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_75_cast_fu_1243_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_cast_fu_1252_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_66_cast_fu_1261_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_71_cast_fu_1270_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1279_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_cast_fu_1288_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_67_cast_fu_1297_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_72_cast_fu_1306_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_1315_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_cast_fu_1324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_68_cast_fu_1333_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_73_cast_fu_1350_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_78_cast_fu_1367_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_64_cast_fu_1371_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_69_cast_fu_1375_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_74_cast_fu_1379_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_79_cast_fu_1383_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_535_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state132 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state132 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal ap_CS_fsm_state23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal ap_CS_fsm_state38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state38 : signal is "none";
signal ap_CS_fsm_state43 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state43 : signal is "none";
signal ap_CS_fsm_state48 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state48 : signal is "none";
signal ap_CS_fsm_state53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state53 : signal is "none";
signal ap_CS_fsm_state58 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state58 : signal is "none";
signal ap_CS_fsm_state63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state63 : signal is "none";
signal ap_CS_fsm_state68 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state68 : signal is "none";
signal ap_CS_fsm_state73 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state73 : signal is "none";
signal ap_CS_fsm_state78 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state78 : signal is "none";
signal ap_CS_fsm_state83 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state83 : signal is "none";
signal ap_CS_fsm_state88 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state88 : signal is "none";
signal ap_CS_fsm_state93 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state93 : signal is "none";
signal ap_CS_fsm_state98 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state98 : signal is "none";
signal ap_CS_fsm_state103 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state103 : signal is "none";
signal ap_CS_fsm_state108 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state108 : signal is "none";
signal ap_CS_fsm_state113 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state113 : signal is "none";
signal ap_CS_fsm_state118 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state118 : signal is "none";
signal ap_CS_fsm_state123 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state123 : signal is "none";
signal ap_CS_fsm_state128 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state128 : signal is "none";
signal tmp_2_fu_568_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl_cast_fu_576_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_cast4_cast_fu_564_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_7_fu_580_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_33_fu_606_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl1_cast_fu_614_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_cast3_cast_fu_602_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_fu_640_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_s_fu_640_p2 : signal is "no";
signal tmp_10_fu_650_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_10_fu_650_p2 : signal is "no";
signal tmp_11_fu_660_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_11_fu_660_p2 : signal is "no";
signal tmp_12_fu_670_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_12_fu_670_p2 : signal is "no";
signal tmp_13_fu_680_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_13_fu_680_p2 : signal is "no";
signal tmp_14_fu_690_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_14_fu_690_p2 : signal is "no";
signal tmp_15_fu_700_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_15_fu_700_p2 : signal is "no";
signal tmp_16_fu_710_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_16_fu_710_p2 : signal is "no";
signal tmp_17_fu_720_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_17_fu_720_p2 : signal is "no";
signal tmp_18_fu_730_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_18_fu_730_p2 : signal is "no";
signal tmp_19_fu_740_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_19_fu_740_p2 : signal is "no";
signal tmp_20_fu_750_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_20_fu_750_p2 : signal is "no";
signal tmp_21_fu_760_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_21_fu_760_p2 : signal is "no";
signal tmp_22_fu_770_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_22_fu_770_p2 : signal is "no";
signal tmp_23_fu_780_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_23_fu_780_p2 : signal is "no";
signal tmp_24_fu_790_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_24_fu_790_p2 : signal is "no";
signal tmp_25_fu_800_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_25_fu_800_p2 : signal is "no";
signal tmp_26_fu_810_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_26_fu_810_p2 : signal is "no";
signal tmp_27_fu_820_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_27_fu_820_p2 : signal is "no";
signal tmp_28_fu_830_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_28_fu_830_p2 : signal is "no";
signal tmp_29_fu_840_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_29_fu_840_p2 : signal is "no";
signal tmp_30_fu_850_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_30_fu_850_p2 : signal is "no";
signal tmp_31_fu_860_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_31_fu_860_p2 : signal is "no";
signal tmp_32_fu_870_p2 : STD_LOGIC_VECTOR (8 downto 0);
attribute use_dsp48 of tmp_32_fu_870_p2 : signal is "no";
signal row_b_cast2_cast_fu_887_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_35_fu_891_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_36_fu_900_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl3_cast_fu_904_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_cast_fu_896_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal row_b_cast2_cast1_fu_883_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_38_fu_918_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_39_fu_923_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_1_cast_cast_fu_951_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_41_fu_955_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_42_fu_964_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl7_cast_fu_968_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_42_cast_fu_960_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal row_b_cast_fu_935_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_2_fu_982_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_2_cast_cast_fu_988_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_44_fu_992_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_45_fu_1001_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl6_cast_fu_1005_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_45_cast_fu_997_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_3_fu_1019_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_3_cast_cast_fu_1025_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_47_fu_1029_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl5_cast_fu_1038_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_48_cast_fu_1034_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_s_fu_1052_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_4_cast_cast_fu_1060_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_49_fu_1064_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_50_fu_1073_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl4_cast_fu_1077_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_cast_fu_1069_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal col_b_cast1_cast_fu_1095_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_52_fu_1099_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_fu_1109_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_54_fu_1119_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_55_fu_1129_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_56_fu_1139_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal col_b_cast1_cast8_fu_1091_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_57_fu_1149_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_58_fu_1178_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_2_fu_1188_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_63_fu_1197_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_3_fu_1207_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_68_fu_1216_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_0_s_fu_1226_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_73_fu_1238_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_59_fu_1248_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_fu_1257_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_fu_1266_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_fu_1275_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_60_fu_1284_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_1293_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_1302_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_75_fu_1311_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_61_fu_1320_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_66_fu_1329_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_1346_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_1387_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_1387_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_1387_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (136 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_adEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (4 downto 0);
din1 : IN STD_LOGIC_VECTOR (1 downto 0);
din2 : IN STD_LOGIC_VECTOR (5 downto 0);
dout : OUT STD_LOGIC_VECTOR (8 downto 0) );
end component;
begin
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_535_p0,
din1 => reg_553,
ce => ap_const_logic_1,
dout => grp_fu_535_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_543,
din1 => reg_548,
ce => ap_const_logic_1,
dout => grp_fu_539_p2);
convolve_kernel_adEe_U3 : component convolve_kernel_adEe
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 5,
din1_WIDTH => 2,
din2_WIDTH => 6,
dout_WIDTH => 9)
port map (
din0 => grp_fu_1387_p0,
din1 => grp_fu_1387_p1,
din2 => grp_fu_1387_p2,
dout => grp_fu_1387_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
col_b_reg_523_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_fu_939_p2 = ap_const_lv1_0))) then
col_b_reg_523 <= ap_const_lv2_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state137)) then
col_b_reg_523 <= col_b_1_reg_1682;
end if;
end if;
end process;
row_b_reg_512_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (tmp_1_reg_1443 = ap_const_lv1_0))) then
row_b_reg_512 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_1 = tmp_5_fu_1163_p2))) then
row_b_reg_512 <= row_b_1_reg_1602;
end if;
end if;
end process;
ti_b_reg_501_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_590_p2))) then
ti_b_reg_501 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_fu_939_p2 = ap_const_lv1_1))) then
ti_b_reg_501 <= ti_b_1_reg_1447;
end if;
end if;
end process;
to_b_reg_490_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (tmp_1_reg_1443 = ap_const_lv1_1))) then
to_b_reg_490 <= to_b_1_reg_1403;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
to_b_reg_490 <= ap_const_lv2_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
bufi_addr_10_reg_1653 <= tmp_56_cast_fu_1124_p1(8 - 1 downto 0);
bufi_addr_15_reg_1658 <= tmp_57_cast_fu_1134_p1(8 - 1 downto 0);
bufi_addr_20_reg_1663 <= tmp_58_cast_fu_1144_p1(8 - 1 downto 0);
bufi_addr_5_reg_1648 <= tmp_55_cast_fu_1114_p1(8 - 1 downto 0);
bufo_addr_reg_1668 <= tmp_59_cast_fu_1154_p1(5 - 1 downto 0);
col_b_1_reg_1682 <= col_b_1_fu_1169_p2;
col_b_cast_reg_1673(1 downto 0) <= col_b_cast_fu_1159_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
bufo_load_reg_1688 <= bufo_Dout_A;
col_b_1_cast_cast_reg_1693(1 downto 0) <= col_b_1_cast_cast_fu_1175_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
bufw_addr_10_reg_1502 <= tmp_19_cast_fu_735_p1(8 - 1 downto 0);
bufw_addr_11_reg_1507 <= tmp_20_cast_fu_745_p1(8 - 1 downto 0);
bufw_addr_12_reg_1512 <= tmp_21_cast_fu_755_p1(8 - 1 downto 0);
bufw_addr_13_reg_1517 <= tmp_22_cast_fu_765_p1(8 - 1 downto 0);
bufw_addr_14_reg_1522 <= tmp_23_cast_fu_775_p1(8 - 1 downto 0);
bufw_addr_15_reg_1527 <= tmp_24_cast_fu_785_p1(8 - 1 downto 0);
bufw_addr_16_reg_1532 <= tmp_25_cast_fu_795_p1(8 - 1 downto 0);
bufw_addr_17_reg_1537 <= tmp_26_cast_fu_805_p1(8 - 1 downto 0);
bufw_addr_18_reg_1542 <= tmp_27_cast_fu_815_p1(8 - 1 downto 0);
bufw_addr_19_reg_1547 <= tmp_28_cast_fu_825_p1(8 - 1 downto 0);
bufw_addr_1_reg_1457 <= tmp_10_cast_fu_645_p1(8 - 1 downto 0);
bufw_addr_20_reg_1552 <= tmp_29_cast_fu_835_p1(8 - 1 downto 0);
bufw_addr_21_reg_1557 <= tmp_30_cast_fu_845_p1(8 - 1 downto 0);
bufw_addr_22_reg_1562 <= tmp_31_cast_fu_855_p1(8 - 1 downto 0);
bufw_addr_23_reg_1567 <= tmp_32_cast_fu_865_p1(8 - 1 downto 0);
bufw_addr_24_reg_1572 <= tmp_33_cast_fu_875_p1(8 - 1 downto 0);
bufw_addr_2_reg_1462 <= tmp_11_cast_fu_655_p1(8 - 1 downto 0);
bufw_addr_3_reg_1467 <= tmp_12_cast_fu_665_p1(8 - 1 downto 0);
bufw_addr_4_reg_1472 <= tmp_13_cast_fu_675_p1(8 - 1 downto 0);
bufw_addr_5_reg_1477 <= tmp_14_cast_fu_685_p1(8 - 1 downto 0);
bufw_addr_6_reg_1482 <= tmp_15_cast_fu_695_p1(8 - 1 downto 0);
bufw_addr_7_reg_1487 <= tmp_16_cast_fu_705_p1(8 - 1 downto 0);
bufw_addr_8_reg_1492 <= tmp_17_cast_fu_715_p1(8 - 1 downto 0);
bufw_addr_9_reg_1497 <= tmp_18_cast_fu_725_p1(8 - 1 downto 0);
bufw_addr_reg_1452 <= tmp_9_cast_fu_636_p1(8 - 1 downto 0);
tmp_35_cast_reg_1577 <= tmp_35_cast_fu_880_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state37) or (ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state47) or (ap_const_logic_1 = ap_CS_fsm_state52) or (ap_const_logic_1 = ap_CS_fsm_state57) or (ap_const_logic_1 = ap_CS_fsm_state62) or (ap_const_logic_1 = ap_CS_fsm_state67) or (ap_const_logic_1 = ap_CS_fsm_state72) or (ap_const_logic_1 = ap_CS_fsm_state77) or (ap_const_logic_1 = ap_CS_fsm_state82) or (ap_const_logic_1 = ap_CS_fsm_state87) or (ap_const_logic_1 = ap_CS_fsm_state92) or (ap_const_logic_1 = ap_CS_fsm_state97) or (ap_const_logic_1 = ap_CS_fsm_state102) or (ap_const_logic_1 = ap_CS_fsm_state107) or (ap_const_logic_1 = ap_CS_fsm_state112) or (ap_const_logic_1 = ap_CS_fsm_state117) or (ap_const_logic_1 = ap_CS_fsm_state122) or (ap_const_logic_1 = ap_CS_fsm_state127))) then
reg_543 <= bufw_Dout_A;
reg_548 <= bufi_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state56) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state91) or (ap_const_logic_1 = ap_CS_fsm_state96) or (ap_const_logic_1 = ap_CS_fsm_state101) or (ap_const_logic_1 = ap_CS_fsm_state106) or (ap_const_logic_1 = ap_CS_fsm_state111) or (ap_const_logic_1 = ap_CS_fsm_state116) or (ap_const_logic_1 = ap_CS_fsm_state121) or (ap_const_logic_1 = ap_CS_fsm_state126) or (ap_const_logic_1 = ap_CS_fsm_state131))) then
reg_553 <= grp_fu_539_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state56) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state91) or (ap_const_logic_1 = ap_CS_fsm_state96) or (ap_const_logic_1 = ap_CS_fsm_state101) or (ap_const_logic_1 = ap_CS_fsm_state106) or (ap_const_logic_1 = ap_CS_fsm_state111) or (ap_const_logic_1 = ap_CS_fsm_state116) or (ap_const_logic_1 = ap_CS_fsm_state121) or (ap_const_logic_1 = ap_CS_fsm_state126) or (ap_const_logic_1 = ap_CS_fsm_state131) or (ap_const_logic_1 = ap_CS_fsm_state136))) then
reg_558 <= grp_fu_535_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
row_b_1_reg_1602 <= row_b_1_fu_945_p2;
tmp_37_reg_1585 <= tmp_37_fu_912_p2;
tmp_40_reg_1594 <= tmp_40_fu_929_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
ti_b_1_reg_1447 <= ti_b_1_fu_630_p2;
tmp_1_reg_1443 <= tmp_1_fu_624_p2;
tmp_34_reg_1437 <= tmp_34_fu_618_p2;
tmp_9_reg_1408 <= grp_fu_1387_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
tmp_2_0_2_cast_cast_reg_1706(2 downto 0) <= tmp_2_0_2_cast_cast_fu_1193_p1(2 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state21)) then
tmp_2_0_3_cast_cast_reg_1719(2 downto 0) <= tmp_2_0_3_cast_cast_fu_1212_p1(2 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
tmp_2_0_4_cast_cast_reg_1732(1 downto 0) <= tmp_2_0_4_cast_cast_fu_1234_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_fu_939_p2 = ap_const_lv1_0))) then
tmp_43_reg_1607 <= tmp_43_fu_976_p2;
tmp_46_reg_1616 <= tmp_46_fu_1013_p2;
tmp_48_reg_1625 <= tmp_48_fu_1046_p2;
tmp_51_reg_1634 <= tmp_51_fu_1085_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state96)) then
tmp_62_reg_1795 <= tmp_62_fu_1338_p2;
tmp_67_reg_1800 <= tmp_67_fu_1342_p2;
tmp_72_reg_1810 <= tmp_72_fu_1355_p2;
tmp_76_reg_1815 <= tmp_76_fu_1359_p2;
tmp_77_reg_1820 <= tmp_77_fu_1363_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
tmp_7_cast_reg_1394 <= tmp_7_cast_fu_586_p1;
to_b_1_reg_1403 <= to_b_1_fu_596_p2;
end if;
end if;
end process;
col_b_cast_reg_1673(2) <= '0';
col_b_1_cast_cast_reg_1693(8 downto 2) <= "0000000";
tmp_2_0_2_cast_cast_reg_1706(8 downto 3) <= "000000";
tmp_2_0_3_cast_cast_reg_1719(8 downto 3) <= "000000";
tmp_2_0_4_cast_cast_reg_1732(8 downto 2) <= "0000001";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_1_reg_1443, ap_CS_fsm_state4, ap_CS_fsm_state5, tmp_3_fu_939_p2, ap_CS_fsm_state6, tmp_fu_590_p2, tmp_5_fu_1163_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = tmp_fu_590_p2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (tmp_1_reg_1443 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_fu_939_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_1 = tmp_5_fu_1163_p2))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state39;
when ap_ST_fsm_state39 =>
ap_NS_fsm <= ap_ST_fsm_state40;
when ap_ST_fsm_state40 =>
ap_NS_fsm <= ap_ST_fsm_state41;
when ap_ST_fsm_state41 =>
ap_NS_fsm <= ap_ST_fsm_state42;
when ap_ST_fsm_state42 =>
ap_NS_fsm <= ap_ST_fsm_state43;
when ap_ST_fsm_state43 =>
ap_NS_fsm <= ap_ST_fsm_state44;
when ap_ST_fsm_state44 =>
ap_NS_fsm <= ap_ST_fsm_state45;
when ap_ST_fsm_state45 =>
ap_NS_fsm <= ap_ST_fsm_state46;
when ap_ST_fsm_state46 =>
ap_NS_fsm <= ap_ST_fsm_state47;
when ap_ST_fsm_state47 =>
ap_NS_fsm <= ap_ST_fsm_state48;
when ap_ST_fsm_state48 =>
ap_NS_fsm <= ap_ST_fsm_state49;
when ap_ST_fsm_state49 =>
ap_NS_fsm <= ap_ST_fsm_state50;
when ap_ST_fsm_state50 =>
ap_NS_fsm <= ap_ST_fsm_state51;
when ap_ST_fsm_state51 =>
ap_NS_fsm <= ap_ST_fsm_state52;
when ap_ST_fsm_state52 =>
ap_NS_fsm <= ap_ST_fsm_state53;
when ap_ST_fsm_state53 =>
ap_NS_fsm <= ap_ST_fsm_state54;
when ap_ST_fsm_state54 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when ap_ST_fsm_state55 =>
ap_NS_fsm <= ap_ST_fsm_state56;
when ap_ST_fsm_state56 =>
ap_NS_fsm <= ap_ST_fsm_state57;
when ap_ST_fsm_state57 =>
ap_NS_fsm <= ap_ST_fsm_state58;
when ap_ST_fsm_state58 =>
ap_NS_fsm <= ap_ST_fsm_state59;
when ap_ST_fsm_state59 =>
ap_NS_fsm <= ap_ST_fsm_state60;
when ap_ST_fsm_state60 =>
ap_NS_fsm <= ap_ST_fsm_state61;
when ap_ST_fsm_state61 =>
ap_NS_fsm <= ap_ST_fsm_state62;
when ap_ST_fsm_state62 =>
ap_NS_fsm <= ap_ST_fsm_state63;
when ap_ST_fsm_state63 =>
ap_NS_fsm <= ap_ST_fsm_state64;
when ap_ST_fsm_state64 =>
ap_NS_fsm <= ap_ST_fsm_state65;
when ap_ST_fsm_state65 =>
ap_NS_fsm <= ap_ST_fsm_state66;
when ap_ST_fsm_state66 =>
ap_NS_fsm <= ap_ST_fsm_state67;
when ap_ST_fsm_state67 =>
ap_NS_fsm <= ap_ST_fsm_state68;
when ap_ST_fsm_state68 =>
ap_NS_fsm <= ap_ST_fsm_state69;
when ap_ST_fsm_state69 =>
ap_NS_fsm <= ap_ST_fsm_state70;
when ap_ST_fsm_state70 =>
ap_NS_fsm <= ap_ST_fsm_state71;
when ap_ST_fsm_state71 =>
ap_NS_fsm <= ap_ST_fsm_state72;
when ap_ST_fsm_state72 =>
ap_NS_fsm <= ap_ST_fsm_state73;
when ap_ST_fsm_state73 =>
ap_NS_fsm <= ap_ST_fsm_state74;
when ap_ST_fsm_state74 =>
ap_NS_fsm <= ap_ST_fsm_state75;
when ap_ST_fsm_state75 =>
ap_NS_fsm <= ap_ST_fsm_state76;
when ap_ST_fsm_state76 =>
ap_NS_fsm <= ap_ST_fsm_state77;
when ap_ST_fsm_state77 =>
ap_NS_fsm <= ap_ST_fsm_state78;
when ap_ST_fsm_state78 =>
ap_NS_fsm <= ap_ST_fsm_state79;
when ap_ST_fsm_state79 =>
ap_NS_fsm <= ap_ST_fsm_state80;
when ap_ST_fsm_state80 =>
ap_NS_fsm <= ap_ST_fsm_state81;
when ap_ST_fsm_state81 =>
ap_NS_fsm <= ap_ST_fsm_state82;
when ap_ST_fsm_state82 =>
ap_NS_fsm <= ap_ST_fsm_state83;
when ap_ST_fsm_state83 =>
ap_NS_fsm <= ap_ST_fsm_state84;
when ap_ST_fsm_state84 =>
ap_NS_fsm <= ap_ST_fsm_state85;
when ap_ST_fsm_state85 =>
ap_NS_fsm <= ap_ST_fsm_state86;
when ap_ST_fsm_state86 =>
ap_NS_fsm <= ap_ST_fsm_state87;
when ap_ST_fsm_state87 =>
ap_NS_fsm <= ap_ST_fsm_state88;
when ap_ST_fsm_state88 =>
ap_NS_fsm <= ap_ST_fsm_state89;
when ap_ST_fsm_state89 =>
ap_NS_fsm <= ap_ST_fsm_state90;
when ap_ST_fsm_state90 =>
ap_NS_fsm <= ap_ST_fsm_state91;
when ap_ST_fsm_state91 =>
ap_NS_fsm <= ap_ST_fsm_state92;
when ap_ST_fsm_state92 =>
ap_NS_fsm <= ap_ST_fsm_state93;
when ap_ST_fsm_state93 =>
ap_NS_fsm <= ap_ST_fsm_state94;
when ap_ST_fsm_state94 =>
ap_NS_fsm <= ap_ST_fsm_state95;
when ap_ST_fsm_state95 =>
ap_NS_fsm <= ap_ST_fsm_state96;
when ap_ST_fsm_state96 =>
ap_NS_fsm <= ap_ST_fsm_state97;
when ap_ST_fsm_state97 =>
ap_NS_fsm <= ap_ST_fsm_state98;
when ap_ST_fsm_state98 =>
ap_NS_fsm <= ap_ST_fsm_state99;
when ap_ST_fsm_state99 =>
ap_NS_fsm <= ap_ST_fsm_state100;
when ap_ST_fsm_state100 =>
ap_NS_fsm <= ap_ST_fsm_state101;
when ap_ST_fsm_state101 =>
ap_NS_fsm <= ap_ST_fsm_state102;
when ap_ST_fsm_state102 =>
ap_NS_fsm <= ap_ST_fsm_state103;
when ap_ST_fsm_state103 =>
ap_NS_fsm <= ap_ST_fsm_state104;
when ap_ST_fsm_state104 =>
ap_NS_fsm <= ap_ST_fsm_state105;
when ap_ST_fsm_state105 =>
ap_NS_fsm <= ap_ST_fsm_state106;
when ap_ST_fsm_state106 =>
ap_NS_fsm <= ap_ST_fsm_state107;
when ap_ST_fsm_state107 =>
ap_NS_fsm <= ap_ST_fsm_state108;
when ap_ST_fsm_state108 =>
ap_NS_fsm <= ap_ST_fsm_state109;
when ap_ST_fsm_state109 =>
ap_NS_fsm <= ap_ST_fsm_state110;
when ap_ST_fsm_state110 =>
ap_NS_fsm <= ap_ST_fsm_state111;
when ap_ST_fsm_state111 =>
ap_NS_fsm <= ap_ST_fsm_state112;
when ap_ST_fsm_state112 =>
ap_NS_fsm <= ap_ST_fsm_state113;
when ap_ST_fsm_state113 =>
ap_NS_fsm <= ap_ST_fsm_state114;
when ap_ST_fsm_state114 =>
ap_NS_fsm <= ap_ST_fsm_state115;
when ap_ST_fsm_state115 =>
ap_NS_fsm <= ap_ST_fsm_state116;
when ap_ST_fsm_state116 =>
ap_NS_fsm <= ap_ST_fsm_state117;
when ap_ST_fsm_state117 =>
ap_NS_fsm <= ap_ST_fsm_state118;
when ap_ST_fsm_state118 =>
ap_NS_fsm <= ap_ST_fsm_state119;
when ap_ST_fsm_state119 =>
ap_NS_fsm <= ap_ST_fsm_state120;
when ap_ST_fsm_state120 =>
ap_NS_fsm <= ap_ST_fsm_state121;
when ap_ST_fsm_state121 =>
ap_NS_fsm <= ap_ST_fsm_state122;
when ap_ST_fsm_state122 =>
ap_NS_fsm <= ap_ST_fsm_state123;
when ap_ST_fsm_state123 =>
ap_NS_fsm <= ap_ST_fsm_state124;
when ap_ST_fsm_state124 =>
ap_NS_fsm <= ap_ST_fsm_state125;
when ap_ST_fsm_state125 =>
ap_NS_fsm <= ap_ST_fsm_state126;
when ap_ST_fsm_state126 =>
ap_NS_fsm <= ap_ST_fsm_state127;
when ap_ST_fsm_state127 =>
ap_NS_fsm <= ap_ST_fsm_state128;
when ap_ST_fsm_state128 =>
ap_NS_fsm <= ap_ST_fsm_state129;
when ap_ST_fsm_state129 =>
ap_NS_fsm <= ap_ST_fsm_state130;
when ap_ST_fsm_state130 =>
ap_NS_fsm <= ap_ST_fsm_state131;
when ap_ST_fsm_state131 =>
ap_NS_fsm <= ap_ST_fsm_state132;
when ap_ST_fsm_state132 =>
ap_NS_fsm <= ap_ST_fsm_state133;
when ap_ST_fsm_state133 =>
ap_NS_fsm <= ap_ST_fsm_state134;
when ap_ST_fsm_state134 =>
ap_NS_fsm <= ap_ST_fsm_state135;
when ap_ST_fsm_state135 =>
ap_NS_fsm <= ap_ST_fsm_state136;
when ap_ST_fsm_state136 =>
ap_NS_fsm <= ap_ST_fsm_state137;
when ap_ST_fsm_state137 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state101 <= ap_CS_fsm(100);
ap_CS_fsm_state102 <= ap_CS_fsm(101);
ap_CS_fsm_state103 <= ap_CS_fsm(102);
ap_CS_fsm_state106 <= ap_CS_fsm(105);
ap_CS_fsm_state107 <= ap_CS_fsm(106);
ap_CS_fsm_state108 <= ap_CS_fsm(107);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state111 <= ap_CS_fsm(110);
ap_CS_fsm_state112 <= ap_CS_fsm(111);
ap_CS_fsm_state113 <= ap_CS_fsm(112);
ap_CS_fsm_state116 <= ap_CS_fsm(115);
ap_CS_fsm_state117 <= ap_CS_fsm(116);
ap_CS_fsm_state118 <= ap_CS_fsm(117);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state121 <= ap_CS_fsm(120);
ap_CS_fsm_state122 <= ap_CS_fsm(121);
ap_CS_fsm_state123 <= ap_CS_fsm(122);
ap_CS_fsm_state126 <= ap_CS_fsm(125);
ap_CS_fsm_state127 <= ap_CS_fsm(126);
ap_CS_fsm_state128 <= ap_CS_fsm(127);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state131 <= ap_CS_fsm(130);
ap_CS_fsm_state132 <= ap_CS_fsm(131);
ap_CS_fsm_state136 <= ap_CS_fsm(135);
ap_CS_fsm_state137 <= ap_CS_fsm(136);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state21 <= ap_CS_fsm(20);
ap_CS_fsm_state22 <= ap_CS_fsm(21);
ap_CS_fsm_state23 <= ap_CS_fsm(22);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state28 <= ap_CS_fsm(27);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state31 <= ap_CS_fsm(30);
ap_CS_fsm_state32 <= ap_CS_fsm(31);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state36 <= ap_CS_fsm(35);
ap_CS_fsm_state37 <= ap_CS_fsm(36);
ap_CS_fsm_state38 <= ap_CS_fsm(37);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state41 <= ap_CS_fsm(40);
ap_CS_fsm_state42 <= ap_CS_fsm(41);
ap_CS_fsm_state43 <= ap_CS_fsm(42);
ap_CS_fsm_state46 <= ap_CS_fsm(45);
ap_CS_fsm_state47 <= ap_CS_fsm(46);
ap_CS_fsm_state48 <= ap_CS_fsm(47);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state51 <= ap_CS_fsm(50);
ap_CS_fsm_state52 <= ap_CS_fsm(51);
ap_CS_fsm_state53 <= ap_CS_fsm(52);
ap_CS_fsm_state56 <= ap_CS_fsm(55);
ap_CS_fsm_state57 <= ap_CS_fsm(56);
ap_CS_fsm_state58 <= ap_CS_fsm(57);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state61 <= ap_CS_fsm(60);
ap_CS_fsm_state62 <= ap_CS_fsm(61);
ap_CS_fsm_state63 <= ap_CS_fsm(62);
ap_CS_fsm_state66 <= ap_CS_fsm(65);
ap_CS_fsm_state67 <= ap_CS_fsm(66);
ap_CS_fsm_state68 <= ap_CS_fsm(67);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state71 <= ap_CS_fsm(70);
ap_CS_fsm_state72 <= ap_CS_fsm(71);
ap_CS_fsm_state73 <= ap_CS_fsm(72);
ap_CS_fsm_state76 <= ap_CS_fsm(75);
ap_CS_fsm_state77 <= ap_CS_fsm(76);
ap_CS_fsm_state78 <= ap_CS_fsm(77);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state81 <= ap_CS_fsm(80);
ap_CS_fsm_state82 <= ap_CS_fsm(81);
ap_CS_fsm_state83 <= ap_CS_fsm(82);
ap_CS_fsm_state86 <= ap_CS_fsm(85);
ap_CS_fsm_state87 <= ap_CS_fsm(86);
ap_CS_fsm_state88 <= ap_CS_fsm(87);
ap_CS_fsm_state91 <= ap_CS_fsm(90);
ap_CS_fsm_state92 <= ap_CS_fsm(91);
ap_CS_fsm_state93 <= ap_CS_fsm(92);
ap_CS_fsm_state96 <= ap_CS_fsm(95);
ap_CS_fsm_state97 <= ap_CS_fsm(96);
ap_CS_fsm_state98 <= ap_CS_fsm(97);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_590_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = tmp_fu_590_p2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_590_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = tmp_fu_590_p2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_Addr_A_orig_assign_proc : process(ap_CS_fsm_state11, ap_CS_fsm_state16, ap_CS_fsm_state21, ap_CS_fsm_state26, ap_CS_fsm_state31, ap_CS_fsm_state36, ap_CS_fsm_state41, ap_CS_fsm_state46, ap_CS_fsm_state51, ap_CS_fsm_state56, ap_CS_fsm_state61, ap_CS_fsm_state66, ap_CS_fsm_state71, ap_CS_fsm_state76, ap_CS_fsm_state81, ap_CS_fsm_state86, ap_CS_fsm_state91, ap_CS_fsm_state96, ap_CS_fsm_state101, ap_CS_fsm_state106, ap_CS_fsm_state111, ap_CS_fsm_state116, ap_CS_fsm_state121, ap_CS_fsm_state126, ap_CS_fsm_state6, bufi_addr_5_reg_1648, bufi_addr_10_reg_1653, bufi_addr_15_reg_1658, bufi_addr_20_reg_1663, tmp_54_cast_fu_1104_p1, tmp_60_cast_fu_1183_p1, tmp_65_cast_fu_1202_p1, tmp_70_cast_fu_1221_p1, tmp_75_cast_fu_1243_p1, tmp_61_cast_fu_1252_p1, tmp_66_cast_fu_1261_p1, tmp_71_cast_fu_1270_p1, tmp_76_cast_fu_1279_p1, tmp_62_cast_fu_1288_p1, tmp_67_cast_fu_1297_p1, tmp_72_cast_fu_1306_p1, tmp_77_cast_fu_1315_p1, tmp_63_cast_fu_1324_p1, tmp_68_cast_fu_1333_p1, tmp_73_cast_fu_1350_p1, tmp_78_cast_fu_1367_p1, tmp_64_cast_fu_1371_p1, tmp_69_cast_fu_1375_p1, tmp_74_cast_fu_1379_p1, tmp_79_cast_fu_1383_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state126)) then
bufi_Addr_A_orig <= tmp_79_cast_fu_1383_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state121)) then
bufi_Addr_A_orig <= tmp_74_cast_fu_1379_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state116)) then
bufi_Addr_A_orig <= tmp_69_cast_fu_1375_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state111)) then
bufi_Addr_A_orig <= tmp_64_cast_fu_1371_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state106)) then
bufi_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufi_addr_20_reg_1663),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state101)) then
bufi_Addr_A_orig <= tmp_78_cast_fu_1367_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state96)) then
bufi_Addr_A_orig <= tmp_73_cast_fu_1350_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state91)) then
bufi_Addr_A_orig <= tmp_68_cast_fu_1333_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state86)) then
bufi_Addr_A_orig <= tmp_63_cast_fu_1324_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state81)) then
bufi_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufi_addr_15_reg_1658),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state76)) then
bufi_Addr_A_orig <= tmp_77_cast_fu_1315_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state71)) then
bufi_Addr_A_orig <= tmp_72_cast_fu_1306_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state66)) then
bufi_Addr_A_orig <= tmp_67_cast_fu_1297_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state61)) then
bufi_Addr_A_orig <= tmp_62_cast_fu_1288_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state56)) then
bufi_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufi_addr_10_reg_1653),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state51)) then
bufi_Addr_A_orig <= tmp_76_cast_fu_1279_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state46)) then
bufi_Addr_A_orig <= tmp_71_cast_fu_1270_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state41)) then
bufi_Addr_A_orig <= tmp_66_cast_fu_1261_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then
bufi_Addr_A_orig <= tmp_61_cast_fu_1252_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
bufi_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufi_addr_5_reg_1648),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
bufi_Addr_A_orig <= tmp_75_cast_fu_1243_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
bufi_Addr_A_orig <= tmp_70_cast_fu_1221_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
bufi_Addr_A_orig <= tmp_65_cast_fu_1202_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
bufi_Addr_A_orig <= tmp_60_cast_fu_1183_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
bufi_Addr_A_orig <= tmp_54_cast_fu_1104_p1(32 - 1 downto 0);
else
bufi_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv32_0;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state11, ap_CS_fsm_state16, ap_CS_fsm_state21, ap_CS_fsm_state26, ap_CS_fsm_state31, ap_CS_fsm_state36, ap_CS_fsm_state41, ap_CS_fsm_state46, ap_CS_fsm_state51, ap_CS_fsm_state56, ap_CS_fsm_state61, ap_CS_fsm_state66, ap_CS_fsm_state71, ap_CS_fsm_state76, ap_CS_fsm_state81, ap_CS_fsm_state86, ap_CS_fsm_state91, ap_CS_fsm_state96, ap_CS_fsm_state101, ap_CS_fsm_state106, ap_CS_fsm_state111, ap_CS_fsm_state116, ap_CS_fsm_state121, ap_CS_fsm_state126, ap_CS_fsm_state6)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state56) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state91) or (ap_const_logic_1 = ap_CS_fsm_state96) or (ap_const_logic_1 = ap_CS_fsm_state101) or (ap_const_logic_1 = ap_CS_fsm_state106) or (ap_const_logic_1 = ap_CS_fsm_state111) or (ap_const_logic_1 = ap_CS_fsm_state116) or (ap_const_logic_1 = ap_CS_fsm_state121) or (ap_const_logic_1 = ap_CS_fsm_state126) or (ap_const_logic_1 = ap_CS_fsm_state6))) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst;
bufi_WEN_A <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_1668),32));
bufo_Clk_A <= ap_clk;
bufo_Din_A <= reg_558;
bufo_EN_A_assign_proc : process(ap_CS_fsm_state137, ap_CS_fsm_state10)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state137) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_state137)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state137)) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_Addr_A_orig_assign_proc : process(ap_CS_fsm_state11, ap_CS_fsm_state16, ap_CS_fsm_state21, ap_CS_fsm_state26, ap_CS_fsm_state31, ap_CS_fsm_state36, ap_CS_fsm_state41, ap_CS_fsm_state46, ap_CS_fsm_state51, ap_CS_fsm_state56, ap_CS_fsm_state61, ap_CS_fsm_state66, ap_CS_fsm_state71, ap_CS_fsm_state76, ap_CS_fsm_state81, ap_CS_fsm_state86, ap_CS_fsm_state91, ap_CS_fsm_state96, ap_CS_fsm_state101, ap_CS_fsm_state106, ap_CS_fsm_state111, ap_CS_fsm_state116, ap_CS_fsm_state121, ap_CS_fsm_state126, bufw_addr_reg_1452, bufw_addr_1_reg_1457, bufw_addr_2_reg_1462, bufw_addr_3_reg_1467, bufw_addr_4_reg_1472, bufw_addr_5_reg_1477, bufw_addr_6_reg_1482, bufw_addr_7_reg_1487, bufw_addr_8_reg_1492, bufw_addr_9_reg_1497, bufw_addr_10_reg_1502, bufw_addr_11_reg_1507, bufw_addr_12_reg_1512, bufw_addr_13_reg_1517, bufw_addr_14_reg_1522, bufw_addr_15_reg_1527, bufw_addr_16_reg_1532, bufw_addr_17_reg_1537, bufw_addr_18_reg_1542, bufw_addr_19_reg_1547, bufw_addr_20_reg_1552, bufw_addr_21_reg_1557, bufw_addr_22_reg_1562, bufw_addr_23_reg_1567, bufw_addr_24_reg_1572, ap_CS_fsm_state6)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state126)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_24_reg_1572),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state121)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_23_reg_1567),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state116)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_22_reg_1562),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state111)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_21_reg_1557),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state106)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_20_reg_1552),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state101)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_19_reg_1547),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state96)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_18_reg_1542),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state91)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_17_reg_1537),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state86)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_16_reg_1532),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state81)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_15_reg_1527),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state76)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_14_reg_1522),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state71)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_13_reg_1517),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state66)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_12_reg_1512),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state61)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_11_reg_1507),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state56)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_10_reg_1502),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state51)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_9_reg_1497),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state46)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_8_reg_1492),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state41)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_7_reg_1487),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_6_reg_1482),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_5_reg_1477),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_4_reg_1472),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_3_reg_1467),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_2_reg_1462),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_1_reg_1457),32));
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_reg_1452),32));
else
bufw_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv32_0;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state11, ap_CS_fsm_state16, ap_CS_fsm_state21, ap_CS_fsm_state26, ap_CS_fsm_state31, ap_CS_fsm_state36, ap_CS_fsm_state41, ap_CS_fsm_state46, ap_CS_fsm_state51, ap_CS_fsm_state56, ap_CS_fsm_state61, ap_CS_fsm_state66, ap_CS_fsm_state71, ap_CS_fsm_state76, ap_CS_fsm_state81, ap_CS_fsm_state86, ap_CS_fsm_state91, ap_CS_fsm_state96, ap_CS_fsm_state101, ap_CS_fsm_state106, ap_CS_fsm_state111, ap_CS_fsm_state116, ap_CS_fsm_state121, ap_CS_fsm_state126, ap_CS_fsm_state6)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state56) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state91) or (ap_const_logic_1 = ap_CS_fsm_state96) or (ap_const_logic_1 = ap_CS_fsm_state101) or (ap_const_logic_1 = ap_CS_fsm_state106) or (ap_const_logic_1 = ap_CS_fsm_state111) or (ap_const_logic_1 = ap_CS_fsm_state116) or (ap_const_logic_1 = ap_CS_fsm_state121) or (ap_const_logic_1 = ap_CS_fsm_state126) or (ap_const_logic_1 = ap_CS_fsm_state6))) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst;
bufw_WEN_A <= ap_const_lv4_0;
col_b_1_cast_cast_fu_1175_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_1_reg_1682),9));
col_b_1_fu_1169_p2 <= std_logic_vector(unsigned(col_b_reg_523) + unsigned(ap_const_lv2_1));
col_b_cast1_cast8_fu_1091_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_523),6));
col_b_cast1_cast_fu_1095_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_523),9));
col_b_cast_fu_1159_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_523),3));
grp_fu_1387_p0 <= tmp_7_cast_reg_1394(5 - 1 downto 0);
grp_fu_1387_p1 <= ti_b_cast3_cast_fu_602_p1(2 - 1 downto 0);
grp_fu_1387_p2 <= ap_const_lv9_19(6 - 1 downto 0);
grp_fu_535_p0_assign_proc : process(ap_CS_fsm_state12, ap_CS_fsm_state17, ap_CS_fsm_state22, ap_CS_fsm_state27, ap_CS_fsm_state32, ap_CS_fsm_state37, ap_CS_fsm_state42, ap_CS_fsm_state47, ap_CS_fsm_state52, ap_CS_fsm_state57, ap_CS_fsm_state62, ap_CS_fsm_state67, ap_CS_fsm_state72, ap_CS_fsm_state77, ap_CS_fsm_state82, ap_CS_fsm_state87, ap_CS_fsm_state92, ap_CS_fsm_state97, ap_CS_fsm_state102, ap_CS_fsm_state107, ap_CS_fsm_state112, ap_CS_fsm_state117, ap_CS_fsm_state122, ap_CS_fsm_state127, reg_558, bufo_load_reg_1688, ap_CS_fsm_state132)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state37) or (ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state47) or (ap_const_logic_1 = ap_CS_fsm_state52) or (ap_const_logic_1 = ap_CS_fsm_state57) or (ap_const_logic_1 = ap_CS_fsm_state62) or (ap_const_logic_1 = ap_CS_fsm_state67) or (ap_const_logic_1 = ap_CS_fsm_state72) or (ap_const_logic_1 = ap_CS_fsm_state77) or (ap_const_logic_1 = ap_CS_fsm_state82) or (ap_const_logic_1 = ap_CS_fsm_state87) or (ap_const_logic_1 = ap_CS_fsm_state92) or (ap_const_logic_1 = ap_CS_fsm_state97) or (ap_const_logic_1 = ap_CS_fsm_state102) or (ap_const_logic_1 = ap_CS_fsm_state107) or (ap_const_logic_1 = ap_CS_fsm_state112) or (ap_const_logic_1 = ap_CS_fsm_state117) or (ap_const_logic_1 = ap_CS_fsm_state122) or (ap_const_logic_1 = ap_CS_fsm_state127) or (ap_const_logic_1 = ap_CS_fsm_state132))) then
grp_fu_535_p0 <= reg_558;
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
grp_fu_535_p0 <= bufo_load_reg_1688;
else
grp_fu_535_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_shl1_cast_fu_614_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_fu_606_p3),6));
p_shl3_cast_fu_904_p3 <= (tmp_36_fu_900_p1 & ap_const_lv3_0);
p_shl4_cast_fu_1077_p3 <= (tmp_50_fu_1073_p1 & ap_const_lv3_0);
p_shl5_cast_fu_1038_p3 <= (tmp_47_fu_1029_p2 & ap_const_lv3_0);
p_shl6_cast_fu_1005_p3 <= (tmp_45_fu_1001_p1 & ap_const_lv3_0);
p_shl7_cast_fu_968_p3 <= (tmp_42_fu_964_p1 & ap_const_lv3_0);
p_shl_cast_fu_576_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_fu_568_p3),5));
row_b_1_fu_945_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(row_b_reg_512));
row_b_cast2_cast1_fu_883_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_512),6));
row_b_cast2_cast_fu_887_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_512),7));
row_b_cast_fu_935_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_512),3));
ti_b_1_fu_630_p2 <= std_logic_vector(unsigned(ti_b_reg_501) + unsigned(ap_const_lv2_1));
ti_b_cast3_cast_fu_602_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ti_b_reg_501),6));
tmp_10_cast_fu_645_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_s_fu_640_p2),64));
tmp_10_fu_650_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_2));
tmp_11_cast_fu_655_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_10_fu_650_p2),64));
tmp_11_fu_660_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_3));
tmp_12_cast_fu_665_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_11_fu_660_p2),64));
tmp_12_fu_670_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_4));
tmp_13_cast_fu_675_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_12_fu_670_p2),64));
tmp_13_fu_680_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_5));
tmp_14_cast_fu_685_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_fu_680_p2),64));
tmp_14_fu_690_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_6));
tmp_15_cast_fu_695_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_14_fu_690_p2),64));
tmp_15_fu_700_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_7));
tmp_16_cast_fu_705_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_15_fu_700_p2),64));
tmp_16_fu_710_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_8));
tmp_17_cast_fu_715_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_fu_710_p2),64));
tmp_17_fu_720_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_9));
tmp_18_cast_fu_725_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_17_fu_720_p2),64));
tmp_18_fu_730_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_A));
tmp_19_cast_fu_735_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_18_fu_730_p2),64));
tmp_19_fu_740_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_B));
tmp_1_fu_624_p2 <= "1" when (ti_b_reg_501 = ap_const_lv2_3) else "0";
tmp_20_cast_fu_745_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_19_fu_740_p2),64));
tmp_20_fu_750_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_C));
tmp_21_cast_fu_755_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_20_fu_750_p2),64));
tmp_21_fu_760_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_D));
tmp_22_cast_fu_765_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_21_fu_760_p2),64));
tmp_22_fu_770_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_E));
tmp_23_cast_fu_775_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_22_fu_770_p2),64));
tmp_23_fu_780_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_F));
tmp_24_cast_fu_785_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_23_fu_780_p2),64));
tmp_24_fu_790_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_10));
tmp_25_cast_fu_795_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_24_fu_790_p2),64));
tmp_25_fu_800_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_11));
tmp_26_cast_fu_805_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_25_fu_800_p2),64));
tmp_26_fu_810_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_12));
tmp_27_cast_fu_815_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_26_fu_810_p2),64));
tmp_27_fu_820_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_13));
tmp_28_cast_fu_825_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_27_fu_820_p2),64));
tmp_28_fu_830_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_14));
tmp_29_cast_fu_835_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_28_fu_830_p2),64));
tmp_29_fu_840_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_15));
tmp_2_0_2_cast_cast_fu_1193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_0_2_fu_1188_p2),9));
tmp_2_0_2_fu_1188_p2 <= std_logic_vector(unsigned(col_b_cast_reg_1673) + unsigned(ap_const_lv3_2));
tmp_2_0_3_cast_cast_fu_1212_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_0_3_fu_1207_p2),9));
tmp_2_0_3_fu_1207_p2 <= std_logic_vector(unsigned(col_b_cast_reg_1673) + unsigned(ap_const_lv3_3));
tmp_2_0_4_cast_cast_fu_1234_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_0_s_fu_1226_p3),9));
tmp_2_0_s_fu_1226_p3 <= (ap_const_lv1_1 & col_b_reg_523);
tmp_2_fu_568_p3 <= (to_b_reg_490 & ap_const_lv2_0);
tmp_30_cast_fu_845_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_29_fu_840_p2),64));
tmp_30_fu_850_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_16));
tmp_31_cast_fu_855_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_30_fu_850_p2),64));
tmp_31_fu_860_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_17));
tmp_32_cast_fu_865_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_31_fu_860_p2),64));
tmp_32_fu_870_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_18));
tmp_33_cast_fu_875_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_32_fu_870_p2),64));
tmp_33_fu_606_p3 <= (ti_b_reg_501 & ap_const_lv3_0);
tmp_34_fu_618_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_614_p1) - unsigned(ti_b_cast3_cast_fu_602_p1));
tmp_35_cast_fu_880_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_34_reg_1437),7));
tmp_35_fu_891_p2 <= std_logic_vector(unsigned(row_b_cast2_cast_fu_887_p1) + unsigned(tmp_35_cast_reg_1577));
tmp_36_cast_fu_896_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_35_fu_891_p2),9));
tmp_36_fu_900_p1 <= tmp_35_fu_891_p2(6 - 1 downto 0);
tmp_37_fu_912_p2 <= std_logic_vector(unsigned(p_shl3_cast_fu_904_p3) - unsigned(tmp_36_cast_fu_896_p1));
tmp_38_fu_918_p2 <= std_logic_vector(unsigned(row_b_cast2_cast1_fu_883_p1) + unsigned(tmp_7_cast_reg_1394));
tmp_39_fu_923_p2 <= std_logic_vector(shift_left(unsigned(tmp_38_fu_918_p2),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0)))));
tmp_3_fu_939_p2 <= "1" when (row_b_reg_512 = ap_const_lv2_3) else "0";
tmp_40_fu_929_p2 <= std_logic_vector(unsigned(tmp_39_fu_923_p2) - unsigned(tmp_38_fu_918_p2));
tmp_41_fu_955_p2 <= std_logic_vector(unsigned(tmp_9_1_cast_cast_fu_951_p1) + unsigned(tmp_35_cast_reg_1577));
tmp_42_cast_fu_960_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_41_fu_955_p2),9));
tmp_42_fu_964_p1 <= tmp_41_fu_955_p2(6 - 1 downto 0);
tmp_43_fu_976_p2 <= std_logic_vector(unsigned(p_shl7_cast_fu_968_p3) - unsigned(tmp_42_cast_fu_960_p1));
tmp_44_fu_992_p2 <= std_logic_vector(unsigned(tmp_9_2_cast_cast_fu_988_p1) + unsigned(tmp_35_cast_reg_1577));
tmp_45_cast_fu_997_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_44_fu_992_p2),9));
tmp_45_fu_1001_p1 <= tmp_44_fu_992_p2(6 - 1 downto 0);
tmp_46_fu_1013_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_1005_p3) - unsigned(tmp_45_cast_fu_997_p1));
tmp_47_fu_1029_p2 <= std_logic_vector(unsigned(tmp_9_3_cast_cast_fu_1025_p1) + unsigned(tmp_34_reg_1437));
tmp_48_cast_fu_1034_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_fu_1029_p2),9));
tmp_48_fu_1046_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_1038_p3) - unsigned(tmp_48_cast_fu_1034_p1));
tmp_49_fu_1064_p2 <= std_logic_vector(unsigned(tmp_9_4_cast_cast_fu_1060_p1) + unsigned(tmp_35_cast_reg_1577));
tmp_50_fu_1073_p1 <= tmp_49_fu_1064_p2(6 - 1 downto 0);
tmp_51_cast_fu_1069_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_49_fu_1064_p2),9));
tmp_51_fu_1085_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_1077_p3) - unsigned(tmp_51_cast_fu_1069_p1));
tmp_52_fu_1099_p2 <= std_logic_vector(unsigned(tmp_37_reg_1585) + unsigned(col_b_cast1_cast_fu_1095_p1));
tmp_53_fu_1109_p2 <= std_logic_vector(unsigned(tmp_43_reg_1607) + unsigned(col_b_cast1_cast_fu_1095_p1));
tmp_54_cast_fu_1104_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_52_fu_1099_p2),64));
tmp_54_fu_1119_p2 <= std_logic_vector(unsigned(tmp_46_reg_1616) + unsigned(col_b_cast1_cast_fu_1095_p1));
tmp_55_cast_fu_1114_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_53_fu_1109_p2),64));
tmp_55_fu_1129_p2 <= std_logic_vector(unsigned(tmp_48_reg_1625) + unsigned(col_b_cast1_cast_fu_1095_p1));
tmp_56_cast_fu_1124_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_54_fu_1119_p2),64));
tmp_56_fu_1139_p2 <= std_logic_vector(unsigned(tmp_51_reg_1634) + unsigned(col_b_cast1_cast_fu_1095_p1));
tmp_57_cast_fu_1134_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_fu_1129_p2),64));
tmp_57_fu_1149_p2 <= std_logic_vector(unsigned(tmp_40_reg_1594) + unsigned(col_b_cast1_cast8_fu_1091_p1));
tmp_58_cast_fu_1144_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_56_fu_1139_p2),64));
tmp_58_fu_1178_p2 <= std_logic_vector(unsigned(tmp_37_reg_1585) + unsigned(col_b_1_cast_cast_fu_1175_p1));
tmp_59_cast_fu_1154_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_57_fu_1149_p2),64));
tmp_59_fu_1248_p2 <= std_logic_vector(unsigned(tmp_43_reg_1607) + unsigned(col_b_1_cast_cast_reg_1693));
tmp_5_fu_1163_p2 <= "1" when (col_b_reg_523 = ap_const_lv2_3) else "0";
tmp_60_cast_fu_1183_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_58_fu_1178_p2),64));
tmp_60_fu_1284_p2 <= std_logic_vector(unsigned(tmp_46_reg_1616) + unsigned(col_b_1_cast_cast_reg_1693));
tmp_61_cast_fu_1252_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_59_fu_1248_p2),64));
tmp_61_fu_1320_p2 <= std_logic_vector(unsigned(tmp_48_reg_1625) + unsigned(col_b_1_cast_cast_reg_1693));
tmp_62_cast_fu_1288_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_60_fu_1284_p2),64));
tmp_62_fu_1338_p2 <= std_logic_vector(unsigned(tmp_51_reg_1634) + unsigned(col_b_1_cast_cast_reg_1693));
tmp_63_cast_fu_1324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_61_fu_1320_p2),64));
tmp_63_fu_1197_p2 <= std_logic_vector(unsigned(tmp_37_reg_1585) + unsigned(tmp_2_0_2_cast_cast_fu_1193_p1));
tmp_64_cast_fu_1371_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_62_reg_1795),64));
tmp_64_fu_1257_p2 <= std_logic_vector(unsigned(tmp_43_reg_1607) + unsigned(tmp_2_0_2_cast_cast_reg_1706));
tmp_65_cast_fu_1202_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_63_fu_1197_p2),64));
tmp_65_fu_1293_p2 <= std_logic_vector(unsigned(tmp_46_reg_1616) + unsigned(tmp_2_0_2_cast_cast_reg_1706));
tmp_66_cast_fu_1261_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_64_fu_1257_p2),64));
tmp_66_fu_1329_p2 <= std_logic_vector(unsigned(tmp_48_reg_1625) + unsigned(tmp_2_0_2_cast_cast_reg_1706));
tmp_67_cast_fu_1297_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_65_fu_1293_p2),64));
tmp_67_fu_1342_p2 <= std_logic_vector(unsigned(tmp_51_reg_1634) + unsigned(tmp_2_0_2_cast_cast_reg_1706));
tmp_68_cast_fu_1333_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_66_fu_1329_p2),64));
tmp_68_fu_1216_p2 <= std_logic_vector(unsigned(tmp_37_reg_1585) + unsigned(tmp_2_0_3_cast_cast_fu_1212_p1));
tmp_69_cast_fu_1375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_67_reg_1800),64));
tmp_69_fu_1266_p2 <= std_logic_vector(unsigned(tmp_43_reg_1607) + unsigned(tmp_2_0_3_cast_cast_reg_1719));
tmp_70_cast_fu_1221_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_68_fu_1216_p2),64));
tmp_70_fu_1302_p2 <= std_logic_vector(unsigned(tmp_46_reg_1616) + unsigned(tmp_2_0_3_cast_cast_reg_1719));
tmp_71_cast_fu_1270_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_69_fu_1266_p2),64));
tmp_71_fu_1346_p2 <= std_logic_vector(unsigned(tmp_48_reg_1625) + unsigned(tmp_2_0_3_cast_cast_reg_1719));
tmp_72_cast_fu_1306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_70_fu_1302_p2),64));
tmp_72_fu_1355_p2 <= std_logic_vector(unsigned(tmp_51_reg_1634) + unsigned(tmp_2_0_3_cast_cast_reg_1719));
tmp_73_cast_fu_1350_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_71_fu_1346_p2),64));
tmp_73_fu_1238_p2 <= std_logic_vector(unsigned(tmp_37_reg_1585) + unsigned(tmp_2_0_4_cast_cast_fu_1234_p1));
tmp_74_cast_fu_1379_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_72_reg_1810),64));
tmp_74_fu_1275_p2 <= std_logic_vector(unsigned(tmp_43_reg_1607) + unsigned(tmp_2_0_4_cast_cast_reg_1732));
tmp_75_cast_fu_1243_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_73_fu_1238_p2),64));
tmp_75_fu_1311_p2 <= std_logic_vector(unsigned(tmp_46_reg_1616) + unsigned(tmp_2_0_4_cast_cast_reg_1732));
tmp_76_cast_fu_1279_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_74_fu_1275_p2),64));
tmp_76_fu_1359_p2 <= std_logic_vector(unsigned(tmp_48_reg_1625) + unsigned(tmp_2_0_4_cast_cast_reg_1732));
tmp_77_cast_fu_1315_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_75_fu_1311_p2),64));
tmp_77_fu_1363_p2 <= std_logic_vector(unsigned(tmp_51_reg_1634) + unsigned(tmp_2_0_4_cast_cast_reg_1732));
tmp_78_cast_fu_1367_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_76_reg_1815),64));
tmp_79_cast_fu_1383_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_reg_1820),64));
tmp_7_cast_fu_586_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_7_fu_580_p2),6));
tmp_7_fu_580_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_576_p1) - unsigned(to_b_cast4_cast_fu_564_p1));
tmp_9_1_cast_cast_fu_951_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_1_fu_945_p2),7));
tmp_9_2_cast_cast_fu_988_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_2_fu_982_p2),7));
tmp_9_2_fu_982_p2 <= std_logic_vector(unsigned(ap_const_lv3_2) + unsigned(row_b_cast_fu_935_p1));
tmp_9_3_cast_cast_fu_1025_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_3_fu_1019_p2),6));
tmp_9_3_fu_1019_p2 <= std_logic_vector(unsigned(ap_const_lv3_3) + unsigned(row_b_cast_fu_935_p1));
tmp_9_4_cast_cast_fu_1060_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_s_fu_1052_p3),7));
tmp_9_cast_fu_636_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_9_reg_1408),64));
tmp_9_s_fu_1052_p3 <= (ap_const_lv1_1 & row_b_reg_512);
tmp_fu_590_p2 <= "1" when (to_b_reg_490 = ap_const_lv2_3) else "0";
tmp_s_fu_640_p2 <= std_logic_vector(signed(tmp_9_reg_1408) + signed(ap_const_lv9_1));
to_b_1_fu_596_p2 <= std_logic_vector(unsigned(to_b_reg_490) + unsigned(ap_const_lv2_1));
to_b_cast4_cast_fu_564_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(to_b_reg_490),5));
end behav;
| mit | 7bc5c162c5797e99b1fdb40bb7b6d684 | 0.677414 | 3.212337 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/altera/simprims/altera_primitives.vhd | 2 | 53,558 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
Library ieee;
use ieee.std_logic_1164.all;
entity GLOBAL is
port(
a_in : in std_logic;
a_out : out std_logic);
end GLOBAL;
architecture BEHAVIOR of GLOBAL is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CARRY is
port(
a_in : in std_logic;
a_out : out std_logic);
end CARRY;
architecture BEHAVIOR of CARRY is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CASCADE is
port(
a_in : in std_logic;
a_out : out std_logic);
end CASCADE;
architecture BEHAVIOR of CASCADE is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CARRY_SUM is
port(
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic);
end CARRY_SUM;
architecture BEHAVIOR of CARRY_SUM is
begin
sout <= sin;
cout <= cin;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity EXP is
port(
a_in : in std_logic;
a_out : out std_logic);
end EXP;
architecture BEHAVIOR of EXP is
begin
a_out <= not a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity SOFT is
port(
a_in : in std_logic;
a_out : out std_logic);
end SOFT;
architecture BEHAVIOR of SOFT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity OPNDRN is
port(
a_in : in std_logic;
a_out : out std_logic);
end OPNDRN;
architecture BEHAVIOR of OPNDRN is
begin
process (a_in)
begin
if (a_in = '0') then
a_out <= '0';
elsif (a_in = '1') then
a_out <= 'Z';
else
a_out <= 'X';
end if;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity ROW_GLOBAL is
port(
a_in : in std_logic;
a_out : out std_logic);
end ROW_GLOBAL;
architecture BEHAVIOR of ROW_GLOBAL is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity TRI is
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end TRI;
architecture BEHAVIOR of TRI is
begin
a_out <= a_in when oe = '1'
else 'Z';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity LUT_INPUT is
port(
a_in : in std_logic;
a_out : out std_logic);
end LUT_INPUT;
architecture BEHAVIOR of LUT_INPUT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity LUT_OUTPUT is
port(
a_in : in std_logic;
a_out : out std_logic);
end LUT_OUTPUT;
architecture BEHAVIOR of LUT_OUTPUT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity latch is
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end latch;
architecture BEHAVIOR of latch is
signal iq : std_logic := '0';
begin
process (d, ena)
begin
if (ena = '1') then
iq <= d;
end if;
end process;
q <= iq;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end dlatch;
architecture BEHAVIOR of dlatch is
signal iq : std_logic := '0';
begin
process (d, ena, clrn, prn)
begin
if (clrn = '0') then
iq <= '0';
elsif (prn = '0') then
iq <= '1';
elsif (ena = '1') then
iq <= d;
end if;
end process;
q <= iq;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GDFF is
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end PRIM_GDFF;
architecture BEHAVIOR of PRIM_GDFF is
signal iq : std_logic := '0';
signal init : std_logic := '0';
signal stalled_adata : std_logic := '0';
begin
process (clk, clr, pre, ald, stalled_adata)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (ald = '1') then
iq <= stalled_adata;
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if (sclr = '1') then
iq <= '0';
elsif (sload = '1') then
iq <= stalled_adata;
else
iq <= d;
end if;
end if;
end if;
end process;
process (adt, init)
begin
if (init = '0') then
stalled_adata <= adt;
init <= '1';
else
stalled_adata <= adt after 1 ps;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GDFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end DFF;
architecture BEHAVIOR of DFF is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
ald => zero_bit,
adt => zero_bit,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFFE is
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end DFFE;
architecture BEHAVIOR of DFFE is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
ald => zero_bit,
adt => zero_bit,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFFE
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFFEA is
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end DFFEA;
architecture BEHAVIOR of DFFEA is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
ald => aload,
adt => adata,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFFEA
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.dffeas_pack.all;
entity DFFEAS is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of dffeas : entity is TRUE;
end DFFEAS;
architecture vital_dffeas of dffeas is
attribute VITAL_LEVEL0 of vital_dffeas : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_dffeas;
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GTFF is
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GTFF;
architecture BEHAVIOR of PRIM_GTFF is
signal iq : std_logic := '0';
signal init : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if (t = '1') then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GTFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GTFF;
entity TFF is
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end TFF;
architecture BEHAVIOR of TFF is
component PRIM_GTFF
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GTFF_INST : PRIM_GTFF
port map (
t => t,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- TFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GTFF;
entity TFFE is
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end TFFE;
architecture BEHAVIOR of TFFE is
component PRIM_GTFF
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GTFF_INST : PRIM_GTFF
port map (
t => t,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- TFFE
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GJKFF is
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GJKFF;
architecture BEHAVIOR of PRIM_GJKFF is
signal iq : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if ((j = '1') and (k = '0')) then
iq <= '1';
elsif ((j = '0') and (k = '1')) then
iq <= '0';
elsif ((j = '1') and (k = '1')) then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GJKFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GJKFF;
entity JKFF is
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end JKFF;
architecture BEHAVIOR of JKFF is
component PRIM_GJKFF
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GJKFF_INST : PRIM_GJKFF
port map (
j => j,
k => k,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- JKFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GJKFF;
entity JKFFE is
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end JKFFE;
architecture BEHAVIOR of JKFFE is
component PRIM_GJKFF
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GJKFF_INST : PRIM_GJKFF
port map (
j => j,
k => k,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- JKFFE
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GSRFF is
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GSRFF;
architecture BEHAVIOR of PRIM_GSRFF is
signal iq : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if ((s = '1') and (r = '0')) then
iq <= '1';
elsif ((s = '0') and (r = '1')) then
iq <= '0';
elsif ((s = '1') and (r = '1')) then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GSRFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GSRFF;
entity SRFF is
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end SRFF;
architecture BEHAVIOR of SRFF is
component PRIM_GSRFF
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GSRFF_INST : PRIM_GSRFF
port map (
s => s,
r => r,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- SRFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GSRFF;
entity SRFFE is
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end SRFFE;
architecture BEHAVIOR of SRFFE is
component PRIM_GSRFF
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GSRFF_INST : PRIM_GSRFF
port map (
s => s,
r => r,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- SRFFE
library ieee;
use ieee.std_logic_1164.all;
-- ENTITY DECLARATION
entity clklock is
generic(
input_frequency : natural := 10000; -- units in ps
clockboost : natural := 1
);
port(
inclk : in std_logic; -- required port, input reference clock
outclk : out std_logic -- outclk output
);
end clklock;
-- END ENTITY DECLARATION
-- BEGINNING OF ARCHITECTURE BEHAVIOR
architecture behavior of clklock is
-- CONSTANT DECLARATION
constant valid_lock_cycles : natural := 1;
constant invalid_lock_cycles : natural := 2;
-- SIGNAL DECLARATION
SIGNAL pll_lock : std_logic := '0';
SIGNAL check_lock : std_logic := '0';
SIGNAL outclk_tmp : std_logic := 'X';
begin
-- checking for invalid parameters
MSG: process
begin
if (input_frequency <= 0) then
ASSERT FALSE
REPORT "The period of the input clock (input_frequency) must be greater than 0!"
SEVERITY ERROR;
end if;
if ((clockboost /= 1) and (clockboost /= 2)) then
ASSERT FALSE
REPORT "The clock multiplication factor (clockboost) must be a value of 1 or 2!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
LOCK: process(inclk, pll_lock, check_lock)
-- VARIABLE DECLARATION
variable inclk_ps : time := 0 ps;
variable violation : boolean := false;
variable pll_lock_tmp : std_logic := '0';
variable start_lock_count, stop_lock_count : integer := 0;
variable pll_last_rising_edge, pll_last_falling_edge : time := 0 ps;
variable pll_rising_edge_count : integer := 0;
variable pll_cycle, pll_duty_cycle : time := 0 ps;
variable expected_next_clk_edge : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable last_synchronizing_rising_edge_for_outclk : time := 0 ps;
variable input_cycles_per_outclk : integer := 1;
variable input_cycle_count_to_sync0 : integer := 0;
variable init : boolean := true;
variable output_value : std_logic := '0';
variable vco_per : time := 0 ps;
variable high_time : time := 0 ps;
variable low_time : time := 0 ps;
variable sched_time : time := 0 ps;
variable tmp_per : integer := 0;
variable temp, tmp_rem, my_rem : integer := 0;
variable inc : integer := 1;
variable cycle_to_adjust : integer := 0;
variable outclk_synchronizing_period : time;
variable outclk_cycles_per_sync_period : integer := clockboost;
variable schedule_outclk : boolean := false;
begin
if (init) then
outclk_cycles_per_sync_period := clockboost;
input_cycles_per_outclk := 1;
clk_per_tolerance := (0.1 * real(input_frequency)) * 1 ps;
init := false;
end if;
if (inclk'event and inclk = '1') then
if (pll_lock_tmp = '1') then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
end if;
if pll_rising_edge_count = 0 then -- at 1st rising edge
inclk_ps := (input_frequency / 1) * 1 ps;
pll_duty_cycle := inclk_ps/2;
elsif pll_rising_edge_count = 1 then -- at 2nd rising edge
pll_cycle := now - pll_last_rising_edge; -- calculate period
if ((NOW - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or
(NOW - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then
ASSERT FALSE
REPORT "Inclock_Period Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
else
start_lock_count := 1;
end if;
else
violation := false;
end if;
if ((now - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) or
(now - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2)) then
ASSERT FALSE
REPORT "Duty Cycle Violation"
SEVERITY WARNING;
violation := true;
else
violation := false;
end if;
else
pll_cycle := now - pll_last_rising_edge; -- calculate period
if ((now - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or
(now - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then
ASSERT FALSE
REPORT "Cycle Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
else
start_lock_count := 1;
end if;
else
violation := false;
end if;
end if;
pll_last_rising_edge := now;
pll_rising_edge_count := pll_rising_edge_count +1;
if (not violation) then
if (pll_lock_tmp = '1') then
input_cycle_count_to_sync0 := input_cycle_count_to_sync0 + 1;
if (input_cycle_count_to_sync0 = input_cycles_per_outclk) then
outclk_synchronizing_period := now - last_synchronizing_rising_edge_for_outclk;
last_synchronizing_rising_edge_for_outclk := now;
schedule_outclk := true;
input_cycle_count_to_sync0 := 0;
end if;
else
start_lock_count := start_lock_count + 1;
if (start_lock_count >= valid_lock_cycles) then
pll_lock_tmp := '1';
input_cycle_count_to_sync0 := 0;
outclk_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_outclk) * 1 ps;
last_synchronizing_rising_edge_for_outclk := now;
schedule_outclk := true;
end if;
end if;
else
start_lock_count := 1;
end if;
elsif (inclk'event and inclk= '0') then
if (pll_lock_tmp = '1') then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
if (now > 0 ns and ((now - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) or
(now - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2))) then
ASSERT FALSE
REPORT "Duty Cycle Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
end if;
else
violation := false;
end if;
else
start_lock_count := start_lock_count + 1;
end if;
pll_last_falling_edge := now;
else
if pll_lock_tmp = '1' then
if (inclk = '1') then
expected_next_clk_edge := pll_last_rising_edge + (inclk_ps+clk_per_tolerance)/2.0;
else
expected_next_clk_edge := pll_last_falling_edge + (inclk_ps+clk_per_tolerance)/2.0;
end if;
violation := false;
if (now < expected_next_clk_edge) then
check_lock <= not check_lock after (expected_next_clk_edge - now);
elsif (now = expected_next_clk_edge) then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
else
ASSERT FALSE
REPORT "Inclock_Period Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
else
check_lock <= not check_lock after (inclk_ps/2.0);
end if;
end if;
end if;
end if;
end if;
pll_lock <= pll_lock_tmp;
if (pll_lock'event and pll_lock = '0') then
start_lock_count := 1;
stop_lock_count := 0;
outclk_tmp <= 'X';
end if;
-- outclk output
if (schedule_outclk = true) then
-- initialize variables
sched_time := 0 ps;
cycle_to_adjust := 0;
inc := 1;
output_value := '1';
temp := outclk_synchronizing_period / 1 ps;
my_rem := temp rem outclk_cycles_per_sync_period;
-- schedule <outclk_cycles_per_sync_period> number of output clock
-- cycles in this loop in order to synchronize the output clock to the
-- input clock - to get rid of drifting for cases where the input clock
-- period is not always divisible
for i in 1 to outclk_cycles_per_sync_period loop
tmp_per := temp/outclk_cycles_per_sync_period;
if ((my_rem /= 0) and (inc <= my_rem)) then
tmp_rem := (outclk_cycles_per_sync_period * inc) rem my_rem;
cycle_to_adjust := (outclk_cycles_per_sync_period * inc) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
-- if this cycle is the one to adjust the output period in, then
-- increment the period by 1 unit
if (cycle_to_adjust = i) then
tmp_per := tmp_per + 1;
inc := inc + 1;
end if;
-- adjust the high and low cycle period
vco_per := tmp_per * 1 ps;
high_time := (tmp_per / 2) * 1 ps;
if ((tmp_per rem 2) /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the high and low cycle of 1 output clock period
for j in 1 to 2 loop
outclk_tmp <= transport output_value after sched_time;
output_value := not output_value;
if (output_value = '0') then
sched_time := sched_time + high_time;
elsif (output_value = '1') then
sched_time := sched_time + low_time;
end if;
end loop;
end loop;
-- reset schedule_outclk
schedule_outclk := false;
end if; -- schedule_outclk
end process LOCK;
outclk <= outclk_tmp;
end behavior;
-- END ARCHITECTURE BEHAVIOR
Library ieee;
use ieee.std_logic_1164.all;
entity alt_inbuf is
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end alt_inbuf;
architecture BEHAVIOR of alt_inbuf is
begin
o <= i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end alt_outbuf;
architecture BEHAVIOR of alt_outbuf is
begin
o <= i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_tri is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end alt_outbuf_tri;
architecture BEHAVIOR of alt_outbuf_tri is
begin
o <= i when oe = '1'
else 'Z';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_iobuf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end alt_iobuf;
architecture BEHAVIOR of alt_iobuf is
begin
process(i, io, oe)
begin
if oe = '1' then
io <= i;
else
io <= 'Z';
end if;
o <= io;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_inbuf_diff is
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end alt_inbuf_diff;
architecture BEHAVIOR of alt_inbuf_diff is
begin
process(i, ibar)
variable out_tmp : std_logic;
variable in_tmp : std_logic_vector(1 downto 0);
begin
in_tmp(0) := ibar;
in_tmp(1) := i;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
o <= out_tmp;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic);
end alt_outbuf_diff;
architecture BEHAVIOR of alt_outbuf_diff is
begin
o <= i;
obar <= not i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_tri_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic);
end alt_outbuf_tri_diff;
architecture BEHAVIOR of alt_outbuf_tri_diff is
begin
o <= i when oe = '1'
else 'Z' when oe = '0'
else 'X';
obar <= (not i) when oe = '1'
else 'Z' when oe = '0'
else 'X';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_iobuf_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic);
end alt_iobuf_diff;
architecture BEHAVIOR of alt_iobuf_diff is
begin
process(i, io, iobar, oe)
variable in_tmp : std_logic_vector(1 downto 0);
variable out_tmp : std_logic;
begin
in_tmp(0) := iobar;
in_tmp(1) := io;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= i;
iobar <= not i;
elsif oe = '0' then
io <= 'Z';
iobar <= 'Z';
else
io <= 'X';
iobar <= 'X';
end if;
o <= out_tmp;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_bidir_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic);
end alt_bidir_diff;
architecture BEHAVIOR of alt_bidir_diff is
begin
process(bidirin, io, iobar, oe)
variable in_tmp : std_logic_vector(1 downto 0);
variable out_tmp : std_logic;
begin
in_tmp(0) := iobar;
in_tmp(1) := io;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= bidirin;
iobar <= not bidirin;
bidirin <= 'Z';
elsif oe = '0' then
io <= 'Z';
iobar <= 'Z';
bidirin <= out_tmp;
else
io <= 'X';
iobar <= 'X';
bidirin <= 'X';
end if;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_bidir_buf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic);
end alt_bidir_buf;
architecture BEHAVIOR of alt_bidir_buf is
begin
process(bidirin, io, oe)
variable in_tmp : std_logic;
variable out_tmp : std_logic;
begin
in_tmp := io;
case in_tmp is
when '0' => out_tmp := '0';
when '1' => out_tmp := '1';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= bidirin;
bidirin <= 'Z';
elsif oe = '0' then
io <= 'Z';
bidirin <= out_tmp;
else
io <= 'X';
bidirin <= 'X';
end if;
end process;
end BEHAVIOR;
| gpl-2.0 | c493c75b717f57621c5aeac747c2e84f | 0.46262 | 4.003139 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml605/leon3mp.vhd | 1 | 35,443 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml605.all;
use work.pcie.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF"
);
port (
reset : in std_ulogic;
errorn : out std_ulogic;
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
alatch : out std_ulogic;
-- DDR3 memory
ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
gmiiclk_p : in std_ulogic;
gmiiclk_n : in std_ulogic;
egtx_clk : out std_ulogic;
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
erstn : out std_ulogic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
clk_33 : in std_ulogic; -- SYSACE clock
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- Output signals to LEDs
led : out std_logic_vector(6 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal lclk, clk_ddr, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
signal tb_rst : std_logic;
signal tb_clk : std_logic;
signal phy_init_done : std_logic;
signal lerrorn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- VGA
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal clk100 : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
-- IIC
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
-- SYSACE
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clk_ddr : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_preserve of clk_ddr : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
attribute keep of clk_ddr : signal is true;
constant VCO_FREQ : integer := 1200000; -- MMCM VCO frequency in KHz
constant CPU_FREQ : integer := VCO_FREQ / CFG_MIG_CLK4; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
alatch <= '0';
erstn <= rstn;
-- Glitch free reset that can be used for the Eth Phy and flash memory
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+CFG_PCIEXP,
nahbs => 9)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
lerrorn <= dbgo(0).error and rstn;
error_pad : odpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (errorn, lerrorn);
dsugen : if CFG_DSU = 1 generate
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (level => cmos, voltage => x15v, tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, iomask => 0, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 24)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (writen, memo.writen);
end generate;
bdr : iopadvv generic map (level => cmos, voltage => x25v, tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
-- mig_gen : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : ahb2mig_ml605
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#E00#,
MHz => 400, Mbyte => 512, nosync => boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst => rstn, clk_ahb => clkm, clk_ddr => clk_ddr,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
ddr3ctrl : entity work.mig_37
generic map (SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,CLKOUT_DIVIDE4 => work.config.CFG_MIG_CLK4)
port map(
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
ddr3_dq => ddr3_dq,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
app_wdf_wren => migi.app_wdf_wren,
app_wdf_data => migi.app_wdf_data,
app_wdf_mask => migi.app_wdf_mask,
app_wdf_end => migi.app_wdf_end,
app_addr => migi.app_addr,
app_cmd => migi.app_cmd,
app_en => migi.app_en,
app_rdy => migo.app_rdy,
app_wdf_rdy => migo.app_wdf_rdy,
app_rd_data => migo.app_rd_data,
app_rd_data_valid => migo.app_rd_data_valid,
tb_rst => open,
tb_clk => clk_ddr,
clk_ahb => clkm,
clk100 => clk100,
phy_init_done => phy_init_done,
sys_rst_13 => reset,
sys_rst_14 => rstraw
);
led(3) <= phy_init_done;
led(4) <= rstn;
led(5) <= reset;
led(6) <= '0';
lock <= phy_init_done; -- and cgo.clklock;
-- end generate;
-- noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= cgo.clklock; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 7, hirq => 10, mode => 2,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(7), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
clk_33_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (clk_33, clkace);
sysace_mpa_pads : outpadv generic map (level => cmos, voltage => x25v, width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (sysace_d(7 downto 0), aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpirq, acei.irq);
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
hslvndx => 8,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)
);
end generate;
------------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE),
dapbndx => 8, dapbaddr => 8,dapbirq => 8, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 8, apbndx => 5, apbaddr => 5, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(8),
dahbmo => ahbmo((CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)),
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 8, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 5, paddr => 5,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- VGA + IIC --------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 24000, clk2 => 20000, clk3 => 16000, burstlen => 4,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (clk100, ethi.gtx_clk, lock, clk_sel, vgao, clkvga, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 7, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (level => cmos, voltage => x25v, width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
-- greth1g: if CFG_GRETH1G = 1 generate
gtxclk0 : entity work.gtxclk port map (
clk_p => gmiiclk_p, clk_n => gmiiclk_n, clkint => ethi.gtx_clk,
clkout => egtx_clk);
-- end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1+CFG_PCIEXP) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Virtex6 ML605 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 440393ce3626adf492f0b35f778c7b73 | 0.543577 | 3.469701 | false | false | false | false |
khaledhassan/vhdl-examples | register/register_tb.vhd | 1 | 2,534 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for synchronous register of a given width with a load signal.
library ieee;
use ieee.std_logic_1164.all;
entity reg_tb is
end reg_tb;
architecture TB of reg_tb is
signal rst, clk, load : std_logic;
signal input, output : std_logic_vector(0 downto 0);
constant clk_period : time := 20 ns; -- for a 50MHz clock
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.reg
generic map (
WIDTH => 1
)
port map (
rst => rst,
clk => clk,
load => load,
input => input,
output => output
);
-- Clock process
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
-- Hold reset state
rst <= '1';
load <= '0';
input(0) <= '0';
wait for clk_period;
-- Release reset
rst <= '0';
-- Perform the simulation
input(0) <= '1';
wait for clk_period;
input(0) <= '0';
load <= '1';
wait for clk_period;
input(0) <= '1';
wait for clk_period;
input(0) <= '0';
wait;
end process;
end TB;
| mit | 76f70fae16fbc20b81984c1e649b4231 | 0.619968 | 4.209302 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/ddr_unisim.vhd | 1 | 12,137 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: unisim_iddr_reg
-- File: unisim_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
entity unisim_iddr_reg is
generic (tech : integer := virtex4;arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of unisim_iddr_reg is
attribute BOX_TYPE : string;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preQ1, preQ2 : std_ulogic;
signal D_delay : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
Port map( Q1 => Q1, Q2 => Q2, C => C1, CE => CE,
D => D, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE")
Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
S6 : if (tech = spartan6) generate
noalign : if arch = 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "NONE")
Port map( Q0 => Q1, Q1 => preQ2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
align : if arch /= 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "C0")
Port map( Q0 => preQ1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q1 <= preQ1;
end if;
end process;
end generate;
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
-- CE and S inputs inactive for virtex 2
q1reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
Q1 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q1 <= D;
end if;
end process;
q2reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
preQ2 <= '0';
elsif C1'event and C1='0' then --Clock event - negedge
preQ2 <= D;
end if;
end process;
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
-- S6 : if tech = spartan6 generate
--
-- x0 : IFDDRRSE port map (
-- Q0 => Q1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
-- D => D, R => R, S => S);
--
-- end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.oddr2;
--use unisim.FDDRRSE;
--pragma translate_on
entity unisim_oddr_reg is
generic (tech : integer := virtex4; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR : component is "PRIMITIVE";
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "ASYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR2 : component is "PRIMITIVE";
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
FDDRRSE : component is "PRIMITIVE";
signal preD2 : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
port map(
Q => Q, C => C1, CE => CE, D1 => D1,
D2 => D2, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
, SRTYPE => "ASYNC")
port map(
Q => Q,
C => C1,
CE => CE,
D1 => D1,
D2 => preD2,
R => R,
S => S);
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component FDDRRSE
-- generic map( INIT => '0')
port map(
Q => Q,
D0 => D1,
D1 => preD2,
C0 => C1,
C1 => C2,
CE => CE,
R => R,
S => S);
end generate;
s6 : if tech = spartan6 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => Q,
C0 => C1,
C1 => C2,
CE => CE,
D0 => D1,
D1 => D2,
R => R,
S => S);
end generate;
end ;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
--use unisim.FDDRRSE;
--pragma translate_on
entity oddrv2 is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrv2 is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDDRRSE
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
entity oddrc3e is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrc3e is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
| gpl-2.0 | cb0da5323a7f772d43ae22b983b98109 | 0.520475 | 3.403533 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-asic/bschain.vhd | 1 | 11,906 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.jtag.all;
use work.config.all;
entity bschain is
generic (tech: integer := CFG_FABTECH;
enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
hzsup: integer range 0 to 1 := 1);
port (
-- Chain control signals
chain_tck : in std_ulogic;
chain_tckn : in std_ulogic;
chain_tdi : in std_ulogic;
chain_tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
-- Pad-side signals
Presetn : in std_ulogic;
Pclksel : in std_logic_vector (1 downto 0);
Pclk : in std_ulogic;
Perrorn : out std_ulogic;
Paddress : out std_logic_vector(27 downto 0);
Pdatain : in std_logic_vector(31 downto 0);
Pdataout : out std_logic_vector(31 downto 0);
Pdataen : out std_logic_vector(31 downto 0);
Pcbin : in std_logic_vector(7 downto 0);
Pcbout : out std_logic_vector(7 downto 0);
Pcben : out std_logic_vector(7 downto 0);
Psdclk : out std_ulogic;
Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
Psdwen : out std_ulogic; -- sdram write enable
Psdrasn : out std_ulogic; -- sdram ras
Psdcasn : out std_ulogic; -- sdram cas
Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
Pdsutx : out std_ulogic; -- DSU tx data
Pdsurx : in std_ulogic; -- DSU rx data
Pdsuen : in std_ulogic;
Pdsubre : in std_ulogic;
Pdsuact : out std_ulogic;
Ptxd1 : out std_ulogic; -- UART1 tx data
Prxd1 : in std_ulogic; -- UART1 rx data
Ptxd2 : out std_ulogic; -- UART2 tx data
Prxd2 : in std_ulogic; -- UART2 rx data
Pramsn : out std_logic_vector (4 downto 0);
Pramoen : out std_logic_vector (4 downto 0);
Prwen : out std_logic_vector (3 downto 0);
Poen : out std_ulogic;
Pwriten : out std_ulogic;
Pread : out std_ulogic;
Piosn : out std_ulogic;
Promsn : out std_logic_vector (1 downto 0);
Pbrdyn : in std_ulogic;
Pbexcn : in std_ulogic;
Pwdogn : out std_ulogic;
Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pprom32 : in std_ulogic;
Ppromedac : in std_ulogic;
Pspw_clksel : in std_logic_vector (1 downto 0);
Pspw_clk : in std_ulogic;
Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
Plclk2x : in std_ulogic;
Plclk4x : in std_ulogic;
Plclkdis : out std_ulogic;
Plclklock : in std_ulogic;
Plock : out std_ulogic;
Proen : in std_ulogic;
Proout : out std_ulogic;
-- Core-side signals
Cresetn : out std_ulogic;
Cclksel : out std_logic_vector (1 downto 0);
Cclk : out std_ulogic;
Cerrorn : in std_ulogic;
Caddress : in std_logic_vector(27 downto 0);
Cdatain : out std_logic_vector(31 downto 0);
Cdataout : in std_logic_vector(31 downto 0);
Cdataen : in std_logic_vector(31 downto 0);
Ccbin : out std_logic_vector(7 downto 0);
Ccbout : in std_logic_vector(7 downto 0);
Ccben : in std_logic_vector(7 downto 0);
Csdclk : in std_ulogic;
Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
Csdwen : in std_ulogic; -- sdram write enable
Csdrasn : in std_ulogic; -- sdram ras
Csdcasn : in std_ulogic; -- sdram cas
Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
Cdsutx : in std_ulogic; -- DSU tx data
Cdsurx : out std_ulogic; -- DSU rx data
Cdsuen : out std_ulogic;
Cdsubre : out std_ulogic;
Cdsuact : in std_ulogic;
Ctxd1 : in std_ulogic; -- UART1 tx data
Crxd1 : out std_ulogic; -- UART1 rx data
Ctxd2 : in std_ulogic; -- UART2 tx data
Crxd2 : out std_ulogic; -- UART2 rx data
Cramsn : in std_logic_vector (4 downto 0);
Cramoen : in std_logic_vector (4 downto 0);
Crwen : in std_logic_vector (3 downto 0);
Coen : in std_ulogic;
Cwriten : in std_ulogic;
Cread : in std_ulogic;
Ciosn : in std_ulogic;
Cromsn : in std_logic_vector (1 downto 0);
Cbrdyn : out std_ulogic;
Cbexcn : out std_ulogic;
Cwdogn : in std_ulogic;
Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cprom32 : out std_ulogic;
Cpromedac : out std_ulogic;
Cspw_clksel : out std_logic_vector (1 downto 0);
Cspw_clk : out std_ulogic;
Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
Clclk2x : out std_ulogic;
Clclk4x : out std_ulogic;
Clclkdis : in std_ulogic;
Clclklock : out std_ulogic;
Clock : in std_ulogic;
Croen : out std_ulogic;
Croout : in std_ulogic
);
end;
architecture rtl of bschain is
signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
signal sr1i, sr1o: std_logic_vector(4 downto 0);
signal sr3i, sr3o: std_logic_vector(41 downto 0);
signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
begin
-----------------------------------------------------------------------------
-- Scan chain registers (note: adjust order to match pad ring)
sr1a: bscanregs
generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
Cclk <= sr1o(1); Perrorn <= sr1o(0);
sr1b: bscanregs
generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2a: bscanregsbd
generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2b: bscanregsbd
generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3a: bscanregs
generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3b: bscanregs
generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
Csddqm & Cdsutx & Pdsurx;
sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
sr4: bscanregsbd
generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5: bscanregs
generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
Clclkdis & Plclklock & Clock & Proen & Croout;
Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
Clclk2x <= sr5o(6);
Clclk4x <= sr5o(5);
Plclkdis <= sr5o(4);
Clclklock <= sr5o(3);
Plock <= sr5o(2);
Croen <= sr5o(1);
Proout <= sr5o(0);
end;
| gpl-2.0 | 60ce40e0b8fb70682e78aeb94c042e9b | 0.585503 | 3.045792 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/umc18/components/umc_simprims.vhd | 1 | 17,431 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umc_simprims
-- File: umc_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple UMC 0.18 simulation models
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPU is begin
Z <= to_X01(A) after 1 ns; --A <= 'H';
end;
-- input pad with pull-down
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPD is begin
Z <= to_X01(A) after 1 ns; --A <= 'L';
end;
-- schmitt input pad
library ieee;
use ieee.std_logic_1164.all;
entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;
-- output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;
-- tri-state output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR4 is begin
Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR12 is begin
Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR24 is begin
Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
end;
-- bidirectional pads
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V4 is begin
IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V12 is begin
IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V24 is begin
IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Receiver is port( A, AN : in std_logic; Z : out std_logic); end;
architecture struct of LVDS_Receiver is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;
Z <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;
architecture struct of LVDS_Driver is begin
Z <= A after 1 ns;
ZN <= not A after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;
architecture struct of LVDS_Biasmodule is begin end;
-- single-port memory
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end;
architecture behav of UMC_SIM_SRAM is
subtype memword is std_logic_vector(dbits-1 downto 0);
type mem_type is array (0 to 2**abits-1) of memword;
signal qint : memword;
begin
m : process(clk)
variable mem : mem_type;
begin
if rising_edge(clk) then
qint <= (others => 'X');
if to_X01(wen) = '0' then mem(conv_integer(a)) := data;
elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;
end if;
end process;
q <= qint when to_X01(oen) = '0' else
(others => 'Z') when to_X01(oen) = '1' else (others => 'X');
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);
end;
-- pragma translate_on
| gpl-2.0 | 410b14cd1ee4f2998cd35f1e764b55f3 | 0.632379 | 2.730848 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd | 1 | 22,014 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
| gpl-2.0 | 9f0b81fd6d3b99c8e31f649e3f9564e5 | 0.629599 | 2.971251 | false | false | false | false |
JimLewis/OSVVM | MemoryPkg_2019.vhd | 1 | 27,493 | --
-- File Name: MemoryPkg_2019.vhd
-- Design Unit Name: MemoryPkg_2019
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description
-- Package defines a protected type, MemoryPType, and methods
-- for efficiently implementing memory data structures
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 05/2005 0.1 Initial revision
-- 06/2015 2015.06 Updated for Alerts, ...
-- Numerous revisions for VHDL Testbenches and Verification
-- 01/2016 2016.01 Update for buf.all(buf'left)
-- 11/2016 2016.11 Refinement to MemRead to return value, X (if X), U (if not initialized)
-- 01/2020 2020.01 Updated Licenses to Apache
-- 12/2020 2020.12 Beta version of MemoryPType with VHDL-2019 generics.
-- Used in place of MemoryPkg. Tested in RivieraPro.
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.numeric_std.all ;
use IEEE.numeric_std_unsigned.all ;
use IEEE.math_real.all ;
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
package MemoryPkg_2019 is
type MemoryPType is protected
generic (
constant AddrWidth : integer ;
constant DataWidth : integer
) ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) ;
------------------------------------------------------------
procedure MemRead (
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase ;
procedure deallocate ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadH (FileName : string) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadB (FileName : string) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteH (FileName : string) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteB (FileName : string) ;
end protected MemoryPType ;
end MemoryPkg_2019 ;
package body MemoryPkg_2019 is
constant BLOCK_WIDTH : integer := 10 ;
type MemoryPType is protected body
type MemBlockType is array (integer range <>) of integer ;
type MemBlockPtrType is access MemBlockType ;
type MemArrayType is array (integer range <>) of MemBlockPtrType ;
type ArrayPtrVarType is access MemArrayType ;
--!! variable ArrayPtrVar : ArrayPtrVarType := NULL ;
--!! variable AddrWidthVar : integer := -1 ; -- set by MemInit - merges addr length and initialized checks.
--!! variable DataWidthVar : natural := 1 ; -- set by MemInit
--!! variable BlockkWidthVar : natural := 0 ; -- set by MemInit
--!!
--!! TODO: AddrWidthVar f(AddrWidth, DataWidth)
--!! TODO: DataWidthVar f(DataWidth mod 16)
--!!
variable DataWidthVar : natural := DataWidth ; -- set by Generic
variable AddrWidthVar : integer := AddrWidth ; -- set by Generic
variable BlockkWidthVar : natural := minimum(BLOCK_WIDTH, AddrWidth) ; -- set by Generic
variable ArrayPtrVar : ArrayPtrVarType := new MemArrayType(0 to 2**(AddrWidth-BlockkWidthVar)-1) ;
variable AlertLogIDVar : AlertLogIDType := OSVVM_ALERTLOG_ID ;
type FileFormatType is (BINARY, HEX) ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) is
------------------------------------------------------------
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
-- Check Bounds of Address and if memory is initialized
if Addr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Memory not initialized, Write Ignored.", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= DataWidthVar then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(DataWidthVar), FAILURE) ;
return ;
end if ;
if is_X( Addr ) then
Alert(AlertLogIDVar, "MemoryPType.MemWrite: Address X, Write Ignored.") ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockkWidthVar then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockkWidthVar)) ;
else
BlockAddr := 0 ;
end if ;
-- If empty, allocate a memory block
if (ArrayPtrVar(BlockAddr) = NULL) then
ArrayPtrVar(BlockAddr) := new MemBlockType(0 to 2**BlockkWidthVar-1) ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockkWidthVar -1 downto 0)) ;
-- Write to BlockAddr, WordAddr
if (Is_X(Data)) then
ArrayPtrVar(BlockAddr)(WordAddr) := -1 ;
else
ArrayPtrVar(BlockAddr)(WordAddr) := to_integer( Data ) ;
end if ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
Addr : In std_logic_vector ;
Data : Out std_logic_vector
) is
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
-- Check Bounds of Address and if memory is initialized
if Addr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.MemRead: Memory not initialized. Returning U", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.MemRead: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= DataWidthVar then
Alert(AlertLogIDVar, "MemoryPType.MemRead: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(DataWidthVar), FAILURE) ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- If Addr X, data = X
if is_X( aAddr ) then
Data := (Data'range => 'X') ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockkWidthVar then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockkWidthVar)) ;
else
BlockAddr := 0 ;
end if ;
-- Empty Block, return all U
if (ArrayPtrVar(BlockAddr) = NULL) then
Data := (Data'range => 'U') ;
return ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockkWidthVar -1 downto 0)) ;
if ArrayPtrVar(BlockAddr)(WordAddr) >= 0 then
-- Get the Word from the Array
Data := to_slv(ArrayPtrVar(BlockAddr)(WordAddr), Data'length) ;
elsif ArrayPtrVar(BlockAddr)(WordAddr) = -1 then
-- X in Word, return all X
Data := (Data'range => 'X') ;
else
-- Location Uninitialized, return all X
Data := (Data'range => 'U') ;
end if ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector is
------------------------------------------------------------
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
variable Data : std_logic_vector(DataWidthVar-1 downto 0) ;
begin
MemRead(Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase is
-- Deallocate the memory, but not the array of pointers
------------------------------------------------------------
begin
for BlockAddr in ArrayPtrVar'range loop
if (ArrayPtrVar(BlockAddr) /= NULL) then
deallocate (ArrayPtrVar(BlockAddr)) ;
end if ;
end loop ;
end procedure ;
------------------------------------------------------------
procedure deallocate is
-- Deallocate all allocated memory
------------------------------------------------------------
begin
MemErase ;
deallocate(ArrayPtrVar) ;
AddrWidthVar := -1 ;
DataWidthVar := 1 ;
BlockkWidthVar := 0 ;
end procedure ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar ;
end function GetAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure FileReadX (
-- Hexadecimal or Binary File Read
------------------------------------------------------------
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
-- Format:
-- @hh..h -- Address in hex
-- hhh_XX_ZZ -- data values in hex - space delimited
-- "--" or "//" -- comments
file MemFile : text open READ_MODE is FileName ;
variable Addr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable SmallAddr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable BigAddr : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable Data : std_logic_vector(DataWidthVar - 1 downto 0) ;
variable LineNum : natural ;
variable ItemNum : natural ;
variable AddrInc : std_logic_vector(AddrWidthVar - 1 downto 0) ;
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean ;
variable NextChar : character ;
variable StrLen : integer ;
begin
MultiLineComment := FALSE ;
if StartAddr'length /= AddrWidthVar and EndAddr'length /= AddrWidthVar then
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.FileReadX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
Alert(AlertLogIDVar, "MemoryPType.FileReadX: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
Addr := StartAddr ;
LineNum := 0 ;
if StartAddr <= EndAddr then
SmallAddr := StartAddr ;
BigAddr := EndAddr ;
AddrInc := (AddrWidthVar -1 downto 0 => '0') + 1 ;
else
SmallAddr := EndAddr ;
BigAddr := StartAddr ;
AddrInc := (others => '1') ; -- -1
end if;
ReadLineLoop : while not EndFile(MemFile) loop
ReadLine(MemFile, buf) ;
LineNum := LineNum + 1 ;
ItemNum := 0 ;
ItemLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ItemLoop when Empty ;
ItemNum := ItemNum + 1 ;
NextChar := buf.all(buf'left) ;
if (NextChar = '@') then
-- Get Address
read(buf, NextChar) ;
ReadHexToken(buf, Addr, StrLen) ;
exit ReadLineLoop when AlertIf(AlertLogIDVar, StrLen = 0, "MemoryPType.FileReadX: Address length 0 on line: " & to_string(LineNum), FAILURE) ;
exit ItemLoop when AlertIf(AlertLogIDVar, Addr < SmallAddr,
"MemoryPType.FileReadX: Address in file: " & to_hstring(Addr) &
" < StartAddr: " & to_hstring(StartAddr) & " on line: " & to_string(LineNum)) ;
exit ItemLoop when AlertIf(AlertLogIDVar, Addr > BigAddr,
"MemoryPType.FileReadX: Address in file: " & to_hstring(Addr) &
" > EndAddr: " & to_hstring(BigAddr) & " on line: " & to_string(LineNum)) ;
elsif DataFormat = HEX and ishex(NextChar) then
-- Get Hex Data
ReadHexToken(buf, data, StrLen) ;
exit ReadLineLoop when AlertIfNot(AlertLogIDVar, StrLen > 0,
"MemoryPType.FileReadH: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log("MemoryPType.FileReadX: MemWrite(Addr => " & to_hstring(Addr) & ", Data => " & to_hstring(Data) & ")", DEBUG) ;
MemWrite(Addr, data) ;
Addr := Addr + AddrInc ;
elsif DataFormat = BINARY and isstd_logic(NextChar) then
-- Get Binary Data
-- read(buf, data, ReadValid) ;
ReadBinaryToken(buf, data, StrLen) ;
-- exit ReadLineLoop when AlertIfNot(AlertLogIDVar, ReadValid,
exit ReadLineLoop when AlertIfNot(AlertLogIDVar, StrLen > 0,
"MemoryPType.FileReadB: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log("MemoryPType.FileReadX: MemWrite(Addr => " & to_hstring(Addr) & ", Data => " & to_string(Data) & ")", DEBUG) ;
MemWrite(Addr, data) ;
Addr := Addr + AddrInc ;
else
-- Invalid Text, Issue Warning and skip it
Alert(AlertLogIDVar,
"MemoryPType.FileReadX: Invalid text on line: " & to_string(LineNum) &
" Item: " & to_string(ItemNum) & ". Skipping text: " & buf.all) ;
exit ItemLoop ;
end if ;
end loop ItemLoop ;
end loop ReadLineLoop ;
-- -- must read EndAddr-StartAddr number of words if both start and end specified
-- if (StartAddr /= 0 or (not EndAddr) /= 0) and (Addr /= EndAddr) then
-- Alert("MemoryPType.FileReadH: insufficient data values", WARNING) ;
-- end if ;
file_close(MemFile) ;
end FileReadX ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Read
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string) is
-- Hexadecimal File Read
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadB (
-- Binary File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Read
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string) is
-- Binary File Read
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileReadX(FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- PT Local
procedure FileWriteX (
-- Hexadecimal or Binary File Write
------------------------------------------------------------
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
-- Format:
-- @hh..h -- Address in hex
-- hhhhh -- data one per line in either hex or binary as specified
file MemFile : text open WRITE_MODE is FileName ;
alias normStartAddr : std_logic_vector(StartAddr'length-1 downto 0) is StartAddr ;
alias normEndAddr : std_logic_vector(EndAddr'length-1 downto 0) is EndAddr ;
variable StartBlockAddr : natural ;
variable EndBlockAddr : natural ;
variable StartWordAddr : natural ;
variable EndWordAddr : natural ;
variable Data : std_logic_vector(DataWidthVar - 1 downto 0) ;
variable FoundData : boolean ;
variable buf : line ;
begin
if StartAddr'length /= AddrWidthVar and EndAddr'length /= AddrWidthVar then
-- Check StartAddr and EndAddr Widths and Memory not initialized
if (ArrayPtrVar = NULL) then
Alert(AlertLogIDVar, "MemoryPType.FileWriteX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
AlertIf(AlertLogIDVar, StartAddr'length /= AddrWidthVar, "MemoryPType.FileWriteX: StartAddr'length: "
& to_string(StartAddr'length) &
" /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
AlertIf(AlertLogIDVar, EndAddr'length /= AddrWidthVar, "MemoryPType.FileWriteX: EndAddr'length: "
& to_string(EndAddr'length) &
" /= Memory Address Width: " & to_string(AddrWidthVar), FAILURE) ;
end if ;
return ;
end if ;
if StartAddr > EndAddr then
-- Only support ascending addresses
Alert(AlertLogIDVar, "MemoryPType.FileWriteX: StartAddr: " & to_hstring(StartAddr) &
" > EndAddr: " & to_hstring(EndAddr), FAILURE) ;
return ;
end if ;
-- Slice out upper address to form block address
if AddrWidthVar >= BlockkWidthVar then
StartBlockAddr := to_integer(normStartAddr(AddrWidthVar-1 downto BlockkWidthVar)) ;
EndBlockAddr := to_integer( normEndAddr(AddrWidthVar-1 downto BlockkWidthVar)) ;
else
StartBlockAddr := 0 ;
EndBlockAddr := 0 ;
end if ;
BlockAddrLoop : for BlockAddr in StartBlockAddr to EndBlockAddr loop
next BlockAddrLoop when ArrayPtrVar(BlockAddr) = NULL ;
if BlockAddr = StartBlockAddr then
StartWordAddr := to_integer(normStartAddr(BlockkWidthVar-1 downto 0)) ;
else
StartWordAddr := 0 ;
end if ;
if BlockAddr = EndBlockAddr then
EndWordAddr := to_integer(normEndAddr(BlockkWidthVar-1 downto 0)) ;
else
EndWordAddr := 2**BlockkWidthVar-1 ;
end if ;
FoundData := FALSE ;
WordAddrLoop : for WordAddr in StartWordAddr to EndWordAddr loop
if (ArrayPtrVar(BlockAddr)(WordAddr) < 0) then
-- X in Word, return all X
Data := (Data'range => 'X') ;
FoundData := FALSE ;
else
-- Get the Word from the Array
Data := to_slv(ArrayPtrVar(BlockAddr)(WordAddr), Data'length) ;
if not FoundData then
-- Write Address
write(buf, '@') ;
hwrite(buf, to_slv(BlockAddr, AddrWidthVar-BlockkWidthVar) & to_slv(WordAddr, BlockkWidthVar)) ;
writeline(MemFile, buf) ;
end if ;
FoundData := TRUE ;
end if ;
if FoundData then -- Write Data
if DataFormat = HEX then
hwrite(buf, Data) ;
writeline(MemFile, buf) ;
else
write(buf, Data) ;
writeline(MemFile, buf) ;
end if;
end if ;
end loop WordAddrLoop ;
end loop BlockAddrLoop ;
file_close(MemFile) ;
end FileWriteX ;
------------------------------------------------------------
procedure FileWriteH (
-- Hexadecimal File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Write
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string) is
-- Hexadecimal File Write
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteB (
-- Binary File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Write
------------------------------------------------------------
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string) is
-- Binary File Write
------------------------------------------------------------
constant StartAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '0') ;
constant EndAddr : std_logic_vector(AddrWidthVar - 1 downto 0) := (others => '1') ;
begin
FileWriteX(FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
end protected body MemoryPType ;
end MemoryPkg_2019 ; | artistic-2.0 | 6b71eab7aaf08fbcf3519f30ddb5ff54 | 0.519332 | 4.642519 | false | false | false | false |
juskojan/Bc.FIT | 2BIT/INP/Projekt 1/fpga/ledc8x8.vhd | 1 | 2,239 | --vypracoval Ján Jusko xjusko00
-- 2.11.2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ledc8x8 is
port(
SMCLK: in std_logic;
RESET: in std_logic;
ROW: out std_logic_vector (0 to 7);
LED: out std_logic_vector (0 to 7)
);
end ledc8x8;
architecture behavior of ledc8x8 is
signal ce: std_logic; -- clock enable
signal ce_cnt: std_logic_vector(7 downto 0) := (others => '0'); -- kontrolny citac
signal row_cnt: std_logic_vector(7 downto 0); -- citac riadku
signal inicialy: std_logic_vector(7 downto 0);
begin
--delenie signalu 256
vydelSignal: process(RESET, SMCLK)
begin
if RESET = '1' then
ce_cnt <= "00000000";
elsif (SMCLK'event and SMCLK = '1') then
ce_cnt <= ce_cnt + 1;
end if;
end process vydelSignal;
ce <= '1' when ce_cnt = "10000000" else '0';
--dekoder riadkov
dekoder: process(row_cnt)
begin
case row_cnt is
when "00000001" => inicialy <= "10011111";
when "00000010" => inicialy <= "01101111";
when "00000100" => inicialy <= "01101001";
when "00001000" => inicialy <= "11100110";
when "00010000" => inicialy <= "11100110";
when "00100000" => inicialy <= "11101110";
when "01000000" => inicialy <= "11111110";
when "10000000" => inicialy <= "11111110";
when others => inicialy <= "11111111";
end case;
end process dekoder;
--rotacia riadkov
rotacia: process(RESET, ce)
begin
if RESET = '1' then
row_cnt <= "00000001";
elsif (ce'event and ce = '1') then
case row_cnt is
when "00000001" => row_cnt <= "00000010";
when "00000010" => row_cnt <= "00000100";
when "00000100" => row_cnt <= "00001000";
when "00001000" => row_cnt <= "00010000";
when "00010000" => row_cnt <= "00100000";
when "00100000" => row_cnt <= "01000000";
when "01000000" => row_cnt <= "10000000";
when "10000000" => row_cnt <= "00000001";
when others => null;
end case;
end if;
end process rotacia;
--svietenie
sviet: process(inicialy)
begin
ROW <= row_cnt;
LED <= inicialy;
end process sviet;
end architecture behavior;
| gpl-3.0 | ada90b1b4e3a9fcc4706b29a997e5621 | 0.604288 | 3.013459 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/MROM.vhd | 1 | 3,415 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- LOAD - 000
-- STORE - 001
-- ADD - 010
-- SUB - 011
-- HALT - 100
-- JNZ - 101
-- JNSB - 110
entity MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out std_logic_vector(8 downto 0)
);
end MROM;
architecture Beh_Max of MROM is
subtype inst is std_logic_vector(8 downto 0);
type tROM is array (0 to 63) of inst;
constant ROM: tROM :=(
-- OP_CODE | RAM ADR | N Hex | N DEC | instruction
"000" & "000001", -- 000000 | 00 |LOAD a[0]
"001" & "000110", -- 000001 | 01 |STORE res
"011" & "000010", -- 000010 | 02 |SUB a[1]
"110" & "000110", -- 000011 | 03 |JNSB m1
"000" & "000010", -- 000100 | 04 |LOAD a[1]
"001" & "000110", -- 000101 | 05 |STORE res
"000" & "000110", -- 000110 | 06 |LOAD res : m1
"011" & "000011", -- 000111 | 07 |SUB a[2]
"110" & "001011", -- 001000 | 08 |JNSB m2
"000" & "000011", -- 001001 | 09 |LOAD a[2]
"001" & "000110", -- 001010 | 10 |STORE res
"000" & "000110", -- 001011 | 11 |LOAD res : m2
"011" & "000100", -- 001100 | 12 |SUB a[3]
"110" & "010000", -- 001101 | 13 |JNSB m3
"000" & "000100", -- 001110 | 14 |LOAD a[3]
"001" & "000110", -- 001111 | 15 |STORE res
"000" & "000110", -- 010000 | 16 |LOAD res : m3
"011" & "000101", -- 010001 | 17 |SUB a[4]
"110" & "010101", -- 010010 | 18 |JNSB m4
"000" & "000101", -- 010011 | 19 |LOAD a[4]
"001" & "000110", -- 010100 | 20 |STORE res
"000" & "000110", -- 010101 | 21 |LOAD res : m4
"100" & "000000", -- 010110 | 22 |HALT
others => "100" & "000000"
);
signal data: inst;
begin
data <= ROM(conv_integer(adr));
zbufs: process (RE, data)
begin
if (RE = '1') then
DOUT <= data;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh_Max;
architecture Beh_Zer of MROM is
subtype inst is std_logic_vector(8 downto 0);
type tROM is array (0 to 63) of inst;
constant ROM: tROM :=(
-- OP_CODE | RAM ADR | N Hex | N DEC | instruction
"000" & "000001", -- 000000 | 00 | LOAD a[0]
"101" & "000101", -- 000001 | 01 | JNZ m1
"000" & "000110", -- 000010 | 02 | LOAD res
"010" & "000111", -- 000011 | 03 | ADD 1
"001" & "000110", -- 000100 | 04 | STORE res
"000" & "000010", -- 000101 | 05 | LOAD a[1] : m1
"101" & "001010", -- 000110 | 06 | JNZ m2
"000" & "000110", -- 000111 | 07 | LOAD res
"010" & "000111", -- 001000 | 08 | ADD 1
"001" & "000110", -- 001001 | 09 | STORE res
"000" & "000011", -- 001010 | 10 | LOAD a[2] : m2
"101" & "001111", -- 001011 | 11 | JNZ m3
"000" & "000110", -- 001100 | 12 | LOAD res
"010" & "000111", -- 001101 | 13 | ADD 1
"001" & "000110", -- 001110 | 14 | STORE res
"000" & "000100", -- 001111 | 15 | LOAD a[3] : m3
"101" & "010100", -- 010000 | 16 | JNZ m4
"000" & "000110", -- 010001 | 17 | LOAD res
"010" & "000111", -- 010010 | 18 | ADD 1
"001" & "000110", -- 010011 | 19 | STORE res
"000" & "000101", -- 010100 | 20 | LOAD a[4] : m4
"101" & "011001", -- 010101 | 21 | JNZ m5
"000" & "000110", -- 010110 | 22 | LOAD res
"010" & "000111", -- 010111 | 23 | ADD 1
"001" & "000110", -- 011000 | 24 | STORE res
"100" & "000000", -- 011001 | 25 | HALT : m5
others => "100" & "000000"
);
signal data: inst;
begin
data <= ROM(conv_integer(adr));
zbufs: process (RE, data)
begin
if (RE = '1') then
DOUT <= data;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh_Zer; | mit | 8e3f2fce30d41f709ff6a5dee6c27070 | 0.551098 | 2.369882 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_sim_netlist.vhdl | 1 | 217,579 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:50:59 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_sim_netlist.vhdl
-- Design : ip_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_crossbar_v2_1_15_addr_arbiter_sasd is
port (
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_ready_d0_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_2\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_atarget_enc_reg[1]_2\ : in STD_LOGIC;
\gen_axilite.s_axi_arready_i_reg\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_3\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_crossbar_v2_1_15_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_15_addr_arbiter_sasd";
end ip_design_xbar_0_axi_crossbar_v2_1_15_addr_arbiter_sasd;
architecture STRUCTURE of ip_design_xbar_0_axi_crossbar_v2_1_15_addr_arbiter_sasd is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_grant_any : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_1\ : STD_LOGIC;
signal \^gen_axilite.s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[5]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_10_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_11_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_12_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_5_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_6_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_7_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_8_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_9_n_0\ : STD_LOGIC;
signal \^m_axi_arprot[2]\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_12\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_9\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_bready[4]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair16";
begin
SR(0) <= \^sr\(0);
aa_grant_rnw <= \^aa_grant_rnw\;
\gen_axilite.s_axi_bvalid_i_reg\ <= \^gen_axilite.s_axi_bvalid_i_reg\;
\gen_axilite.s_axi_bvalid_i_reg_0\ <= \^gen_axilite.s_axi_bvalid_i_reg_0\;
\gen_axilite.s_axi_bvalid_i_reg_1\ <= \^gen_axilite.s_axi_bvalid_i_reg_1\;
\gen_axilite.s_axi_rvalid_i_reg\ <= \^gen_axilite.s_axi_rvalid_i_reg\;
\m_axi_arprot[2]\(34 downto 0) <= \^m_axi_arprot[2]\(34 downto 0);
m_ready_d0(0) <= \^m_ready_d0\(0);
m_valid_i <= \^m_valid_i\;
\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5C505050F0F0F0F0"
)
port map (
I0 => \^gen_axilite.s_axi_bvalid_i_reg\,
I1 => mi_wready(0),
I2 => mi_bvalid(0),
I3 => \^gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \^gen_axilite.s_axi_bvalid_i_reg_1\,
I5 => Q(6),
O => \gen_axilite.s_axi_bvalid_i_reg_2\
);
\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => m_ready_d(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_bvalid_i_reg_1\
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d_1(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_rvalid_i_reg\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF5300000050"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aa_grant_any,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^m_axi_arprot[2]\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^m_axi_arprot[2]\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^m_axi_arprot[2]\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^m_axi_arprot[2]\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^m_axi_arprot[2]\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^m_axi_arprot[2]\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^m_axi_arprot[2]\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^m_axi_arprot[2]\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^m_axi_arprot[2]\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^m_axi_arprot[2]\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^m_axi_arprot[2]\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^m_axi_arprot[2]\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^m_axi_arprot[2]\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^m_axi_arprot[2]\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^m_axi_arprot[2]\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^m_axi_arprot[2]\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^m_axi_arprot[2]\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^m_axi_arprot[2]\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^m_axi_arprot[2]\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^m_axi_arprot[2]\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^m_axi_arprot[2]\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^m_axi_arprot[2]\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^m_axi_arprot[2]\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^m_axi_arprot[2]\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^m_axi_arprot[2]\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^m_axi_arprot[2]\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^m_axi_arprot[2]\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^m_axi_arprot[2]\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^m_axi_arprot[2]\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^m_axi_arprot[2]\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^m_axi_arprot[2]\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^m_axi_arprot[2]\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^m_axi_arprot[2]\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^m_axi_arprot[2]\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^m_axi_arprot[2]\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AAA800000000"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => aresetn_d,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00EFFFFFFFEFFFFF"
)
port map (
I0 => \m_ready_d_reg[0]_1\,
I1 => \m_ready_d_reg[1]\,
I2 => \^m_ready_d0\(0),
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => \m_ready_d[0]_i_4_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30020002"
)
port map (
I0 => m_axi_wready(0),
I1 => \m_atarget_enc_reg[2]_3\(2),
I2 => \m_atarget_enc_reg[2]_3\(1),
I3 => \m_atarget_enc_reg[2]_3\(0),
I4 => m_axi_wready(1),
O => \gen_no_arbiter.m_valid_i_reg_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => aa_grant_any,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8AAA"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_3_n_0\,
I2 => \m_atarget_hot[6]_i_5_n_0\,
I3 => \m_atarget_hot[5]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(0)
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_4_n_0\,
I2 => \m_atarget_hot[6]_i_3_n_0\,
I3 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(1)
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000020AAAAAAAA"
)
port map (
I0 => aresetn_d,
I1 => \m_atarget_hot[6]_i_6_n_0\,
I2 => \m_atarget_hot[6]_i_5_n_0\,
I3 => \m_atarget_hot[6]_i_4_n_0\,
I4 => \m_atarget_hot[6]_i_3_n_0\,
I5 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_enc_reg[2]\(2)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_4_n_0\,
I1 => aa_grant_any,
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_3_n_0\,
I1 => aa_grant_any,
O => D(1)
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[6]_i_6_n_0\,
I1 => aa_grant_any,
O => D(2)
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \m_atarget_hot[6]_i_5_n_0\,
O => D(3)
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[4]_i_2_n_0\,
I1 => aa_grant_any,
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arprot[2]\(17),
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \^m_axi_arprot[2]\(16),
I3 => \^m_axi_arprot[2]\(19),
I4 => \^m_axi_arprot[2]\(18),
I5 => \m_atarget_hot[6]_i_7_n_0\,
O => \m_atarget_hot[4]_i_2_n_0\
);
\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \m_atarget_hot[5]_i_2_n_0\,
O => D(5)
);
\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \m_atarget_hot[6]_i_7_n_0\,
I1 => \^m_axi_arprot[2]\(17),
I2 => \m_atarget_hot[6]_i_8_n_0\,
I3 => \^m_axi_arprot[2]\(19),
I4 => \^m_axi_arprot[2]\(18),
I5 => \^m_axi_arprot[2]\(16),
O => \m_atarget_hot[5]_i_2_n_0\
);
\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000020000000000"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[6]_i_3_n_0\,
I2 => \m_atarget_hot[6]_i_4_n_0\,
I3 => \m_atarget_hot[6]_i_5_n_0\,
I4 => \m_atarget_hot[6]_i_6_n_0\,
I5 => aa_grant_any,
O => D(6)
);
\m_atarget_hot[6]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \^m_axi_arprot[2]\(24),
I1 => \^m_axi_arprot[2]\(20),
I2 => \^m_axi_arprot[2]\(21),
I3 => \^m_axi_arprot[2]\(23),
I4 => \^m_axi_arprot[2]\(22),
I5 => \^m_axi_arprot[2]\(25),
O => \m_atarget_hot[6]_i_10_n_0\
);
\m_atarget_hot[6]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^m_axi_arprot[2]\(18),
I1 => \^m_axi_arprot[2]\(19),
I2 => \^m_axi_arprot[2]\(16),
I3 => \^m_axi_arprot[2]\(13),
I4 => \^m_axi_arprot[2]\(12),
O => \m_atarget_hot[6]_i_11_n_0\
);
\m_atarget_hot[6]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^m_axi_arprot[2]\(19),
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(16),
O => \m_atarget_hot[6]_i_12_n_0\
);
\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \m_atarget_hot[6]_i_7_n_0\,
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(19),
I3 => \m_atarget_hot[6]_i_8_n_0\,
I4 => \^m_axi_arprot[2]\(17),
O => \m_atarget_hot[6]_i_2_n_0\
);
\m_atarget_hot[6]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \m_atarget_hot[6]_i_9_n_0\,
I1 => \m_atarget_hot[6]_i_10_n_0\,
I2 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_3_n_0\
);
\m_atarget_hot[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \m_atarget_hot[6]_i_11_n_0\,
I3 => \^m_axi_arprot[2]\(14),
I4 => \^m_axi_arprot[2]\(17),
I5 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_4_n_0\
);
\m_atarget_hot[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \m_atarget_hot[6]_i_8_n_0\,
I2 => \m_atarget_hot[6]_i_12_n_0\,
I3 => \^m_axi_arprot[2]\(14),
I4 => \^m_axi_arprot[2]\(17),
I5 => \^m_axi_arprot[2]\(15),
O => \m_atarget_hot[6]_i_5_n_0\
);
\m_atarget_hot[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \m_atarget_hot[6]_i_10_n_0\,
I1 => \^m_axi_arprot[2]\(17),
I2 => \m_atarget_hot[6]_i_8_n_0\,
I3 => \^m_axi_arprot[2]\(16),
I4 => \^m_axi_arprot[2]\(19),
I5 => \^m_axi_arprot[2]\(18),
O => \m_atarget_hot[6]_i_6_n_0\
);
\m_atarget_hot[6]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFDFF"
)
port map (
I0 => \^m_axi_arprot[2]\(24),
I1 => \^m_axi_arprot[2]\(20),
I2 => \^m_axi_arprot[2]\(25),
I3 => \^m_axi_arprot[2]\(21),
I4 => \^m_axi_arprot[2]\(23),
I5 => \^m_axi_arprot[2]\(22),
O => \m_atarget_hot[6]_i_7_n_0\
);
\m_atarget_hot[6]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \^m_axi_arprot[2]\(26),
I1 => \^m_axi_arprot[2]\(29),
I2 => \^m_axi_arprot[2]\(27),
I3 => \^m_axi_arprot[2]\(30),
I4 => \^m_axi_arprot[2]\(31),
I5 => \^m_axi_arprot[2]\(28),
O => \m_atarget_hot[6]_i_8_n_0\
);
\m_atarget_hot[6]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^m_axi_arprot[2]\(16),
I1 => \^m_axi_arprot[2]\(18),
I2 => \^m_axi_arprot[2]\(19),
I3 => \m_atarget_hot[6]_i_8_n_0\,
I4 => \^m_axi_arprot[2]\(17),
O => \m_atarget_hot[6]_i_9_n_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(3)
);
\m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(4)
);
\m_axi_arvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => Q(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(1),
O => m_axi_arvalid(5)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(3)
);
\m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(4)
);
\m_axi_awvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => Q(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(5)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(0),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(1),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(2),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(3),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(4),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(4)
);
\m_axi_bready[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(5),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(5)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(0),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(1),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(2),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(3),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(3)
);
\m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(4),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(4)
);
\m_axi_wvalid[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => Q(5),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(5)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_1(0),
I4 => sr_rvalid,
O => E(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(0),
O => \^gen_axilite.s_axi_bvalid_i_reg\
);
\m_ready_d[0]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \m_ready_d_reg[0]_0\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFA8AA"
)
port map (
I0 => \^gen_axilite.s_axi_rvalid_i_reg\,
I1 => \m_atarget_enc_reg[1]_2\,
I2 => \gen_axilite.s_axi_arready_i_reg\,
I3 => \m_atarget_enc_reg[1]_3\,
I4 => m_ready_d_1(1),
I5 => m_valid_i_reg_0,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(1),
O => \^gen_axilite.s_axi_bvalid_i_reg_0\
);
\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFDFF00FF00FF00"
)
port map (
I0 => \m_atarget_enc_reg[1]_3\,
I1 => \gen_axilite.s_axi_arready_i_reg\,
I2 => \m_atarget_enc_reg[1]_2\,
I3 => m_ready_d_1(1),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => m_ready_d0_0(0)
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FFFDFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \m_atarget_enc_reg[2]_2\,
I2 => \m_atarget_enc_reg[1]_0\,
I3 => m_ready_d(2),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \^m_ready_d0\(0)
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(1),
I1 => m_valid_i_i_2_n_0,
I2 => m_valid_i_i_3_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => sr_rvalid,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_rready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAA8AAA8AAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d_1(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => \m_atarget_enc_reg[0]\,
I5 => \m_atarget_enc_reg[1]_1\,
O => m_valid_i_i_3_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \m_atarget_enc_reg[1]\,
O => s_axi_bvalid(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_grant_any,
I1 => sr_rvalid,
O => s_axi_rvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \m_atarget_enc_reg[2]_0\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \aresetn_d_reg[1]\(0),
I1 => m_valid_i_i_3_n_0,
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_crossbar_v2_1_15_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[1]_1\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\m_ready_d_reg[2]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_crossbar_v2_1_15_decerr_slave : entity is "axi_crossbar_v2_1_15_decerr_slave";
end ip_design_xbar_0_axi_crossbar_v2_1_15_decerr_slave;
architecture STRUCTURE of ip_design_xbar_0_axi_crossbar_v2_1_15_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal m_valid_i_i_6_n_0 : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F07F0000"
)
port map (
I0 => Q(0),
I1 => \m_ready_d_reg[1]_2\,
I2 => mi_arready(6),
I3 => mi_rvalid(6),
I4 => aresetn_d,
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
Q => mi_arready(6),
R => '0'
);
\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => \m_ready_d_reg[2]_0\,
I3 => Q(0),
I4 => \^mi_wready\(0),
O => \gen_axilite.s_axi_awready_i_i_1_n_0\
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_i_1_n_0\,
Q => \^mi_wready\(0),
R => SR(0)
);
\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_reg_0\,
Q => \^mi_bvalid\(0),
R => SR(0)
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF8800"
)
port map (
I0 => mi_arready(6),
I1 => \m_ready_d_reg[1]_2\,
I2 => aa_rready,
I3 => Q(0),
I4 => mi_rvalid(6),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
Q => mi_rvalid(6),
R => SR(0)
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"08300800"
)
port map (
I0 => mi_arready(6),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_arready(0),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F3F5FFFFF3F5F"
)
port map (
I0 => m_axi_awready(0),
I1 => m_axi_awready(1),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => \^mi_wready\(0),
O => \m_ready_d_reg[2]\
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF08030800"
)
port map (
I0 => m_axi_rvalid(2),
I1 => \m_atarget_enc_reg[2]\(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rvalid(0),
I5 => m_valid_i_i_6_n_0,
O => m_valid_i_reg
);
m_valid_i_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"08300800"
)
port map (
I0 => mi_rvalid(6),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rvalid(1),
O => m_valid_i_i_6_n_0
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A008A8A"
)
port map (
I0 => \m_atarget_enc_reg[1]_0\,
I1 => \m_atarget_enc_reg[1]_1\,
I2 => m_axi_bvalid(1),
I3 => \m_atarget_enc_reg[2]_2\,
I4 => m_axi_bvalid(2),
I5 => \^m_ready_d_reg[0]_0\,
O => \m_ready_d_reg[0]\
);
\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00830080"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => m_axi_bvalid(0),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008A008A8A"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[1]\,
I2 => m_axi_wready(0),
I3 => \m_atarget_enc_reg[2]_1\,
I4 => m_axi_wready(2),
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d_reg[1]\
);
\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B000800"
)
port map (
I0 => \^mi_wready\(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_crossbar_v2_1_15_splitter is
port (
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
\gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_2\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[0]_3\ : out STD_LOGIC;
\m_ready_d_reg[1]_2\ : out STD_LOGIC;
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\gen_axilite.s_axi_awready_i_reg\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
aresetn_d : in STD_LOGIC;
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_crossbar_v2_1_15_splitter : entity is "axi_crossbar_v2_1_15_splitter";
end ip_design_xbar_0_axi_crossbar_v2_1_15_splitter;
architecture STRUCTURE of ip_design_xbar_0_axi_crossbar_v2_1_15_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_3_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_8_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_ready_d[2]_i_5\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_6\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_8\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_3\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_4\ : label is "soft_lutpair27";
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[0]_1\ <= \^m_ready_d_reg[0]_1\;
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \^m_ready_d_reg[1]_0\,
I2 => \m_atarget_enc_reg[2]_0\,
I3 => \gen_axilite.s_axi_awready_i_reg\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
O => \gen_no_arbiter.m_valid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_atarget_enc_reg[1]\,
I2 => \gen_no_arbiter.grant_rnw_reg_0\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BA000000"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_atarget_enc_reg[2]\,
I2 => \gen_no_arbiter.grant_rnw_reg\,
I3 => \m_ready_d[2]_i_3_n_0\,
I4 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_ready_d0(0),
I1 => \m_ready_d[2]_i_3_n_0\,
I2 => aresetn_d,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABBFFFF"
)
port map (
I0 => \^m_ready_d_reg[0]_0\,
I1 => \^m_ready_d\(1),
I2 => \m_atarget_enc_reg[2]\,
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => m_ready_d0(0),
O => \m_ready_d[2]_i_3_n_0\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"23002000"
)
port map (
I0 => m_axi_awready(3),
I1 => Q(2),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_awready(2),
O => \m_ready_d_reg[2]_1\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00320002"
)
port map (
I0 => m_axi_awready(0),
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => m_axi_awready(1),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00045555"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \^m_ready_d_reg[0]_1\,
I2 => \m_ready_d[2]_i_8_n_0\,
I3 => \gen_axilite.s_axi_bvalid_i_reg\,
I4 => \gen_no_arbiter.grant_rnw_reg_0\,
O => \^m_ready_d_reg[0]_0\
);
\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C080008"
)
port map (
I0 => m_axi_bvalid(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_bvalid(4),
O => \m_ready_d[2]_i_8_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF053FFFFFF53F"
)
port map (
I0 => m_axi_bvalid(0),
I1 => m_axi_bvalid(1),
I2 => Q(1),
I3 => Q(0),
I4 => Q(2),
I5 => m_axi_bvalid(2),
O => \^m_ready_d_reg[0]_1\
);
\s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
O => \m_ready_d_reg[0]_2\
);
\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => \m_ready_d_reg[0]_3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF530FFFFF53FF"
)
port map (
I0 => m_axi_wready(2),
I1 => m_axi_wready(0),
I2 => Q(2),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_wready(1),
O => \^m_ready_d_reg[1]_0\
);
\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
O => \m_ready_d_reg[1]_1\
);
\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => \m_ready_d_reg[1]_2\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ip_design_xbar_0_axi_crossbar_v2_1_15_splitter__parameterized0\ is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
sr_rvalid : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ip_design_xbar_0_axi_crossbar_v2_1_15_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_15_splitter";
end \ip_design_xbar_0_axi_crossbar_v2_1_15_splitter__parameterized0\;
architecture STRUCTURE of \ip_design_xbar_0_axi_crossbar_v2_1_15_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0080"
)
port map (
I0 => sr_rvalid,
I1 => \m_payload_i_reg[0]\(0),
I2 => s_axi_rready(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^m_ready_d\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => m_valid_i_reg,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FF5F3FFFFF5F3F"
)
port map (
I0 => m_axi_arready(2),
I1 => m_axi_arready(1),
I2 => Q(1),
I3 => Q(0),
I4 => Q(2),
I5 => m_axi_arready(4),
O => \m_ready_d_reg[1]_1\
);
\m_ready_d[1]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => m_axi_arready(3),
I1 => Q(1),
I2 => Q(2),
I3 => Q(0),
I4 => m_axi_arready(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_register_slice_v2_1_14_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
m_valid_i_reg_0 : out STD_LOGIC;
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_hot_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_register_slice_v2_1_14_axic_register_slice : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end ip_design_xbar_0_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of ip_design_xbar_0_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[10]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_3_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair21";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_rready <= \^aa_rready\;
m_valid_i_reg_1(1 downto 0) <= \^m_valid_i_reg_1\(1 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_1\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_1\(0),
Q => \^m_valid_i_reg_1\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(3),
O => m_axi_rready(3)
);
\m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(4),
O => m_axi_rready(4)
);
\m_axi_rready[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[5]\(5),
O => m_axi_rready(5)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CA000F00CA0000"
)
port map (
I0 => m_axi_rdata(135),
I1 => m_axi_rdata(167),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(7),
O => \m_payload_i[10]_i_2_n_0\
);
\m_payload_i[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(71),
I1 => m_axi_rdata(103),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(39),
O => \m_payload_i[10]_i_3_n_0\
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(8),
I1 => m_axi_rdata(168),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(136),
O => \m_payload_i[11]_i_2_n_0\
);
\m_payload_i[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_axi_rdata(40),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(104),
O => \m_payload_i[11]_i_3_n_0\
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(9),
I1 => m_axi_rdata(137),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(169),
O => \m_payload_i[12]_i_2_n_0\
);
\m_payload_i[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_axi_rdata(41),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(105),
O => \m_payload_i[12]_i_3_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(10),
I1 => m_axi_rdata(138),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(170),
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_axi_rdata(42),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(106),
O => \m_payload_i[13]_i_3_n_0\
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(11),
I1 => m_axi_rdata(139),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(171),
O => \m_payload_i[14]_i_2_n_0\
);
\m_payload_i[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0F0A000C000A00"
)
port map (
I0 => m_axi_rdata(43),
I1 => m_axi_rdata(107),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(75),
O => \m_payload_i[14]_i_3_n_0\
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(76),
I1 => m_axi_rdata(44),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(108),
O => \m_payload_i[15]_i_2_n_0\
);
\m_payload_i[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_axi_rdata(140),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(172),
O => \m_payload_i[15]_i_3_n_0\
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(13),
I1 => m_axi_rdata(141),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(173),
O => \m_payload_i[16]_i_2_n_0\
);
\m_payload_i[16]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(77),
I1 => m_axi_rdata(45),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(109),
O => \m_payload_i[16]_i_3_n_0\
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(14),
I1 => m_axi_rdata(142),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(174),
O => \m_payload_i[17]_i_2_n_0\
);
\m_payload_i[17]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(78),
I1 => m_axi_rdata(46),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(110),
O => \m_payload_i[17]_i_3_n_0\
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(15),
I1 => m_axi_rdata(175),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(143),
O => \m_payload_i[18]_i_2_n_0\
);
\m_payload_i[18]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(79),
I1 => m_axi_rdata(47),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(111),
O => \m_payload_i[18]_i_3_n_0\
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(16),
I1 => m_axi_rdata(176),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(144),
O => \m_payload_i[19]_i_2_n_0\
);
\m_payload_i[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_axi_rdata(112),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(48),
O => \m_payload_i[19]_i_3_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[1]_i_2_n_0\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_rresp(8),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(2),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rresp(0),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rresp(4),
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00A2AAAA0AA2AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(6),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(10),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(17),
I1 => m_axi_rdata(177),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(145),
O => \m_payload_i[20]_i_2_n_0\
);
\m_payload_i[20]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(113),
I1 => m_axi_rdata(49),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(81),
O => \m_payload_i[20]_i_3_n_0\
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(18),
I1 => m_axi_rdata(146),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(178),
O => \m_payload_i[21]_i_2_n_0\
);
\m_payload_i[21]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(82),
I1 => m_axi_rdata(50),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(114),
O => \m_payload_i[21]_i_3_n_0\
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(19),
I1 => m_axi_rdata(179),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(147),
O => \m_payload_i[22]_i_2_n_0\
);
\m_payload_i[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(83),
I1 => m_axi_rdata(51),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(115),
O => \m_payload_i[22]_i_3_n_0\
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(20),
I1 => m_axi_rdata(180),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(148),
O => \m_payload_i[23]_i_2_n_0\
);
\m_payload_i[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(84),
I1 => m_axi_rdata(52),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(116),
O => \m_payload_i[23]_i_3_n_0\
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(21),
I1 => m_axi_rdata(149),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(181),
O => \m_payload_i[24]_i_2_n_0\
);
\m_payload_i[24]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_axi_rdata(53),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(117),
O => \m_payload_i[24]_i_3_n_0\
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(22),
I1 => m_axi_rdata(150),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(182),
O => \m_payload_i[25]_i_2_n_0\
);
\m_payload_i[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(86),
I1 => m_axi_rdata(54),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(118),
O => \m_payload_i[25]_i_3_n_0\
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_axi_rdata(183),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(151),
O => \m_payload_i[26]_i_2_n_0\
);
\m_payload_i[26]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(87),
I1 => m_axi_rdata(55),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(119),
O => \m_payload_i[26]_i_3_n_0\
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(24),
I1 => m_axi_rdata(184),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(152),
O => \m_payload_i[27]_i_2_n_0\
);
\m_payload_i[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(120),
I1 => m_axi_rdata(56),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(88),
O => \m_payload_i[27]_i_3_n_0\
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(121),
I1 => m_axi_rdata(57),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(89),
O => \m_payload_i[28]_i_2_n_0\
);
\m_payload_i[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_axi_rdata(153),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(185),
O => \m_payload_i[28]_i_3_n_0\
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(122),
I1 => m_axi_rdata(58),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(90),
O => \m_payload_i[29]_i_2_n_0\
);
\m_payload_i[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(26),
I1 => m_axi_rdata(154),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(186),
O => \m_payload_i[29]_i_3_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
I4 => \m_payload_i[2]_i_4_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02300200"
)
port map (
I0 => m_axi_rresp(9),
I1 => \m_atarget_enc_reg[2]\(1),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => m_axi_rresp(3),
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => m_axi_rresp(1),
I1 => \m_atarget_enc_reg[2]\(2),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => m_axi_rresp(5),
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A00A2AAAA0AA2AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(7),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rresp(11),
O => \m_payload_i[2]_i_4_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(27),
I1 => m_axi_rdata(155),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(187),
O => \m_payload_i[30]_i_2_n_0\
);
\m_payload_i[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_axi_rdata(123),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(59),
O => \m_payload_i[30]_i_3_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(92),
I1 => m_axi_rdata(60),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(124),
O => \m_payload_i[31]_i_2_n_0\
);
\m_payload_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_axi_rdata(156),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(188),
O => \m_payload_i[31]_i_3_n_0\
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[32]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0F0C000A000C00"
)
port map (
I0 => m_axi_rdata(125),
I1 => m_axi_rdata(61),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(93),
O => \m_payload_i[32]_i_2_n_0\
);
\m_payload_i[32]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(29),
I1 => m_axi_rdata(157),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(189),
O => \m_payload_i[32]_i_3_n_0\
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(30),
I1 => m_axi_rdata(158),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(190),
O => \m_payload_i[33]_i_2_n_0\
);
\m_payload_i[33]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(94),
I1 => m_axi_rdata(62),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(126),
O => \m_payload_i[33]_i_3_n_0\
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(31),
I1 => m_axi_rdata(159),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(191),
O => \m_payload_i[34]_i_3_n_0\
);
\m_payload_i[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_axi_rdata(63),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(127),
O => \m_payload_i[34]_i_4_n_0\
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(0),
I1 => m_axi_rdata(128),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(160),
O => \m_payload_i[3]_i_2_n_0\
);
\m_payload_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_axi_rdata(96),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(32),
O => \m_payload_i[3]_i_3_n_0\
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(1),
I1 => m_axi_rdata(161),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(129),
O => \m_payload_i[4]_i_2_n_0\
);
\m_payload_i[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(65),
I1 => m_axi_rdata(33),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(97),
O => \m_payload_i[4]_i_3_n_0\
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(2),
I1 => m_axi_rdata(130),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(162),
O => \m_payload_i[5]_i_2_n_0\
);
\m_payload_i[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(66),
I1 => m_axi_rdata(34),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(98),
O => \m_payload_i[5]_i_3_n_0\
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_axi_rdata(163),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(131),
O => \m_payload_i[6]_i_2_n_0\
);
\m_payload_i[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_axi_rdata(99),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(35),
O => \m_payload_i[6]_i_3_n_0\
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CF000A00C0000A"
)
port map (
I0 => m_axi_rdata(4),
I1 => m_axi_rdata(164),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(1),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rdata(132),
O => \m_payload_i[7]_i_2_n_0\
);
\m_payload_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(68),
I1 => m_axi_rdata(36),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(100),
O => \m_payload_i[7]_i_3_n_0\
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(5),
I1 => m_axi_rdata(133),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(165),
O => \m_payload_i[8]_i_2_n_0\
);
\m_payload_i[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_axi_rdata(37),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(101),
O => \m_payload_i[8]_i_3_n_0\
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
I2 => \^aa_rready\,
I3 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FC0A00000C0A"
)
port map (
I0 => m_axi_rdata(6),
I1 => m_axi_rdata(134),
I2 => \m_atarget_enc_reg[2]\(0),
I3 => \m_atarget_enc_reg[2]\(2),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(166),
O => \m_payload_i[9]_i_2_n_0\
);
\m_payload_i[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_rdata(70),
I1 => m_axi_rdata(38),
I2 => \m_atarget_enc_reg[2]\(2),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(1),
I5 => m_axi_rdata(102),
O => \m_payload_i[9]_i_3_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => \^sr_rvalid\,
I1 => \^q\(0),
I2 => s_axi_rready(0),
I3 => aa_grant_rnw,
I4 => m_valid_i,
I5 => m_ready_d(0),
O => \m_ready_d_reg[1]\
);
m_valid_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF05F3FFFFF5F3F"
)
port map (
I0 => m_axi_rvalid(1),
I1 => m_axi_rvalid(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \m_atarget_enc_reg[2]\(0),
I4 => \m_atarget_enc_reg[2]\(2),
I5 => m_axi_rvalid(2),
O => m_valid_i_reg_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7FFF00"
)
port map (
I0 => \m_atarget_enc_reg[2]\(2),
I1 => \m_atarget_enc_reg[2]\(0),
I2 => \m_atarget_enc_reg[2]\(1),
I3 => \skid_buffer_reg_n_0_[0]\,
I4 => \^aa_rready\,
O => skid_buffer(0)
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[10]_i_2_n_0\,
I1 => \m_payload_i[10]_i_3_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \m_payload_i[11]_i_3_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[12]_i_2_n_0\,
I1 => \m_payload_i[12]_i_3_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[13]_i_2_n_0\,
I1 => \m_payload_i[13]_i_3_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[14]_i_2_n_0\,
I1 => \m_payload_i[14]_i_3_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[15]_i_2_n_0\,
I1 => \m_payload_i[15]_i_3_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[16]_i_2_n_0\,
I1 => \m_payload_i[16]_i_3_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[17]_i_2_n_0\,
I1 => \m_payload_i[17]_i_3_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[18]_i_2_n_0\,
I1 => \m_payload_i[18]_i_3_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[19]_i_2_n_0\,
I1 => \m_payload_i[19]_i_3_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[20]_i_2_n_0\,
I1 => \m_payload_i[20]_i_3_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \m_payload_i[21]_i_3_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[22]_i_2_n_0\,
I1 => \m_payload_i[22]_i_3_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \m_payload_i[23]_i_3_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[24]_i_2_n_0\,
I1 => \m_payload_i[24]_i_3_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[25]_i_2_n_0\,
I1 => \m_payload_i[25]_i_3_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[26]_i_2_n_0\,
I1 => \m_payload_i[26]_i_3_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[27]_i_2_n_0\,
I1 => \m_payload_i[27]_i_3_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[28]_i_2_n_0\,
I1 => \m_payload_i[28]_i_3_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[29]_i_2_n_0\,
I1 => \m_payload_i[29]_i_3_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[30]_i_2_n_0\,
I1 => \m_payload_i[30]_i_3_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[31]_i_2_n_0\,
I1 => \m_payload_i[31]_i_3_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \m_payload_i[32]_i_3_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[33]_i_2_n_0\,
I1 => \m_payload_i[33]_i_3_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
I1 => \m_payload_i[34]_i_4_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[3]_i_2_n_0\,
I1 => \m_payload_i[3]_i_3_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[4]_i_2_n_0\,
I1 => \m_payload_i[4]_i_3_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[5]_i_2_n_0\,
I1 => \m_payload_i[5]_i_3_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[6]_i_2_n_0\,
I1 => \m_payload_i[6]_i_3_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[7]_i_2_n_0\,
I1 => \m_payload_i[7]_i_3_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[8]_i_2_n_0\,
I1 => \m_payload_i[8]_i_3_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \m_payload_i[9]_i_3_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_crossbar_v2_1_15_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_crossbar_v2_1_15_crossbar_sasd : entity is "axi_crossbar_v2_1_15_crossbar_sasd";
end ip_design_xbar_0_axi_crossbar_v2_1_15_crossbar_sasd;
architecture STRUCTURE of ip_design_xbar_0_axi_crossbar_v2_1_15_crossbar_sasd is
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_10 : STD_LOGIC;
signal addr_arbiter_inst_n_19 : STD_LOGIC;
signal addr_arbiter_inst_n_27 : STD_LOGIC;
signal addr_arbiter_inst_n_3 : STD_LOGIC;
signal addr_arbiter_inst_n_34 : STD_LOGIC;
signal addr_arbiter_inst_n_35 : STD_LOGIC;
signal addr_arbiter_inst_n_36 : STD_LOGIC;
signal addr_arbiter_inst_n_38 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_46 : STD_LOGIC;
signal addr_arbiter_inst_n_47 : STD_LOGIC;
signal addr_arbiter_inst_n_51 : STD_LOGIC;
signal addr_arbiter_inst_n_52 : STD_LOGIC;
signal addr_arbiter_inst_n_53 : STD_LOGIC;
signal addr_arbiter_inst_n_6 : STD_LOGIC;
signal addr_arbiter_inst_n_8 : STD_LOGIC;
signal addr_arbiter_inst_n_89 : STD_LOGIC;
signal addr_arbiter_inst_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_atarget_hot : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 5 downto 3 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 2 to 2 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_bvalid : STD_LOGIC_VECTOR ( 6 to 6 );
signal mi_wready : STD_LOGIC_VECTOR ( 6 to 6 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_37 : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
signal splitter_ar_n_1 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_10 : STD_LOGIC;
signal splitter_aw_n_11 : STD_LOGIC;
signal splitter_aw_n_12 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal splitter_aw_n_7 : STD_LOGIC;
signal splitter_aw_n_8 : STD_LOGIC;
signal splitter_aw_n_9 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
begin
addr_arbiter_inst: entity work.ip_design_xbar_0_axi_crossbar_v2_1_15_addr_arbiter_sasd
port map (
D(6) => addr_arbiter_inst_n_4,
D(5) => m_atarget_hot0(5),
D(4) => addr_arbiter_inst_n_6,
D(3) => m_atarget_hot0(3),
D(2) => addr_arbiter_inst_n_8,
D(1) => addr_arbiter_inst_n_9,
D(0) => addr_arbiter_inst_n_10,
E(0) => p_1_in,
Q(6 downto 0) => m_atarget_hot(6 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\aresetn_d_reg[1]\(1) => reg_slice_r_n_45,
\aresetn_d_reg[1]\(0) => reg_slice_r_n_46,
\gen_axilite.s_axi_arready_i_reg\ => \gen_decerr.decerr_slave_inst_n_7\,
\gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_19,
\gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_27,
\gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_34,
\gen_axilite.s_axi_bvalid_i_reg_2\ => addr_arbiter_inst_n_89,
\gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_38,
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_47,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_2\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_7,
\m_atarget_enc_reg[1]_1\ => reg_slice_r_n_38,
\m_atarget_enc_reg[1]_2\ => splitter_ar_n_0,
\m_atarget_enc_reg[1]_3\ => splitter_ar_n_1,
\m_atarget_enc_reg[2]\(2) => addr_arbiter_inst_n_51,
\m_atarget_enc_reg[2]\(1) => addr_arbiter_inst_n_52,
\m_atarget_enc_reg[2]\(0) => addr_arbiter_inst_n_53,
\m_atarget_enc_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_9,
\m_atarget_enc_reg[2]_3\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_axi_arprot[2]\(34 downto 0) => Q(34 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_wready(1) => m_axi_wready(3),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
m_ready_d0_0(0) => m_ready_d0(1),
m_ready_d_1(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_3,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_46,
\m_ready_d_reg[0]_1\ => splitter_aw_n_0,
\m_ready_d_reg[1]\ => splitter_aw_n_5,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_36,
m_valid_i_reg_0 => reg_slice_r_n_2,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_35,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.ip_design_xbar_0_axi_crossbar_v2_1_15_decerr_slave
port map (
Q(0) => m_atarget_hot(6),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_89,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_27,
\m_atarget_enc_reg[1]\ => splitter_aw_n_10,
\m_atarget_enc_reg[1]_0\ => splitter_aw_n_4,
\m_atarget_enc_reg[1]_1\ => splitter_aw_n_8,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_enc_reg[2]_0\ => splitter_aw_n_6,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_12,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_11,
m_axi_arready(0) => m_axi_arready(1),
m_axi_awready(1 downto 0) => m_axi_awready(5 downto 4),
m_axi_bvalid(2 downto 1) => m_axi_bvalid(5 downto 4),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rvalid(2) => m_axi_rvalid(5),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(2 downto 1) => m_axi_wready(3 downto 2),
m_axi_wready(0) => m_axi_wready(0),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_4\,
\m_ready_d_reg[1]_1\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[1]_2\ => addr_arbiter_inst_n_38,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_34,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_2\,
mi_bvalid(0) => mi_bvalid(6),
mi_wready(0) => mi_wready(6)
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_53,
Q => m_atarget_enc(0),
R => '0'
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_52,
Q => m_atarget_enc(1),
R => '0'
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_51,
Q => m_atarget_enc(2),
R => '0'
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_10,
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_9,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_8,
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(3),
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_6,
Q => m_atarget_hot(4),
R => reset
);
\m_atarget_hot_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(5),
Q => m_atarget_hot(5),
R => reset
);
\m_atarget_hot_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_4,
Q => m_atarget_hot(6),
R => reset
);
reg_slice_r: entity work.ip_design_xbar_0_axi_register_slice_v2_1_14_axic_register_slice
port map (
E(0) => p_1_in,
Q(34 downto 1) => \s_axi_rdata[31]\(33 downto 0),
Q(0) => reg_slice_r_n_37,
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_35,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_36,
\m_atarget_enc_reg[2]\(2 downto 0) => m_atarget_enc(2 downto 0),
\m_atarget_hot_reg[5]\(5 downto 0) => m_atarget_hot(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(2 downto 0) => m_axi_rvalid(4 downto 2),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_38,
m_valid_i_reg_1(1) => reg_slice_r_n_45,
m_valid_i_reg_1(0) => reg_slice_r_n_46,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[0]_INST_0_i_2_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(0),
I1 => m_axi_bresp(8),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(10),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(4),
I1 => m_axi_bresp(2),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(6),
O => \s_axi_bresp[0]_INST_0_i_2_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
I1 => \s_axi_bresp[1]_INST_0_i_2_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00FC0A0F000C0A"
)
port map (
I0 => m_axi_bresp(1),
I1 => m_axi_bresp(9),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(11),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0A0C00000A0C00"
)
port map (
I0 => m_axi_bresp(5),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(7),
O => \s_axi_bresp[1]_INST_0_i_2_n_0\
);
splitter_ar: entity work.\ip_design_xbar_0_axi_crossbar_v2_1_15_splitter__parameterized0\
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_3,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_46,
m_axi_arready(4 downto 1) => m_axi_arready(5 downto 2),
m_axi_arready(0) => m_axi_arready(0),
\m_payload_i_reg[0]\(0) => reg_slice_r_n_37,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_ready_d0(0) => m_ready_d0(1),
\m_ready_d_reg[1]_0\ => splitter_ar_n_0,
\m_ready_d_reg[1]_1\ => splitter_ar_n_1,
m_valid_i_reg => reg_slice_r_n_2,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.ip_design_xbar_0_axi_crossbar_v2_1_15_splitter
port map (
Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg\ => \gen_decerr.decerr_slave_inst_n_4\,
\gen_axilite.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_6\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_27,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_19,
\gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_5,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_0\ => addr_arbiter_inst_n_47,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_bvalid(4 downto 0) => m_axi_bvalid(5 downto 1),
m_axi_wready(2 downto 1) => m_axi_wready(5 downto 4),
m_axi_wready(0) => m_axi_wready(1),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
m_ready_d0(0) => m_ready_d0_0(2),
\m_ready_d_reg[0]_0\ => splitter_aw_n_0,
\m_ready_d_reg[0]_1\ => splitter_aw_n_4,
\m_ready_d_reg[0]_2\ => splitter_aw_n_8,
\m_ready_d_reg[0]_3\ => splitter_aw_n_11,
\m_ready_d_reg[1]_0\ => splitter_aw_n_6,
\m_ready_d_reg[1]_1\ => splitter_aw_n_10,
\m_ready_d_reg[1]_2\ => splitter_aw_n_12,
\m_ready_d_reg[2]_0\ => splitter_aw_n_7,
\m_ready_d_reg[2]_1\ => splitter_aw_n_9
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "axi_crossbar_v2_1_15_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar : entity is "1'b1";
end ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar;
architecture STRUCTURE of ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 191 downto 172 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_araddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_araddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_arburst(11) <= \<const0>\;
m_axi_arburst(10) <= \<const0>\;
m_axi_arburst(9) <= \<const0>\;
m_axi_arburst(8) <= \<const0>\;
m_axi_arburst(7) <= \<const0>\;
m_axi_arburst(6) <= \<const0>\;
m_axi_arburst(5) <= \<const0>\;
m_axi_arburst(4) <= \<const0>\;
m_axi_arburst(3) <= \<const0>\;
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(23) <= \<const0>\;
m_axi_arcache(22) <= \<const0>\;
m_axi_arcache(21) <= \<const0>\;
m_axi_arcache(20) <= \<const0>\;
m_axi_arcache(19) <= \<const0>\;
m_axi_arcache(18) <= \<const0>\;
m_axi_arcache(17) <= \<const0>\;
m_axi_arcache(16) <= \<const0>\;
m_axi_arcache(15) <= \<const0>\;
m_axi_arcache(14) <= \<const0>\;
m_axi_arcache(13) <= \<const0>\;
m_axi_arcache(12) <= \<const0>\;
m_axi_arcache(11) <= \<const0>\;
m_axi_arcache(10) <= \<const0>\;
m_axi_arcache(9) <= \<const0>\;
m_axi_arcache(8) <= \<const0>\;
m_axi_arcache(7) <= \<const0>\;
m_axi_arcache(6) <= \<const0>\;
m_axi_arcache(5) <= \<const0>\;
m_axi_arcache(4) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(47) <= \<const0>\;
m_axi_arlen(46) <= \<const0>\;
m_axi_arlen(45) <= \<const0>\;
m_axi_arlen(44) <= \<const0>\;
m_axi_arlen(43) <= \<const0>\;
m_axi_arlen(42) <= \<const0>\;
m_axi_arlen(41) <= \<const0>\;
m_axi_arlen(40) <= \<const0>\;
m_axi_arlen(39) <= \<const0>\;
m_axi_arlen(38) <= \<const0>\;
m_axi_arlen(37) <= \<const0>\;
m_axi_arlen(36) <= \<const0>\;
m_axi_arlen(35) <= \<const0>\;
m_axi_arlen(34) <= \<const0>\;
m_axi_arlen(33) <= \<const0>\;
m_axi_arlen(32) <= \<const0>\;
m_axi_arlen(31) <= \<const0>\;
m_axi_arlen(30) <= \<const0>\;
m_axi_arlen(29) <= \<const0>\;
m_axi_arlen(28) <= \<const0>\;
m_axi_arlen(27) <= \<const0>\;
m_axi_arlen(26) <= \<const0>\;
m_axi_arlen(25) <= \<const0>\;
m_axi_arlen(24) <= \<const0>\;
m_axi_arlen(23) <= \<const0>\;
m_axi_arlen(22) <= \<const0>\;
m_axi_arlen(21) <= \<const0>\;
m_axi_arlen(20) <= \<const0>\;
m_axi_arlen(19) <= \<const0>\;
m_axi_arlen(18) <= \<const0>\;
m_axi_arlen(17) <= \<const0>\;
m_axi_arlen(16) <= \<const0>\;
m_axi_arlen(15) <= \<const0>\;
m_axi_arlen(14) <= \<const0>\;
m_axi_arlen(13) <= \<const0>\;
m_axi_arlen(12) <= \<const0>\;
m_axi_arlen(11) <= \<const0>\;
m_axi_arlen(10) <= \<const0>\;
m_axi_arlen(9) <= \<const0>\;
m_axi_arlen(8) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(5) <= \<const0>\;
m_axi_arlock(4) <= \<const0>\;
m_axi_arlock(3) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(23) <= \<const0>\;
m_axi_arqos(22) <= \<const0>\;
m_axi_arqos(21) <= \<const0>\;
m_axi_arqos(20) <= \<const0>\;
m_axi_arqos(19) <= \<const0>\;
m_axi_arqos(18) <= \<const0>\;
m_axi_arqos(17) <= \<const0>\;
m_axi_arqos(16) <= \<const0>\;
m_axi_arqos(15) <= \<const0>\;
m_axi_arqos(14) <= \<const0>\;
m_axi_arqos(13) <= \<const0>\;
m_axi_arqos(12) <= \<const0>\;
m_axi_arqos(11) <= \<const0>\;
m_axi_arqos(10) <= \<const0>\;
m_axi_arqos(9) <= \<const0>\;
m_axi_arqos(8) <= \<const0>\;
m_axi_arqos(7) <= \<const0>\;
m_axi_arqos(6) <= \<const0>\;
m_axi_arqos(5) <= \<const0>\;
m_axi_arqos(4) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(23) <= \<const0>\;
m_axi_arregion(22) <= \<const0>\;
m_axi_arregion(21) <= \<const0>\;
m_axi_arregion(20) <= \<const0>\;
m_axi_arregion(19) <= \<const0>\;
m_axi_arregion(18) <= \<const0>\;
m_axi_arregion(17) <= \<const0>\;
m_axi_arregion(16) <= \<const0>\;
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(17) <= \<const0>\;
m_axi_arsize(16) <= \<const0>\;
m_axi_arsize(15) <= \<const0>\;
m_axi_arsize(14) <= \<const0>\;
m_axi_arsize(13) <= \<const0>\;
m_axi_arsize(12) <= \<const0>\;
m_axi_arsize(11) <= \<const0>\;
m_axi_arsize(10) <= \<const0>\;
m_axi_arsize(9) <= \<const0>\;
m_axi_arsize(8) <= \<const0>\;
m_axi_arsize(7) <= \<const0>\;
m_axi_arsize(6) <= \<const0>\;
m_axi_arsize(5) <= \<const0>\;
m_axi_arsize(4) <= \<const0>\;
m_axi_arsize(3) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(5) <= \<const0>\;
m_axi_aruser(4) <= \<const0>\;
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(191 downto 172) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(171 downto 160) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(159 downto 140) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(139 downto 128) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(127 downto 108) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(95 downto 76) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(63 downto 44) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
m_axi_awaddr(31 downto 12) <= \^m_axi_awaddr\(191 downto 172);
m_axi_awaddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
m_axi_awburst(11) <= \<const0>\;
m_axi_awburst(10) <= \<const0>\;
m_axi_awburst(9) <= \<const0>\;
m_axi_awburst(8) <= \<const0>\;
m_axi_awburst(7) <= \<const0>\;
m_axi_awburst(6) <= \<const0>\;
m_axi_awburst(5) <= \<const0>\;
m_axi_awburst(4) <= \<const0>\;
m_axi_awburst(3) <= \<const0>\;
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(23) <= \<const0>\;
m_axi_awcache(22) <= \<const0>\;
m_axi_awcache(21) <= \<const0>\;
m_axi_awcache(20) <= \<const0>\;
m_axi_awcache(19) <= \<const0>\;
m_axi_awcache(18) <= \<const0>\;
m_axi_awcache(17) <= \<const0>\;
m_axi_awcache(16) <= \<const0>\;
m_axi_awcache(15) <= \<const0>\;
m_axi_awcache(14) <= \<const0>\;
m_axi_awcache(13) <= \<const0>\;
m_axi_awcache(12) <= \<const0>\;
m_axi_awcache(11) <= \<const0>\;
m_axi_awcache(10) <= \<const0>\;
m_axi_awcache(9) <= \<const0>\;
m_axi_awcache(8) <= \<const0>\;
m_axi_awcache(7) <= \<const0>\;
m_axi_awcache(6) <= \<const0>\;
m_axi_awcache(5) <= \<const0>\;
m_axi_awcache(4) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(47) <= \<const0>\;
m_axi_awlen(46) <= \<const0>\;
m_axi_awlen(45) <= \<const0>\;
m_axi_awlen(44) <= \<const0>\;
m_axi_awlen(43) <= \<const0>\;
m_axi_awlen(42) <= \<const0>\;
m_axi_awlen(41) <= \<const0>\;
m_axi_awlen(40) <= \<const0>\;
m_axi_awlen(39) <= \<const0>\;
m_axi_awlen(38) <= \<const0>\;
m_axi_awlen(37) <= \<const0>\;
m_axi_awlen(36) <= \<const0>\;
m_axi_awlen(35) <= \<const0>\;
m_axi_awlen(34) <= \<const0>\;
m_axi_awlen(33) <= \<const0>\;
m_axi_awlen(32) <= \<const0>\;
m_axi_awlen(31) <= \<const0>\;
m_axi_awlen(30) <= \<const0>\;
m_axi_awlen(29) <= \<const0>\;
m_axi_awlen(28) <= \<const0>\;
m_axi_awlen(27) <= \<const0>\;
m_axi_awlen(26) <= \<const0>\;
m_axi_awlen(25) <= \<const0>\;
m_axi_awlen(24) <= \<const0>\;
m_axi_awlen(23) <= \<const0>\;
m_axi_awlen(22) <= \<const0>\;
m_axi_awlen(21) <= \<const0>\;
m_axi_awlen(20) <= \<const0>\;
m_axi_awlen(19) <= \<const0>\;
m_axi_awlen(18) <= \<const0>\;
m_axi_awlen(17) <= \<const0>\;
m_axi_awlen(16) <= \<const0>\;
m_axi_awlen(15) <= \<const0>\;
m_axi_awlen(14) <= \<const0>\;
m_axi_awlen(13) <= \<const0>\;
m_axi_awlen(12) <= \<const0>\;
m_axi_awlen(11) <= \<const0>\;
m_axi_awlen(10) <= \<const0>\;
m_axi_awlen(9) <= \<const0>\;
m_axi_awlen(8) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(5) <= \<const0>\;
m_axi_awlock(4) <= \<const0>\;
m_axi_awlock(3) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(23) <= \<const0>\;
m_axi_awqos(22) <= \<const0>\;
m_axi_awqos(21) <= \<const0>\;
m_axi_awqos(20) <= \<const0>\;
m_axi_awqos(19) <= \<const0>\;
m_axi_awqos(18) <= \<const0>\;
m_axi_awqos(17) <= \<const0>\;
m_axi_awqos(16) <= \<const0>\;
m_axi_awqos(15) <= \<const0>\;
m_axi_awqos(14) <= \<const0>\;
m_axi_awqos(13) <= \<const0>\;
m_axi_awqos(12) <= \<const0>\;
m_axi_awqos(11) <= \<const0>\;
m_axi_awqos(10) <= \<const0>\;
m_axi_awqos(9) <= \<const0>\;
m_axi_awqos(8) <= \<const0>\;
m_axi_awqos(7) <= \<const0>\;
m_axi_awqos(6) <= \<const0>\;
m_axi_awqos(5) <= \<const0>\;
m_axi_awqos(4) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(23) <= \<const0>\;
m_axi_awregion(22) <= \<const0>\;
m_axi_awregion(21) <= \<const0>\;
m_axi_awregion(20) <= \<const0>\;
m_axi_awregion(19) <= \<const0>\;
m_axi_awregion(18) <= \<const0>\;
m_axi_awregion(17) <= \<const0>\;
m_axi_awregion(16) <= \<const0>\;
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(17) <= \<const0>\;
m_axi_awsize(16) <= \<const0>\;
m_axi_awsize(15) <= \<const0>\;
m_axi_awsize(14) <= \<const0>\;
m_axi_awsize(13) <= \<const0>\;
m_axi_awsize(12) <= \<const0>\;
m_axi_awsize(11) <= \<const0>\;
m_axi_awsize(10) <= \<const0>\;
m_axi_awsize(9) <= \<const0>\;
m_axi_awsize(8) <= \<const0>\;
m_axi_awsize(7) <= \<const0>\;
m_axi_awsize(6) <= \<const0>\;
m_axi_awsize(5) <= \<const0>\;
m_axi_awsize(4) <= \<const0>\;
m_axi_awsize(3) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(5) <= \<const0>\;
m_axi_awuser(4) <= \<const0>\;
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(191 downto 160) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(159 downto 128) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(5) <= \<const0>\;
m_axi_wlast(4) <= \<const0>\;
m_axi_wlast(3) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
m_axi_wstrb(23 downto 20) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(19 downto 16) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(5) <= \<const0>\;
m_axi_wuser(4) <= \<const0>\;
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.ip_design_xbar_0_axi_crossbar_v2_1_15_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
Q(31 downto 12) => \^m_axi_awaddr\(191 downto 172),
Q(11 downto 0) => \^m_axi_araddr\(11 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(33 downto 2) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_xbar_0 : entity is "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of ip_design_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of ip_design_xbar_0 : entity is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3";
end ip_design_xbar_0;
architecture STRUCTURE of ip_design_xbar_0 is
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 6;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "6'b111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "6'b111111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15]";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5]";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10]";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160]";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5]";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20]";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5]";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
inst: entity work.ip_design_xbar_0_axi_crossbar_v2_1_15_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(191 downto 0) => m_axi_araddr(191 downto 0),
m_axi_arburst(11 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(11 downto 0),
m_axi_arcache(23 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(23 downto 0),
m_axi_arid(5 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(5 downto 0),
m_axi_arlen(47 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(47 downto 0),
m_axi_arlock(5 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(5 downto 0),
m_axi_arprot(17 downto 0) => m_axi_arprot(17 downto 0),
m_axi_arqos(23 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(23 downto 0),
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_axi_arregion(23 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(23 downto 0),
m_axi_arsize(17 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(17 downto 0),
m_axi_aruser(5 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(5 downto 0),
m_axi_arvalid(5 downto 0) => m_axi_arvalid(5 downto 0),
m_axi_awaddr(191 downto 0) => m_axi_awaddr(191 downto 0),
m_axi_awburst(11 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(11 downto 0),
m_axi_awcache(23 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(23 downto 0),
m_axi_awid(5 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(5 downto 0),
m_axi_awlen(47 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(47 downto 0),
m_axi_awlock(5 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(5 downto 0),
m_axi_awprot(17 downto 0) => m_axi_awprot(17 downto 0),
m_axi_awqos(23 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(23 downto 0),
m_axi_awready(5 downto 0) => m_axi_awready(5 downto 0),
m_axi_awregion(23 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(23 downto 0),
m_axi_awsize(17 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(17 downto 0),
m_axi_awuser(5 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(5 downto 0),
m_axi_awvalid(5 downto 0) => m_axi_awvalid(5 downto 0),
m_axi_bid(5 downto 0) => B"000000",
m_axi_bready(5 downto 0) => m_axi_bready(5 downto 0),
m_axi_bresp(11 downto 0) => m_axi_bresp(11 downto 0),
m_axi_buser(5 downto 0) => B"000000",
m_axi_bvalid(5 downto 0) => m_axi_bvalid(5 downto 0),
m_axi_rdata(191 downto 0) => m_axi_rdata(191 downto 0),
m_axi_rid(5 downto 0) => B"000000",
m_axi_rlast(5 downto 0) => B"111111",
m_axi_rready(5 downto 0) => m_axi_rready(5 downto 0),
m_axi_rresp(11 downto 0) => m_axi_rresp(11 downto 0),
m_axi_ruser(5 downto 0) => B"000000",
m_axi_rvalid(5 downto 0) => m_axi_rvalid(5 downto 0),
m_axi_wdata(191 downto 0) => m_axi_wdata(191 downto 0),
m_axi_wid(5 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(5 downto 0),
m_axi_wlast(5 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(5 downto 0),
m_axi_wready(5 downto 0) => m_axi_wready(5 downto 0),
m_axi_wstrb(23 downto 0) => m_axi_wstrb(23 downto 0),
m_axi_wuser(5 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(5 downto 0),
m_axi_wvalid(5 downto 0) => m_axi_wvalid(5 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast(0) => '1',
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 6661e95c4d99db5918212e3cae25f3b9 | 0.556331 | 2.629417 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/allclkgen.vhd | 1 | 20,630 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allclkgen
-- File: allclkgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex7
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 25000);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkand_ut90nhbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkrand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_rh_lib18t
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut130hbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut90nhbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_fusion
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_fusion
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3e
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3l
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_rhumc
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_saed32
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_saed32
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_saed32
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_saed32
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_dare
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_dare
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhumc
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_dare
generic (
noclkfb : integer := 1
);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clk8x : out std_logic
);
end component;
component clkgen_easic90
generic (
clk_mul : integer;
clk_div : integer;
freq : integer;
pcisysclk : integer;
pcien : integer);
port (
clkin : in std_ulogic;
pciclkin : in std_ulogic;
clk : out std_ulogic;
clk2x : out std_ulogic;
clk4x : out std_ulogic;
clkn : out std_ulogic;
lock : out std_ulogic);
end component;
component clkmux_dare
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkmux_rhlib18t
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_n2x
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_n2x
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_n2x
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk270en : integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic; -- unscaled 2X clock
clk270 : out std_ulogic -- clk shifted 270 degrees
);
end component;
component clkgen_ut130hbd
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
clk4x : out std_ulogic;
clk8x : out std_ulogic;
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component clkgen_ut90nhbd is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
end;
| gpl-2.0 | 53dd54931bdf81b0de20300ce5e88fc0 | 0.549976 | 3.36377 | false | false | false | false |
offox/offox-fpga-projects | digital-watch/digital_watch.vhd | 1 | 995 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--top module(full adder) entity declaration
entity digital_watch is
port ( --Ai, Bi, Ci, Di : in std_logic;
variabkey : in std_logic;
hour_dec : out std_logic_vector(6 downto 0);
hour_uni : out std_logic_vector(6 downto 0);
min_dec : out std_logic_vector(6 downto 0);
min_uni : out std_logic_vector(6 downto 0));
end digital_watch;
--top module architecture declaration.
architecture behavior of digital_watch is
--signal s1,c1,c2 : std_logic:='0';
signal Ai, Bi, Ci, Di : std_logic:='0';
attribute altera_chip_pin_lc of hour_dec : signal is "Ao, Bo, Co, Do, Eo, Fo, Go";
begin
--instantiate and do port map for the first half adder.
process (key)
begin
if (key = '0') then
Ai <= '0';
Bi <= '1';
else
Ai <= '1';
Bi <= '0';
end if;
end process;
HA1 : entity work.CI_4511 port map(Ai, Bi, Ci, Di, Ao, Bo, Co, Do, Eo, Fo, Go);
--instantiate and do port map for the second half adder.
end; | gpl-2.0 | 16a88ac61044989d9adf1258b909451c | 0.659296 | 2.787115 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd | 1 | 16,873 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp605
-- File: ahb2mig_sp605.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp605 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_p : in std_logic;
clk_mem_n : in std_logic;
clk_125 : out std_logic;
clk_50 : out std_logic
);
end ;
architecture rtl of ahb2mig_sp605 is
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : entity work.mig_38 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
-- C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_i => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error,
clk_125 => clk_125,
clk_50 => clk_50
);
end;
| gpl-2.0 | 2e503dd7cad3b091e2854e06e5cf682d | 0.518699 | 2.903631 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/GPR/src/DPATH.vhd | 1 | 1,698 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library gpr;
use gpr.OneHotGPR.all;
entity DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand 1
OP1: in operand;
-- operand 2
OP2: in operand;
-- result
RES: out operand;
-- zero flag
ZF: out std_logic
);
end DPATH;
architecture Beh_GPR of DPATH is
signal res_g: operand;
signal res_add: operand;
signal res_sub: operand;
signal res_shift: operand;
signal res_copy: operand;
signal t_zf: std_logic;
Begin
res_add <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(OP1) + CONV_INTEGER(OP2), 16);
res_sub <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(OP1) - CONV_INTEGER(OP2), 16);
res_copy <= OP1;
REGA: process (EN, OT, OP1, res_add, res_sub, res_shift, res_copy)
begin
if rising_edge(EN) then
case OT is
when ADD => res_g <= res_add;
when SUBT => res_g <= res_sub;
when SHIFT => res_g <= res_shift;
when COPY => res_g <= res_copy;
when others => null;
end case;
end if;
end process;
FLAGS: process(res_g)
begin
if res_g = (res_g'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
GRAY: process(OP1)
begin
for i in 0 to 14 loop
res_shift(i) <= OP1(i) xor OP1(i+1);
end loop;
res_shift(15) <= OP1(15);
end process;
RES <= res_g;
ZF <= t_zf;
End Beh_GPR; | mit | 5715f100852d10a81ee9cc362b3060c6 | 0.517668 | 3.228137 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl | 1 | 374,622 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:53 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[1:0][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:2][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[5:4][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:22][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[25:24][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:26][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[29:28][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:30][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:6][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[9:8][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:10][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[13:12][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:14][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[17:16][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:18][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[21:20][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[10].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(21 downto 20),
dinb(1 downto 0) => dinb(21 downto 20),
douta(1 downto 0) => douta(21 downto 20),
doutb(1 downto 0) => doutb(21 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[11].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(23 downto 22),
dinb(1 downto 0) => dinb(23 downto 22),
douta(1 downto 0) => douta(23 downto 22),
doutb(1 downto 0) => doutb(23 downto 22),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[12].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(25 downto 24),
dinb(1 downto 0) => dinb(25 downto 24),
douta(1 downto 0) => douta(25 downto 24),
doutb(1 downto 0) => doutb(25 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[13].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(27 downto 26),
dinb(1 downto 0) => dinb(27 downto 26),
douta(1 downto 0) => douta(27 downto 26),
doutb(1 downto 0) => doutb(27 downto 26),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[14].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(29 downto 28),
dinb(1 downto 0) => dinb(29 downto 28),
douta(1 downto 0) => douta(29 downto 28),
doutb(1 downto 0) => doutb(29 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[15].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(31 downto 30),
dinb(1 downto 0) => dinb(31 downto 30),
douta(1 downto 0) => douta(31 downto 30),
doutb(1 downto 0) => doutb(31 downto 30),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[1].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
dinb(1 downto 0) => dinb(3 downto 2),
douta(1 downto 0) => douta(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(5 downto 4),
dinb(1 downto 0) => dinb(5 downto 4),
douta(1 downto 0) => douta(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(7 downto 6),
dinb(1 downto 0) => dinb(7 downto 6),
douta(1 downto 0) => douta(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(9 downto 8),
dinb(1 downto 0) => dinb(9 downto 8),
douta(1 downto 0) => douta(9 downto 8),
doutb(1 downto 0) => doutb(9 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[5].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(11 downto 10),
dinb(1 downto 0) => dinb(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
doutb(1 downto 0) => doutb(11 downto 10),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[6].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(13 downto 12),
dinb(1 downto 0) => dinb(13 downto 12),
douta(1 downto 0) => douta(13 downto 12),
doutb(1 downto 0) => doutb(13 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[7].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(15 downto 14),
dinb(1 downto 0) => dinb(15 downto 14),
douta(1 downto 0) => douta(15 downto 14),
doutb(1 downto 0) => doutb(15 downto 14),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[8].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(17 downto 16),
dinb(1 downto 0) => dinb(17 downto 16),
douta(1 downto 0) => douta(17 downto 16),
doutb(1 downto 0) => doutb(17 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[9].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(19 downto 18),
dinb(1 downto 0) => dinb(19 downto 18),
douta(1 downto 0) => douta(19 downto 18),
doutb(1 downto 0) => doutb(19 downto 18),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth : entity is "blk_mem_gen_v8_3_6_synth";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_v8_3_6";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "yes";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth
port map (
addra(13 downto 0) => addra(15 downto 2),
addrb(13 downto 0) => addrb(15 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2";
end zynq_design_1_axi_bram_ctrl_0_bram_0;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
| mit | bcf2f673f27db207abce9e5dd0d4c120 | 0.741617 | 4.651898 | false | false | false | false |
a4a881d4/ringbus4xilinx | src/example/dummySrc.vhd | 2 | 1,619 | ---------------------------------------------------------------------------------------------------
--
-- Title : dummy source for test
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : dummySrc.vhd
-- Generated : 2013/9/7
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : dummy source for test
--
-- Rev: 3.0
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.rb_config.all;
entity DUMMYSRC is
generic(
Awidth : natural;
Bwidth : natural
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Addr : in std_logic_vector( Awidth-1 downto 0 );
Q : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
ren : in STD_LOGIC
);
end DUMMYSRC;
architecture behave of DUMMYSRC is
signal Q_in: STD_LOGIC_VECTOR( Bwidth-1 downto 0 ) := ( others=>'0' );
begin
process(clk,rst)
begin
if rst='1' then
Q_in<=zeros( Bwidth-1 downto 0 );
elsif rising_edge(clk) then
if ren='1' then
Q_in( Awidth-1 downto 0 )<=Addr;
if addr=ones( Awidth-1 downto 0 ) then
Q_in( Bwidth-1 downto Awidth ) <= Q_in( Bwidth-1 downto Awidth )+1;
end if;
end if;
end if;
end process;
Q<=Q_in;
end behave; | gpl-2.0 | 194c00969c5ff84ab113329ecca9a8f0 | 0.434219 | 3.54267 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/sim/zynq_design_1_axi_gpio_0_1.vhd | 2 | 8,848 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zynq_design_1_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zynq_design_1_axi_gpio_0_1;
ARCHITECTURE zynq_design_1_axi_gpio_0_1_arch OF zynq_design_1_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_design_1_axi_gpio_0_1_arch;
| mit | fd8ba439aee2ef55c2efbed39e374ee7 | 0.679476 | 3.231556 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd | 1 | 9,518 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 1000 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | ad916fe70393261dbe0646fa2423dd13 | 0.526791 | 3.522576 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution3/syn/vhdl/fir_mul_32s_32s_3bkb.vhd | 2 | 2,417 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir_mul_32s_32s_3bkb_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of fir_mul_32s_32s_3bkb_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_i) * signed(b_i))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
p_tmp <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_mul_32s_32s_3bkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of fir_mul_32s_32s_3bkb is
component fir_mul_32s_32s_3bkb_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_mul_32s_32s_3bkb_MulnS_0_U : component fir_mul_32s_32s_3bkb_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| mit | e5b15be5be269bd1da3248c26e7741c9 | 0.548614 | 3.266216 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/apbctrl.vhd | 1 | 11,741 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture rtl of apbctrl is
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( 1, 6, 0, VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask, 12);
type reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(haddr => (others => '0'), hwrite => '0', hready => '1', penable => '0',
psel => '0', prdata => (others => '0'), pwdata => (others => '0'),
state => (others => '0'), cfgsel => '0');
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, r, rst)
variable v : reg_type;
variable psel : std_logic_vector(0 to 31);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(apbmax downto 0);
variable apbaddr2 : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : integer range 0 to nslaves-1;
variable bnslave : std_logic_vector(3 downto 0);
begin
v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
pirq := (others => '0');
-- detect start of cycle
if (ahbi.hready = '1') then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
(ahbi.hsel(hindex) = '1')
then
v.hready := '0'; v.hwrite := ahbi.hwrite;
v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
v.state := "01"; v.psel := not ahbi.hwrite;
end if;
end if;
case r.state is
when "00" => null; -- idle
when "01" =>
if r.hwrite = '0' then v.penable := '1';
else v.pwdata := ahbreadword(ahbi.hwdata, r.haddr(4 downto 2)); end if;
v.psel := '1'; v.state := "10";
when others =>
if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
v.state := "00"; v.hready := '1';
end case;
psel := (others => '0');
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(i) := '1'; end if;
end loop;
bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
psel(9) or psel(11) or psel(13) or psel(15);
bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
psel(10) or psel(11) or psel(14) or psel(15);
bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
psel(12) or psel(13) or psel(14) or psel(15);
bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
psel(12) or psel(13) or psel(14) or psel(15);
nslave := conv_integer(bnslave);
if (r.haddr(19 downto 12) = "11111111") then
v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
else v.cfgsel := '0'; end if;
v.prdata := apbo(nslave).prdata;
if r.cfgsel = '1' then
v.prdata := apbo(conv_integer(r.haddr(6 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
if nslaves <= conv_integer(r.haddr(6 downto 3)) then
v.prdata := (others => '0');
end if;
end if;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
ahbo.hready <= r.hready;
ahbo.hrdata <= ahbdrivedata(r.prdata);
ahbo.hirq <= pirq;
if (not RESET_ALL) and (rst = '0') then
v.penable := RES.penable; v.hready := RES.hready;
v.psel := RES.psel; v.state := RES.state;
v.hwrite := RES.hwrite;
-- pragma translate_off
v.haddr := RES.haddr;
-- pragma translate_on
end if;
rin <= v;
-- drive APB bus
apbaddr2 := (others => '0');
apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
apbi.paddr <= apbaddr2;
apbi.pwdata <= r.pwdata;
apbi.pwrite <= r.hwrite;
apbi.penable <= r.penable;
apbi.pirq <= ahbi.hirq;
apbi.testen <= ahbi.testen;
apbi.testoen <= ahbi.testoen;
apbi.scanen <= ahbi.scanen;
apbi.testrst <= ahbi.testrst;
apbi.testin <= ahbi.testin;
apbi.psel <= (others => '0');
for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_off
lapbi.paddr <= apbaddr2;
lapbi.pwdata <= r.pwdata;
lapbi.pwrite <= r.hwrite;
lapbi.penable <= r.penable;
lapbi.pirq <= ahbi.hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_on
end process;
ahbo.hindex <= hindex;
ahbo.hconfig <= hconfig;
ahbo.hsplit <= (others => '0');
ahbo.hresp <= HRESP_OKAY;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
type apb_memarea_type is record
start : std_logic_vector(31 downto 20);
stop : std_logic_vector(31 downto 20);
end record;
type memmap_type is array (0 to nslaves-1) of apb_memarea_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable L1 : line := new string'("");
variable memmap : memmap_type;
begin
wait for 3 ns;
if debug > 0 then
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
if mcheck /= 0 then
memmap(i).start := (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4));
memmap(i).stop := memmap(i).start + 2**k;
end if;
end if;
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) &
". Detected index value " & tost(apbo(i).pindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
if memmap(i).start /= memmap(i).stop then
assert ((memmap(i).start >= memmap(j).stop) or
(memmap(i).stop <= memmap(j).start) or (i = j))
report "APB slave " & tost(i) & " memory area" &
" intersects with APB slave " & tost(j) & " memory area."
severity failure;
end if;
end loop;
end if;
else
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " appears to be disabled, " &
"but the config record is not driven to zero"
severity warning;
end loop;
end if;
end loop;
if nslaves < NAPBSLV then
for i in nslaves to NAPBSLV-1 loop
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " is outside the range of decoded " &
"slave indexes but the config record is not driven to zero"
severity warning;
end loop; -- j
end loop; -- i
end if;
wait;
end process;
-- pragma translate_on
end;
| gpl-2.0 | eb77637310fb7fb42aaf80efdb253e8c | 0.56077 | 3.502685 | false | true | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3C/matrix_mult_prj/solution1/syn/vhdl/matrix_mult.vhd | 2 | 17,072 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.492500,HLS_SYN_LAT=686,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=1,HLS_SYN_FF=177,HLS_SYN_LUT=165}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal tmp_7_fu_137_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_reg_251 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_1_fu_149_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_260 : STD_LOGIC_VECTOR (2 downto 0);
signal j_cast2_cast_fu_155_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal j_cast2_cast_reg_265 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal prod_addr_reg_270 : STD_LOGIC_VECTOR (4 downto 0);
signal j_1_fu_175_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_278 : STD_LOGIC_VECTOR (2 downto 0);
signal a_addr_reg_283 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal b_addr_reg_288 : STD_LOGIC_VECTOR (4 downto 0);
signal k_1_fu_229_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal k_1_reg_296 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal grp_fu_243_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal i_reg_75 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond1_fu_169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal j_reg_86 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond2_fu_143_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal prod_load_reg_97 : STD_LOGIC_VECTOR (15 downto 0);
signal k_reg_110 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_8_cast_fu_164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_cast_fu_190_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_cast_fu_218_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_6_fu_125_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal i_cast3_cast_fu_121_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl_cast_fu_133_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_159_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal k_cast1_cast_fu_181_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_fu_185_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_fu_195_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl1_cast_fu_203_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_fu_207_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_fu_213_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
component matrix_mult_mac_mbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mac_mbkb_U0 : component matrix_mult_mac_mbkb
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => a_q0,
din2 => prod_load_reg_97,
ce => ap_const_logic_1,
dout => grp_fu_243_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
i_reg_75_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_1))) then
i_reg_75 <= i_1_reg_260;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_75 <= ap_const_lv3_0;
end if;
end if;
end process;
j_reg_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_223_p2))) then
j_reg_86 <= j_1_reg_278;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_143_p2 = ap_const_lv1_0))) then
j_reg_86 <= ap_const_lv3_0;
end if;
end if;
end process;
k_reg_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
k_reg_110 <= k_1_reg_296;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_0))) then
k_reg_110 <= ap_const_lv3_0;
end if;
end if;
end process;
prod_load_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
prod_load_reg_97 <= grp_fu_243_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_0))) then
prod_load_reg_97 <= ap_const_lv16_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
a_addr_reg_283 <= tmp_9_cast_fu_190_p1(5 - 1 downto 0);
b_addr_reg_288 <= tmp_12_cast_fu_218_p1(5 - 1 downto 0);
k_1_reg_296 <= k_1_fu_229_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_1_reg_260 <= i_1_fu_149_p2;
tmp_7_reg_251 <= tmp_7_fu_137_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
j_1_reg_278 <= j_1_fu_175_p2;
j_cast2_cast_reg_265(2 downto 0) <= j_cast2_cast_fu_155_p1(2 downto 0);
prod_addr_reg_270 <= tmp_8_cast_fu_164_p1(5 - 1 downto 0);
end if;
end if;
end process;
j_cast2_cast_reg_265(5 downto 3) <= "000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state4, exitcond1_fu_169_p2, exitcond2_fu_143_p2, exitcond_fu_223_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_169_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_223_p2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
a_address0 <= a_addr_reg_283;
a_ce0_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_done_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_143_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_143_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_1 = exitcond2_fu_143_p2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
b_address0 <= b_addr_reg_288;
b_ce0_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
exitcond1_fu_169_p2 <= "1" when (j_reg_86 = ap_const_lv3_5) else "0";
exitcond2_fu_143_p2 <= "1" when (i_reg_75 = ap_const_lv3_5) else "0";
exitcond_fu_223_p2 <= "1" when (k_reg_110 = ap_const_lv3_5) else "0";
i_1_fu_149_p2 <= std_logic_vector(unsigned(i_reg_75) + unsigned(ap_const_lv3_1));
i_cast3_cast_fu_121_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_75),6));
j_1_fu_175_p2 <= std_logic_vector(unsigned(j_reg_86) + unsigned(ap_const_lv3_1));
j_cast2_cast_fu_155_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_86),6));
k_1_fu_229_p2 <= std_logic_vector(unsigned(k_reg_110) + unsigned(ap_const_lv3_1));
k_cast1_cast_fu_181_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(k_reg_110),6));
p_shl1_cast_fu_203_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_195_p3),6));
p_shl_cast_fu_133_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_fu_125_p3),6));
prod_address0 <= prod_addr_reg_270;
prod_ce0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_d0 <= prod_load_reg_97;
prod_we0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_207_p2 <= std_logic_vector(unsigned(k_cast1_cast_fu_181_p1) + unsigned(p_shl1_cast_fu_203_p1));
tmp_11_fu_213_p2 <= std_logic_vector(unsigned(tmp_10_fu_207_p2) + unsigned(j_cast2_cast_reg_265));
tmp_12_cast_fu_218_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_213_p2),32));
tmp_6_fu_125_p3 <= (i_reg_75 & ap_const_lv2_0);
tmp_7_fu_137_p2 <= std_logic_vector(unsigned(i_cast3_cast_fu_121_p1) + unsigned(p_shl_cast_fu_133_p1));
tmp_8_cast_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_fu_159_p2),32));
tmp_8_fu_159_p2 <= std_logic_vector(unsigned(tmp_7_reg_251) + unsigned(j_cast2_cast_fu_155_p1));
tmp_9_cast_fu_190_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_fu_185_p2),32));
tmp_9_fu_185_p2 <= std_logic_vector(unsigned(tmp_7_reg_251) + unsigned(k_cast1_cast_fu_181_p1));
tmp_s_fu_195_p3 <= (k_reg_110 & ap_const_lv2_0);
end behav;
| mit | ab3cbbd44b92b185a03ddec090fe192a | 0.567537 | 2.952101 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-nuhorizons-3s1500/testbench.vhd | 1 | 13,633 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8+8*CFG_MCTRL_RAM16BIT; -- rom data width (8/16)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal flash_d : std_logic_vector(15 downto 0);
signal romsn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal ereset : std_logic;
signal led : std_logic_vector(8 downto 1);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal ba : std_logic_vector(3 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal pb_sw : std_logic_vector(4 downto 1);
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_en : std_ulogic;
signal lcd_backl: std_ulogic;
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal smsc_addr : std_logic_vector(21 downto 0);
signal smsc_data : std_logic_vector(31 downto 0);
signal smsc_nbe : std_logic_vector(3 downto 0);
signal smsc_resetn : std_ulogic;
signal smsc_ardy : std_ulogic;
signal smsc_intr : std_ulogic;
signal smsc_nldev : std_ulogic;
signal smsc_nrd : std_ulogic;
signal smsc_nwr : std_ulogic;
signal smsc_ncs : std_ulogic;
signal smsc_aen : std_ulogic;
signal smsc_lclk : std_ulogic;
signal smsc_wnr : std_ulogic;
signal smsc_rdyrtn : std_ulogic;
signal smsc_cycle : std_ulogic;
signal smsc_nads : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1'; error <= led(8); sa(14 downto 12) <= "000";
pb_sw <= rst & "00" & dsubre;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (pb_sw, clk, led, address(21 downto 1), flash_d,
sa(11 downto 0), sd, ba, sddqm, sdclk, sdcke, sdcsn, sdwen, sdrasn,
sdcasn, txd1, rxd1, open, gnd, dsutx, dsurx, open, gnd,
oen, writen, romsn, open, vcc, open, open,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, emdc, gnd, ereset, gpio,
-- lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_backl,
can_txd, can_rxd,
smsc_addr(14 downto 0), smsc_data, smsc_nbe, smsc_resetn, smsc_ardy,-- smsc_intr,
smsc_nldev, smsc_nrd, smsc_nwr, smsc_ncs, smsc_aen, smsc_lclk,
smsc_wnr, smsc_rdyrtn, smsc_cycle, smsc_nads);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => ba(1 downto 0), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => ba(3 downto 2), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
rom8 : if romwidth /= 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= flash_d(15);
end generate;
rom16 : if romwidth = 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= '0';
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
flash_d <= buskeep(flash_d) after 5 ns;
sd <= buskeep(sd) after 5 ns;
smsc_data <= buskeep(smsc_data) after 5 ns;
smsc_addr(21 downto 15) <= (others => '0');
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), smsc_data,
smsc_ncs, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | d6d817a79f83801b5699cf6c543b7de8 | 0.591946 | 3.045119 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/0a0e961c932ad738/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl | 1 | 79,172 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:40 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:0][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:16][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(31 downto 16),
dinb(15 downto 0) => dinb(31 downto 16),
douta(15 downto 0) => douta(31 downto 16),
doutb(15 downto 0) => doutb(31 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(3 downto 2),
web(1 downto 0) => web(3 downto 2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
port map (
addra(10 downto 0) => addra(12 downto 2),
addrb(10 downto 0) => addrb(12 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
| mit | 601eabc2931ba8d1411be4b73f7265e0 | 0.713661 | 3.760783 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/sdram_phy.vhd | 1 | 7,900 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdram_phy
-- File: sdram_phy.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: SDRAM PHY with tech mapping, includes pads and can be
-- implemented with registers on all signals.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity sdram_phy is
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end;
architecture rtl of sdram_phy is
signal laddrx : std_logic_vector(aw-1 downto 0);
signal ldq_dinx : std_logic_vector(dw-1 downto 0);
signal ldq_doutx : std_logic_vector(dw-1 downto 0);
signal ldq_oenx : std_logic_vector(dw-1 downto 0);
signal lckex : std_logic_vector(ncs-1 downto 0);
signal lsnx : std_logic_vector(ncs-1 downto 0);
signal lwenx : std_ulogic;
signal lrasnx : std_ulogic;
signal lcasnx : std_ulogic;
signal ldqmx : std_logic_vector(dw/8-1 downto 0);
signal oen : std_ulogic;
signal voen : std_logic_vector(dw-1 downto 0);
-- Determines if there is a customized phy available for target tech,
-- otherwise a generic PHY will be built
constant has_sdram_phy : tech_ability_type :=
(easic45 => 1, others => 0);
-- Determines if target tech has pads with built in registers (or rather if
-- target technology requires special pad instantiations in order to get
-- registers into pad ring).
constant tech_has_padregs : tech_ability_type :=
(easic45 => 1, others => 0);
begin
oen <= not ldq_oen(0) when padoen_polarity(tech) /= oepol else ldq_oen(0);
voen <= not ldq_oen when padoen_polarity(tech) /= oepol else ldq_oen;
nopadregs : if (reg = 0) or (tech_has_padregs(tech) /= 0) generate
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= voen;
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end generate;
padregs : if (reg /= 0) and (tech_has_padregs(tech) = 0) generate
regproc : process(clk, rstn)
begin
if rising_edge(clk) then
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= (others => oen);
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end if;
if rstn = '0' then
lsnx <= (others => '1');
for i in ldq_oenx'range loop
ldq_oenx(i) <= conv_std_logic(padoen_polarity(tech) = 0);
end loop;
end if;
end process;
end generate;
gen : if has_sdram_phy(tech) = 0 generate
-- SDRAM address
sa_pad : outpadv
generic map (
width => aw,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (addr, laddrx, cfgi_cmd);
-- SDRAM data
sd_pad : iopadvv
generic map (
width => dw,
tech => tech,
level => level,
voltage => voltage,
strength => strength,
oepol => padoen_polarity(tech))
port map (dq, ldq_doutx, ldq_oenx, ldq_dinx, cfgi_dq);
-- SDRAM clock enable
sdcke_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (cke, lckex, cfgi_cmd);
-- SDRAM write enable
sdwen_pad : outpad generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (wen, lwenx, cfgi_cmd);
-- SDRAM chip select
sdcsn_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (sn, lsnx, cfgi_cmd);
-- SDRAM ras
sdras_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (rasn, lrasnx, cfgi_cmd);
-- SDRAM cas
sdcas_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (casn, lcasnx, cfgi_cmd);
-- SDRAM dqm
sddqm_pad : outpadv
generic map (
width => dw/8,
level => level,
voltage => voltage,
tech => tech,
strength => strength)
port map (dqm, ldqmx, cfgi_cmd);
end generate;
n2x : if (tech = easic45) generate
phy0 : n2x_sdram_phy
generic map (
level => level, voltage => voltage, strength => strength,
aw => aw, dw => dw, ncs => ncs, reg => reg)
port map (
addr, dq, cke, sn, wen, rasn, casn, dqm,
laddrx, ldq_dinx, ldq_doutx, ldq_oenx, lckex,
lsnx, lwenx, lrasnx, lcasnx, ldqmx,
rstn, clk,
cfgi_cmd, cfgi_dq);
end generate;
end;
| gpl-2.0 | bc0184b6ca9cd5eb0fb2a700d34ebeb0 | 0.554937 | 3.695042 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_gpio.vhd | 1 | 33,253 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_gpio.vhd
--!
--! @brief fpgaMSP430 constant Digital I/O interface
--
--! @author Emmanuel Amadio, [email protected]
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_gpio is
generic (
P1_EN : boolean := true; --! Enable Port 1
P2_EN : boolean := true; --! Enable Port 2
P3_EN : boolean := false; --! Enable Port 3
P4_EN : boolean := false; --! Enable Port 4
P5_EN : boolean := false; --! Enable Port 5
P6_EN : boolean := false; --! Enable Port 6
SYNC_P1 : boolean := true; --! Synchronize Port 1 inputs
SYNC_P2 : boolean := true; --! Synchronize Port 2 inputs
SYNC_P3 : boolean := true; --! Synchronize Port 3 inputs
SYNC_P4 : boolean := true; --! Synchronize Port 4 inputs
SYNC_P5 : boolean := true; --! Synchronize Port 5 inputs
SYNC_P6 : boolean := true --! Synchronize Port 6 inputs
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
p1_din : in std_logic_vector(7 downto 0); --! Port 1 data input
p2_din : in std_logic_vector(7 downto 0); --! Port 2 data input
p3_din : in std_logic_vector(7 downto 0); --! Port 3 data input
p4_din : in std_logic_vector(7 downto 0); --! Port 4 data input
p5_din : in std_logic_vector(7 downto 0); --! Port 5 data input
p6_din : in std_logic_vector(7 downto 0); --! Port 6 data input
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! OUTPUTs
irq_port1 : out std_logic; --! Port 1 interrupt
irq_port2 : out std_logic; --! Port 2 interrupt
p1_dout : out std_logic_vector(7 downto 0); --! Port 1 data output
p1_dout_en : out std_logic_vector(7 downto 0); --! Port 1 data output enable
p1_sel : out std_logic_vector(7 downto 0); --! Port 1 function select
p2_dout : out std_logic_vector(7 downto 0); --! Port 2 data output
p2_dout_en : out std_logic_vector(7 downto 0); --! Port 2 data output enable
p2_sel : out std_logic_vector(7 downto 0); --! Port 2 function select
p3_dout : out std_logic_vector(7 downto 0); --! Port 3 data output
p3_dout_en : out std_logic_vector(7 downto 0); --! Port 3 data output enable
p3_sel : out std_logic_vector(7 downto 0); --! Port 3 function select
p4_dout : out std_logic_vector(7 downto 0); --! Port 4 data output
p4_dout_en : out std_logic_vector(7 downto 0); --! Port 4 data output enable
p4_sel : out std_logic_vector(7 downto 0); --! Port 4 function select
p5_dout : out std_logic_vector(7 downto 0); --! Port 5 data output
p5_dout_en : out std_logic_vector(7 downto 0); --! Port 5 data output enable
p5_sel : out std_logic_vector(7 downto 0); --! Port 5 function select
p6_dout : out std_logic_vector(7 downto 0); --! Port 6 data output
p6_dout_en : out std_logic_vector(7 downto 0); --! Port 6 data output enable
p6_sel : out std_logic_vector(7 downto 0); --! Port 6 function select
per_dout : out std_logic_vector(15 downto 0) --! Peripheral data output
);
end entity fmsp_gpio;
architecture RTL of fmsp_gpio is
--=============================================================================
--! 1) PARAMETER DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000000000000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 7;
--! Register addresses offset
constant LED_CTRL : integer := 0; --! ''h0,
constant P1IN : integer := 32; --! ''h20, --! Port 1
constant P1OUT : integer := 33; --! ''h21,
constant P1DIR : integer := 34; --! ''h22,
constant P1IFG : integer := 35; --! ''h23,
constant P1IES : integer := 36; --! ''h24,
constant P1IE : integer := 37; --! ''h25,
constant P1SEL : integer := 38; --! ''h26,
constant P2IN : integer := 40; --! ''h28, --! Port 2
constant P2OUT : integer := 41; --! ''h29,
constant P2DIR : integer := 42; --! ''h2A,
constant P2IFG : integer := 43; --! ''h2B,
constant P2IES : integer := 44; --! ''h2C,
constant P2IE : integer := 45; --! ''h2D,
constant P2SEL : integer := 46; --! ''h2E,
constant P3IN : integer := 24; --! ''h18, --! Port 3
constant P3OUT : integer := 25; --! ''h19,
constant P3DIR : integer := 26; --! ''h1A,
constant P3SEL : integer := 27; --! ''h1B,
constant P4IN : integer := 28; --! ''h1C, --! Port 4
constant P4OUT : integer := 29; --! ''h1D,
constant P4DIR : integer := 30; --! ''h1E,
constant P4SEL : integer := 31; --! ''h1F,
constant P5IN : integer := 48; --! ''h30, --! Port 5
constant P5OUT : integer := 49; --! ''h31,
constant P5DIR : integer := 50; --! ''h32,
constant P5SEL : integer := 51; --! ''h33,
constant P6IN : integer := 52; --! ''h34, --! Port 6
constant P6OUT : integer := 53; --! ''h35,
constant P6DIR : integer := 54; --! ''h36,
constant P6SEL : integer := 55; --! ''h37;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
type fmsp_gpio_in_type is record
p1_din : std_logic_vector(7 downto 0); --! Port 1 data input
p2_din : std_logic_vector(7 downto 0); --! Port 2 data input
p3_din : std_logic_vector(7 downto 0); --! Port 3 data input
p4_din : std_logic_vector(7 downto 0); --! Port 4 data input
p5_din : std_logic_vector(7 downto 0); --! Port 5 data input
p6_din : std_logic_vector(7 downto 0); --! Port 6 data input
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! From sub modules
p1in : std_logic_vector(7 downto 0); --! Port 1 data input
p2in : std_logic_vector(7 downto 0); --! Port 2 data input
p3in : std_logic_vector(7 downto 0); --! Port 3 data input
p4in : std_logic_vector(7 downto 0); --! Port 4 data input
p5in : std_logic_vector(7 downto 0); --! Port 5 data input
p6in : std_logic_vector(7 downto 0); --! Port 6 data input
end record;
type reg_type is record
p1out : std_logic_vector(7 downto 0);
p1dir : std_logic_vector(7 downto 0);
p1ifg : std_logic_vector(7 downto 0);
p1ies : std_logic_vector(7 downto 0);
p1ie : std_logic_vector(7 downto 0);
p1sel : std_logic_vector(7 downto 0);
p2out : std_logic_vector(7 downto 0);
p2dir : std_logic_vector(7 downto 0);
p2ifg : std_logic_vector(7 downto 0);
p2ies : std_logic_vector(7 downto 0);
p2ie : std_logic_vector(7 downto 0);
p2sel : std_logic_vector(7 downto 0);
p3out : std_logic_vector(7 downto 0);
p3dir : std_logic_vector(7 downto 0);
p3sel : std_logic_vector(7 downto 0);
p4out : std_logic_vector(7 downto 0);
p4dir : std_logic_vector(7 downto 0);
p4sel : std_logic_vector(7 downto 0);
p5out : std_logic_vector(7 downto 0);
p5dir : std_logic_vector(7 downto 0);
p5sel : std_logic_vector(7 downto 0);
p6out : std_logic_vector(7 downto 0);
p6dir : std_logic_vector(7 downto 0);
p6sel : std_logic_vector(7 downto 0);
p1in_dly : std_logic_vector(7 downto 0);
p2in_dly : std_logic_vector(7 downto 0);
end record;
signal d : fmsp_gpio_in_type;
signal r : reg_type := ( p1out => "00000000",
p1dir => "00000000",
p1ifg => "00000000",
p1ies => "00000000",
p1ie => "00000000",
p1sel => "00000000",
p2out => "00000000",
p2dir => "00000000",
p2ifg => "00000000",
p2ies => "00000000",
p2ie => "00000000",
p2sel => "00000000",
p3out => "00000000",
p3dir => "00000000",
p3sel => "00000000",
p4out => "00000000",
p4dir => "00000000",
p4sel => "00000000",
p5out => "00000000",
p5dir => "00000000",
p5sel => "00000000",
p6out => "00000000",
p6dir => "00000000",
p6sel => "00000000",
p1in_dly => "00000000",
p2in_dly => "00000000"
);
signal rin : reg_type;
begin
d.p1_din <= p1_din;
d.p2_din <= p2_din;
d.p3_din <= p3_din;
d.p4_din <= p4_din;
d.p5_din <= p5_din;
d.p6_din <= p6_din;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
COMB : process (d, r)
variable v : reg_type;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_lo_write : std_logic;
variable v_reg_hi_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
--! P1OUT Register
variable v_p1in : std_logic_vector(7 downto 0);
variable v_p1out_wr : std_logic;
variable v_p1out_nxt : std_logic_vector(7 downto 0);
--! P1DIR Register
variable v_p1dir_wr : std_logic;
variable v_p1dir_nxt : std_logic_vector(7 downto 0);
variable v_p1_dout_en : std_logic_vector(7 downto 0);
--! P1IFG Register
variable v_p1ifg_wr : std_logic;
variable v_p1ifg_nxt : std_logic_vector(7 downto 0);
variable v_p1ifg_set : std_logic_vector(7 downto 0);
--! P1IES Register
variable v_p1ies_wr : std_logic;
variable v_p1ies_nxt : std_logic_vector(7 downto 0);
--! P1IE Register
variable v_p1ie_wr : std_logic;
variable v_p1ie_nxt : std_logic_vector(7 downto 0);
--! P1SEL Register
variable v_p1sel_wr : std_logic;
variable v_p1sel_nxt : std_logic_vector(7 downto 0);
variable v_p1_sel : std_logic_vector(7 downto 0);
--! P2IN Register
variable v_p2in : std_logic_vector(7 downto 0);
--! P2OUT Register
variable v_p2out_wr : std_logic;
variable v_p2out_nxt : std_logic_vector(7 downto 0);
--! P2DIR Register
variable v_p2dir_wr : std_logic;
variable v_p2dir_nxt : std_logic_vector(7 downto 0);
variable v_p2_dout_en : std_logic_vector(7 downto 0);
--! P2IFG Register
variable v_p2ifg_wr : std_logic;
variable v_p2ifg_nxt : std_logic_vector(7 downto 0);
variable v_p2ifg_set : std_logic_vector(7 downto 0);
--! P2IES Register
variable v_p2ies_wr : std_logic;
variable v_p2ies_nxt : std_logic_vector(7 downto 0);
--! P2IE Register
variable v_p2ie_wr : std_logic;
variable v_p2ie_nxt : std_logic_vector(7 downto 0);
--! P2SEL Register
variable v_p2sel_wr : std_logic;
variable v_p2sel_nxt : std_logic_vector(7 downto 0);
variable v_p2_sel : std_logic_vector(7 downto 0);
--! P3OUT Register
variable v_p3in : std_logic_vector(7 downto 0);
variable v_p3out_wr : std_logic;
variable v_p3out_nxt : std_logic_vector(7 downto 0);
--! P3DIR Register
variable v_p3dir_wr : std_logic;
variable v_p3dir_nxt : std_logic_vector(7 downto 0);
variable v_p3_dout_en : std_logic;
--! P3SEL Register
variable v_p3sel_wr : std_logic;
variable v_p3sel_nxt : std_logic_vector(7 downto 0);
variable v_p3_sel : std_logic_vector(7 downto 0);
--! P4OUT Register
variable v_p4in : std_logic_vector(7 downto 0);
variable v_p4out_wr : std_logic;
variable v_p4out_nxt : std_logic_vector(7 downto 0);
--! P4DIR Register
variable v_p4dir_wr : std_logic;
variable v_p4dir_nxt : std_logic_vector(7 downto 0);
variable v_p4_dout_en : std_logic_vector(7 downto 0);
--! P4SEL Register
variable v_p4sel_wr : std_logic;
variable v_p4sel_nxt : std_logic_vector(7 downto 0);
variable v_p4_sel : std_logic_vector(7 downto 0);
--! P5OUT Register
variable v_p5in : std_logic_vector(7 downto 0);
variable v_p5out_wr : std_logic;
variable v_p5out_nxt : std_logic_vector(7 downto 0);
--! P5DIR Register
variable v_p5dir_wr : std_logic;
variable v_p5dir_nxt : std_logic_vector(7 downto 0);
variable v_p5_dout_en : std_logic;
--! P5SEL Register
variable v_p5sel_wr : std_logic;
variable v_p5sel_nxt : std_logic_vector(7 downto 0);
variable v_p5_sel : std_logic_vector(7 downto 0);
--! P6OUT Register
variable v_p6in : std_logic_vector(7 downto 0);
variable v_p6out_wr : std_logic;
variable v_p6out_nxt : std_logic_vector(7 downto 0);
--! P6DIR Register
variable v_p6dir_wr : std_logic;
variable v_p6dir_nxt : std_logic_vector(7 downto 0);
variable v_p6_dout_en : std_logic_vector(7 downto 0);
--! P6SEL Register
variable v_p6sel_wr : std_logic;
variable v_p6sel_nxt : std_logic_vector(7 downto 0);
variable v_p6_sel : std_logic_vector(7 downto 0);
--! 4) INTERRUPT GENERATION
--! Port 1 interrupt
--! Edge detection
variable v_p1in_re : std_logic_vector(7 downto 0);
variable v_p1in_fe : std_logic_vector(7 downto 0);
--! Set interrupt flag
--variable v_p1ifg_set : std_logic;
--! Generate CPU interrupt
variable v_irq_port1 : std_logic;
--! Port 1 interrupt
--------------------
--! Delay input
--! Edge detection
variable v_p2in_re : std_logic_vector(7 downto 0);
variable v_p2in_fe : std_logic_vector(7 downto 0);
--! Set interrupt flag
--variable v_p2ifg_set : std_logic;
--! Generate CPU interrupt
variable v_irq_port2 : std_logic;
--! Data output mux
variable v_p1in_rd : std_logic_vector(15 downto 0);
variable v_p1out_rd : std_logic_vector(15 downto 0);
variable v_p1dir_rd : std_logic_vector(15 downto 0);
variable v_p1ifg_rd : std_logic_vector(15 downto 0);
variable v_p1ies_rd : std_logic_vector(15 downto 0);
variable v_p1ie_rd : std_logic_vector(15 downto 0);
variable v_p1sel_rd : std_logic_vector(15 downto 0);
variable v_p2in_rd : std_logic_vector(15 downto 0);
variable v_p2out_rd : std_logic_vector(15 downto 0);
variable v_p2dir_rd : std_logic_vector(15 downto 0);
variable v_p2ifg_rd : std_logic_vector(15 downto 0);
variable v_p2ies_rd : std_logic_vector(15 downto 0);
variable v_p2ie_rd : std_logic_vector(15 downto 0);
variable v_p2sel_rd : std_logic_vector(15 downto 0);
variable v_p3in_rd : std_logic_vector(15 downto 0);
variable v_p3out_rd : std_logic_vector(15 downto 0);
variable v_p3dir_rd : std_logic_vector(15 downto 0);
variable v_p3sel_rd : std_logic_vector(15 downto 0);
variable v_p4in_rd : std_logic_vector(15 downto 0);
variable v_p4out_rd : std_logic_vector(15 downto 0);
variable v_p4dir_rd : std_logic_vector(15 downto 0);
variable v_p4sel_rd : std_logic_vector(15 downto 0);
variable v_p5in_rd : std_logic_vector(15 downto 0);
variable v_p5out_rd : std_logic_vector(15 downto 0);
variable v_p5dir_rd : std_logic_vector(15 downto 0);
variable v_p5sel_rd : std_logic_vector(15 downto 0);
variable v_p6in_rd : std_logic_vector(15 downto 0);
variable v_p6out_rd : std_logic_vector(15 downto 0);
variable v_p6dir_rd : std_logic_vector(15 downto 0);
variable v_p6sel_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_lo_write := v_reg_sel and d.per_we(0);
v_reg_hi_write := v_reg_sel and d.per_we(1);
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_lo_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_hi_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 4) INTERRUPT GENERATION
--============================================================================
--! Port 1 interrupt
if (P1_EN = false) then
v_p1in := "00000000";
elsif (SYNC_P1 = true) then
v_p1in := d.p1in;
else
v_p1in := d.p1_din;
end if;
--! Delay input
v.p1in_dly := v_p1in;
--! Edge detection
v_p1in_re := v_p1in and not( r.p1in_dly);
v_p1in_fe := not(v_p1in) and r.p1in_dly;
--! Set interrupt flag
for i in 0 to 7 loop
if (P1_EN = false) then
v_p1ifg_set(i) := '0';
elsif (r.p1ies(i) = '1') then
v_p1ifg_set(i) := v_p1in_fe(i);
else
v_p1ifg_set(i) := v_p1in_re(i);
end if;
end loop;
--! Generate CPU interrupt
if (P1_EN = false) then
v_irq_port1 := '0';
elsif ( (r.p1ie and r.p1ifg) /= "00000000") then
v_irq_port1 := '1';
else
v_irq_port1 := '0';
end if;
--! Port 2 interrupt
if (P2_EN = false) then
v_p2in := "00000000";
elsif (SYNC_P2 = true) then
v_p2in := d.p2in;
else
v_p2in := d.p2_din;
end if;
--! Delay input
v.p2in_dly := v_p2in;
--! Edge detection
v_p2in_re := d.p2in and not( r.p2in_dly);
v_p2in_fe := not(d.p2in) and r.p2in_dly;
--! Set interrupt flag
for i in 0 to 7 loop
if (P2_EN = false) then
v_p2ifg_set(i) := '0';
elsif (r.p2ies(i) = '1') then
v_p2ifg_set(i) := v_p2in_fe(i);
else
v_p2ifg_set(i) := v_p2in_re(i);
end if;
end loop;
--! Generate CPU interrupt
if (P2_EN = false) then
v_irq_port2 := '0';
elsif ( (r.p2ie and r.p2ifg) /= "00000000") then
v_irq_port2 := '1';
else
v_irq_port2 := '0';
end if;
--============================================================================
--! 3) REGISTERS
--============================================================================
--! P1IFG Register
v_p1ifg_wr := v_reg_wr(P1IFG);
v_p1ifg_nxt := byte_per_select_din( P1IFG, d.per_din );
if (P1_EN = false) then
v.p1ifg := "00000000";
elsif (v_p1ies_wr = '1') then
v.p1ifg := v_p1ifg_nxt or v_p1ifg_set;
else
v.p1ifg := r.p1ifg or v_p1ifg_set;
end if;
--! P1IES Register
v_p1ies_wr := v_reg_wr(P1IES);
v_p1ies_nxt := byte_per_select_din( P1IES, d.per_din );
if (P1_EN = false) then
v.p1ies := "00000000";
elsif (v_p1ies_wr = '1') then
v.p1ies := v_p1ies_nxt;
end if;
--! P1IE Register
v_p1ie_wr := v_reg_wr(P1IE);
v_p1ie_nxt := byte_per_select_din( P1IE, d.per_din );
if (P1_EN = false) then
v.p1ie := "00000000";
elsif (v_p1ie_wr = '1') then
v.p1ie := v_p1ie_nxt;
end if;
--! P2IFG Register
v_p2ifg_wr := v_reg_wr(P2IFG);
v_p2ifg_nxt := byte_per_select_din( P2IFG, d.per_din );
if (P2_EN = false) then
v.p2ifg := "00000000";
elsif (v_p2ies_wr = '1') then
v.p2ifg := v_p2ifg_nxt or v_p2ifg_set;
else
v.p2ifg := r.p2ifg or v_p2ifg_set;
end if;
--! P2IES Register
v_p2ies_wr := v_reg_wr(P2IES);
v_p2ies_nxt := byte_per_select_din( P2IES, d.per_din );
if (P2_EN = false) then
v.p2ies := "00000000";
elsif (v_p2ies_wr = '1') then
v.p2ies := v_p2ies_nxt;
end if;
--! P2IE Register
v_p2ie_wr := v_reg_wr(P2IE);
v_p2ie_nxt := byte_per_select_din( P2IE, d.per_din );
if (P2_EN = false) then
v.p2ie := "00000000";
elsif (v_p2ie_wr = '1') then
v.p2ie := v_p2ie_nxt;
end if;
--! P1OUT Register
v_p1out_wr := v_reg_wr(P1OUT);
v_p1out_nxt := byte_per_select_din( P1OUT, d.per_din );
if (P1_EN = false) then
v.p1out := "00000000";
elsif (v_p1out_wr = '1') then
v.p1out := v_p1out_nxt;
end if;
--! P1DIR Register
v_p1dir_wr := v_reg_wr(P1DIR);
v_p1dir_nxt := byte_per_select_din( P1DIR, d.per_din );
if (P1_EN = false) then
v.p1dir := "00000000";
elsif (v_p1dir_wr = '1') then
v.p1dir := v_p1dir_nxt;
end if;
--! P1SEL Register
v_p1sel_wr := v_reg_wr(P1SEL);
v_p1sel_nxt := byte_per_select_din( P1SEL, d.per_din );
if (P1_EN = false) then
v.p1sel := "00000000";
elsif (v_p1sel_wr = '1') then
v.p1sel := v_p1sel_nxt;
end if;
--! P2OUT Register
v_p2out_wr := v_reg_wr(P2OUT);
v_p2out_nxt := byte_per_select_din( P2OUT, d.per_din );
if (P2_EN = false) then
v.p2out := "00000000";
elsif (v_p2out_wr = '1') then
v.p2out := v_p2out_nxt;
end if;
--! P2DIR Register
v_p2dir_wr := v_reg_wr(P2DIR);
v_p2dir_nxt := byte_per_select_din( P2DIR, d.per_din );
if (P2_EN = false) then
v.p2dir := "00000000";
elsif (v_p2dir_wr = '1') then
v.p2dir := v_p2dir_nxt;
end if;
--! P2SEL Register
v_p2sel_wr := v_reg_wr(P2SEL);
v_p2sel_nxt := byte_per_select_din( P2SEL, d.per_din );
if (P2_EN = false) then
v.p2sel := "00000000";
elsif (v_p2sel_wr = '1') then
v.p2sel := v_p2sel_nxt;
end if;
--! P3IN Register
if (P3_EN = false) then
v_p3in := "00000000";
elsif (SYNC_P3 = true) then
v_p3in := d.p3in;
else
v_p3in := d.p3_din;
end if;
--! P3OUT Register
v_p3out_wr := v_reg_wr(P3OUT);
v_p3out_nxt := byte_per_select_din( P3OUT, d.per_din );
if (P3_EN = false) then
v.p3out := "00000000";
elsif (v_p3out_wr = '1') then
v.p3out := v_p3out_nxt;
end if;
--! P3DIR Register
v_p3dir_wr := v_reg_wr(P3DIR);
v_p3dir_nxt := byte_per_select_din( P3DIR, d.per_din );
if (P3_EN = false) then
v.p3dir := "00000000";
elsif (v_p3dir_wr = '1') then
v.p3dir := v_p3dir_nxt;
end if;
--! P3SEL Register
v_p3sel_wr := v_reg_wr(P3SEL);
v_p3sel_nxt := byte_per_select_din( P3SEL, d.per_din );
if (P3_EN = false) then
v.p3sel := "00000000";
elsif (v_p3sel_wr = '1') then
v.p3sel := v_p3sel_nxt;
end if;
--! P4IN Register
if (P4_EN = false) then
v_p4in := "00000000";
elsif (SYNC_P4 = true) then
v_p4in := d.p4in;
else
v_p4in := d.p4_din;
end if;
--! P4OUT Register
v_p4out_wr := v_reg_wr(P4OUT);
v_p4out_nxt := byte_per_select_din( P4OUT, d.per_din );
if (P4_EN = false) then
v.p4out := "00000000";
elsif (v_p4out_wr = '1') then
v.p4out := v_p4out_nxt;
end if;
--! P4DIR Register
v_p4dir_wr := v_reg_wr(P4DIR);
v_p4dir_nxt := byte_per_select_din( P4DIR, d.per_din );
if (P4_EN = false) then
v.p4dir := "00000000";
elsif (v_p4dir_wr = '1') then
v.p4dir := v_p4dir_nxt;
end if;
--! P4SEL Register
v_p4sel_wr := v_reg_wr(P4SEL);
v_p4sel_nxt := byte_per_select_din( P4SEL, d.per_din );
if (P4_EN = false) then
v.p4sel := "00000000";
elsif (v_p4sel_wr = '1') then
v.p4sel := v_p4sel_nxt;
end if;
--! P5IN Register
if (P5_EN = false) then
v_p5in := "00000000";
elsif (SYNC_P5 = true) then
v_p5in := d.p5in;
else
v_p5in := d.p5_din;
end if;
--! P5OUT Register
v_p5out_wr := v_reg_wr(P5OUT);
v_p5out_nxt := byte_per_select_din( P5OUT, d.per_din );
if (P5_EN = false) then
v.p5out := "00000000";
elsif (v_p5out_wr = '1') then
v.p5out := v_p5out_nxt;
end if;
--! P5DIR Register
v_p5dir_wr := v_reg_wr(P5DIR);
v_p5dir_nxt := byte_per_select_din( P5DIR, d.per_din );
if (P5_EN = false) then
v.p5dir := "00000000";
elsif (v_p5dir_wr = '1') then
v.p5dir := v_p5dir_nxt;
end if;
--! P5SEL Register
v_p5sel_wr := v_reg_wr(P5SEL);
v_p5sel_nxt := byte_per_select_din( P5SEL, d.per_din );
if (P5_EN = false) then
v.p5sel := "00000000";
elsif (v_p5sel_wr = '1') then
v.p5sel := v_p5sel_nxt;
end if;
--! P6IN Register
if (P6_EN = false) then
v_p6in := "00000000";
elsif (SYNC_P6 = true) then
v_p6in := d.p6in;
else
v_p6in := d.p6_din;
end if;
--! P6OUT Register
v_p6out_wr := v_reg_wr(P6OUT);
v_p6out_nxt := byte_per_select_din( P6OUT, d.per_din );
if (P6_EN = false) then
v.p6out := "00000000";
elsif (v_p6out_wr = '1') then
v.p6out := v_p6out_nxt;
end if;
--! P6DIR Register
v_p6dir_wr := v_reg_wr(P6DIR);
v_p6dir_nxt := byte_per_select_din( P6DIR, d.per_din );
if (P6_EN = false) then
v.p6dir := "00000000";
elsif (v_p6dir_wr = '1') then
v.p6dir := v_p6dir_nxt;
end if;
--! P6SEL Register
v_p6sel_wr := v_reg_wr(P6SEL);
v_p6sel_nxt := byte_per_select_din( P6SEL, d.per_din );
if (P6_EN = false) then
v.p6sel := "00000000";
elsif (v_p6sel_wr = '1') then
v.p6sel := v_p6sel_nxt;
end if;
--============================================================================
--! 5) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_p1in_rd := byte_per_select_dout( P1IN, v_reg_rd, v_p1in );
v_p1out_rd := byte_per_select_dout( P1OUT, v_reg_rd, r.p1out );
v_p1dir_rd := byte_per_select_dout( P1DIR, v_reg_rd, r.p1dir );
v_p1ifg_rd := byte_per_select_dout( P1IFG, v_reg_rd, r.p1ifg );
v_p1ies_rd := byte_per_select_dout( P1IES, v_reg_rd, r.p1ies );
v_p1ie_rd := byte_per_select_dout( P1IE, v_reg_rd, r.p1ie );
v_p1sel_rd := byte_per_select_dout( P1SEL, v_reg_rd, r.p1sel );
v_p2in_rd := byte_per_select_dout( P2IN, v_reg_rd, v_p2in );
v_p2out_rd := byte_per_select_dout( P2OUT, v_reg_rd, r.p2out );
v_p2dir_rd := byte_per_select_dout( P2DIR, v_reg_rd, r.p2dir );
v_p2ifg_rd := byte_per_select_dout( P2IFG, v_reg_rd, r.p2ifg );
v_p2ies_rd := byte_per_select_dout( P2IES, v_reg_rd, r.p2ies );
v_p2ie_rd := byte_per_select_dout( P2IE, v_reg_rd, r.p2ie );
v_p2sel_rd := byte_per_select_dout( P2SEL, v_reg_rd, r.p2sel );
v_p3in_rd := byte_per_select_dout( P3IN, v_reg_rd, v_p3in );
v_p3out_rd := byte_per_select_dout( P3OUT, v_reg_rd, r.p3out );
v_p3dir_rd := byte_per_select_dout( P3DIR, v_reg_rd, r.p3dir );
v_p3sel_rd := byte_per_select_dout( P3SEL, v_reg_rd, r.p3sel );
v_p4in_rd := byte_per_select_dout( P4IN, v_reg_rd, v_p4in );
v_p4out_rd := byte_per_select_dout( P4OUT, v_reg_rd, r.p4out );
v_p4dir_rd := byte_per_select_dout( P4DIR, v_reg_rd, r.p4dir );
v_p4sel_rd := byte_per_select_dout( P4SEL, v_reg_rd, r.p4sel );
v_p5in_rd := byte_per_select_dout( P5IN, v_reg_rd, v_p5in );
v_p5out_rd := byte_per_select_dout( P5OUT, v_reg_rd, r.p5out );
v_p5dir_rd := byte_per_select_dout( P5DIR, v_reg_rd, r.p5dir );
v_p5sel_rd := byte_per_select_dout( P5SEL, v_reg_rd, r.p5sel );
v_p6in_rd := byte_per_select_dout( P6IN, v_reg_rd, v_p6in );
v_p6out_rd := byte_per_select_dout( P6OUT, v_reg_rd, r.p6out );
v_p6dir_rd := byte_per_select_dout( P6DIR, v_reg_rd, r.p6dir );
v_p6sel_rd := byte_per_select_dout( P6SEL, v_reg_rd, r.p6sel );
v_per_dout := v_p1in_rd
or v_p1out_rd
or v_p1dir_rd
or v_p1ifg_rd
or v_p1ies_rd
or v_p1ie_rd
or v_p1sel_rd
or v_p2in_rd
or v_p2out_rd
or v_p2dir_rd
or v_p2ifg_rd
or v_p2ies_rd
or v_p2ie_rd
or v_p2sel_rd
or v_p3in_rd
or v_p3out_rd
or v_p3dir_rd
or v_p3sel_rd
or v_p4in_rd
or v_p4out_rd
or v_p4dir_rd
or v_p4sel_rd
or v_p5in_rd
or v_p5out_rd
or v_p5dir_rd
or v_p5sel_rd
or v_p6in_rd
or v_p6out_rd
or v_p6dir_rd
or v_p6sel_rd;
--! drive register inputs
rin <= v;
--! drive module outputs
irq_port1 <= v_irq_port1; --! Port 1 interrupt
irq_port2 <= v_irq_port2; --! Port 2 interrupt
p1_dout <= r.p1out; --! Port 1 data output
p1_dout_en <= r.p1dir; --! Port 1 data output enable
p1_sel <= r.p1sel; --! Port 1 function select
p2_dout <= r.p2out; --! Port 2 data output
p2_dout_en <= r.p2dir; --! Port 2 data output enable
p2_sel <= r.p2sel; --! Port 2 function select
p3_dout <= r.p3out; --! Port 3 data output
p3_dout_en <= r.p3dir; --! Port 3 data output enable
p3_sel <= r.p3sel; --! Port 3 function select
p4_dout <= r.p4out; --! Port 4 data output
p4_dout_en <= r.p4dir; --! Port 4 data output enable
p4_sel <= r.p4sel; --! Port 4 function select
p5_dout <= r.p5out; --! Port 5 data output
p5_dout_en <= r.p5dir; --! Port 5 data output enable
p5_sel <= r.p5sel; --! Port 5 function select
p6_dout <= r.p6out; --! Port 6 data output
p6_dout_en <= r.p6dir; --! Port 6 data output enable
p6_sel <= r.p6sel; --! Port 6 function select
per_dout <= v_per_dout; --! Peripheral data output
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r.p1out <= "00000000";
r.p1dir <= "00000000";
r.p1ifg <= "00000000";
r.p1ies <= "00000000";
r.p1ie <= "00000000";
r.p1sel <= "00000000";
r.p2out <= "00000000";
r.p2dir <= "00000000";
r.p2ifg <= "00000000";
r.p2ies <= "00000000";
r.p2ie <= "00000000";
r.p2sel <= "00000000";
r.p3out <= "00000000";
r.p3dir <= "00000000";
r.p3sel <= "00000000";
r.p4out <= "00000000";
r.p4dir <= "00000000";
r.p4sel <= "00000000";
r.p5out <= "00000000";
r.p5dir <= "00000000";
r.p5sel <= "00000000";
r.p6out <= "00000000";
r.p6dir <= "00000000";
r.p6sel <= "00000000";
r.p1in_dly <= "00000000";
r.p2in_dly <= "00000000";
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
p1_in_sync : for i in 0 to 7 generate
sync_cell_p1in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p1_din(i),
data_out => d.p1in(i)
);
end generate;
p2_in_sync : for i in 0 to 7 generate
sync_cell_p2in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p2_din(i),
data_out => d.p2in(i)
);
end generate;
p3_in_sync : for i in 0 to 7 generate
sync_cell_p3in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p3_din(i),
data_out => d.p3in(i)
);
end generate;
p4_in_sync : for i in 0 to 7 generate
sync_cell_p4in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p4_din(i),
data_out => d.p4in(i)
);
end generate;
p5_in_sync : for i in 0 to 7 generate
sync_cell_p5in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p5_din(i),
data_out => d.p5in(i)
);
end generate;
p6_in_sync : for i in 0 to 7 generate
sync_cell_p6in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p6_din(i),
data_out => d.p6in(i)
);
end generate;
end RTL; --! fmsp_gpio
| bsd-3-clause | 14f484adc25e7634be7b3f55e29863bc | 0.588067 | 2.354528 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/game_rom.vhd | 1 | 126,188 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity game_rom is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end game_rom;
architecture Behavioral of game_rom is
type RAM is array ( ( 16 * 4096 ) - 1 downto 0 ) of std_logic_vector( 7 downto 0 );
signal sys_RAM : RAM := (
-- light travels left
(0 + 136) => x"00", (0 + 137) => x"00", -- delay
(0 + 138) => x"00",
512 => x"66", 513 => x"01", -- LD V6, 0x01
514 => x"61", 515 => x"3C", -- LD V1, 0x3C
516 => x"F1", 517 => x"15", -- LD DT, V1; ; loop
518 => x"86", 519 => x"6E", -- SHL V6, V6
520 => x"4F", 521 => x"01", -- SNE VF, 0x01
522 => x"66", 523 => x"01", -- LD V6, 0x01
524 => x"80", 525 => x"60", -- LD V0, V6
526 => x"A1", 527 => x"FF", -- LD I, 0x1FF
528 => x"F0", 529 => x"55", -- LD [I], V0
530 => x"F2", 531 => x"07", -- LD V2, DT ; wait
532 => x"32", 533 => x"00", -- SE V2, 0x00
534 => x"12", 535 => x"12", -- JP wait
536 => x"12", 537 => x"04", -- JP loop
-- light travels right
(4096 + 136) => x"00", (4096 + 137) => x"00", -- delay
(4096 + 138) => x"00",
(4096 + 512) => x"66", (4096 + 513) => x"80", -- LD V6, 0x80
(4096 + 514) => x"61", (4096 + 515) => x"3C", -- LD V1, 0x3C
(4096 + 516) => x"F1", (4096 + 517) => x"15", -- LD DT, V1; ; loop
(4096 + 518) => x"86", (4096 + 519) => x"66", -- SHR V6, V6
(4096 + 520) => x"4F", (4096 + 521) => x"01", -- SNE VF, 0x01
(4096 + 522) => x"66", (4096 + 523) => x"80", -- LD V6, 0x80
(4096 + 524) => x"80", (4096 + 525) => x"60", -- LD V0, V6
(4096 + 526) => x"A1", (4096 + 527) => x"FF", -- LD I, 0x1FF
(4096 + 528) => x"F0", (4096 + 529) => x"55", -- LD [I], V0
(4096 + 530) => x"F2", (4096 + 531) => x"07", -- LD V2, DT ; wait
(4096 + 532) => x"32", (4096 + 533) => x"00", -- SE V2, 0x00
(4096 + 534) => x"12", (4096 + 535) => x"12", -- JP wait
(4096 + 536) => x"12", (4096 + 537) => x"04", -- JP loop
-- random lights
(8192 + 136) => x"00", (8192 + 137) => x"00", -- delay
(8192 + 138) => x"00",
(8192 + 512) => x"61", (8192 + 513) => x"3C", -- LD V1, 0x3C
(8192 + 514) => x"F1", (8192 + 515) => x"15", -- LD DT, V1; ; loop
(8192 + 516) => x"C0", (8192 + 517) => x"FF", -- RND V0, FF
(8192 + 518) => x"A1", (8192 + 519) => x"FF", -- LD I, 0x1FF
(8192 + 520) => x"F0", (8192 + 521) => x"55", -- LD [I], V0
(8192 + 522) => x"F2", (8192 + 523) => x"07", -- LD V2, DT ; wait
(8192 + 524) => x"32", (8192 + 525) => x"00", -- SE V2, 0x00
(8192 + 526) => x"12", (8192 + 527) => x"0A", -- JP wait
(8192 + 528) => x"12", (8192 + 529) => x"02", -- JP loop
-- PONG by Paul Vervalin
(12288 + 128) => x"0C", (12288 + 129) => x"00",
(12288 + 130) => x"F0", (12288 + 131) => x"00",
(12288 + 132) => x"00", (12288 + 133) => x"00",
(12288 + 134) => x"BE", (12288 + 135) => x"00",
(12288 + 136) => x"00", (12288 + 137) => x"30", -- delay
(12288 + 138) => x"00",
(12288 + 512) => x"6a", (12288 + 513) => x"02", (12288 + 514) => x"6b", (12288 + 515) => x"0c", (12288 + 516) => x"6c", (12288 + 517) => x"3f", (12288 + 518) => x"6d", (12288 + 519) => x"0c", (12288 + 520) => x"a2", (12288 + 521) => x"ea", (12288 + 522) => x"da", (12288 + 523) => x"b6", (12288 + 524) => x"dc", (12288 + 525) => x"d6", (12288 + 526) => x"6e", (12288 + 527) => x"00", (12288 + 528) => x"22", (12288 + 529) => x"d4", (12288 + 530) => x"66", (12288 + 531) => x"03", (12288 + 532) => x"68", (12288 + 533) => x"02", (12288 + 534) => x"60", (12288 + 535) => x"60", (12288 + 536) => x"f0", (12288 + 537) => x"15", (12288 + 538) => x"f0", (12288 + 539) => x"07", (12288 + 540) => x"30", (12288 + 541) => x"00", (12288 + 542) => x"12", (12288 + 543) => x"1a", (12288 + 544) => x"c7", (12288 + 545) => x"17", (12288 + 546) => x"77", (12288 + 547) => x"08", (12288 + 548) => x"69", (12288 + 549) => x"ff", (12288 + 550) => x"a2", (12288 + 551) => x"f0", (12288 + 552) => x"d6", (12288 + 553) => x"71", (12288 + 554) => x"a2", (12288 + 555) => x"ea", (12288 + 556) => x"da", (12288 + 557) => x"b6", (12288 + 558) => x"dc", (12288 + 559) => x"d6", (12288 + 560) => x"60", (12288 + 561) => x"01", (12288 + 562) => x"e0", (12288 + 563) => x"a1", (12288 + 564) => x"7b", (12288 + 565) => x"fe", (12288 + 566) => x"60", (12288 + 567) => x"04", (12288 + 568) => x"e0", (12288 + 569) => x"a1", (12288 + 570) => x"7b", (12288 + 571) => x"02", (12288 + 572) => x"60", (12288 + 573) => x"1f", (12288 + 574) => x"8b", (12288 + 575) => x"02", (12288 + 576) => x"da", (12288 + 577) => x"b6", (12288 + 578) => x"60", (12288 + 579) => x"0c", (12288 + 580) => x"e0", (12288 + 581) => x"a1", (12288 + 582) => x"7d", (12288 + 583) => x"fe", (12288 + 584) => x"60", (12288 + 585) => x"0d", (12288 + 586) => x"e0", (12288 + 587) => x"a1", (12288 + 588) => x"7d", (12288 + 589) => x"02", (12288 + 590) => x"60", (12288 + 591) => x"1f", (12288 + 592) => x"8d", (12288 + 593) => x"02", (12288 + 594) => x"dc", (12288 + 595) => x"d6", (12288 + 596) => x"a2", (12288 + 597) => x"f0", (12288 + 598) => x"d6", (12288 + 599) => x"71", (12288 + 600) => x"86", (12288 + 601) => x"84", (12288 + 602) => x"87", (12288 + 603) => x"94", (12288 + 604) => x"60", (12288 + 605) => x"3f", (12288 + 606) => x"86", (12288 + 607) => x"02", (12288 + 608) => x"61", (12288 + 609) => x"1f", (12288 + 610) => x"87", (12288 + 611) => x"12", (12288 + 612) => x"46", (12288 + 613) => x"02", (12288 + 614) => x"12", (12288 + 615) => x"78", (12288 + 616) => x"46", (12288 + 617) => x"3f", (12288 + 618) => x"12", (12288 + 619) => x"82", (12288 + 620) => x"47", (12288 + 621) => x"1f", (12288 + 622) => x"69", (12288 + 623) => x"ff", (12288 + 624) => x"47", (12288 + 625) => x"00", (12288 + 626) => x"69", (12288 + 627) => x"01", (12288 + 628) => x"d6", (12288 + 629) => x"71", (12288 + 630) => x"12", (12288 + 631) => x"2a", (12288 + 632) => x"68", (12288 + 633) => x"02", (12288 + 634) => x"63", (12288 + 635) => x"01", (12288 + 636) => x"80", (12288 + 637) => x"70", (12288 + 638) => x"80", (12288 + 639) => x"b5", (12288 + 640) => x"12", (12288 + 641) => x"8a", (12288 + 642) => x"68", (12288 + 643) => x"fe", (12288 + 644) => x"63", (12288 + 645) => x"0a", (12288 + 646) => x"80", (12288 + 647) => x"70", (12288 + 648) => x"80", (12288 + 649) => x"d5", (12288 + 650) => x"3f", (12288 + 651) => x"01", (12288 + 652) => x"12", (12288 + 653) => x"a2", (12288 + 654) => x"61", (12288 + 655) => x"02", (12288 + 656) => x"80", (12288 + 657) => x"15", (12288 + 658) => x"3f", (12288 + 659) => x"01", (12288 + 660) => x"12", (12288 + 661) => x"ba", (12288 + 662) => x"80", (12288 + 663) => x"15", (12288 + 664) => x"3f", (12288 + 665) => x"01", (12288 + 666) => x"12", (12288 + 667) => x"c8", (12288 + 668) => x"80", (12288 + 669) => x"15", (12288 + 670) => x"3f", (12288 + 671) => x"01", (12288 + 672) => x"12", (12288 + 673) => x"c2", (12288 + 674) => x"60", (12288 + 675) => x"20", (12288 + 676) => x"f0", (12288 + 677) => x"18", (12288 + 678) => x"22", (12288 + 679) => x"d4", (12288 + 680) => x"8e", (12288 + 681) => x"34", (12288 + 682) => x"22", (12288 + 683) => x"d4", (12288 + 684) => x"66", (12288 + 685) => x"3e", (12288 + 686) => x"33", (12288 + 687) => x"01", (12288 + 688) => x"66", (12288 + 689) => x"03", (12288 + 690) => x"68", (12288 + 691) => x"fe", (12288 + 692) => x"33", (12288 + 693) => x"01", (12288 + 694) => x"68", (12288 + 695) => x"02", (12288 + 696) => x"12", (12288 + 697) => x"16", (12288 + 698) => x"79", (12288 + 699) => x"ff", (12288 + 700) => x"49", (12288 + 701) => x"fe", (12288 + 702) => x"69", (12288 + 703) => x"ff", (12288 + 704) => x"12", (12288 + 705) => x"c8", (12288 + 706) => x"79", (12288 + 707) => x"01", (12288 + 708) => x"49", (12288 + 709) => x"02", (12288 + 710) => x"69", (12288 + 711) => x"01", (12288 + 712) => x"60", (12288 + 713) => x"04", (12288 + 714) => x"f0", (12288 + 715) => x"18", (12288 + 716) => x"76", (12288 + 717) => x"01", (12288 + 718) => x"46", (12288 + 719) => x"40", (12288 + 720) => x"76", (12288 + 721) => x"fe", (12288 + 722) => x"12", (12288 + 723) => x"6c", (12288 + 724) => x"a2", (12288 + 725) => x"f2", (12288 + 726) => x"fe", (12288 + 727) => x"33", (12288 + 728) => x"f2", (12288 + 729) => x"65", (12288 + 730) => x"f1", (12288 + 731) => x"29", (12288 + 732) => x"64", (12288 + 733) => x"14", (12288 + 734) => x"65", (12288 + 735) => x"00", (12288 + 736) => x"d4", (12288 + 737) => x"55", (12288 + 738) => x"74", (12288 + 739) => x"15", (12288 + 740) => x"f2", (12288 + 741) => x"29", (12288 + 742) => x"d4", (12288 + 743) => x"55", (12288 + 744) => x"00", (12288 + 745) => x"ee", (12288 + 746) => x"80", (12288 + 747) => x"80", (12288 + 748) => x"80", (12288 + 749) => x"80", (12288 + 750) => x"80", (12288 + 751) => x"80", (12288 + 752) => x"80", (12288 + 753) => x"00", (12288 + 754) => x"00", (12288 + 755) => x"00", (12288 + 756) => x"00", (12288 + 757) => x"00",
-- Tetris by Fran Dachille
(16384 + 128) => x"00", (16384 + 129) => x"F0",
(16384 + 130) => x"DC", (16384 + 131) => x"E0",
(16384 + 132) => x"F0", (16384 + 133) => x"00",
(16384 + 134) => x"BE", (16384 + 135) => x"00",
(16384 + 136) => x"00", (16384 + 137) => x"20", -- delay
(16384 + 138) => x"00",
(16384 + 512) => x"a2", (16384 + 513) => x"b4", (16384 + 514) => x"23", (16384 + 515) => x"e6", (16384 + 516) => x"22", (16384 + 517) => x"b6", (16384 + 518) => x"70", (16384 + 519) => x"01", (16384 + 520) => x"d0", (16384 + 521) => x"11", (16384 + 522) => x"30", (16384 + 523) => x"25", (16384 + 524) => x"12", (16384 + 525) => x"06", (16384 + 526) => x"71", (16384 + 527) => x"ff", (16384 + 528) => x"d0", (16384 + 529) => x"11", (16384 + 530) => x"60", (16384 + 531) => x"1a", (16384 + 532) => x"d0", (16384 + 533) => x"11", (16384 + 534) => x"60", (16384 + 535) => x"25", (16384 + 536) => x"31", (16384 + 537) => x"00", (16384 + 538) => x"12", (16384 + 539) => x"0e", (16384 + 540) => x"c4", (16384 + 541) => x"70", (16384 + 542) => x"44", (16384 + 543) => x"70", (16384 + 544) => x"12", (16384 + 545) => x"1c", (16384 + 546) => x"c3", (16384 + 547) => x"03", (16384 + 548) => x"60", (16384 + 549) => x"1e", (16384 + 550) => x"61", (16384 + 551) => x"03", (16384 + 552) => x"22", (16384 + 553) => x"5c", (16384 + 554) => x"f5", (16384 + 555) => x"15", (16384 + 556) => x"d0", (16384 + 557) => x"14", (16384 + 558) => x"3f", (16384 + 559) => x"01", (16384 + 560) => x"12", (16384 + 561) => x"3c", (16384 + 562) => x"d0", (16384 + 563) => x"14", (16384 + 564) => x"71", (16384 + 565) => x"ff", (16384 + 566) => x"d0", (16384 + 567) => x"14", (16384 + 568) => x"23", (16384 + 569) => x"40", (16384 + 570) => x"12", (16384 + 571) => x"1c", (16384 + 572) => x"e7", (16384 + 573) => x"a1", (16384 + 574) => x"22", (16384 + 575) => x"72", (16384 + 576) => x"e8", (16384 + 577) => x"a1", (16384 + 578) => x"22", (16384 + 579) => x"84", (16384 + 580) => x"e9", (16384 + 581) => x"a1", (16384 + 582) => x"22", (16384 + 583) => x"96", (16384 + 584) => x"e2", (16384 + 585) => x"9e", (16384 + 586) => x"12", (16384 + 587) => x"50", (16384 + 588) => x"66", (16384 + 589) => x"00", (16384 + 590) => x"f6", (16384 + 591) => x"15", (16384 + 592) => x"f6", (16384 + 593) => x"07", (16384 + 594) => x"36", (16384 + 595) => x"00", (16384 + 596) => x"12", (16384 + 597) => x"3c", (16384 + 598) => x"d0", (16384 + 599) => x"14", (16384 + 600) => x"71", (16384 + 601) => x"01", (16384 + 602) => x"12", (16384 + 603) => x"2a", (16384 + 604) => x"a2", (16384 + 605) => x"c4", (16384 + 606) => x"f4", (16384 + 607) => x"1e", (16384 + 608) => x"66", (16384 + 609) => x"00", (16384 + 610) => x"43", (16384 + 611) => x"01", (16384 + 612) => x"66", (16384 + 613) => x"04", (16384 + 614) => x"43", (16384 + 615) => x"02", (16384 + 616) => x"66", (16384 + 617) => x"08", (16384 + 618) => x"43", (16384 + 619) => x"03", (16384 + 620) => x"66", (16384 + 621) => x"0c", (16384 + 622) => x"f6", (16384 + 623) => x"1e", (16384 + 624) => x"00", (16384 + 625) => x"ee", (16384 + 626) => x"d0", (16384 + 627) => x"14", (16384 + 628) => x"70", (16384 + 629) => x"ff", (16384 + 630) => x"23", (16384 + 631) => x"34", (16384 + 632) => x"3f", (16384 + 633) => x"01", (16384 + 634) => x"00", (16384 + 635) => x"ee", (16384 + 636) => x"d0", (16384 + 637) => x"14", (16384 + 638) => x"70", (16384 + 639) => x"01", (16384 + 640) => x"23", (16384 + 641) => x"34", (16384 + 642) => x"00", (16384 + 643) => x"ee", (16384 + 644) => x"d0", (16384 + 645) => x"14", (16384 + 646) => x"70", (16384 + 647) => x"01", (16384 + 648) => x"23", (16384 + 649) => x"34", (16384 + 650) => x"3f", (16384 + 651) => x"01", (16384 + 652) => x"00", (16384 + 653) => x"ee", (16384 + 654) => x"d0", (16384 + 655) => x"14", (16384 + 656) => x"70", (16384 + 657) => x"ff", (16384 + 658) => x"23", (16384 + 659) => x"34", (16384 + 660) => x"00", (16384 + 661) => x"ee", (16384 + 662) => x"d0", (16384 + 663) => x"14", (16384 + 664) => x"73", (16384 + 665) => x"01", (16384 + 666) => x"43", (16384 + 667) => x"04", (16384 + 668) => x"63", (16384 + 669) => x"00", (16384 + 670) => x"22", (16384 + 671) => x"5c", (16384 + 672) => x"23", (16384 + 673) => x"34", (16384 + 674) => x"3f", (16384 + 675) => x"01", (16384 + 676) => x"00", (16384 + 677) => x"ee", (16384 + 678) => x"d0", (16384 + 679) => x"14", (16384 + 680) => x"73", (16384 + 681) => x"ff", (16384 + 682) => x"43", (16384 + 683) => x"ff", (16384 + 684) => x"63", (16384 + 685) => x"03", (16384 + 686) => x"22", (16384 + 687) => x"5c", (16384 + 688) => x"23", (16384 + 689) => x"34", (16384 + 690) => x"00", (16384 + 691) => x"ee", (16384 + 692) => x"80", (16384 + 693) => x"00", (16384 + 694) => x"67", (16384 + 695) => x"05", (16384 + 696) => x"68", (16384 + 697) => x"06", (16384 + 698) => x"69", (16384 + 699) => x"04", (16384 + 700) => x"61", (16384 + 701) => x"1f", (16384 + 702) => x"65", (16384 + 703) => x"10", (16384 + 704) => x"62", (16384 + 705) => x"07", (16384 + 706) => x"00", (16384 + 707) => x"ee", (16384 + 708) => x"40", (16384 + 709) => x"e0", (16384 + 710) => x"00", (16384 + 711) => x"00", (16384 + 712) => x"40", (16384 + 713) => x"c0", (16384 + 714) => x"40", (16384 + 715) => x"00", (16384 + 716) => x"00", (16384 + 717) => x"e0", (16384 + 718) => x"40", (16384 + 719) => x"00", (16384 + 720) => x"40", (16384 + 721) => x"60", (16384 + 722) => x"40", (16384 + 723) => x"00", (16384 + 724) => x"40", (16384 + 725) => x"40", (16384 + 726) => x"60", (16384 + 727) => x"00", (16384 + 728) => x"20", (16384 + 729) => x"e0", (16384 + 730) => x"00", (16384 + 731) => x"00", (16384 + 732) => x"c0", (16384 + 733) => x"40", (16384 + 734) => x"40", (16384 + 735) => x"00", (16384 + 736) => x"00", (16384 + 737) => x"e0", (16384 + 738) => x"80", (16384 + 739) => x"00", (16384 + 740) => x"40", (16384 + 741) => x"40", (16384 + 742) => x"c0", (16384 + 743) => x"00", (16384 + 744) => x"00", (16384 + 745) => x"e0", (16384 + 746) => x"20", (16384 + 747) => x"00", (16384 + 748) => x"60", (16384 + 749) => x"40", (16384 + 750) => x"40", (16384 + 751) => x"00", (16384 + 752) => x"80", (16384 + 753) => x"e0", (16384 + 754) => x"00", (16384 + 755) => x"00", (16384 + 756) => x"40", (16384 + 757) => x"c0", (16384 + 758) => x"80", (16384 + 759) => x"00", (16384 + 760) => x"c0", (16384 + 761) => x"60", (16384 + 762) => x"00", (16384 + 763) => x"00", (16384 + 764) => x"40", (16384 + 765) => x"c0", (16384 + 766) => x"80", (16384 + 767) => x"00", (16384 + 768) => x"c0", (16384 + 769) => x"60", (16384 + 770) => x"00", (16384 + 771) => x"00", (16384 + 772) => x"80", (16384 + 773) => x"c0", (16384 + 774) => x"40", (16384 + 775) => x"00", (16384 + 776) => x"00", (16384 + 777) => x"60", (16384 + 778) => x"c0", (16384 + 779) => x"00", (16384 + 780) => x"80", (16384 + 781) => x"c0", (16384 + 782) => x"40", (16384 + 783) => x"00", (16384 + 784) => x"00", (16384 + 785) => x"60", (16384 + 786) => x"c0", (16384 + 787) => x"00", (16384 + 788) => x"c0", (16384 + 789) => x"c0", (16384 + 790) => x"00", (16384 + 791) => x"00", (16384 + 792) => x"c0", (16384 + 793) => x"c0", (16384 + 794) => x"00", (16384 + 795) => x"00", (16384 + 796) => x"c0", (16384 + 797) => x"c0", (16384 + 798) => x"00", (16384 + 799) => x"00", (16384 + 800) => x"c0", (16384 + 801) => x"c0", (16384 + 802) => x"00", (16384 + 803) => x"00", (16384 + 804) => x"40", (16384 + 805) => x"40", (16384 + 806) => x"40", (16384 + 807) => x"40", (16384 + 808) => x"00", (16384 + 809) => x"f0", (16384 + 810) => x"00", (16384 + 811) => x"00", (16384 + 812) => x"40", (16384 + 813) => x"40", (16384 + 814) => x"40", (16384 + 815) => x"40", (16384 + 816) => x"00", (16384 + 817) => x"f0", (16384 + 818) => x"00", (16384 + 819) => x"00", (16384 + 820) => x"d0", (16384 + 821) => x"14", (16384 + 822) => x"66", (16384 + 823) => x"35", (16384 + 824) => x"76", (16384 + 825) => x"ff", (16384 + 826) => x"36", (16384 + 827) => x"00", (16384 + 828) => x"13", (16384 + 829) => x"38", (16384 + 830) => x"00", (16384 + 831) => x"ee", (16384 + 832) => x"a2", (16384 + 833) => x"b4", (16384 + 834) => x"8c", (16384 + 835) => x"10", (16384 + 836) => x"3c", (16384 + 837) => x"1e", (16384 + 838) => x"7c", (16384 + 839) => x"01", (16384 + 840) => x"3c", (16384 + 841) => x"1e", (16384 + 842) => x"7c", (16384 + 843) => x"01", (16384 + 844) => x"3c", (16384 + 845) => x"1e", (16384 + 846) => x"7c", (16384 + 847) => x"01", (16384 + 848) => x"23", (16384 + 849) => x"5e", (16384 + 850) => x"4b", (16384 + 851) => x"0a", (16384 + 852) => x"23", (16384 + 853) => x"72", (16384 + 854) => x"91", (16384 + 855) => x"c0", (16384 + 856) => x"00", (16384 + 857) => x"ee", (16384 + 858) => x"71", (16384 + 859) => x"01", (16384 + 860) => x"13", (16384 + 861) => x"50", (16384 + 862) => x"60", (16384 + 863) => x"1b", (16384 + 864) => x"6b", (16384 + 865) => x"00", (16384 + 866) => x"d0", (16384 + 867) => x"11", (16384 + 868) => x"3f", (16384 + 869) => x"00", (16384 + 870) => x"7b", (16384 + 871) => x"01", (16384 + 872) => x"d0", (16384 + 873) => x"11", (16384 + 874) => x"70", (16384 + 875) => x"01", (16384 + 876) => x"30", (16384 + 877) => x"25", (16384 + 878) => x"13", (16384 + 879) => x"62", (16384 + 880) => x"00", (16384 + 881) => x"ee", (16384 + 882) => x"60", (16384 + 883) => x"1b", (16384 + 884) => x"d0", (16384 + 885) => x"11", (16384 + 886) => x"70", (16384 + 887) => x"01", (16384 + 888) => x"30", (16384 + 889) => x"25", (16384 + 890) => x"13", (16384 + 891) => x"74", (16384 + 892) => x"8e", (16384 + 893) => x"10", (16384 + 894) => x"8d", (16384 + 895) => x"e0", (16384 + 896) => x"7e", (16384 + 897) => x"ff", (16384 + 898) => x"60", (16384 + 899) => x"1b", (16384 + 900) => x"6b", (16384 + 901) => x"00", (16384 + 902) => x"d0", (16384 + 903) => x"e1", (16384 + 904) => x"3f", (16384 + 905) => x"00", (16384 + 906) => x"13", (16384 + 907) => x"90", (16384 + 908) => x"d0", (16384 + 909) => x"e1", (16384 + 910) => x"13", (16384 + 911) => x"94", (16384 + 912) => x"d0", (16384 + 913) => x"d1", (16384 + 914) => x"7b", (16384 + 915) => x"01", (16384 + 916) => x"70", (16384 + 917) => x"01", (16384 + 918) => x"30", (16384 + 919) => x"25", (16384 + 920) => x"13", (16384 + 921) => x"86", (16384 + 922) => x"4b", (16384 + 923) => x"00", (16384 + 924) => x"13", (16384 + 925) => x"a6", (16384 + 926) => x"7d", (16384 + 927) => x"ff", (16384 + 928) => x"7e", (16384 + 929) => x"ff", (16384 + 930) => x"3d", (16384 + 931) => x"01", (16384 + 932) => x"13", (16384 + 933) => x"82", (16384 + 934) => x"23", (16384 + 935) => x"c0", (16384 + 936) => x"3f", (16384 + 937) => x"01", (16384 + 938) => x"23", (16384 + 939) => x"c0", (16384 + 940) => x"7a", (16384 + 941) => x"01", (16384 + 942) => x"23", (16384 + 943) => x"c0", (16384 + 944) => x"80", (16384 + 945) => x"a0", (16384 + 946) => x"6d", (16384 + 947) => x"07", (16384 + 948) => x"80", (16384 + 949) => x"d2", (16384 + 950) => x"40", (16384 + 951) => x"04", (16384 + 952) => x"75", (16384 + 953) => x"fe", (16384 + 954) => x"45", (16384 + 955) => x"02", (16384 + 956) => x"65", (16384 + 957) => x"04", (16384 + 958) => x"00", (16384 + 959) => x"ee", (16384 + 960) => x"a7", (16384 + 961) => x"00", (16384 + 962) => x"f2", (16384 + 963) => x"55", (16384 + 964) => x"a8", (16384 + 965) => x"04", (16384 + 966) => x"fa", (16384 + 967) => x"33", (16384 + 968) => x"f2", (16384 + 969) => x"65", (16384 + 970) => x"f0", (16384 + 971) => x"29", (16384 + 972) => x"6d", (16384 + 973) => x"32", (16384 + 974) => x"6e", (16384 + 975) => x"00", (16384 + 976) => x"dd", (16384 + 977) => x"e5", (16384 + 978) => x"7d", (16384 + 979) => x"05", (16384 + 980) => x"f1", (16384 + 981) => x"29", (16384 + 982) => x"dd", (16384 + 983) => x"e5", (16384 + 984) => x"7d", (16384 + 985) => x"05", (16384 + 986) => x"f2", (16384 + 987) => x"29", (16384 + 988) => x"dd", (16384 + 989) => x"e5", (16384 + 990) => x"a7", (16384 + 991) => x"00", (16384 + 992) => x"f2", (16384 + 993) => x"65", (16384 + 994) => x"a2", (16384 + 995) => x"b4", (16384 + 996) => x"00", (16384 + 997) => x"ee", (16384 + 998) => x"6a", (16384 + 999) => x"00", (16384 + 1000) => x"60", (16384 + 1001) => x"19", (16384 + 1002) => x"00", (16384 + 1003) => x"ee", (16384 + 1004) => x"37", (16384 + 1005) => x"23",
-- Blitz by David Winter
(20480 + 128) => x"00", (20480 + 129) => x"00",
(20480 + 130) => x"0D", (20480 + 131) => x"00",
(20480 + 132) => x"00", (20480 + 133) => x"00",
(20480 + 134) => x"00", (20480 + 135) => x"00",
(20480 + 136) => x"00", (20480 + 137) => x"20", -- delay
(20480 + 138) => x"00",
(20480 + 512) => x"12", (20480 + 513) => x"17", (20480 + 514) => x"42", (20480 + 515) => x"4c", (20480 + 516) => x"49", (20480 + 517) => x"54", (20480 + 518) => x"5a", (20480 + 519) => x"20", (20480 + 520) => x"42", (20480 + 521) => x"79", (20480 + 522) => x"20", (20480 + 523) => x"44", (20480 + 524) => x"61", (20480 + 525) => x"76", (20480 + 526) => x"69", (20480 + 527) => x"64", (20480 + 528) => x"20", (20480 + 529) => x"57", (20480 + 530) => x"49", (20480 + 531) => x"4e", (20480 + 532) => x"54", (20480 + 533) => x"45", (20480 + 534) => x"52", (20480 + 535) => x"a3", (20480 + 536) => x"41", (20480 + 537) => x"60", (20480 + 538) => x"04", (20480 + 539) => x"61", (20480 + 540) => x"09", (20480 + 541) => x"62", (20480 + 542) => x"0e", (20480 + 543) => x"67", (20480 + 544) => x"04", (20480 + 545) => x"d0", (20480 + 546) => x"1e", (20480 + 547) => x"f2", (20480 + 548) => x"1e", (20480 + 549) => x"70", (20480 + 550) => x"0c", (20480 + 551) => x"30", (20480 + 552) => x"40", (20480 + 553) => x"12", (20480 + 554) => x"21", (20480 + 555) => x"f0", (20480 + 556) => x"0a", (20480 + 557) => x"00", (20480 + 558) => x"e0", (20480 + 559) => x"22", (20480 + 560) => x"d9", (20480 + 561) => x"f0", (20480 + 562) => x"0a", (20480 + 563) => x"00", (20480 + 564) => x"e0", (20480 + 565) => x"8e", (20480 + 566) => x"70", (20480 + 567) => x"a3", (20480 + 568) => x"1e", (20480 + 569) => x"6b", (20480 + 570) => x"1f", (20480 + 571) => x"cc", (20480 + 572) => x"1f", (20480 + 573) => x"8c", (20480 + 574) => x"c4", (20480 + 575) => x"dc", (20480 + 576) => x"b2", (20480 + 577) => x"3f", (20480 + 578) => x"01", (20480 + 579) => x"12", (20480 + 580) => x"49", (20480 + 581) => x"dc", (20480 + 582) => x"b2", (20480 + 583) => x"12", (20480 + 584) => x"39", (20480 + 585) => x"ca", (20480 + 586) => x"07", (20480 + 587) => x"7a", (20480 + 588) => x"01", (20480 + 589) => x"7b", (20480 + 590) => x"fe", (20480 + 591) => x"dc", (20480 + 592) => x"b2", (20480 + 593) => x"7a", (20480 + 594) => x"ff", (20480 + 595) => x"3a", (20480 + 596) => x"00", (20480 + 597) => x"12", (20480 + 598) => x"4d", (20480 + 599) => x"7e", (20480 + 600) => x"ff", (20480 + 601) => x"3e", (20480 + 602) => x"00", (20480 + 603) => x"12", (20480 + 604) => x"39", (20480 + 605) => x"6b", (20480 + 606) => x"00", (20480 + 607) => x"8c", (20480 + 608) => x"70", (20480 + 609) => x"6d", (20480 + 610) => x"00", (20480 + 611) => x"6e", (20480 + 612) => x"00", (20480 + 613) => x"a3", (20480 + 614) => x"1b", (20480 + 615) => x"dd", (20480 + 616) => x"e3", (20480 + 617) => x"3f", (20480 + 618) => x"00", (20480 + 619) => x"12", (20480 + 620) => x"c1", (20480 + 621) => x"3b", (20480 + 622) => x"00", (20480 + 623) => x"12", (20480 + 624) => x"81", (20480 + 625) => x"60", (20480 + 626) => x"05", (20480 + 627) => x"e0", (20480 + 628) => x"9e", (20480 + 629) => x"12", (20480 + 630) => x"87", (20480 + 631) => x"6b", (20480 + 632) => x"01", (20480 + 633) => x"88", (20480 + 634) => x"d0", (20480 + 635) => x"78", (20480 + 636) => x"02", (20480 + 637) => x"89", (20480 + 638) => x"e0", (20480 + 639) => x"79", (20480 + 640) => x"03", (20480 + 641) => x"a3", (20480 + 642) => x"1e", (20480 + 643) => x"d8", (20480 + 644) => x"91", (20480 + 645) => x"81", (20480 + 646) => x"f0", (20480 + 647) => x"60", (20480 + 648) => x"05", (20480 + 649) => x"f0", (20480 + 650) => x"15", (20480 + 651) => x"f0", (20480 + 652) => x"07", (20480 + 653) => x"30", (20480 + 654) => x"00", (20480 + 655) => x"12", (20480 + 656) => x"8b", (20480 + 657) => x"3b", (20480 + 658) => x"01", (20480 + 659) => x"12", (20480 + 660) => x"ab", (20480 + 661) => x"a3", (20480 + 662) => x"1e", (20480 + 663) => x"31", (20480 + 664) => x"01", (20480 + 665) => x"d8", (20480 + 666) => x"91", (20480 + 667) => x"79", (20480 + 668) => x"01", (20480 + 669) => x"39", (20480 + 670) => x"20", (20480 + 671) => x"12", (20480 + 672) => x"ab", (20480 + 673) => x"6b", (20480 + 674) => x"00", (20480 + 675) => x"31", (20480 + 676) => x"00", (20480 + 677) => x"7c", (20480 + 678) => x"ff", (20480 + 679) => x"4c", (20480 + 680) => x"00", (20480 + 681) => x"12", (20480 + 682) => x"bb", (20480 + 683) => x"a3", (20480 + 684) => x"1b", (20480 + 685) => x"dd", (20480 + 686) => x"e3", (20480 + 687) => x"7d", (20480 + 688) => x"02", (20480 + 689) => x"3d", (20480 + 690) => x"40", (20480 + 691) => x"12", (20480 + 692) => x"b9", (20480 + 693) => x"6d", (20480 + 694) => x"00", (20480 + 695) => x"7e", (20480 + 696) => x"01", (20480 + 697) => x"12", (20480 + 698) => x"65", (20480 + 699) => x"00", (20480 + 700) => x"e0", (20480 + 701) => x"77", (20480 + 702) => x"02", (20480 + 703) => x"12", (20480 + 704) => x"2d", (20480 + 705) => x"a3", (20480 + 706) => x"1b", (20480 + 707) => x"dd", (20480 + 708) => x"e3", (20480 + 709) => x"60", (20480 + 710) => x"14", (20480 + 711) => x"61", (20480 + 712) => x"02", (20480 + 713) => x"62", (20480 + 714) => x"0b", (20480 + 715) => x"a3", (20480 + 716) => x"20", (20480 + 717) => x"d0", (20480 + 718) => x"1b", (20480 + 719) => x"f2", (20480 + 720) => x"1e", (20480 + 721) => x"70", (20480 + 722) => x"08", (20480 + 723) => x"30", (20480 + 724) => x"2c", (20480 + 725) => x"12", (20480 + 726) => x"cd", (20480 + 727) => x"12", (20480 + 728) => x"d7", (20480 + 729) => x"60", (20480 + 730) => x"0a", (20480 + 731) => x"61", (20480 + 732) => x"0d", (20480 + 733) => x"62", (20480 + 734) => x"05", (20480 + 735) => x"a3", (20480 + 736) => x"07", (20480 + 737) => x"d0", (20480 + 738) => x"15", (20480 + 739) => x"f2", (20480 + 740) => x"1e", (20480 + 741) => x"70", (20480 + 742) => x"08", (20480 + 743) => x"30", (20480 + 744) => x"2a", (20480 + 745) => x"12", (20480 + 746) => x"e1", (20480 + 747) => x"80", (20480 + 748) => x"70", (20480 + 749) => x"70", (20480 + 750) => x"fe", (20480 + 751) => x"80", (20480 + 752) => x"06", (20480 + 753) => x"a3", (20480 + 754) => x"87", (20480 + 755) => x"f0", (20480 + 756) => x"33", (20480 + 757) => x"f2", (20480 + 758) => x"65", (20480 + 759) => x"60", (20480 + 760) => x"2d", (20480 + 761) => x"f1", (20480 + 762) => x"29", (20480 + 763) => x"61", (20480 + 764) => x"0d", (20480 + 765) => x"d0", (20480 + 766) => x"15", (20480 + 767) => x"70", (20480 + 768) => x"05", (20480 + 769) => x"f2", (20480 + 770) => x"29", (20480 + 771) => x"d0", (20480 + 772) => x"15", (20480 + 773) => x"00", (20480 + 774) => x"ee", (20480 + 775) => x"83", (20480 + 776) => x"82", (20480 + 777) => x"83", (20480 + 778) => x"82", (20480 + 779) => x"fb", (20480 + 780) => x"e8", (20480 + 781) => x"08", (20480 + 782) => x"88", (20480 + 783) => x"05", (20480 + 784) => x"e2", (20480 + 785) => x"be", (20480 + 786) => x"a0", (20480 + 787) => x"b8", (20480 + 788) => x"20", (20480 + 789) => x"3e", (20480 + 790) => x"80", (20480 + 791) => x"80", (20480 + 792) => x"80", (20480 + 793) => x"80", (20480 + 794) => x"f8", (20480 + 795) => x"80", (20480 + 796) => x"f8", (20480 + 797) => x"fc", (20480 + 798) => x"c0", (20480 + 799) => x"c0", (20480 + 800) => x"f9", (20480 + 801) => x"81", (20480 + 802) => x"db", (20480 + 803) => x"cb", (20480 + 804) => x"fb", (20480 + 805) => x"00", (20480 + 806) => x"fa", (20480 + 807) => x"8a", (20480 + 808) => x"9a", (20480 + 809) => x"99", (20480 + 810) => x"f8", (20480 + 811) => x"ef", (20480 + 812) => x"2a", (20480 + 813) => x"e8", (20480 + 814) => x"29", (20480 + 815) => x"29", (20480 + 816) => x"00", (20480 + 817) => x"6f", (20480 + 818) => x"68", (20480 + 819) => x"2e", (20480 + 820) => x"4c", (20480 + 821) => x"8f", (20480 + 822) => x"be", (20480 + 823) => x"a0", (20480 + 824) => x"b8", (20480 + 825) => x"b0", (20480 + 826) => x"be", (20480 + 827) => x"00", (20480 + 828) => x"be", (20480 + 829) => x"22", (20480 + 830) => x"3e", (20480 + 831) => x"34", (20480 + 832) => x"b2", (20480 + 833) => x"d8", (20480 + 834) => x"d8", (20480 + 835) => x"00", (20480 + 836) => x"c3", (20480 + 837) => x"c3", (20480 + 838) => x"00", (20480 + 839) => x"d8", (20480 + 840) => x"d8", (20480 + 841) => x"00", (20480 + 842) => x"c3", (20480 + 843) => x"c3", (20480 + 844) => x"00", (20480 + 845) => x"d8", (20480 + 846) => x"d8", (20480 + 847) => x"c0", (20480 + 848) => x"c0", (20480 + 849) => x"00", (20480 + 850) => x"c0", (20480 + 851) => x"c0", (20480 + 852) => x"00", (20480 + 853) => x"c0", (20480 + 854) => x"c0", (20480 + 855) => x"00", (20480 + 856) => x"c0", (20480 + 857) => x"c0", (20480 + 858) => x"00", (20480 + 859) => x"db", (20480 + 860) => x"db", (20480 + 861) => x"db", (20480 + 862) => x"db", (20480 + 863) => x"00", (20480 + 864) => x"18", (20480 + 865) => x"18", (20480 + 866) => x"00", (20480 + 867) => x"18", (20480 + 868) => x"18", (20480 + 869) => x"00", (20480 + 870) => x"18", (20480 + 871) => x"18", (20480 + 872) => x"00", (20480 + 873) => x"db", (20480 + 874) => x"db", (20480 + 875) => x"db", (20480 + 876) => x"db", (20480 + 877) => x"00", (20480 + 878) => x"18", (20480 + 879) => x"18", (20480 + 880) => x"00", (20480 + 881) => x"18", (20480 + 882) => x"18", (20480 + 883) => x"00", (20480 + 884) => x"18", (20480 + 885) => x"18", (20480 + 886) => x"00", (20480 + 887) => x"18", (20480 + 888) => x"18", (20480 + 889) => x"db", (20480 + 890) => x"db", (20480 + 891) => x"00", (20480 + 892) => x"03", (20480 + 893) => x"03", (20480 + 894) => x"00", (20480 + 895) => x"18", (20480 + 896) => x"18", (20480 + 897) => x"00", (20480 + 898) => x"c0", (20480 + 899) => x"c0", (20480 + 900) => x"00", (20480 + 901) => x"db", (20480 + 902) => x"db", (20480 + 903) => x"00",
-- Brix by Andre Gustafsson
(24576 + 128) => x"00", (24576 + 129) => x"00",
(24576 + 130) => x"C0", (24576 + 131) => x"E0",
(24576 + 132) => x"00", (24576 + 133) => x"00",
(24576 + 134) => x"00", (24576 + 135) => x"00",
(24576 + 136) => x"00", (24576 + 137) => x"30", -- delay
(24576 + 138) => x"00",
(24576 + 512) => x"6e", (24576 + 513) => x"05", (24576 + 514) => x"65", (24576 + 515) => x"00", (24576 + 516) => x"6b", (24576 + 517) => x"06", (24576 + 518) => x"6a", (24576 + 519) => x"00", (24576 + 520) => x"a3", (24576 + 521) => x"0c", (24576 + 522) => x"da", (24576 + 523) => x"b1", (24576 + 524) => x"7a", (24576 + 525) => x"04", (24576 + 526) => x"3a", (24576 + 527) => x"40", (24576 + 528) => x"12", (24576 + 529) => x"08", (24576 + 530) => x"7b", (24576 + 531) => x"02", (24576 + 532) => x"3b", (24576 + 533) => x"12", (24576 + 534) => x"12", (24576 + 535) => x"06", (24576 + 536) => x"6c", (24576 + 537) => x"20", (24576 + 538) => x"6d", (24576 + 539) => x"1f", (24576 + 540) => x"a3", (24576 + 541) => x"10", (24576 + 542) => x"dc", (24576 + 543) => x"d1", (24576 + 544) => x"22", (24576 + 545) => x"f6", (24576 + 546) => x"60", (24576 + 547) => x"00", (24576 + 548) => x"61", (24576 + 549) => x"00", (24576 + 550) => x"a3", (24576 + 551) => x"12", (24576 + 552) => x"d0", (24576 + 553) => x"11", (24576 + 554) => x"70", (24576 + 555) => x"08", (24576 + 556) => x"a3", (24576 + 557) => x"0e", (24576 + 558) => x"d0", (24576 + 559) => x"11", (24576 + 560) => x"60", (24576 + 561) => x"40", (24576 + 562) => x"f0", (24576 + 563) => x"15", (24576 + 564) => x"f0", (24576 + 565) => x"07", (24576 + 566) => x"30", (24576 + 567) => x"00", (24576 + 568) => x"12", (24576 + 569) => x"34", (24576 + 570) => x"c6", (24576 + 571) => x"0f", (24576 + 572) => x"67", (24576 + 573) => x"1e", (24576 + 574) => x"68", (24576 + 575) => x"01", (24576 + 576) => x"69", (24576 + 577) => x"ff", (24576 + 578) => x"a3", (24576 + 579) => x"0e", (24576 + 580) => x"d6", (24576 + 581) => x"71", (24576 + 582) => x"a3", (24576 + 583) => x"10", (24576 + 584) => x"dc", (24576 + 585) => x"d1", (24576 + 586) => x"60", (24576 + 587) => x"04", (24576 + 588) => x"e0", (24576 + 589) => x"a1", (24576 + 590) => x"7c", (24576 + 591) => x"fe", (24576 + 592) => x"60", (24576 + 593) => x"06", (24576 + 594) => x"e0", (24576 + 595) => x"a1", (24576 + 596) => x"7c", (24576 + 597) => x"02", (24576 + 598) => x"60", (24576 + 599) => x"3f", (24576 + 600) => x"8c", (24576 + 601) => x"02", (24576 + 602) => x"dc", (24576 + 603) => x"d1", (24576 + 604) => x"a3", (24576 + 605) => x"0e", (24576 + 606) => x"d6", (24576 + 607) => x"71", (24576 + 608) => x"86", (24576 + 609) => x"84", (24576 + 610) => x"87", (24576 + 611) => x"94", (24576 + 612) => x"60", (24576 + 613) => x"3f", (24576 + 614) => x"86", (24576 + 615) => x"02", (24576 + 616) => x"61", (24576 + 617) => x"1f", (24576 + 618) => x"87", (24576 + 619) => x"12", (24576 + 620) => x"47", (24576 + 621) => x"1f", (24576 + 622) => x"12", (24576 + 623) => x"ac", (24576 + 624) => x"46", (24576 + 625) => x"00", (24576 + 626) => x"68", (24576 + 627) => x"01", (24576 + 628) => x"46", (24576 + 629) => x"3f", (24576 + 630) => x"68", (24576 + 631) => x"ff", (24576 + 632) => x"47", (24576 + 633) => x"00", (24576 + 634) => x"69", (24576 + 635) => x"01", (24576 + 636) => x"d6", (24576 + 637) => x"71", (24576 + 638) => x"3f", (24576 + 639) => x"01", (24576 + 640) => x"12", (24576 + 641) => x"aa", (24576 + 642) => x"47", (24576 + 643) => x"1f", (24576 + 644) => x"12", (24576 + 645) => x"aa", (24576 + 646) => x"60", (24576 + 647) => x"05", (24576 + 648) => x"80", (24576 + 649) => x"75", (24576 + 650) => x"3f", (24576 + 651) => x"00", (24576 + 652) => x"12", (24576 + 653) => x"aa", (24576 + 654) => x"60", (24576 + 655) => x"01", (24576 + 656) => x"f0", (24576 + 657) => x"18", (24576 + 658) => x"80", (24576 + 659) => x"60", (24576 + 660) => x"61", (24576 + 661) => x"fc", (24576 + 662) => x"80", (24576 + 663) => x"12", (24576 + 664) => x"a3", (24576 + 665) => x"0c", (24576 + 666) => x"d0", (24576 + 667) => x"71", (24576 + 668) => x"60", (24576 + 669) => x"fe", (24576 + 670) => x"89", (24576 + 671) => x"03", (24576 + 672) => x"22", (24576 + 673) => x"f6", (24576 + 674) => x"75", (24576 + 675) => x"01", (24576 + 676) => x"22", (24576 + 677) => x"f6", (24576 + 678) => x"45", (24576 + 679) => x"60", (24576 + 680) => x"12", (24576 + 681) => x"de", (24576 + 682) => x"12", (24576 + 683) => x"46", (24576 + 684) => x"69", (24576 + 685) => x"ff", (24576 + 686) => x"80", (24576 + 687) => x"60", (24576 + 688) => x"80", (24576 + 689) => x"c5", (24576 + 690) => x"3f", (24576 + 691) => x"01", (24576 + 692) => x"12", (24576 + 693) => x"ca", (24576 + 694) => x"61", (24576 + 695) => x"02", (24576 + 696) => x"80", (24576 + 697) => x"15", (24576 + 698) => x"3f", (24576 + 699) => x"01", (24576 + 700) => x"12", (24576 + 701) => x"e0", (24576 + 702) => x"80", (24576 + 703) => x"15", (24576 + 704) => x"3f", (24576 + 705) => x"01", (24576 + 706) => x"12", (24576 + 707) => x"ee", (24576 + 708) => x"80", (24576 + 709) => x"15", (24576 + 710) => x"3f", (24576 + 711) => x"01", (24576 + 712) => x"12", (24576 + 713) => x"e8", (24576 + 714) => x"60", (24576 + 715) => x"20", (24576 + 716) => x"f0", (24576 + 717) => x"18", (24576 + 718) => x"a3", (24576 + 719) => x"0e", (24576 + 720) => x"7e", (24576 + 721) => x"ff", (24576 + 722) => x"80", (24576 + 723) => x"e0", (24576 + 724) => x"80", (24576 + 725) => x"04", (24576 + 726) => x"61", (24576 + 727) => x"00", (24576 + 728) => x"d0", (24576 + 729) => x"11", (24576 + 730) => x"3e", (24576 + 731) => x"00", (24576 + 732) => x"12", (24576 + 733) => x"30", (24576 + 734) => x"12", (24576 + 735) => x"de", (24576 + 736) => x"78", (24576 + 737) => x"ff", (24576 + 738) => x"48", (24576 + 739) => x"fe", (24576 + 740) => x"68", (24576 + 741) => x"ff", (24576 + 742) => x"12", (24576 + 743) => x"ee", (24576 + 744) => x"78", (24576 + 745) => x"01", (24576 + 746) => x"48", (24576 + 747) => x"02", (24576 + 748) => x"68", (24576 + 749) => x"01", (24576 + 750) => x"60", (24576 + 751) => x"04", (24576 + 752) => x"f0", (24576 + 753) => x"18", (24576 + 754) => x"69", (24576 + 755) => x"ff", (24576 + 756) => x"12", (24576 + 757) => x"70", (24576 + 758) => x"a3", (24576 + 759) => x"14", (24576 + 760) => x"f5", (24576 + 761) => x"33", (24576 + 762) => x"f2", (24576 + 763) => x"65", (24576 + 764) => x"f1", (24576 + 765) => x"29", (24576 + 766) => x"63", (24576 + 767) => x"37", (24576 + 768) => x"64", (24576 + 769) => x"00", (24576 + 770) => x"d3", (24576 + 771) => x"45", (24576 + 772) => x"73", (24576 + 773) => x"05", (24576 + 774) => x"f2", (24576 + 775) => x"29", (24576 + 776) => x"d3", (24576 + 777) => x"45", (24576 + 778) => x"00", (24576 + 779) => x"ee", (24576 + 780) => x"e0", (24576 + 781) => x"00", (24576 + 782) => x"80", (24576 + 783) => x"00", (24576 + 784) => x"fc", (24576 + 785) => x"00", (24576 + 786) => x"aa", (24576 + 787) => x"00", (24576 + 788) => x"00", (24576 + 789) => x"00", (24576 + 790) => x"00", (24576 + 791) => x"00",
-- Cave by 199x
(28672 + 128) => x"00", (28672 + 129) => x"B0",
(28672 + 130) => x"C0", (28672 + 131) => x"E0",
(28672 + 132) => x"F0", (28672 + 133) => x"00",
(28672 + 134) => x"BE", (28672 + 135) => x"0D",
(28672 + 136) => x"00", (28672 + 137) => x"30", -- delay
(28672 + 138) => x"00",
(28672 + 512) => x"00", (28672 + 513) => x"e0", (28672 + 514) => x"64", (28672 + 515) => x"00", (28672 + 516) => x"65", (28672 + 517) => x"00", (28672 + 518) => x"a2", (28672 + 519) => x"0a", (28672 + 520) => x"12", (28672 + 521) => x"0c", (28672 + 522) => x"cc", (28672 + 523) => x"33", (28672 + 524) => x"66", (28672 + 525) => x"1e", (28672 + 526) => x"d4", (28672 + 527) => x"52", (28672 + 528) => x"d4", (28672 + 529) => x"62", (28672 + 530) => x"74", (28672 + 531) => x"08", (28672 + 532) => x"44", (28672 + 533) => x"40", (28672 + 534) => x"12", (28672 + 535) => x"1a", (28672 + 536) => x"12", (28672 + 537) => x"0e", (28672 + 538) => x"a2", (28672 + 539) => x"1e", (28672 + 540) => x"12", (28672 + 541) => x"2c", (28672 + 542) => x"ff", (28672 + 543) => x"ff", (28672 + 544) => x"c0", (28672 + 545) => x"c0", (28672 + 546) => x"c0", (28672 + 547) => x"c0", (28672 + 548) => x"c0", (28672 + 549) => x"c0", (28672 + 550) => x"c0", (28672 + 551) => x"c0", (28672 + 552) => x"c0", (28672 + 553) => x"c0", (28672 + 554) => x"ff", (28672 + 555) => x"ff", (28672 + 556) => x"64", (28672 + 557) => x"0d", (28672 + 558) => x"65", (28672 + 559) => x"09", (28672 + 560) => x"d4", (28672 + 561) => x"5e", (28672 + 562) => x"74", (28672 + 563) => x"0a", (28672 + 564) => x"a2", (28672 + 565) => x"3a", (28672 + 566) => x"d4", (28672 + 567) => x"5e", (28672 + 568) => x"12", (28672 + 569) => x"48", (28672 + 570) => x"ff", (28672 + 571) => x"ff", (28672 + 572) => x"c3", (28672 + 573) => x"c3", (28672 + 574) => x"c3", (28672 + 575) => x"c3", (28672 + 576) => x"c3", (28672 + 577) => x"ff", (28672 + 578) => x"ff", (28672 + 579) => x"c3", (28672 + 580) => x"c3", (28672 + 581) => x"c3", (28672 + 582) => x"c3", (28672 + 583) => x"c3", (28672 + 584) => x"74", (28672 + 585) => x"0a", (28672 + 586) => x"a2", (28672 + 587) => x"50", (28672 + 588) => x"d4", (28672 + 589) => x"5e", (28672 + 590) => x"12", (28672 + 591) => x"5e", (28672 + 592) => x"c3", (28672 + 593) => x"c3", (28672 + 594) => x"c3", (28672 + 595) => x"c3", (28672 + 596) => x"c3", (28672 + 597) => x"66", (28672 + 598) => x"66", (28672 + 599) => x"66", (28672 + 600) => x"66", (28672 + 601) => x"66", (28672 + 602) => x"3c", (28672 + 603) => x"3c", (28672 + 604) => x"18", (28672 + 605) => x"18", (28672 + 606) => x"74", (28672 + 607) => x"0a", (28672 + 608) => x"a2", (28672 + 609) => x"66", (28672 + 610) => x"d4", (28672 + 611) => x"5e", (28672 + 612) => x"12", (28672 + 613) => x"74", (28672 + 614) => x"ff", (28672 + 615) => x"ff", (28672 + 616) => x"c0", (28672 + 617) => x"c0", (28672 + 618) => x"c0", (28672 + 619) => x"c0", (28672 + 620) => x"ff", (28672 + 621) => x"ff", (28672 + 622) => x"c0", (28672 + 623) => x"c0", (28672 + 624) => x"c0", (28672 + 625) => x"c0", (28672 + 626) => x"ff", (28672 + 627) => x"ff", (28672 + 628) => x"6a", (28672 + 629) => x"01", (28672 + 630) => x"6b", (28672 + 631) => x"04", (28672 + 632) => x"6c", (28672 + 633) => x"0e", (28672 + 634) => x"6d", (28672 + 635) => x"00", (28672 + 636) => x"a2", (28672 + 637) => x"81", (28672 + 638) => x"12", (28672 + 639) => x"a6", (28672 + 640) => x"80", (28672 + 641) => x"ff", (28672 + 642) => x"ff", (28672 + 643) => x"ff", (28672 + 644) => x"ff", (28672 + 645) => x"ff", (28672 + 646) => x"ff", (28672 + 647) => x"ff", (28672 + 648) => x"ff", (28672 + 649) => x"ff", (28672 + 650) => x"00", (28672 + 651) => x"e0", (28672 + 652) => x"64", (28672 + 653) => x"00", (28672 + 654) => x"65", (28672 + 655) => x"00", (28672 + 656) => x"d4", (28672 + 657) => x"58", (28672 + 658) => x"74", (28672 + 659) => x"08", (28672 + 660) => x"44", (28672 + 661) => x"40", (28672 + 662) => x"22", (28672 + 663) => x"9e", (28672 + 664) => x"45", (28672 + 665) => x"20", (28672 + 666) => x"12", (28672 + 667) => x"a4", (28672 + 668) => x"12", (28672 + 669) => x"90", (28672 + 670) => x"64", (28672 + 671) => x"00", (28672 + 672) => x"75", (28672 + 673) => x"08", (28672 + 674) => x"00", (28672 + 675) => x"ee", (28672 + 676) => x"12", (28672 + 677) => x"ae", (28672 + 678) => x"60", (28672 + 679) => x"0f", (28672 + 680) => x"e0", (28672 + 681) => x"9e", (28672 + 682) => x"12", (28672 + 683) => x"a8", (28672 + 684) => x"12", (28672 + 685) => x"8a", (28672 + 686) => x"4a", (28672 + 687) => x"01", (28672 + 688) => x"22", (28672 + 689) => x"d0", (28672 + 690) => x"4a", (28672 + 691) => x"02", (28672 + 692) => x"23", (28672 + 693) => x"8a", (28672 + 694) => x"4a", (28672 + 695) => x"03", (28672 + 696) => x"23", (28672 + 697) => x"b8", (28672 + 698) => x"4a", (28672 + 699) => x"04", (28672 + 700) => x"23", (28672 + 701) => x"e0", (28672 + 702) => x"4a", (28672 + 703) => x"05", (28672 + 704) => x"24", (28672 + 705) => x"18", (28672 + 706) => x"4a", (28672 + 707) => x"06", (28672 + 708) => x"24", (28672 + 709) => x"78", (28672 + 710) => x"4a", (28672 + 711) => x"07", (28672 + 712) => x"24", (28672 + 713) => x"e6", (28672 + 714) => x"4a", (28672 + 715) => x"08", (28672 + 716) => x"25", (28672 + 717) => x"10", (28672 + 718) => x"13", (28672 + 719) => x"18", (28672 + 720) => x"a2", (28672 + 721) => x"81", (28672 + 722) => x"64", (28672 + 723) => x"02", (28672 + 724) => x"65", (28672 + 725) => x"02", (28672 + 726) => x"d4", (28672 + 727) => x"58", (28672 + 728) => x"65", (28672 + 729) => x"0a", (28672 + 730) => x"d4", (28672 + 731) => x"58", (28672 + 732) => x"65", (28672 + 733) => x"12", (28672 + 734) => x"d4", (28672 + 735) => x"58", (28672 + 736) => x"64", (28672 + 737) => x"0a", (28672 + 738) => x"65", (28672 + 739) => x"05", (28672 + 740) => x"d4", (28672 + 741) => x"53", (28672 + 742) => x"64", (28672 + 743) => x"12", (28672 + 744) => x"d4", (28672 + 745) => x"53", (28672 + 746) => x"64", (28672 + 747) => x"1a", (28672 + 748) => x"d4", (28672 + 749) => x"53", (28672 + 750) => x"64", (28672 + 751) => x"22", (28672 + 752) => x"d4", (28672 + 753) => x"53", (28672 + 754) => x"64", (28672 + 755) => x"2a", (28672 + 756) => x"d4", (28672 + 757) => x"53", (28672 + 758) => x"64", (28672 + 759) => x"32", (28672 + 760) => x"d4", (28672 + 761) => x"53", (28672 + 762) => x"a2", (28672 + 763) => x"fe", (28672 + 764) => x"13", (28672 + 765) => x"0a", (28672 + 766) => x"fc", (28672 + 767) => x"fc", (28672 + 768) => x"fc", (28672 + 769) => x"fc", (28672 + 770) => x"fc", (28672 + 771) => x"fc", (28672 + 772) => x"fc", (28672 + 773) => x"fc", (28672 + 774) => x"fc", (28672 + 775) => x"fc", (28672 + 776) => x"fc", (28672 + 777) => x"fc", (28672 + 778) => x"75", (28672 + 779) => x"03", (28672 + 780) => x"74", (28672 + 781) => x"02", (28672 + 782) => x"d4", (28672 + 783) => x"5c", (28672 + 784) => x"74", (28672 + 785) => x"06", (28672 + 786) => x"75", (28672 + 787) => x"09", (28672 + 788) => x"d4", (28672 + 789) => x"53", (28672 + 790) => x"00", (28672 + 791) => x"ee", (28672 + 792) => x"a2", (28672 + 793) => x"80", (28672 + 794) => x"db", (28672 + 795) => x"c1", (28672 + 796) => x"4f", (28672 + 797) => x"01", (28672 + 798) => x"13", (28672 + 799) => x"72", (28672 + 800) => x"60", (28672 + 801) => x"02", (28672 + 802) => x"e0", (28672 + 803) => x"a1", (28672 + 804) => x"6d", (28672 + 805) => x"02", (28672 + 806) => x"60", (28672 + 807) => x"04", (28672 + 808) => x"e0", (28672 + 809) => x"a1", (28672 + 810) => x"6d", (28672 + 811) => x"04", (28672 + 812) => x"60", (28672 + 813) => x"06", (28672 + 814) => x"e0", (28672 + 815) => x"a1", (28672 + 816) => x"6d", (28672 + 817) => x"06", (28672 + 818) => x"60", (28672 + 819) => x"08", (28672 + 820) => x"e0", (28672 + 821) => x"a1", (28672 + 822) => x"6d", (28672 + 823) => x"08", (28672 + 824) => x"db", (28672 + 825) => x"c1", (28672 + 826) => x"4d", (28672 + 827) => x"02", (28672 + 828) => x"7c", (28672 + 829) => x"ff", (28672 + 830) => x"4d", (28672 + 831) => x"04", (28672 + 832) => x"7b", (28672 + 833) => x"ff", (28672 + 834) => x"4d", (28672 + 835) => x"06", (28672 + 836) => x"7b", (28672 + 837) => x"01", (28672 + 838) => x"4d", (28672 + 839) => x"08", (28672 + 840) => x"7c", (28672 + 841) => x"01", (28672 + 842) => x"4b", (28672 + 843) => x"40", (28672 + 844) => x"13", (28672 + 845) => x"5e", (28672 + 846) => x"4b", (28672 + 847) => x"ff", (28672 + 848) => x"13", (28672 + 849) => x"64", (28672 + 850) => x"60", (28672 + 851) => x"02", (28672 + 852) => x"f0", (28672 + 853) => x"15", (28672 + 854) => x"f0", (28672 + 855) => x"07", (28672 + 856) => x"30", (28672 + 857) => x"00", (28672 + 858) => x"13", (28672 + 859) => x"56", (28672 + 860) => x"13", (28672 + 861) => x"18", (28672 + 862) => x"7a", (28672 + 863) => x"01", (28672 + 864) => x"4a", (28672 + 865) => x"09", (28672 + 866) => x"15", (28672 + 867) => x"3a", (28672 + 868) => x"6b", (28672 + 869) => x"01", (28672 + 870) => x"a2", (28672 + 871) => x"81", (28672 + 872) => x"12", (28672 + 873) => x"8a", (28672 + 874) => x"7a", (28672 + 875) => x"ff", (28672 + 876) => x"6b", (28672 + 877) => x"3e", (28672 + 878) => x"a2", (28672 + 879) => x"81", (28672 + 880) => x"12", (28672 + 881) => x"8a", (28672 + 882) => x"60", (28672 + 883) => x"03", (28672 + 884) => x"f0", (28672 + 885) => x"18", (28672 + 886) => x"60", (28672 + 887) => x"0f", (28672 + 888) => x"e0", (28672 + 889) => x"9e", (28672 + 890) => x"13", (28672 + 891) => x"78", (28672 + 892) => x"6a", (28672 + 893) => x"01", (28672 + 894) => x"6b", (28672 + 895) => x"04", (28672 + 896) => x"6c", (28672 + 897) => x"0e", (28672 + 898) => x"6d", (28672 + 899) => x"00", (28672 + 900) => x"a2", (28672 + 901) => x"81", (28672 + 902) => x"00", (28672 + 903) => x"e0", (28672 + 904) => x"12", (28672 + 905) => x"8a", (28672 + 906) => x"64", (28672 + 907) => x"00", (28672 + 908) => x"65", (28672 + 909) => x"11", (28672 + 910) => x"a2", (28672 + 911) => x"81", (28672 + 912) => x"d4", (28672 + 913) => x"53", (28672 + 914) => x"74", (28672 + 915) => x"08", (28672 + 916) => x"d4", (28672 + 917) => x"53", (28672 + 918) => x"74", (28672 + 919) => x"08", (28672 + 920) => x"75", (28672 + 921) => x"ff", (28672 + 922) => x"d4", (28672 + 923) => x"53", (28672 + 924) => x"74", (28672 + 925) => x"08", (28672 + 926) => x"75", (28672 + 927) => x"ff", (28672 + 928) => x"d4", (28672 + 929) => x"53", (28672 + 930) => x"74", (28672 + 931) => x"08", (28672 + 932) => x"d4", (28672 + 933) => x"53", (28672 + 934) => x"74", (28672 + 935) => x"08", (28672 + 936) => x"d4", (28672 + 937) => x"53", (28672 + 938) => x"74", (28672 + 939) => x"08", (28672 + 940) => x"75", (28672 + 941) => x"01", (28672 + 942) => x"d4", (28672 + 943) => x"53", (28672 + 944) => x"74", (28672 + 945) => x"08", (28672 + 946) => x"75", (28672 + 947) => x"01", (28672 + 948) => x"d4", (28672 + 949) => x"53", (28672 + 950) => x"00", (28672 + 951) => x"ee", (28672 + 952) => x"64", (28672 + 953) => x"00", (28672 + 954) => x"65", (28672 + 955) => x"11", (28672 + 956) => x"a2", (28672 + 957) => x"81", (28672 + 958) => x"d4", (28672 + 959) => x"53", (28672 + 960) => x"74", (28672 + 961) => x"08", (28672 + 962) => x"d4", (28672 + 963) => x"53", (28672 + 964) => x"74", (28672 + 965) => x"08", (28672 + 966) => x"75", (28672 + 967) => x"02", (28672 + 968) => x"d4", (28672 + 969) => x"52", (28672 + 970) => x"74", (28672 + 971) => x"08", (28672 + 972) => x"d4", (28672 + 973) => x"51", (28672 + 974) => x"74", (28672 + 975) => x"08", (28672 + 976) => x"d4", (28672 + 977) => x"51", (28672 + 978) => x"74", (28672 + 979) => x"08", (28672 + 980) => x"d4", (28672 + 981) => x"51", (28672 + 982) => x"74", (28672 + 983) => x"08", (28672 + 984) => x"d4", (28672 + 985) => x"51", (28672 + 986) => x"74", (28672 + 987) => x"08", (28672 + 988) => x"d4", (28672 + 989) => x"51", (28672 + 990) => x"00", (28672 + 991) => x"ee", (28672 + 992) => x"64", (28672 + 993) => x"00", (28672 + 994) => x"65", (28672 + 995) => x"13", (28672 + 996) => x"a2", (28672 + 997) => x"81", (28672 + 998) => x"d4", (28672 + 999) => x"51", (28672 + 1000) => x"a2", (28672 + 1001) => x"80", (28672 + 1002) => x"74", (28672 + 1003) => x"08", (28672 + 1004) => x"d4", (28672 + 1005) => x"51", (28672 + 1006) => x"75", (28672 + 1007) => x"01", (28672 + 1008) => x"d4", (28672 + 1009) => x"51", (28672 + 1010) => x"75", (28672 + 1011) => x"01", (28672 + 1012) => x"a2", (28672 + 1013) => x"81", (28672 + 1014) => x"d4", (28672 + 1015) => x"51", (28672 + 1016) => x"74", (28672 + 1017) => x"08", (28672 + 1018) => x"d4", (28672 + 1019) => x"51", (28672 + 1020) => x"74", (28672 + 1021) => x"08", (28672 + 1022) => x"d4", (28672 + 1023) => x"52", (28672 + 1024) => x"74", (28672 + 1025) => x"08", (28672 + 1026) => x"75", (28672 + 1027) => x"ff", (28672 + 1028) => x"d4", (28672 + 1029) => x"53", (28672 + 1030) => x"74", (28672 + 1031) => x"08", (28672 + 1032) => x"d4", (28672 + 1033) => x"54", (28672 + 1034) => x"74", (28672 + 1035) => x"08", (28672 + 1036) => x"75", (28672 + 1037) => x"ff", (28672 + 1038) => x"d4", (28672 + 1039) => x"56", (28672 + 1040) => x"74", (28672 + 1041) => x"08", (28672 + 1042) => x"75", (28672 + 1043) => x"ff", (28672 + 1044) => x"d4", (28672 + 1045) => x"58", (28672 + 1046) => x"00", (28672 + 1047) => x"ee", (28672 + 1048) => x"64", (28672 + 1049) => x"00", (28672 + 1050) => x"65", (28672 + 1051) => x"12", (28672 + 1052) => x"a2", (28672 + 1053) => x"81", (28672 + 1054) => x"d4", (28672 + 1055) => x"58", (28672 + 1056) => x"74", (28672 + 1057) => x"08", (28672 + 1058) => x"d4", (28672 + 1059) => x"58", (28672 + 1060) => x"74", (28672 + 1061) => x"08", (28672 + 1062) => x"d4", (28672 + 1063) => x"58", (28672 + 1064) => x"74", (28672 + 1065) => x"08", (28672 + 1066) => x"d4", (28672 + 1067) => x"58", (28672 + 1068) => x"74", (28672 + 1069) => x"08", (28672 + 1070) => x"d4", (28672 + 1071) => x"58", (28672 + 1072) => x"74", (28672 + 1073) => x"08", (28672 + 1074) => x"d4", (28672 + 1075) => x"58", (28672 + 1076) => x"74", (28672 + 1077) => x"08", (28672 + 1078) => x"d4", (28672 + 1079) => x"58", (28672 + 1080) => x"a2", (28672 + 1081) => x"80", (28672 + 1082) => x"75", (28672 + 1083) => x"ff", (28672 + 1084) => x"74", (28672 + 1085) => x"20", (28672 + 1086) => x"d4", (28672 + 1087) => x"51", (28672 + 1088) => x"75", (28672 + 1089) => x"ff", (28672 + 1090) => x"d4", (28672 + 1091) => x"51", (28672 + 1092) => x"75", (28672 + 1093) => x"ff", (28672 + 1094) => x"d4", (28672 + 1095) => x"51", (28672 + 1096) => x"75", (28672 + 1097) => x"ff", (28672 + 1098) => x"d4", (28672 + 1099) => x"51", (28672 + 1100) => x"75", (28672 + 1101) => x"ff", (28672 + 1102) => x"d4", (28672 + 1103) => x"51", (28672 + 1104) => x"75", (28672 + 1105) => x"ff", (28672 + 1106) => x"d4", (28672 + 1107) => x"51", (28672 + 1108) => x"75", (28672 + 1109) => x"ff", (28672 + 1110) => x"d4", (28672 + 1111) => x"51", (28672 + 1112) => x"75", (28672 + 1113) => x"ff", (28672 + 1114) => x"d4", (28672 + 1115) => x"51", (28672 + 1116) => x"75", (28672 + 1117) => x"ff", (28672 + 1118) => x"a2", (28672 + 1119) => x"81", (28672 + 1120) => x"d4", (28672 + 1121) => x"51", (28672 + 1122) => x"74", (28672 + 1123) => x"08", (28672 + 1124) => x"d4", (28672 + 1125) => x"51", (28672 + 1126) => x"74", (28672 + 1127) => x"08", (28672 + 1128) => x"d4", (28672 + 1129) => x"51", (28672 + 1130) => x"74", (28672 + 1131) => x"08", (28672 + 1132) => x"d4", (28672 + 1133) => x"51", (28672 + 1134) => x"74", (28672 + 1135) => x"08", (28672 + 1136) => x"d4", (28672 + 1137) => x"51", (28672 + 1138) => x"74", (28672 + 1139) => x"08", (28672 + 1140) => x"d4", (28672 + 1141) => x"51", (28672 + 1142) => x"00", (28672 + 1143) => x"ee", (28672 + 1144) => x"64", (28672 + 1145) => x"00", (28672 + 1146) => x"65", (28672 + 1147) => x"09", (28672 + 1148) => x"a2", (28672 + 1149) => x"81", (28672 + 1150) => x"d4", (28672 + 1151) => x"51", (28672 + 1152) => x"74", (28672 + 1153) => x"08", (28672 + 1154) => x"d4", (28672 + 1155) => x"51", (28672 + 1156) => x"74", (28672 + 1157) => x"08", (28672 + 1158) => x"d4", (28672 + 1159) => x"51", (28672 + 1160) => x"74", (28672 + 1161) => x"08", (28672 + 1162) => x"d4", (28672 + 1163) => x"51", (28672 + 1164) => x"74", (28672 + 1165) => x"08", (28672 + 1166) => x"d4", (28672 + 1167) => x"51", (28672 + 1168) => x"74", (28672 + 1169) => x"08", (28672 + 1170) => x"d4", (28672 + 1171) => x"51", (28672 + 1172) => x"a2", (28672 + 1173) => x"80", (28672 + 1174) => x"75", (28672 + 1175) => x"01", (28672 + 1176) => x"d4", (28672 + 1177) => x"51", (28672 + 1178) => x"75", (28672 + 1179) => x"01", (28672 + 1180) => x"d4", (28672 + 1181) => x"51", (28672 + 1182) => x"75", (28672 + 1183) => x"01", (28672 + 1184) => x"d4", (28672 + 1185) => x"51", (28672 + 1186) => x"75", (28672 + 1187) => x"01", (28672 + 1188) => x"d4", (28672 + 1189) => x"51", (28672 + 1190) => x"75", (28672 + 1191) => x"01", (28672 + 1192) => x"d4", (28672 + 1193) => x"51", (28672 + 1194) => x"75", (28672 + 1195) => x"01", (28672 + 1196) => x"d4", (28672 + 1197) => x"51", (28672 + 1198) => x"75", (28672 + 1199) => x"01", (28672 + 1200) => x"d4", (28672 + 1201) => x"51", (28672 + 1202) => x"75", (28672 + 1203) => x"01", (28672 + 1204) => x"d4", (28672 + 1205) => x"51", (28672 + 1206) => x"75", (28672 + 1207) => x"01", (28672 + 1208) => x"a2", (28672 + 1209) => x"81", (28672 + 1210) => x"d4", (28672 + 1211) => x"51", (28672 + 1212) => x"74", (28672 + 1213) => x"08", (28672 + 1214) => x"d4", (28672 + 1215) => x"51", (28672 + 1216) => x"74", (28672 + 1217) => x"08", (28672 + 1218) => x"d4", (28672 + 1219) => x"51", (28672 + 1220) => x"00", (28672 + 1221) => x"ee", (28672 + 1222) => x"64", (28672 + 1223) => x"00", (28672 + 1224) => x"65", (28672 + 1225) => x"1a", (28672 + 1226) => x"a2", (28672 + 1227) => x"81", (28672 + 1228) => x"d4", (28672 + 1229) => x"51", (28672 + 1230) => x"74", (28672 + 1231) => x"08", (28672 + 1232) => x"d4", (28672 + 1233) => x"51", (28672 + 1234) => x"74", (28672 + 1235) => x"08", (28672 + 1236) => x"d4", (28672 + 1237) => x"51", (28672 + 1238) => x"74", (28672 + 1239) => x"08", (28672 + 1240) => x"d4", (28672 + 1241) => x"51", (28672 + 1242) => x"74", (28672 + 1243) => x"08", (28672 + 1244) => x"d4", (28672 + 1245) => x"51", (28672 + 1246) => x"75", (28672 + 1247) => x"ff", (28672 + 1248) => x"d4", (28672 + 1249) => x"51", (28672 + 1250) => x"74", (28672 + 1251) => x"08", (28672 + 1252) => x"d4", (28672 + 1253) => x"51", (28672 + 1254) => x"74", (28672 + 1255) => x"08", (28672 + 1256) => x"d4", (28672 + 1257) => x"51", (28672 + 1258) => x"74", (28672 + 1259) => x"08", (28672 + 1260) => x"d4", (28672 + 1261) => x"51", (28672 + 1262) => x"00", (28672 + 1263) => x"ee", (28672 + 1264) => x"64", (28672 + 1265) => x"00", (28672 + 1266) => x"65", (28672 + 1267) => x"19", (28672 + 1268) => x"a2", (28672 + 1269) => x"81", (28672 + 1270) => x"d4", (28672 + 1271) => x"51", (28672 + 1272) => x"74", (28672 + 1273) => x"08", (28672 + 1274) => x"d4", (28672 + 1275) => x"51", (28672 + 1276) => x"74", (28672 + 1277) => x"08", (28672 + 1278) => x"d4", (28672 + 1279) => x"51", (28672 + 1280) => x"74", (28672 + 1281) => x"08", (28672 + 1282) => x"d4", (28672 + 1283) => x"51", (28672 + 1284) => x"74", (28672 + 1285) => x"08", (28672 + 1286) => x"d4", (28672 + 1287) => x"51", (28672 + 1288) => x"75", (28672 + 1289) => x"ff", (28672 + 1290) => x"d4", (28672 + 1291) => x"51", (28672 + 1292) => x"74", (28672 + 1293) => x"08", (28672 + 1294) => x"d4", (28672 + 1295) => x"51", (28672 + 1296) => x"74", (28672 + 1297) => x"08", (28672 + 1298) => x"d4", (28672 + 1299) => x"51", (28672 + 1300) => x"74", (28672 + 1301) => x"08", (28672 + 1302) => x"d4", (28672 + 1303) => x"51", (28672 + 1304) => x"00", (28672 + 1305) => x"ee", (28672 + 1306) => x"00", (28672 + 1307) => x"e0", (28672 + 1308) => x"67", (28672 + 1309) => x"03", (28672 + 1310) => x"68", (28672 + 1311) => x"03", (28672 + 1312) => x"a5", (28672 + 1313) => x"44", (28672 + 1314) => x"15", (28672 + 1315) => x"5c", (28672 + 1316) => x"ae", (28672 + 1317) => x"aa", (28672 + 1318) => x"ea", (28672 + 1319) => x"4a", (28672 + 1320) => x"4e", (28672 + 1321) => x"00", (28672 + 1322) => x"a4", (28672 + 1323) => x"a4", (28672 + 1324) => x"a4", (28672 + 1325) => x"a5", (28672 + 1326) => x"e2", (28672 + 1327) => x"00", (28672 + 1328) => x"5d", (28672 + 1329) => x"55", (28672 + 1330) => x"55", (28672 + 1331) => x"55", (28672 + 1332) => x"9d", (28672 + 1333) => x"00", (28672 + 1334) => x"c8", (28672 + 1335) => x"48", (28672 + 1336) => x"48", (28672 + 1337) => x"40", (28672 + 1338) => x"48", (28672 + 1339) => x"00", (28672 + 1340) => x"d7", (28672 + 1341) => x"85", (28672 + 1342) => x"a5", (28672 + 1343) => x"4a", (28672 + 1344) => x"77", (28672 + 1345) => x"08", (28672 + 1346) => x"d7", (28672 + 1347) => x"85", (28672 + 1348) => x"77", (28672 + 1349) => x"08", (28672 + 1350) => x"a5", (28672 + 1351) => x"50", (28672 + 1352) => x"d7", (28672 + 1353) => x"85", (28672 + 1354) => x"77", (28672 + 1355) => x"08", (28672 + 1356) => x"a5", (28672 + 1357) => x"56", (28672 + 1358) => x"d7", (28672 + 1359) => x"85", (28672 + 1360) => x"15", (28672 + 1361) => x"70",
-- Hidden by David Winter
(32768 + 128) => x"00", (32768 + 129) => x"B0",
(32768 + 130) => x"CD", (32768 + 131) => x"E0",
(32768 + 132) => x"F0", (32768 + 133) => x"00",
(32768 + 134) => x"BE", (32768 + 135) => x"00",
(32768 + 136) => x"00", (32768 + 137) => x"60", -- delay
(32768 + 138) => x"00",
(32768 + 512) => x"12", (32768 + 513) => x"1d", (32768 + 514) => x"48", (32768 + 515) => x"49", (32768 + 516) => x"44", (32768 + 517) => x"44", (32768 + 518) => x"45", (32768 + 519) => x"4e", (32768 + 520) => x"21", (32768 + 521) => x"20", (32768 + 522) => x"31", (32768 + 523) => x"2e", (32768 + 524) => x"30", (32768 + 525) => x"20", (32768 + 526) => x"42", (32768 + 527) => x"79", (32768 + 528) => x"20", (32768 + 529) => x"44", (32768 + 530) => x"61", (32768 + 531) => x"76", (32768 + 532) => x"69", (32768 + 533) => x"64", (32768 + 534) => x"20", (32768 + 535) => x"57", (32768 + 536) => x"49", (32768 + 537) => x"4e", (32768 + 538) => x"54", (32768 + 539) => x"45", (32768 + 540) => x"52", (32768 + 541) => x"a4", (32768 + 542) => x"3f", (32768 + 543) => x"60", (32768 + 544) => x"00", (32768 + 545) => x"61", (32768 + 546) => x"40", (32768 + 547) => x"f1", (32768 + 548) => x"55", (32768 + 549) => x"a4", (32768 + 550) => x"3f", (32768 + 551) => x"60", (32768 + 552) => x"00", (32768 + 553) => x"f0", (32768 + 554) => x"55", (32768 + 555) => x"00", (32768 + 556) => x"e0", (32768 + 557) => x"a4", (32768 + 558) => x"7e", (32768 + 559) => x"60", (32768 + 560) => x"0c", (32768 + 561) => x"61", (32768 + 562) => x"08", (32768 + 563) => x"62", (32768 + 564) => x"0f", (32768 + 565) => x"d0", (32768 + 566) => x"1f", (32768 + 567) => x"70", (32768 + 568) => x"08", (32768 + 569) => x"f2", (32768 + 570) => x"1e", (32768 + 571) => x"30", (32768 + 572) => x"34", (32768 + 573) => x"12", (32768 + 574) => x"35", (32768 + 575) => x"f0", (32768 + 576) => x"0a", (32768 + 577) => x"00", (32768 + 578) => x"e0", (32768 + 579) => x"a4", (32768 + 580) => x"c9", (32768 + 581) => x"60", (32768 + 582) => x"13", (32768 + 583) => x"61", (32768 + 584) => x"0d", (32768 + 585) => x"62", (32768 + 586) => x"04", (32768 + 587) => x"d0", (32768 + 588) => x"14", (32768 + 589) => x"70", (32768 + 590) => x"08", (32768 + 591) => x"f2", (32768 + 592) => x"1e", (32768 + 593) => x"30", (32768 + 594) => x"2b", (32768 + 595) => x"12", (32768 + 596) => x"4b", (32768 + 597) => x"a4", (32768 + 598) => x"1f", (32768 + 599) => x"ff", (32768 + 600) => x"65", (32768 + 601) => x"a4", (32768 + 602) => x"2f", (32768 + 603) => x"ff", (32768 + 604) => x"55", (32768 + 605) => x"63", (32768 + 606) => x"40", (32768 + 607) => x"66", (32768 + 608) => x"08", (32768 + 609) => x"c1", (32768 + 610) => x"0f", (32768 + 611) => x"c2", (32768 + 612) => x"0f", (32768 + 613) => x"a4", (32768 + 614) => x"2f", (32768 + 615) => x"f1", (32768 + 616) => x"1e", (32768 + 617) => x"f0", (32768 + 618) => x"65", (32768 + 619) => x"84", (32768 + 620) => x"00", (32768 + 621) => x"a4", (32768 + 622) => x"2f", (32768 + 623) => x"f2", (32768 + 624) => x"1e", (32768 + 625) => x"f0", (32768 + 626) => x"65", (32768 + 627) => x"85", (32768 + 628) => x"00", (32768 + 629) => x"80", (32768 + 630) => x"40", (32768 + 631) => x"f0", (32768 + 632) => x"55", (32768 + 633) => x"a4", (32768 + 634) => x"2f", (32768 + 635) => x"f1", (32768 + 636) => x"1e", (32768 + 637) => x"80", (32768 + 638) => x"50", (32768 + 639) => x"f0", (32768 + 640) => x"55", (32768 + 641) => x"73", (32768 + 642) => x"ff", (32768 + 643) => x"33", (32768 + 644) => x"00", (32768 + 645) => x"12", (32768 + 646) => x"61", (32768 + 647) => x"00", (32768 + 648) => x"e0", (32768 + 649) => x"60", (32768 + 650) => x"00", (32768 + 651) => x"61", (32768 + 652) => x"00", (32768 + 653) => x"a4", (32768 + 654) => x"77", (32768 + 655) => x"d0", (32768 + 656) => x"17", (32768 + 657) => x"70", (32768 + 658) => x"08", (32768 + 659) => x"30", (32768 + 660) => x"20", (32768 + 661) => x"12", (32768 + 662) => x"8f", (32768 + 663) => x"60", (32768 + 664) => x"00", (32768 + 665) => x"71", (32768 + 666) => x"08", (32768 + 667) => x"31", (32768 + 668) => x"20", (32768 + 669) => x"12", (32768 + 670) => x"8f", (32768 + 671) => x"6c", (32768 + 672) => x"00", (32768 + 673) => x"6d", (32768 + 674) => x"00", (32768 + 675) => x"6e", (32768 + 676) => x"00", (32768 + 677) => x"a4", (32768 + 678) => x"3f", (32768 + 679) => x"f0", (32768 + 680) => x"65", (32768 + 681) => x"70", (32768 + 682) => x"01", (32768 + 683) => x"f0", (32768 + 684) => x"55", (32768 + 685) => x"23", (32768 + 686) => x"b9", (32768 + 687) => x"6a", (32768 + 688) => x"10", (32768 + 689) => x"23", (32768 + 690) => x"5d", (32768 + 691) => x"23", (32768 + 692) => x"cd", (32768 + 693) => x"8a", (32768 + 694) => x"90", (32768 + 695) => x"87", (32768 + 696) => x"d0", (32768 + 697) => x"88", (32768 + 698) => x"e0", (32768 + 699) => x"23", (32768 + 700) => x"5d", (32768 + 701) => x"23", (32768 + 702) => x"cd", (32768 + 703) => x"23", (32768 + 704) => x"b9", (32768 + 705) => x"a4", (32768 + 706) => x"2f", (32768 + 707) => x"f9", (32768 + 708) => x"1e", (32768 + 709) => x"f0", (32768 + 710) => x"65", (32768 + 711) => x"81", (32768 + 712) => x"00", (32768 + 713) => x"a4", (32768 + 714) => x"2f", (32768 + 715) => x"fa", (32768 + 716) => x"1e", (32768 + 717) => x"f0", (32768 + 718) => x"65", (32768 + 719) => x"50", (32768 + 720) => x"10", (32768 + 721) => x"13", (32768 + 722) => x"2b", (32768 + 723) => x"23", (32768 + 724) => x"df", (32768 + 725) => x"60", (32768 + 726) => x"20", (32768 + 727) => x"24", (32768 + 728) => x"01", (32768 + 729) => x"23", (32768 + 730) => x"df", (32768 + 731) => x"60", (32768 + 732) => x"00", (32768 + 733) => x"a4", (32768 + 734) => x"2f", (32768 + 735) => x"f9", (32768 + 736) => x"1e", (32768 + 737) => x"f0", (32768 + 738) => x"55", (32768 + 739) => x"a4", (32768 + 740) => x"2f", (32768 + 741) => x"fa", (32768 + 742) => x"1e", (32768 + 743) => x"f0", (32768 + 744) => x"55", (32768 + 745) => x"76", (32768 + 746) => x"ff", (32768 + 747) => x"36", (32768 + 748) => x"00", (32768 + 749) => x"12", (32768 + 750) => x"a5", (32768 + 751) => x"a4", (32768 + 752) => x"3f", (32768 + 753) => x"f1", (32768 + 754) => x"65", (32768 + 755) => x"82", (32768 + 756) => x"00", (32768 + 757) => x"80", (32768 + 758) => x"15", (32768 + 759) => x"3f", (32768 + 760) => x"00", (32768 + 761) => x"13", (32768 + 762) => x"01", (32768 + 763) => x"80", (32768 + 764) => x"20", (32768 + 765) => x"81", (32768 + 766) => x"20", (32768 + 767) => x"f1", (32768 + 768) => x"55", (32768 + 769) => x"00", (32768 + 770) => x"e0", (32768 + 771) => x"a5", (32768 + 772) => x"19", (32768 + 773) => x"60", (32768 + 774) => x"10", (32768 + 775) => x"61", (32768 + 776) => x"07", (32768 + 777) => x"62", (32768 + 778) => x"0e", (32768 + 779) => x"d0", (32768 + 780) => x"1f", (32768 + 781) => x"70", (32768 + 782) => x"08", (32768 + 783) => x"f2", (32768 + 784) => x"1e", (32768 + 785) => x"30", (32768 + 786) => x"30", (32768 + 787) => x"13", (32768 + 788) => x"0b", (32768 + 789) => x"a4", (32768 + 790) => x"3f", (32768 + 791) => x"f1", (32768 + 792) => x"65", (32768 + 793) => x"84", (32768 + 794) => x"10", (32768 + 795) => x"83", (32768 + 796) => x"00", (32768 + 797) => x"66", (32768 + 798) => x"09", (32768 + 799) => x"24", (32768 + 800) => x"0b", (32768 + 801) => x"66", (32768 + 802) => x"0f", (32768 + 803) => x"83", (32768 + 804) => x"40", (32768 + 805) => x"24", (32768 + 806) => x"0b", (32768 + 807) => x"f0", (32768 + 808) => x"0a", (32768 + 809) => x"12", (32768 + 810) => x"25", (32768 + 811) => x"23", (32768 + 812) => x"db", (32768 + 813) => x"60", (32768 + 814) => x"80", (32768 + 815) => x"24", (32768 + 816) => x"01", (32768 + 817) => x"23", (32768 + 818) => x"db", (32768 + 819) => x"a4", (32768 + 820) => x"2f", (32768 + 821) => x"fa", (32768 + 822) => x"1e", (32768 + 823) => x"f0", (32768 + 824) => x"65", (32768 + 825) => x"70", (32768 + 826) => x"ff", (32768 + 827) => x"23", (32768 + 828) => x"f3", (32768 + 829) => x"a4", (32768 + 830) => x"41", (32768 + 831) => x"f0", (32768 + 832) => x"1e", (32768 + 833) => x"d7", (32768 + 834) => x"87", (32768 + 835) => x"a4", (32768 + 836) => x"77", (32768 + 837) => x"d7", (32768 + 838) => x"87", (32768 + 839) => x"a4", (32768 + 840) => x"2f", (32768 + 841) => x"f9", (32768 + 842) => x"1e", (32768 + 843) => x"f0", (32768 + 844) => x"65", (32768 + 845) => x"70", (32768 + 846) => x"ff", (32768 + 847) => x"23", (32768 + 848) => x"f3", (32768 + 849) => x"a4", (32768 + 850) => x"41", (32768 + 851) => x"f0", (32768 + 852) => x"1e", (32768 + 853) => x"dd", (32768 + 854) => x"e7", (32768 + 855) => x"a4", (32768 + 856) => x"77", (32768 + 857) => x"dd", (32768 + 858) => x"e7", (32768 + 859) => x"12", (32768 + 860) => x"a5", (32768 + 861) => x"a4", (32768 + 862) => x"71", (32768 + 863) => x"dd", (32768 + 864) => x"e7", (32768 + 865) => x"fb", (32768 + 866) => x"0a", (32768 + 867) => x"dd", (32768 + 868) => x"e7", (32768 + 869) => x"3b", (32768 + 870) => x"04", (32768 + 871) => x"13", (32768 + 872) => x"71", (32768 + 873) => x"4d", (32768 + 874) => x"00", (32768 + 875) => x"13", (32768 + 876) => x"5d", (32768 + 877) => x"7d", (32768 + 878) => x"f8", (32768 + 879) => x"7c", (32768 + 880) => x"ff", (32768 + 881) => x"3b", (32768 + 882) => x"06", (32768 + 883) => x"13", (32768 + 884) => x"7d", (32768 + 885) => x"4d", (32768 + 886) => x"18", (32768 + 887) => x"13", (32768 + 888) => x"5d", (32768 + 889) => x"7d", (32768 + 890) => x"08", (32768 + 891) => x"7c", (32768 + 892) => x"01", (32768 + 893) => x"3b", (32768 + 894) => x"02", (32768 + 895) => x"13", (32768 + 896) => x"89", (32768 + 897) => x"4e", (32768 + 898) => x"00", (32768 + 899) => x"13", (32768 + 900) => x"5d", (32768 + 901) => x"7e", (32768 + 902) => x"f8", (32768 + 903) => x"7c", (32768 + 904) => x"fc", (32768 + 905) => x"3b", (32768 + 906) => x"08", (32768 + 907) => x"13", (32768 + 908) => x"95", (32768 + 909) => x"4e", (32768 + 910) => x"18", (32768 + 911) => x"13", (32768 + 912) => x"5d", (32768 + 913) => x"7e", (32768 + 914) => x"08", (32768 + 915) => x"7c", (32768 + 916) => x"04", (32768 + 917) => x"3b", (32768 + 918) => x"05", (32768 + 919) => x"13", (32768 + 920) => x"5d", (32768 + 921) => x"a4", (32768 + 922) => x"2f", (32768 + 923) => x"fc", (32768 + 924) => x"1e", (32768 + 925) => x"f0", (32768 + 926) => x"65", (32768 + 927) => x"40", (32768 + 928) => x"00", (32768 + 929) => x"13", (32768 + 930) => x"5d", (32768 + 931) => x"89", (32768 + 932) => x"c0", (32768 + 933) => x"99", (32768 + 934) => x"a0", (32768 + 935) => x"13", (32768 + 936) => x"5d", (32768 + 937) => x"70", (32768 + 938) => x"ff", (32768 + 939) => x"a4", (32768 + 940) => x"77", (32768 + 941) => x"dd", (32768 + 942) => x"e7", (32768 + 943) => x"a4", (32768 + 944) => x"41", (32768 + 945) => x"23", (32768 + 946) => x"f3", (32768 + 947) => x"f0", (32768 + 948) => x"1e", (32768 + 949) => x"dd", (32768 + 950) => x"e7", (32768 + 951) => x"00", (32768 + 952) => x"ee", (32768 + 953) => x"a4", (32768 + 954) => x"d5", (32768 + 955) => x"60", (32768 + 956) => x"24", (32768 + 957) => x"61", (32768 + 958) => x"0a", (32768 + 959) => x"62", (32768 + 960) => x"0b", (32768 + 961) => x"d0", (32768 + 962) => x"1b", (32768 + 963) => x"70", (32768 + 964) => x"08", (32768 + 965) => x"f2", (32768 + 966) => x"1e", (32768 + 967) => x"30", (32768 + 968) => x"3c", (32768 + 969) => x"13", (32768 + 970) => x"c1", (32768 + 971) => x"00", (32768 + 972) => x"ee", (32768 + 973) => x"60", (32768 + 974) => x"34", (32768 + 975) => x"61", (32768 + 976) => x"10", (32768 + 977) => x"a4", (32768 + 978) => x"f1", (32768 + 979) => x"d0", (32768 + 980) => x"15", (32768 + 981) => x"a4", (32768 + 982) => x"f6", (32768 + 983) => x"d0", (32768 + 984) => x"15", (32768 + 985) => x"00", (32768 + 986) => x"ee", (32768 + 987) => x"a4", (32768 + 988) => x"fb", (32768 + 989) => x"13", (32768 + 990) => x"e1", (32768 + 991) => x"a5", (32768 + 992) => x"0a", (32768 + 993) => x"60", (32768 + 994) => x"24", (32768 + 995) => x"61", (32768 + 996) => x"0d", (32768 + 997) => x"62", (32768 + 998) => x"05", (32768 + 999) => x"d0", (32768 + 1000) => x"15", (32768 + 1001) => x"70", (32768 + 1002) => x"08", (32768 + 1003) => x"f2", (32768 + 1004) => x"1e", (32768 + 1005) => x"30", (32768 + 1006) => x"3c", (32768 + 1007) => x"13", (32768 + 1008) => x"e7", (32768 + 1009) => x"00", (32768 + 1010) => x"ee", (32768 + 1011) => x"81", (32768 + 1012) => x"00", (32768 + 1013) => x"81", (32768 + 1014) => x"14", (32768 + 1015) => x"80", (32768 + 1016) => x"04", (32768 + 1017) => x"80", (32768 + 1018) => x"04", (32768 + 1019) => x"80", (32768 + 1020) => x"04", (32768 + 1021) => x"80", (32768 + 1022) => x"15", (32768 + 1023) => x"00", (32768 + 1024) => x"ee", (32768 + 1025) => x"f0", (32768 + 1026) => x"15", (32768 + 1027) => x"f0", (32768 + 1028) => x"07", (32768 + 1029) => x"30", (32768 + 1030) => x"00", (32768 + 1031) => x"14", (32768 + 1032) => x"03", (32768 + 1033) => x"00", (32768 + 1034) => x"ee", (32768 + 1035) => x"a4", (32768 + 1036) => x"2f", (32768 + 1037) => x"f3", (32768 + 1038) => x"33", (32768 + 1039) => x"f2", (32768 + 1040) => x"65", (32768 + 1041) => x"65", (32768 + 1042) => x"23", (32768 + 1043) => x"f1", (32768 + 1044) => x"29", (32768 + 1045) => x"d5", (32768 + 1046) => x"65", (32768 + 1047) => x"65", (32768 + 1048) => x"28", (32768 + 1049) => x"f2", (32768 + 1050) => x"29", (32768 + 1051) => x"d5", (32768 + 1052) => x"65", (32768 + 1053) => x"00", (32768 + 1054) => x"ee", (32768 + 1055) => x"01", (32768 + 1056) => x"02", (32768 + 1057) => x"03", (32768 + 1058) => x"04", (32768 + 1059) => x"08", (32768 + 1060) => x"07", (32768 + 1061) => x"06", (32768 + 1062) => x"05", (32768 + 1063) => x"05", (32768 + 1064) => x"06", (32768 + 1065) => x"07", (32768 + 1066) => x"08", (32768 + 1067) => x"04", (32768 + 1068) => x"03", (32768 + 1069) => x"02", (32768 + 1070) => x"01", (32768 + 1071) => x"01", (32768 + 1072) => x"02", (32768 + 1073) => x"03", (32768 + 1074) => x"04", (32768 + 1075) => x"08", (32768 + 1076) => x"07", (32768 + 1077) => x"06", (32768 + 1078) => x"05", (32768 + 1079) => x"05", (32768 + 1080) => x"06", (32768 + 1081) => x"07", (32768 + 1082) => x"08", (32768 + 1083) => x"04", (32768 + 1084) => x"03", (32768 + 1085) => x"02", (32768 + 1086) => x"01", (32768 + 1087) => x"00", (32768 + 1088) => x"00", (32768 + 1089) => x"fe", (32768 + 1090) => x"ee", (32768 + 1091) => x"c6", (32768 + 1092) => x"82", (32768 + 1093) => x"c6", (32768 + 1094) => x"ee", (32768 + 1095) => x"fe", (32768 + 1096) => x"fe", (32768 + 1097) => x"c6", (32768 + 1098) => x"c6", (32768 + 1099) => x"c6", (32768 + 1100) => x"fe", (32768 + 1101) => x"fe", (32768 + 1102) => x"c6", (32768 + 1103) => x"aa", (32768 + 1104) => x"82", (32768 + 1105) => x"aa", (32768 + 1106) => x"c6", (32768 + 1107) => x"fe", (32768 + 1108) => x"c6", (32768 + 1109) => x"82", (32768 + 1110) => x"82", (32768 + 1111) => x"82", (32768 + 1112) => x"c6", (32768 + 1113) => x"fe", (32768 + 1114) => x"ba", (32768 + 1115) => x"d6", (32768 + 1116) => x"ee", (32768 + 1117) => x"d6", (32768 + 1118) => x"ba", (32768 + 1119) => x"fe", (32768 + 1120) => x"ee", (32768 + 1121) => x"ee", (32768 + 1122) => x"82", (32768 + 1123) => x"ee", (32768 + 1124) => x"ee", (32768 + 1125) => x"fe", (32768 + 1126) => x"82", (32768 + 1127) => x"fe", (32768 + 1128) => x"82", (32768 + 1129) => x"fe", (32768 + 1130) => x"82", (32768 + 1131) => x"fe", (32768 + 1132) => x"aa", (32768 + 1133) => x"aa", (32768 + 1134) => x"aa", (32768 + 1135) => x"aa", (32768 + 1136) => x"aa", (32768 + 1137) => x"fe", (32768 + 1138) => x"fe", (32768 + 1139) => x"fe", (32768 + 1140) => x"fe", (32768 + 1141) => x"fe", (32768 + 1142) => x"fe", (32768 + 1143) => x"fe", (32768 + 1144) => x"aa", (32768 + 1145) => x"d6", (32768 + 1146) => x"aa", (32768 + 1147) => x"d6", (32768 + 1148) => x"aa", (32768 + 1149) => x"fe", (32768 + 1150) => x"8b", (32768 + 1151) => x"88", (32768 + 1152) => x"f8", (32768 + 1153) => x"88", (32768 + 1154) => x"8b", (32768 + 1155) => x"00", (32768 + 1156) => x"00", (32768 + 1157) => x"00", (32768 + 1158) => x"00", (32768 + 1159) => x"00", (32768 + 1160) => x"f0", (32768 + 1161) => x"48", (32768 + 1162) => x"48", (32768 + 1163) => x"48", (32768 + 1164) => x"f2", (32768 + 1165) => x"ef", (32768 + 1166) => x"84", (32768 + 1167) => x"84", (32768 + 1168) => x"84", (32768 + 1169) => x"ef", (32768 + 1170) => x"00", (32768 + 1171) => x"08", (32768 + 1172) => x"08", (32768 + 1173) => x"0a", (32768 + 1174) => x"00", (32768 + 1175) => x"8a", (32768 + 1176) => x"8a", (32768 + 1177) => x"aa", (32768 + 1178) => x"aa", (32768 + 1179) => x"52", (32768 + 1180) => x"3c", (32768 + 1181) => x"92", (32768 + 1182) => x"92", (32768 + 1183) => x"92", (32768 + 1184) => x"3c", (32768 + 1185) => x"00", (32768 + 1186) => x"e2", (32768 + 1187) => x"a3", (32768 + 1188) => x"e3", (32768 + 1189) => x"00", (32768 + 1190) => x"8b", (32768 + 1191) => x"c8", (32768 + 1192) => x"a8", (32768 + 1193) => x"98", (32768 + 1194) => x"88", (32768 + 1195) => x"fa", (32768 + 1196) => x"83", (32768 + 1197) => x"e2", (32768 + 1198) => x"82", (32768 + 1199) => x"fa", (32768 + 1200) => x"00", (32768 + 1201) => x"28", (32768 + 1202) => x"b8", (32768 + 1203) => x"90", (32768 + 1204) => x"00", (32768 + 1205) => x"ef", (32768 + 1206) => x"88", (32768 + 1207) => x"8e", (32768 + 1208) => x"88", (32768 + 1209) => x"8f", (32768 + 1210) => x"21", (32768 + 1211) => x"21", (32768 + 1212) => x"a1", (32768 + 1213) => x"60", (32768 + 1214) => x"21", (32768 + 1215) => x"00", (32768 + 1216) => x"00", (32768 + 1217) => x"00", (32768 + 1218) => x"00", (32768 + 1219) => x"00", (32768 + 1220) => x"bc", (32768 + 1221) => x"22", (32768 + 1222) => x"3c", (32768 + 1223) => x"28", (32768 + 1224) => x"a4", (32768 + 1225) => x"89", (32768 + 1226) => x"8a", (32768 + 1227) => x"ab", (32768 + 1228) => x"52", (32768 + 1229) => x"97", (32768 + 1230) => x"51", (32768 + 1231) => x"d1", (32768 + 1232) => x"51", (32768 + 1233) => x"c0", (32768 + 1234) => x"00", (32768 + 1235) => x"00", (32768 + 1236) => x"15", (32768 + 1237) => x"6a", (32768 + 1238) => x"8a", (32768 + 1239) => x"8e", (32768 + 1240) => x"8a", (32768 + 1241) => x"6a", (32768 + 1242) => x"00", (32768 + 1243) => x"64", (32768 + 1244) => x"8a", (32768 + 1245) => x"8e", (32768 + 1246) => x"8a", (32768 + 1247) => x"6a", (32768 + 1248) => x"44", (32768 + 1249) => x"aa", (32768 + 1250) => x"aa", (32768 + 1251) => x"aa", (32768 + 1252) => x"44", (32768 + 1253) => x"00", (32768 + 1254) => x"cc", (32768 + 1255) => x"aa", (32768 + 1256) => x"ca", (32768 + 1257) => x"aa", (32768 + 1258) => x"ac", (32768 + 1259) => x"6e", (32768 + 1260) => x"88", (32768 + 1261) => x"4c", (32768 + 1262) => x"28", (32768 + 1263) => x"ce", (32768 + 1264) => x"00", (32768 + 1265) => x"04", (32768 + 1266) => x"0c", (32768 + 1267) => x"04", (32768 + 1268) => x"04", (32768 + 1269) => x"0e", (32768 + 1270) => x"0c", (32768 + 1271) => x"12", (32768 + 1272) => x"04", (32768 + 1273) => x"08", (32768 + 1274) => x"1e", (32768 + 1275) => x"63", (32768 + 1276) => x"94", (32768 + 1277) => x"94", (32768 + 1278) => x"94", (32768 + 1279) => x"63", (32768 + 1280) => x"38", (32768 + 1281) => x"a5", (32768 + 1282) => x"b8", (32768 + 1283) => x"a0", (32768 + 1284) => x"21", (32768 + 1285) => x"e1", (32768 + 1286) => x"01", (32768 + 1287) => x"c1", (32768 + 1288) => x"20", (32768 + 1289) => x"c1", (32768 + 1290) => x"89", (32768 + 1291) => x"8a", (32768 + 1292) => x"52", (32768 + 1293) => x"22", (32768 + 1294) => x"21", (32768 + 1295) => x"cf", (32768 + 1296) => x"28", (32768 + 1297) => x"2f", (32768 + 1298) => x"28", (32768 + 1299) => x"c8", (32768 + 1300) => x"02", (32768 + 1301) => x"82", (32768 + 1302) => x"02", (32768 + 1303) => x"00", (32768 + 1304) => x"02", (32768 + 1305) => x"ff", (32768 + 1306) => x"80", (32768 + 1307) => x"8f", (32768 + 1308) => x"90", (32768 + 1309) => x"8e", (32768 + 1310) => x"81", (32768 + 1311) => x"9e", (32768 + 1312) => x"80", (32768 + 1313) => x"91", (32768 + 1314) => x"91", (32768 + 1315) => x"9f", (32768 + 1316) => x"91", (32768 + 1317) => x"91", (32768 + 1318) => x"80", (32768 + 1319) => x"ff", (32768 + 1320) => x"00", (32768 + 1321) => x"3c", (32768 + 1322) => x"40", (32768 + 1323) => x"40", (32768 + 1324) => x"40", (32768 + 1325) => x"3c", (32768 + 1326) => x"00", (32768 + 1327) => x"7c", (32768 + 1328) => x"10", (32768 + 1329) => x"10", (32768 + 1330) => x"10", (32768 + 1331) => x"7c", (32768 + 1332) => x"00", (32768 + 1333) => x"ff", (32768 + 1334) => x"00", (32768 + 1335) => x"00", (32768 + 1336) => x"80", (32768 + 1337) => x"00", (32768 + 1338) => x"80", (32768 + 1339) => x"00", (32768 + 1340) => x"00", (32768 + 1341) => x"00", (32768 + 1342) => x"80", (32768 + 1343) => x"00", (32768 + 1344) => x"80", (32768 + 1345) => x"00", (32768 + 1346) => x"00", (32768 + 1347) => x"ff", (32768 + 1348) => x"01", (32768 + 1349) => x"01", (32768 + 1350) => x"01", (32768 + 1351) => x"01", (32768 + 1352) => x"01", (32768 + 1353) => x"01", (32768 + 1354) => x"01", (32768 + 1355) => x"01", (32768 + 1356) => x"01", (32768 + 1357) => x"01", (32768 + 1358) => x"01", (32768 + 1359) => x"01", (32768 + 1360) => x"01", (32768 + 1361) => x"ff",
-- Kaleid by Joseph Weisbecker (RCA)
(36864 + 128) => x"00", (36864 + 129) => x"B0",
(36864 + 130) => x"CD", (36864 + 131) => x"E0",
(36864 + 132) => x"F0", (36864 + 133) => x"00",
(36864 + 134) => x"BE", (36864 + 135) => x"00",
(36864 + 136) => x"00", (36864 + 137) => x"20", -- delay
(36864 + 138) => x"00",
(36864 + 512) => x"60", (36864 + 513) => x"00", (36864 + 514) => x"63", (36864 + 515) => x"80", (36864 + 516) => x"61", (36864 + 517) => x"1f", (36864 + 518) => x"62", (36864 + 519) => x"0f", (36864 + 520) => x"22", (36864 + 521) => x"32", (36864 + 522) => x"a2", (36864 + 523) => x"00", (36864 + 524) => x"f3", (36864 + 525) => x"1e", (36864 + 526) => x"f0", (36864 + 527) => x"0a", (36864 + 528) => x"f0", (36864 + 529) => x"55", (36864 + 530) => x"40", (36864 + 531) => x"00", (36864 + 532) => x"12", (36864 + 533) => x"1c", (36864 + 534) => x"73", (36864 + 535) => x"01", (36864 + 536) => x"33", (36864 + 537) => x"00", (36864 + 538) => x"12", (36864 + 539) => x"08", (36864 + 540) => x"63", (36864 + 541) => x"80", (36864 + 542) => x"a2", (36864 + 543) => x"00", (36864 + 544) => x"f3", (36864 + 545) => x"1e", (36864 + 546) => x"f0", (36864 + 547) => x"65", (36864 + 548) => x"40", (36864 + 549) => x"00", (36864 + 550) => x"12", (36864 + 551) => x"1c", (36864 + 552) => x"73", (36864 + 553) => x"01", (36864 + 554) => x"43", (36864 + 555) => x"00", (36864 + 556) => x"12", (36864 + 557) => x"1c", (36864 + 558) => x"22", (36864 + 559) => x"32", (36864 + 560) => x"12", (36864 + 561) => x"1e", (36864 + 562) => x"40", (36864 + 563) => x"02", (36864 + 564) => x"72", (36864 + 565) => x"ff", (36864 + 566) => x"40", (36864 + 567) => x"04", (36864 + 568) => x"71", (36864 + 569) => x"ff", (36864 + 570) => x"40", (36864 + 571) => x"06", (36864 + 572) => x"71", (36864 + 573) => x"01", (36864 + 574) => x"40", (36864 + 575) => x"08", (36864 + 576) => x"72", (36864 + 577) => x"01", (36864 + 578) => x"a2", (36864 + 579) => x"77", (36864 + 580) => x"6a", (36864 + 581) => x"e0", (36864 + 582) => x"8a", (36864 + 583) => x"12", (36864 + 584) => x"6b", (36864 + 585) => x"1f", (36864 + 586) => x"81", (36864 + 587) => x"b2", (36864 + 588) => x"3a", (36864 + 589) => x"00", (36864 + 590) => x"72", (36864 + 591) => x"01", (36864 + 592) => x"6a", (36864 + 593) => x"f0", (36864 + 594) => x"8a", (36864 + 595) => x"22", (36864 + 596) => x"6b", (36864 + 597) => x"0f", (36864 + 598) => x"82", (36864 + 599) => x"b2", (36864 + 600) => x"3a", (36864 + 601) => x"00", (36864 + 602) => x"71", (36864 + 603) => x"01", (36864 + 604) => x"6b", (36864 + 605) => x"1f", (36864 + 606) => x"81", (36864 + 607) => x"b2", (36864 + 608) => x"d1", (36864 + 609) => x"21", (36864 + 610) => x"8a", (36864 + 611) => x"10", (36864 + 612) => x"6b", (36864 + 613) => x"1f", (36864 + 614) => x"8b", (36864 + 615) => x"25", (36864 + 616) => x"da", (36864 + 617) => x"b1", (36864 + 618) => x"6a", (36864 + 619) => x"3f", (36864 + 620) => x"8a", (36864 + 621) => x"15", (36864 + 622) => x"da", (36864 + 623) => x"b1", (36864 + 624) => x"8b", (36864 + 625) => x"20", (36864 + 626) => x"da", (36864 + 627) => x"b1", (36864 + 628) => x"00", (36864 + 629) => x"ee", (36864 + 630) => x"01", (36864 + 631) => x"80",
-- Merlin by David Winter
(40960 + 128) => x"00", (40960 + 129) => x"00",
(40960 + 130) => x"CB", (40960 + 131) => x"0F",
(40960 + 132) => x"E0", (40960 + 133) => x"00",
(40960 + 134) => x"BE", (40960 + 135) => x"00",
(40960 + 136) => x"00", (40960 + 137) => x"30", -- delay
(40960 + 138) => x"00",
(40960 + 512) => x"12", (40960 + 513) => x"19", (40960 + 514) => x"20", (40960 + 515) => x"4d", (40960 + 516) => x"45", (40960 + 517) => x"52", (40960 + 518) => x"4c", (40960 + 519) => x"49", (40960 + 520) => x"4e", (40960 + 521) => x"20", (40960 + 522) => x"42", (40960 + 523) => x"79", (40960 + 524) => x"20", (40960 + 525) => x"44", (40960 + 526) => x"61", (40960 + 527) => x"76", (40960 + 528) => x"69", (40960 + 529) => x"64", (40960 + 530) => x"20", (40960 + 531) => x"57", (40960 + 532) => x"49", (40960 + 533) => x"4e", (40960 + 534) => x"54", (40960 + 535) => x"45", (40960 + 536) => x"52", (40960 + 537) => x"22", (40960 + 538) => x"f9", (40960 + 539) => x"a3", (40960 + 540) => x"1d", (40960 + 541) => x"60", (40960 + 542) => x"10", (40960 + 543) => x"61", (40960 + 544) => x"00", (40960 + 545) => x"22", (40960 + 546) => x"cb", (40960 + 547) => x"a3", (40960 + 548) => x"31", (40960 + 549) => x"60", (40960 + 550) => x"0b", (40960 + 551) => x"61", (40960 + 552) => x"1b", (40960 + 553) => x"22", (40960 + 554) => x"cb", (40960 + 555) => x"64", (40960 + 556) => x"04", (40960 + 557) => x"22", (40960 + 558) => x"df", (40960 + 559) => x"65", (40960 + 560) => x"00", (40960 + 561) => x"62", (40960 + 562) => x"28", (40960 + 563) => x"22", (40960 + 564) => x"c1", (40960 + 565) => x"c2", (40960 + 566) => x"03", (40960 + 567) => x"80", (40960 + 568) => x"20", (40960 + 569) => x"a3", (40960 + 570) => x"59", (40960 + 571) => x"f5", (40960 + 572) => x"1e", (40960 + 573) => x"f0", (40960 + 574) => x"55", (40960 + 575) => x"60", (40960 + 576) => x"17", (40960 + 577) => x"61", (40960 + 578) => x"08", (40960 + 579) => x"63", (40960 + 580) => x"01", (40960 + 581) => x"83", (40960 + 582) => x"22", (40960 + 583) => x"33", (40960 + 584) => x"00", (40960 + 585) => x"70", (40960 + 586) => x"0a", (40960 + 587) => x"63", (40960 + 588) => x"02", (40960 + 589) => x"83", (40960 + 590) => x"22", (40960 + 591) => x"33", (40960 + 592) => x"00", (40960 + 593) => x"71", (40960 + 594) => x"0a", (40960 + 595) => x"a3", (40960 + 596) => x"17", (40960 + 597) => x"d0", (40960 + 598) => x"16", (40960 + 599) => x"62", (40960 + 600) => x"14", (40960 + 601) => x"22", (40960 + 602) => x"c1", (40960 + 603) => x"d0", (40960 + 604) => x"16", (40960 + 605) => x"62", (40960 + 606) => x"05", (40960 + 607) => x"22", (40960 + 608) => x"c1", (40960 + 609) => x"75", (40960 + 610) => x"01", (40960 + 611) => x"54", (40960 + 612) => x"50", (40960 + 613) => x"12", (40960 + 614) => x"35", (40960 + 615) => x"65", (40960 + 616) => x"00", (40960 + 617) => x"60", (40960 + 618) => x"17", (40960 + 619) => x"61", (40960 + 620) => x"08", (40960 + 621) => x"a3", (40960 + 622) => x"17", (40960 + 623) => x"f3", (40960 + 624) => x"0a", (40960 + 625) => x"33", (40960 + 626) => x"04", (40960 + 627) => x"12", (40960 + 628) => x"79", (40960 + 629) => x"63", (40960 + 630) => x"00", (40960 + 631) => x"12", (40960 + 632) => x"97", (40960 + 633) => x"33", (40960 + 634) => x"05", (40960 + 635) => x"12", (40960 + 636) => x"83", (40960 + 637) => x"70", (40960 + 638) => x"0a", (40960 + 639) => x"63", (40960 + 640) => x"01", (40960 + 641) => x"12", (40960 + 642) => x"97", (40960 + 643) => x"33", (40960 + 644) => x"07", (40960 + 645) => x"12", (40960 + 646) => x"8d", (40960 + 647) => x"71", (40960 + 648) => x"0a", (40960 + 649) => x"63", (40960 + 650) => x"02", (40960 + 651) => x"12", (40960 + 652) => x"97", (40960 + 653) => x"33", (40960 + 654) => x"08", (40960 + 655) => x"12", (40960 + 656) => x"69", (40960 + 657) => x"70", (40960 + 658) => x"0a", (40960 + 659) => x"71", (40960 + 660) => x"0a", (40960 + 661) => x"63", (40960 + 662) => x"03", (40960 + 663) => x"d0", (40960 + 664) => x"16", (40960 + 665) => x"62", (40960 + 666) => x"14", (40960 + 667) => x"22", (40960 + 668) => x"c1", (40960 + 669) => x"d0", (40960 + 670) => x"16", (40960 + 671) => x"a3", (40960 + 672) => x"59", (40960 + 673) => x"f5", (40960 + 674) => x"1e", (40960 + 675) => x"f0", (40960 + 676) => x"65", (40960 + 677) => x"75", (40960 + 678) => x"01", (40960 + 679) => x"50", (40960 + 680) => x"30", (40960 + 681) => x"12", (40960 + 682) => x"b5", (40960 + 683) => x"55", (40960 + 684) => x"40", (40960 + 685) => x"12", (40960 + 686) => x"69", (40960 + 687) => x"22", (40960 + 688) => x"df", (40960 + 689) => x"74", (40960 + 690) => x"01", (40960 + 691) => x"12", (40960 + 692) => x"2d", (40960 + 693) => x"22", (40960 + 694) => x"f9", (40960 + 695) => x"a3", (40960 + 696) => x"45", (40960 + 697) => x"60", (40960 + 698) => x"10", (40960 + 699) => x"61", (40960 + 700) => x"0e", (40960 + 701) => x"22", (40960 + 702) => x"cb", (40960 + 703) => x"12", (40960 + 704) => x"bf", (40960 + 705) => x"f2", (40960 + 706) => x"15", (40960 + 707) => x"f2", (40960 + 708) => x"07", (40960 + 709) => x"32", (40960 + 710) => x"00", (40960 + 711) => x"12", (40960 + 712) => x"c3", (40960 + 713) => x"00", (40960 + 714) => x"ee", (40960 + 715) => x"83", (40960 + 716) => x"00", (40960 + 717) => x"62", (40960 + 718) => x"05", (40960 + 719) => x"d0", (40960 + 720) => x"15", (40960 + 721) => x"f2", (40960 + 722) => x"1e", (40960 + 723) => x"70", (40960 + 724) => x"08", (40960 + 725) => x"85", (40960 + 726) => x"30", (40960 + 727) => x"75", (40960 + 728) => x"20", (40960 + 729) => x"50", (40960 + 730) => x"50", (40960 + 731) => x"12", (40960 + 732) => x"cf", (40960 + 733) => x"00", (40960 + 734) => x"ee", (40960 + 735) => x"a3", (40960 + 736) => x"59", (40960 + 737) => x"83", (40960 + 738) => x"40", (40960 + 739) => x"73", (40960 + 740) => x"fd", (40960 + 741) => x"f3", (40960 + 742) => x"33", (40960 + 743) => x"f2", (40960 + 744) => x"65", (40960 + 745) => x"f1", (40960 + 746) => x"29", (40960 + 747) => x"60", (40960 + 748) => x"2b", (40960 + 749) => x"63", (40960 + 750) => x"1b", (40960 + 751) => x"d0", (40960 + 752) => x"35", (40960 + 753) => x"70", (40960 + 754) => x"05", (40960 + 755) => x"f2", (40960 + 756) => x"29", (40960 + 757) => x"d0", (40960 + 758) => x"35", (40960 + 759) => x"00", (40960 + 760) => x"ee", (40960 + 761) => x"a3", (40960 + 762) => x"0f", (40960 + 763) => x"60", (40960 + 764) => x"17", (40960 + 765) => x"61", (40960 + 766) => x"07", (40960 + 767) => x"d0", (40960 + 768) => x"18", (40960 + 769) => x"70", (40960 + 770) => x"0a", (40960 + 771) => x"d0", (40960 + 772) => x"18", (40960 + 773) => x"71", (40960 + 774) => x"0a", (40960 + 775) => x"d0", (40960 + 776) => x"18", (40960 + 777) => x"70", (40960 + 778) => x"f6", (40960 + 779) => x"d0", (40960 + 780) => x"18", (40960 + 781) => x"00", (40960 + 782) => x"ee", (40960 + 783) => x"ff", (40960 + 784) => x"81", (40960 + 785) => x"81", (40960 + 786) => x"81", (40960 + 787) => x"81", (40960 + 788) => x"81", (40960 + 789) => x"81", (40960 + 790) => x"ff", (40960 + 791) => x"7e", (40960 + 792) => x"7e", (40960 + 793) => x"7e", (40960 + 794) => x"7e", (40960 + 795) => x"7e", (40960 + 796) => x"7e", (40960 + 797) => x"db", (40960 + 798) => x"aa", (40960 + 799) => x"8b", (40960 + 800) => x"cb", (40960 + 801) => x"cb", (40960 + 802) => x"ef", (40960 + 803) => x"08", (40960 + 804) => x"8f", (40960 + 805) => x"0d", (40960 + 806) => x"ec", (40960 + 807) => x"a0", (40960 + 808) => x"a0", (40960 + 809) => x"b0", (40960 + 810) => x"30", (40960 + 811) => x"be", (40960 + 812) => x"5f", (40960 + 813) => x"51", (40960 + 814) => x"51", (40960 + 815) => x"d9", (40960 + 816) => x"d9", (40960 + 817) => x"83", (40960 + 818) => x"82", (40960 + 819) => x"83", (40960 + 820) => x"82", (40960 + 821) => x"fb", (40960 + 822) => x"e8", (40960 + 823) => x"08", (40960 + 824) => x"88", (40960 + 825) => x"05", (40960 + 826) => x"e2", (40960 + 827) => x"be", (40960 + 828) => x"a0", (40960 + 829) => x"b8", (40960 + 830) => x"20", (40960 + 831) => x"3e", (40960 + 832) => x"80", (40960 + 833) => x"80", (40960 + 834) => x"80", (40960 + 835) => x"80", (40960 + 836) => x"f8", (40960 + 837) => x"f7", (40960 + 838) => x"85", (40960 + 839) => x"b7", (40960 + 840) => x"95", (40960 + 841) => x"f5", (40960 + 842) => x"76", (40960 + 843) => x"54", (40960 + 844) => x"56", (40960 + 845) => x"54", (40960 + 846) => x"56", (40960 + 847) => x"3a", (40960 + 848) => x"2a", (40960 + 849) => x"2a", (40960 + 850) => x"2a", (40960 + 851) => x"39", (40960 + 852) => x"b6", (40960 + 853) => x"a5", (40960 + 854) => x"b6", (40960 + 855) => x"a5", (40960 + 856) => x"35", (40960 + 857) => x"00",
-- Missile by David Winter
(45056 + 128) => x"0F", (45056 + 129) => x"00",
(45056 + 130) => x"C0", (45056 + 131) => x"00",
(45056 + 132) => x"D0", (45056 + 133) => x"00",
(45056 + 134) => x"BE", (45056 + 135) => x"00",
(45056 + 136) => x"00", (45056 + 137) => x"30", -- delay
(45056 + 138) => x"00",
(45056 + 512) => x"12", (45056 + 513) => x"19", (45056 + 514) => x"4d", (45056 + 515) => x"49", (45056 + 516) => x"53", (45056 + 517) => x"53", (45056 + 518) => x"49", (45056 + 519) => x"4c", (45056 + 520) => x"45", (45056 + 521) => x"20", (45056 + 522) => x"62", (45056 + 523) => x"79", (45056 + 524) => x"20", (45056 + 525) => x"44", (45056 + 526) => x"61", (45056 + 527) => x"76", (45056 + 528) => x"69", (45056 + 529) => x"64", (45056 + 530) => x"20", (45056 + 531) => x"57", (45056 + 532) => x"49", (45056 + 533) => x"4e", (45056 + 534) => x"54", (45056 + 535) => x"45", (45056 + 536) => x"52", (45056 + 537) => x"6c", (45056 + 538) => x"0c", (45056 + 539) => x"60", (45056 + 540) => x"00", (45056 + 541) => x"61", (45056 + 542) => x"00", (45056 + 543) => x"65", (45056 + 544) => x"08", (45056 + 545) => x"66", (45056 + 546) => x"0a", (45056 + 547) => x"67", (45056 + 548) => x"00", (45056 + 549) => x"6e", (45056 + 550) => x"01", (45056 + 551) => x"a2", (45056 + 552) => x"ad", (45056 + 553) => x"d0", (45056 + 554) => x"14", (45056 + 555) => x"70", (45056 + 556) => x"08", (45056 + 557) => x"30", (45056 + 558) => x"40", (45056 + 559) => x"12", (45056 + 560) => x"29", (45056 + 561) => x"60", (45056 + 562) => x"00", (45056 + 563) => x"61", (45056 + 564) => x"1c", (45056 + 565) => x"a2", (45056 + 566) => x"b0", (45056 + 567) => x"d0", (45056 + 568) => x"14", (45056 + 569) => x"a2", (45056 + 570) => x"b0", (45056 + 571) => x"d0", (45056 + 572) => x"14", (45056 + 573) => x"3e", (45056 + 574) => x"01", (45056 + 575) => x"12", (45056 + 576) => x"49", (45056 + 577) => x"70", (45056 + 578) => x"04", (45056 + 579) => x"40", (45056 + 580) => x"38", (45056 + 581) => x"6e", (45056 + 582) => x"00", (45056 + 583) => x"12", (45056 + 584) => x"4f", (45056 + 585) => x"70", (45056 + 586) => x"fc", (45056 + 587) => x"40", (45056 + 588) => x"00", (45056 + 589) => x"6e", (45056 + 590) => x"01", (45056 + 591) => x"d0", (45056 + 592) => x"14", (45056 + 593) => x"fc", (45056 + 594) => x"15", (45056 + 595) => x"fb", (45056 + 596) => x"07", (45056 + 597) => x"3b", (45056 + 598) => x"00", (45056 + 599) => x"12", (45056 + 600) => x"53", (45056 + 601) => x"62", (45056 + 602) => x"08", (45056 + 603) => x"e2", (45056 + 604) => x"9e", (45056 + 605) => x"12", (45056 + 606) => x"95", (45056 + 607) => x"3c", (45056 + 608) => x"00", (45056 + 609) => x"7c", (45056 + 610) => x"fe", (45056 + 611) => x"63", (45056 + 612) => x"1b", (45056 + 613) => x"82", (45056 + 614) => x"00", (45056 + 615) => x"a2", (45056 + 616) => x"b0", (45056 + 617) => x"d2", (45056 + 618) => x"31", (45056 + 619) => x"64", (45056 + 620) => x"00", (45056 + 621) => x"d2", (45056 + 622) => x"31", (45056 + 623) => x"73", (45056 + 624) => x"ff", (45056 + 625) => x"d2", (45056 + 626) => x"31", (45056 + 627) => x"3f", (45056 + 628) => x"00", (45056 + 629) => x"64", (45056 + 630) => x"01", (45056 + 631) => x"33", (45056 + 632) => x"03", (45056 + 633) => x"12", (45056 + 634) => x"6d", (45056 + 635) => x"d2", (45056 + 636) => x"31", (45056 + 637) => x"34", (45056 + 638) => x"01", (45056 + 639) => x"12", (45056 + 640) => x"91", (45056 + 641) => x"77", (45056 + 642) => x"05", (45056 + 643) => x"75", (45056 + 644) => x"ff", (45056 + 645) => x"82", (45056 + 646) => x"00", (45056 + 647) => x"63", (45056 + 648) => x"00", (45056 + 649) => x"a2", (45056 + 650) => x"ad", (45056 + 651) => x"d2", (45056 + 652) => x"34", (45056 + 653) => x"45", (45056 + 654) => x"00", (45056 + 655) => x"12", (45056 + 656) => x"97", (45056 + 657) => x"76", (45056 + 658) => x"ff", (45056 + 659) => x"36", (45056 + 660) => x"00", (45056 + 661) => x"12", (45056 + 662) => x"39", (45056 + 663) => x"a2", (45056 + 664) => x"b4", (45056 + 665) => x"f7", (45056 + 666) => x"33", (45056 + 667) => x"f2", (45056 + 668) => x"65", (45056 + 669) => x"63", (45056 + 670) => x"1b", (45056 + 671) => x"64", (45056 + 672) => x"0d", (45056 + 673) => x"f1", (45056 + 674) => x"29", (45056 + 675) => x"d3", (45056 + 676) => x"45", (45056 + 677) => x"73", (45056 + 678) => x"05", (45056 + 679) => x"f2", (45056 + 680) => x"29", (45056 + 681) => x"d3", (45056 + 682) => x"45", (45056 + 683) => x"12", (45056 + 684) => x"ab", (45056 + 685) => x"10", (45056 + 686) => x"38", (45056 + 687) => x"38", (45056 + 688) => x"10", (45056 + 689) => x"38", (45056 + 690) => x"7c", (45056 + 691) => x"fe",
-- Puzzle by Joseph Weisbecker (RCA)
(49152 + 128) => x"00", (49152 + 129) => x"B0",
(49152 + 130) => x"C0", (49152 + 131) => x"E0",
(49152 + 132) => x"F0", (49152 + 133) => x"00",
(49152 + 134) => x"BE", (49152 + 135) => x"00",
(49152 + 136) => x"00", (49152 + 137) => x"30", -- delay
(49152 + 138) => x"00",
(49152 + 512) => x"6a", (49152 + 513) => x"12", (49152 + 514) => x"6b", (49152 + 515) => x"01", (49152 + 516) => x"61", (49152 + 517) => x"10", (49152 + 518) => x"62", (49152 + 519) => x"00", (49152 + 520) => x"60", (49152 + 521) => x"00", (49152 + 522) => x"a2", (49152 + 523) => x"b0", (49152 + 524) => x"d1", (49152 + 525) => x"27", (49152 + 526) => x"f0", (49152 + 527) => x"29", (49152 + 528) => x"30", (49152 + 529) => x"00", (49152 + 530) => x"da", (49152 + 531) => x"b5", (49152 + 532) => x"71", (49152 + 533) => x"08", (49152 + 534) => x"7a", (49152 + 535) => x"08", (49152 + 536) => x"31", (49152 + 537) => x"30", (49152 + 538) => x"12", (49152 + 539) => x"24", (49152 + 540) => x"61", (49152 + 541) => x"10", (49152 + 542) => x"72", (49152 + 543) => x"08", (49152 + 544) => x"6a", (49152 + 545) => x"12", (49152 + 546) => x"7b", (49152 + 547) => x"08", (49152 + 548) => x"a3", (49152 + 549) => x"00", (49152 + 550) => x"f0", (49152 + 551) => x"1e", (49152 + 552) => x"f0", (49152 + 553) => x"55", (49152 + 554) => x"70", (49152 + 555) => x"01", (49152 + 556) => x"30", (49152 + 557) => x"10", (49152 + 558) => x"12", (49152 + 559) => x"0a", (49152 + 560) => x"6a", (49152 + 561) => x"12", (49152 + 562) => x"6b", (49152 + 563) => x"01", (49152 + 564) => x"6c", (49152 + 565) => x"00", (49152 + 566) => x"62", (49152 + 567) => x"ff", (49152 + 568) => x"c0", (49152 + 569) => x"06", (49152 + 570) => x"70", (49152 + 571) => x"02", (49152 + 572) => x"22", (49152 + 573) => x"52", (49152 + 574) => x"72", (49152 + 575) => x"ff", (49152 + 576) => x"32", (49152 + 577) => x"00", (49152 + 578) => x"12", (49152 + 579) => x"38", (49152 + 580) => x"6e", (49152 + 581) => x"00", (49152 + 582) => x"6e", (49152 + 583) => x"00", (49152 + 584) => x"f0", (49152 + 585) => x"0a", (49152 + 586) => x"22", (49152 + 587) => x"52", (49152 + 588) => x"7e", (49152 + 589) => x"01", (49152 + 590) => x"7e", (49152 + 591) => x"01", (49152 + 592) => x"12", (49152 + 593) => x"48", (49152 + 594) => x"84", (49152 + 595) => x"a0", (49152 + 596) => x"85", (49152 + 597) => x"b0", (49152 + 598) => x"86", (49152 + 599) => x"c0", (49152 + 600) => x"30", (49152 + 601) => x"02", (49152 + 602) => x"12", (49152 + 603) => x"64", (49152 + 604) => x"45", (49152 + 605) => x"01", (49152 + 606) => x"12", (49152 + 607) => x"64", (49152 + 608) => x"75", (49152 + 609) => x"f8", (49152 + 610) => x"76", (49152 + 611) => x"fc", (49152 + 612) => x"30", (49152 + 613) => x"08", (49152 + 614) => x"12", (49152 + 615) => x"70", (49152 + 616) => x"45", (49152 + 617) => x"19", (49152 + 618) => x"12", (49152 + 619) => x"70", (49152 + 620) => x"75", (49152 + 621) => x"08", (49152 + 622) => x"76", (49152 + 623) => x"04", (49152 + 624) => x"30", (49152 + 625) => x"06", (49152 + 626) => x"12", (49152 + 627) => x"7c", (49152 + 628) => x"44", (49152 + 629) => x"12", (49152 + 630) => x"12", (49152 + 631) => x"7c", (49152 + 632) => x"74", (49152 + 633) => x"f8", (49152 + 634) => x"76", (49152 + 635) => x"ff", (49152 + 636) => x"30", (49152 + 637) => x"04", (49152 + 638) => x"12", (49152 + 639) => x"88", (49152 + 640) => x"44", (49152 + 641) => x"2a", (49152 + 642) => x"12", (49152 + 643) => x"88", (49152 + 644) => x"74", (49152 + 645) => x"08", (49152 + 646) => x"76", (49152 + 647) => x"01", (49152 + 648) => x"a3", (49152 + 649) => x"00", (49152 + 650) => x"f6", (49152 + 651) => x"1e", (49152 + 652) => x"f0", (49152 + 653) => x"65", (49152 + 654) => x"81", (49152 + 655) => x"00", (49152 + 656) => x"60", (49152 + 657) => x"00", (49152 + 658) => x"a3", (49152 + 659) => x"00", (49152 + 660) => x"f6", (49152 + 661) => x"1e", (49152 + 662) => x"f0", (49152 + 663) => x"55", (49152 + 664) => x"a3", (49152 + 665) => x"00", (49152 + 666) => x"fc", (49152 + 667) => x"1e", (49152 + 668) => x"80", (49152 + 669) => x"10", (49152 + 670) => x"f0", (49152 + 671) => x"55", (49152 + 672) => x"f1", (49152 + 673) => x"29", (49152 + 674) => x"d4", (49152 + 675) => x"55", (49152 + 676) => x"da", (49152 + 677) => x"b5", (49152 + 678) => x"8a", (49152 + 679) => x"40", (49152 + 680) => x"8b", (49152 + 681) => x"50", (49152 + 682) => x"8c", (49152 + 683) => x"60", (49152 + 684) => x"00", (49152 + 685) => x"ee", (49152 + 686) => x"ee", (49152 + 687) => x"5e", (49152 + 688) => x"fe", (49152 + 689) => x"fe", (49152 + 690) => x"fe", (49152 + 691) => x"fe", (49152 + 692) => x"fe", (49152 + 693) => x"fe", (49152 + 694) => x"fe", (49152 + 695) => x"fe",
-- Tank by Joseph Weisbecker (RCA)
(53248 + 128) => x"00", (53248 + 129) => x"B0",
(53248 + 130) => x"CD", (53248 + 131) => x"E0",
(53248 + 132) => x"F0", (53248 + 133) => x"00",
(53248 + 134) => x"BE", (53248 + 135) => x"00",
(53248 + 136) => x"00", (53248 + 137) => x"30", -- delay
(53248 + 138) => x"00",
(53248 + 512) => x"12", (53248 + 513) => x"30", (53248 + 514) => x"76", (53248 + 515) => x"fb", (53248 + 516) => x"60", (53248 + 517) => x"20", (53248 + 518) => x"80", (53248 + 519) => x"65", (53248 + 520) => x"4f", (53248 + 521) => x"00", (53248 + 522) => x"66", (53248 + 523) => x"00", (53248 + 524) => x"13", (53248 + 525) => x"84", (53248 + 526) => x"00", (53248 + 527) => x"ff", (53248 + 528) => x"00", (53248 + 529) => x"00", (53248 + 530) => x"00", (53248 + 531) => x"01", (53248 + 532) => x"00", (53248 + 533) => x"0c", (53248 + 534) => x"0a", (53248 + 535) => x"00", (53248 + 536) => x"19", (53248 + 537) => x"02", (53248 + 538) => x"04", (53248 + 539) => x"06", (53248 + 540) => x"08", (53248 + 541) => x"02", (53248 + 542) => x"02", (53248 + 543) => x"03", (53248 + 544) => x"2c", (53248 + 545) => x"00", (53248 + 546) => x"0f", (53248 + 547) => x"00", (53248 + 548) => x"02", (53248 + 549) => x"05", (53248 + 550) => x"2e", (53248 + 551) => x"08", (53248 + 552) => x"00", (53248 + 553) => x"00", (53248 + 554) => x"02", (53248 + 555) => x"05", (53248 + 556) => x"00", (53248 + 557) => x"00", (53248 + 558) => x"00", (53248 + 559) => x"00", (53248 + 560) => x"6e", (53248 + 561) => x"00", (53248 + 562) => x"6d", (53248 + 563) => x"a0", (53248 + 564) => x"6a", (53248 + 565) => x"08", (53248 + 566) => x"69", (53248 + 567) => x"06", (53248 + 568) => x"68", (53248 + 569) => x"04", (53248 + 570) => x"67", (53248 + 571) => x"02", (53248 + 572) => x"66", (53248 + 573) => x"19", (53248 + 574) => x"64", (53248 + 575) => x"10", (53248 + 576) => x"63", (53248 + 577) => x"0c", (53248 + 578) => x"62", (53248 + 579) => x"00", (53248 + 580) => x"61", (53248 + 581) => x"06", (53248 + 582) => x"a2", (53248 + 583) => x"12", (53248 + 584) => x"fa", (53248 + 585) => x"55", (53248 + 586) => x"23", (53248 + 587) => x"d4", (53248 + 588) => x"60", (53248 + 589) => x"40", (53248 + 590) => x"f0", (53248 + 591) => x"15", (53248 + 592) => x"f0", (53248 + 593) => x"07", (53248 + 594) => x"30", (53248 + 595) => x"00", (53248 + 596) => x"12", (53248 + 597) => x"50", (53248 + 598) => x"23", (53248 + 599) => x"d4", (53248 + 600) => x"23", (53248 + 601) => x"0a", (53248 + 602) => x"23", (53248 + 603) => x"62", (53248 + 604) => x"a2", (53248 + 605) => x"12", (53248 + 606) => x"f5", (53248 + 607) => x"65", (53248 + 608) => x"22", (53248 + 609) => x"ae", (53248 + 610) => x"22", (53248 + 611) => x"c6", (53248 + 612) => x"22", (53248 + 613) => x"ec", (53248 + 614) => x"3f", (53248 + 615) => x"01", (53248 + 616) => x"23", (53248 + 617) => x"14", (53248 + 618) => x"3f", (53248 + 619) => x"01", (53248 + 620) => x"22", (53248 + 621) => x"ec", (53248 + 622) => x"3f", (53248 + 623) => x"01", (53248 + 624) => x"22", (53248 + 625) => x"ec", (53248 + 626) => x"3f", (53248 + 627) => x"01", (53248 + 628) => x"22", (53248 + 629) => x"7c", (53248 + 630) => x"4f", (53248 + 631) => x"01", (53248 + 632) => x"13", (53248 + 633) => x"66", (53248 + 634) => x"12", (53248 + 635) => x"62", (53248 + 636) => x"a2", (53248 + 637) => x"12", (53248 + 638) => x"f5", (53248 + 639) => x"65", (53248 + 640) => x"46", (53248 + 641) => x"00", (53248 + 642) => x"35", (53248 + 643) => x"00", (53248 + 644) => x"12", (53248 + 645) => x"88", (53248 + 646) => x"13", (53248 + 647) => x"8c", (53248 + 648) => x"e7", (53248 + 649) => x"a1", (53248 + 650) => x"62", (53248 + 651) => x"09", (53248 + 652) => x"e8", (53248 + 653) => x"a1", (53248 + 654) => x"62", (53248 + 655) => x"04", (53248 + 656) => x"e9", (53248 + 657) => x"a1", (53248 + 658) => x"62", (53248 + 659) => x"06", (53248 + 660) => x"ea", (53248 + 661) => x"a1", (53248 + 662) => x"62", (53248 + 663) => x"01", (53248 + 664) => x"42", (53248 + 665) => x"00", (53248 + 666) => x"00", (53248 + 667) => x"ee", (53248 + 668) => x"22", (53248 + 669) => x"ae", (53248 + 670) => x"81", (53248 + 671) => x"20", (53248 + 672) => x"23", (53248 + 673) => x"9a", (53248 + 674) => x"23", (53248 + 675) => x"ac", (53248 + 676) => x"6c", (53248 + 677) => x"01", (53248 + 678) => x"62", (53248 + 679) => x"00", (53248 + 680) => x"6f", (53248 + 681) => x"00", (53248 + 682) => x"a2", (53248 + 683) => x"12", (53248 + 684) => x"f5", (53248 + 685) => x"55", (53248 + 686) => x"a3", (53248 + 687) => x"ff", (53248 + 688) => x"41", (53248 + 689) => x"01", (53248 + 690) => x"60", (53248 + 691) => x"00", (53248 + 692) => x"41", (53248 + 693) => x"04", (53248 + 694) => x"60", (53248 + 695) => x"13", (53248 + 696) => x"41", (53248 + 697) => x"06", (53248 + 698) => x"60", (53248 + 699) => x"0d", (53248 + 700) => x"41", (53248 + 701) => x"09", (53248 + 702) => x"60", (53248 + 703) => x"06", (53248 + 704) => x"f0", (53248 + 705) => x"1e", (53248 + 706) => x"d3", (53248 + 707) => x"47", (53248 + 708) => x"00", (53248 + 709) => x"ee", (53248 + 710) => x"60", (53248 + 711) => x"05", (53248 + 712) => x"e0", (53248 + 713) => x"9e", (53248 + 714) => x"00", (53248 + 715) => x"ee", (53248 + 716) => x"45", (53248 + 717) => x"0f", (53248 + 718) => x"00", (53248 + 719) => x"ee", (53248 + 720) => x"65", (53248 + 721) => x"0f", (53248 + 722) => x"76", (53248 + 723) => x"ff", (53248 + 724) => x"a2", (53248 + 725) => x"12", (53248 + 726) => x"f5", (53248 + 727) => x"55", (53248 + 728) => x"74", (53248 + 729) => x"03", (53248 + 730) => x"73", (53248 + 731) => x"03", (53248 + 732) => x"23", (53248 + 733) => x"9a", (53248 + 734) => x"23", (53248 + 735) => x"9a", (53248 + 736) => x"23", (53248 + 737) => x"9a", (53248 + 738) => x"a2", (53248 + 739) => x"23", (53248 + 740) => x"f5", (53248 + 741) => x"55", (53248 + 742) => x"a4", (53248 + 743) => x"19", (53248 + 744) => x"d3", (53248 + 745) => x"41", (53248 + 746) => x"00", (53248 + 747) => x"ee", (53248 + 748) => x"a2", (53248 + 749) => x"23", (53248 + 750) => x"f5", (53248 + 751) => x"65", (53248 + 752) => x"45", (53248 + 753) => x"00", (53248 + 754) => x"00", (53248 + 755) => x"ee", (53248 + 756) => x"a4", (53248 + 757) => x"19", (53248 + 758) => x"d3", (53248 + 759) => x"41", (53248 + 760) => x"23", (53248 + 761) => x"9a", (53248 + 762) => x"6c", (53248 + 763) => x"02", (53248 + 764) => x"23", (53248 + 765) => x"be", (53248 + 766) => x"4b", (53248 + 767) => x"bb", (53248 + 768) => x"13", (53248 + 769) => x"0a", (53248 + 770) => x"d3", (53248 + 771) => x"41", (53248 + 772) => x"a2", (53248 + 773) => x"23", (53248 + 774) => x"f5", (53248 + 775) => x"55", (53248 + 776) => x"00", (53248 + 777) => x"ee", (53248 + 778) => x"65", (53248 + 779) => x"00", (53248 + 780) => x"60", (53248 + 781) => x"00", (53248 + 782) => x"a2", (53248 + 783) => x"17", (53248 + 784) => x"f0", (53248 + 785) => x"55", (53248 + 786) => x"13", (53248 + 787) => x"04", (53248 + 788) => x"a2", (53248 + 789) => x"1d", (53248 + 790) => x"f5", (53248 + 791) => x"65", (53248 + 792) => x"35", (53248 + 793) => x"0f", (53248 + 794) => x"13", (53248 + 795) => x"44", (53248 + 796) => x"a4", (53248 + 797) => x"1a", (53248 + 798) => x"d3", (53248 + 799) => x"45", (53248 + 800) => x"32", (53248 + 801) => x"00", (53248 + 802) => x"13", (53248 + 803) => x"32", (53248 + 804) => x"c1", (53248 + 805) => x"03", (53248 + 806) => x"a2", (53248 + 807) => x"19", (53248 + 808) => x"f1", (53248 + 809) => x"1e", (53248 + 810) => x"f0", (53248 + 811) => x"65", (53248 + 812) => x"81", (53248 + 813) => x"00", (53248 + 814) => x"c2", (53248 + 815) => x"0f", (53248 + 816) => x"72", (53248 + 817) => x"01", (53248 + 818) => x"23", (53248 + 819) => x"9a", (53248 + 820) => x"a4", (53248 + 821) => x"1a", (53248 + 822) => x"6c", (53248 + 823) => x"03", (53248 + 824) => x"72", (53248 + 825) => x"ff", (53248 + 826) => x"6f", (53248 + 827) => x"00", (53248 + 828) => x"d3", (53248 + 829) => x"45", (53248 + 830) => x"a2", (53248 + 831) => x"1d", (53248 + 832) => x"f5", (53248 + 833) => x"55", (53248 + 834) => x"00", (53248 + 835) => x"ee", (53248 + 836) => x"c4", (53248 + 837) => x"07", (53248 + 838) => x"a4", (53248 + 839) => x"1f", (53248 + 840) => x"f4", (53248 + 841) => x"1e", (53248 + 842) => x"f0", (53248 + 843) => x"65", (53248 + 844) => x"83", (53248 + 845) => x"00", (53248 + 846) => x"a4", (53248 + 847) => x"27", (53248 + 848) => x"f4", (53248 + 849) => x"1e", (53248 + 850) => x"f0", (53248 + 851) => x"65", (53248 + 852) => x"84", (53248 + 853) => x"00", (53248 + 854) => x"a4", (53248 + 855) => x"1a", (53248 + 856) => x"d3", (53248 + 857) => x"45", (53248 + 858) => x"60", (53248 + 859) => x"20", (53248 + 860) => x"f0", (53248 + 861) => x"18", (53248 + 862) => x"65", (53248 + 863) => x"0f", (53248 + 864) => x"13", (53248 + 865) => x"3e", (53248 + 866) => x"65", (53248 + 867) => x"00", (53248 + 868) => x"13", (53248 + 869) => x"3e", (53248 + 870) => x"4c", (53248 + 871) => x"01", (53248 + 872) => x"12", (53248 + 873) => x"02", (53248 + 874) => x"4c", (53248 + 875) => x"02", (53248 + 876) => x"13", (53248 + 877) => x"82", (53248 + 878) => x"a2", (53248 + 879) => x"23", (53248 + 880) => x"f5", (53248 + 881) => x"65", (53248 + 882) => x"45", (53248 + 883) => x"00", (53248 + 884) => x"12", (53248 + 885) => x"02", (53248 + 886) => x"a4", (53248 + 887) => x"19", (53248 + 888) => x"d3", (53248 + 889) => x"41", (53248 + 890) => x"6f", (53248 + 891) => x"00", (53248 + 892) => x"d3", (53248 + 893) => x"41", (53248 + 894) => x"3f", (53248 + 895) => x"01", (53248 + 896) => x"12", (53248 + 897) => x"02", (53248 + 898) => x"7e", (53248 + 899) => x"0a", (53248 + 900) => x"60", (53248 + 901) => x"40", (53248 + 902) => x"f0", (53248 + 903) => x"18", (53248 + 904) => x"00", (53248 + 905) => x"e0", (53248 + 906) => x"12", (53248 + 907) => x"4a", (53248 + 908) => x"00", (53248 + 909) => x"e0", (53248 + 910) => x"23", (53248 + 911) => x"d4", (53248 + 912) => x"60", (53248 + 913) => x"60", (53248 + 914) => x"f0", (53248 + 915) => x"18", (53248 + 916) => x"13", (53248 + 917) => x"94", (53248 + 918) => x"6e", (53248 + 919) => x"00", (53248 + 920) => x"13", (53248 + 921) => x"84", (53248 + 922) => x"41", (53248 + 923) => x"01", (53248 + 924) => x"74", (53248 + 925) => x"ff", (53248 + 926) => x"41", (53248 + 927) => x"04", (53248 + 928) => x"73", (53248 + 929) => x"ff", (53248 + 930) => x"41", (53248 + 931) => x"06", (53248 + 932) => x"73", (53248 + 933) => x"01", (53248 + 934) => x"41", (53248 + 935) => x"09", (53248 + 936) => x"74", (53248 + 937) => x"01", (53248 + 938) => x"00", (53248 + 939) => x"ee", (53248 + 940) => x"44", (53248 + 941) => x"00", (53248 + 942) => x"74", (53248 + 943) => x"01", (53248 + 944) => x"43", (53248 + 945) => x"00", (53248 + 946) => x"73", (53248 + 947) => x"01", (53248 + 948) => x"43", (53248 + 949) => x"38", (53248 + 950) => x"73", (53248 + 951) => x"ff", (53248 + 952) => x"44", (53248 + 953) => x"18", (53248 + 954) => x"74", (53248 + 955) => x"ff", (53248 + 956) => x"00", (53248 + 957) => x"ee", (53248 + 958) => x"6b", (53248 + 959) => x"00", (53248 + 960) => x"44", (53248 + 961) => x"00", (53248 + 962) => x"13", (53248 + 963) => x"ce", (53248 + 964) => x"43", (53248 + 965) => x"00", (53248 + 966) => x"13", (53248 + 967) => x"ce", (53248 + 968) => x"43", (53248 + 969) => x"3f", (53248 + 970) => x"13", (53248 + 971) => x"ce", (53248 + 972) => x"44", (53248 + 973) => x"1f", (53248 + 974) => x"6b", (53248 + 975) => x"bb", (53248 + 976) => x"6f", (53248 + 977) => x"00", (53248 + 978) => x"00", (53248 + 979) => x"ee", (53248 + 980) => x"63", (53248 + 981) => x"08", (53248 + 982) => x"64", (53248 + 983) => x"08", (53248 + 984) => x"a2", (53248 + 985) => x"29", (53248 + 986) => x"fe", (53248 + 987) => x"33", (53248 + 988) => x"f2", (53248 + 989) => x"65", (53248 + 990) => x"23", (53248 + 991) => x"ec", (53248 + 992) => x"63", (53248 + 993) => x"28", (53248 + 994) => x"a2", (53248 + 995) => x"29", (53248 + 996) => x"f6", (53248 + 997) => x"33", (53248 + 998) => x"f2", (53248 + 999) => x"65", (53248 + 1000) => x"23", (53248 + 1001) => x"f2", (53248 + 1002) => x"00", (53248 + 1003) => x"ee", (53248 + 1004) => x"f0", (53248 + 1005) => x"29", (53248 + 1006) => x"d3", (53248 + 1007) => x"45", (53248 + 1008) => x"73", (53248 + 1009) => x"06", (53248 + 1010) => x"f1", (53248 + 1011) => x"29", (53248 + 1012) => x"d3", (53248 + 1013) => x"45", (53248 + 1014) => x"73", (53248 + 1015) => x"06", (53248 + 1016) => x"f2", (53248 + 1017) => x"29", (53248 + 1018) => x"d3", (53248 + 1019) => x"45", (53248 + 1020) => x"00", (53248 + 1021) => x"ee", (53248 + 1022) => x"01", (53248 + 1023) => x"10", (53248 + 1024) => x"54", (53248 + 1025) => x"7c", (53248 + 1026) => x"6c", (53248 + 1027) => x"7c", (53248 + 1028) => x"7c", (53248 + 1029) => x"44", (53248 + 1030) => x"7c", (53248 + 1031) => x"7c", (53248 + 1032) => x"6c", (53248 + 1033) => x"7c", (53248 + 1034) => x"54", (53248 + 1035) => x"10", (53248 + 1036) => x"00", (53248 + 1037) => x"fc", (53248 + 1038) => x"78", (53248 + 1039) => x"6e", (53248 + 1040) => x"78", (53248 + 1041) => x"fc", (53248 + 1042) => x"00", (53248 + 1043) => x"3f", (53248 + 1044) => x"1e", (53248 + 1045) => x"76", (53248 + 1046) => x"1e", (53248 + 1047) => x"3f", (53248 + 1048) => x"00", (53248 + 1049) => x"80", (53248 + 1050) => x"a8", (53248 + 1051) => x"70", (53248 + 1052) => x"f8", (53248 + 1053) => x"70", (53248 + 1054) => x"a8", (53248 + 1055) => x"0b", (53248 + 1056) => x"1b", (53248 + 1057) => x"28", (53248 + 1058) => x"38", (53248 + 1059) => x"30", (53248 + 1060) => x"20", (53248 + 1061) => x"10", (53248 + 1062) => x"00", (53248 + 1063) => x"00", (53248 + 1064) => x"00", (53248 + 1065) => x"00", (53248 + 1066) => x"08", (53248 + 1067) => x"1b", (53248 + 1068) => x"1b", (53248 + 1069) => x"1b", (53248 + 1070) => x"18", (53248 + 1071) => x"04",
-- Vers by JMN
(57344 + 128) => x"03", (57344 + 129) => x"00",
(57344 + 130) => x"00", (57344 + 131) => x"02",
(57344 + 132) => x"00", (57344 + 133) => x"1C",
(57344 + 134) => x"BF", (57344 + 135) => x"0E",
(57344 + 136) => x"00", (57344 + 137) => x"30", -- delay
(57344 + 138) => x"00",
(57344 + 512) => x"12", (57344 + 513) => x"1a", (57344 + 514) => x"4a", (57344 + 515) => x"4d", (57344 + 516) => x"4e", (57344 + 517) => x"20", (57344 + 518) => x"31", (57344 + 519) => x"39", (57344 + 520) => x"39", (57344 + 521) => x"31", (57344 + 522) => x"20", (57344 + 523) => x"53", (57344 + 524) => x"4f", (57344 + 525) => x"46", (57344 + 526) => x"54", (57344 + 527) => x"57", (57344 + 528) => x"41", (57344 + 529) => x"52", (57344 + 530) => x"45", (57344 + 531) => x"53", (57344 + 532) => x"20", (57344 + 533) => x"80", (57344 + 534) => x"80", (57344 + 535) => x"ff", (57344 + 536) => x"00", (57344 + 537) => x"00", (57344 + 538) => x"63", (57344 + 539) => x"00", (57344 + 540) => x"67", (57344 + 541) => x"00", (57344 + 542) => x"00", (57344 + 543) => x"e0", (57344 + 544) => x"a2", (57344 + 545) => x"17", (57344 + 546) => x"60", (57344 + 547) => x"00", (57344 + 548) => x"61", (57344 + 549) => x"00", (57344 + 550) => x"d0", (57344 + 551) => x"11", (57344 + 552) => x"71", (57344 + 553) => x"ff", (57344 + 554) => x"d0", (57344 + 555) => x"11", (57344 + 556) => x"71", (57344 + 557) => x"01", (57344 + 558) => x"70", (57344 + 559) => x"08", (57344 + 560) => x"30", (57344 + 561) => x"40", (57344 + 562) => x"12", (57344 + 563) => x"26", (57344 + 564) => x"71", (57344 + 565) => x"01", (57344 + 566) => x"a2", (57344 + 567) => x"15", (57344 + 568) => x"d0", (57344 + 569) => x"12", (57344 + 570) => x"70", (57344 + 571) => x"ff", (57344 + 572) => x"d0", (57344 + 573) => x"12", (57344 + 574) => x"70", (57344 + 575) => x"01", (57344 + 576) => x"71", (57344 + 577) => x"02", (57344 + 578) => x"31", (57344 + 579) => x"1f", (57344 + 580) => x"12", (57344 + 581) => x"38", (57344 + 582) => x"60", (57344 + 583) => x"08", (57344 + 584) => x"61", (57344 + 585) => x"10", (57344 + 586) => x"62", (57344 + 587) => x"04", (57344 + 588) => x"64", (57344 + 589) => x"37", (57344 + 590) => x"65", (57344 + 591) => x"0f", (57344 + 592) => x"66", (57344 + 593) => x"02", (57344 + 594) => x"d0", (57344 + 595) => x"11", (57344 + 596) => x"d4", (57344 + 597) => x"51", (57344 + 598) => x"68", (57344 + 599) => x"01", (57344 + 600) => x"e8", (57344 + 601) => x"a1", (57344 + 602) => x"62", (57344 + 603) => x"02", (57344 + 604) => x"68", (57344 + 605) => x"02", (57344 + 606) => x"e8", (57344 + 607) => x"a1", (57344 + 608) => x"62", (57344 + 609) => x"04", (57344 + 610) => x"68", (57344 + 611) => x"07", (57344 + 612) => x"e8", (57344 + 613) => x"a1", (57344 + 614) => x"62", (57344 + 615) => x"01", (57344 + 616) => x"68", (57344 + 617) => x"0a", (57344 + 618) => x"e8", (57344 + 619) => x"a1", (57344 + 620) => x"62", (57344 + 621) => x"03", (57344 + 622) => x"68", (57344 + 623) => x"0b", (57344 + 624) => x"e8", (57344 + 625) => x"a1", (57344 + 626) => x"66", (57344 + 627) => x"02", (57344 + 628) => x"68", (57344 + 629) => x"0f", (57344 + 630) => x"e8", (57344 + 631) => x"a1", (57344 + 632) => x"66", (57344 + 633) => x"04", (57344 + 634) => x"68", (57344 + 635) => x"0c", (57344 + 636) => x"e8", (57344 + 637) => x"a1", (57344 + 638) => x"66", (57344 + 639) => x"01", (57344 + 640) => x"68", (57344 + 641) => x"0d", (57344 + 642) => x"e8", (57344 + 643) => x"a1", (57344 + 644) => x"66", (57344 + 645) => x"03", (57344 + 646) => x"42", (57344 + 647) => x"01", (57344 + 648) => x"71", (57344 + 649) => x"ff", (57344 + 650) => x"42", (57344 + 651) => x"02", (57344 + 652) => x"70", (57344 + 653) => x"ff", (57344 + 654) => x"42", (57344 + 655) => x"03", (57344 + 656) => x"71", (57344 + 657) => x"01", (57344 + 658) => x"42", (57344 + 659) => x"04", (57344 + 660) => x"70", (57344 + 661) => x"01", (57344 + 662) => x"46", (57344 + 663) => x"01", (57344 + 664) => x"75", (57344 + 665) => x"ff", (57344 + 666) => x"46", (57344 + 667) => x"02", (57344 + 668) => x"74", (57344 + 669) => x"ff", (57344 + 670) => x"46", (57344 + 671) => x"03", (57344 + 672) => x"75", (57344 + 673) => x"01", (57344 + 674) => x"46", (57344 + 675) => x"04", (57344 + 676) => x"74", (57344 + 677) => x"01", (57344 + 678) => x"d0", (57344 + 679) => x"11", (57344 + 680) => x"3f", (57344 + 681) => x"00", (57344 + 682) => x"12", (57344 + 683) => x"b4", (57344 + 684) => x"d4", (57344 + 685) => x"51", (57344 + 686) => x"3f", (57344 + 687) => x"00", (57344 + 688) => x"12", (57344 + 689) => x"b8", (57344 + 690) => x"12", (57344 + 691) => x"56", (57344 + 692) => x"77", (57344 + 693) => x"01", (57344 + 694) => x"12", (57344 + 695) => x"ba", (57344 + 696) => x"73", (57344 + 697) => x"01", (57344 + 698) => x"68", (57344 + 699) => x"00", (57344 + 700) => x"78", (57344 + 701) => x"01", (57344 + 702) => x"38", (57344 + 703) => x"00", (57344 + 704) => x"12", (57344 + 705) => x"bc", (57344 + 706) => x"00", (57344 + 707) => x"e0", (57344 + 708) => x"60", (57344 + 709) => x"08", (57344 + 710) => x"61", (57344 + 711) => x"04", (57344 + 712) => x"f3", (57344 + 713) => x"29", (57344 + 714) => x"d0", (57344 + 715) => x"15", (57344 + 716) => x"60", (57344 + 717) => x"34", (57344 + 718) => x"f7", (57344 + 719) => x"29", (57344 + 720) => x"d0", (57344 + 721) => x"15", (57344 + 722) => x"68", (57344 + 723) => x"00", (57344 + 724) => x"78", (57344 + 725) => x"01", (57344 + 726) => x"38", (57344 + 727) => x"00", (57344 + 728) => x"12", (57344 + 729) => x"d4", (57344 + 730) => x"43", (57344 + 731) => x"08", (57344 + 732) => x"12", (57344 + 733) => x"e4", (57344 + 734) => x"47", (57344 + 735) => x"08", (57344 + 736) => x"12", (57344 + 737) => x"e4", (57344 + 738) => x"12", (57344 + 739) => x"1e", (57344 + 740) => x"12", (57344 + 741) => x"e4",
others => ( others => '0')
);
signal read_address : std_logic_vector( 15 downto 0 );
begin
process ( clock )
begin
if ( rising_edge( clock ) ) then
if( we = '1' ) then
sys_RAM( to_integer( unsigned( address ))) <= dataIn;
end if;
read_address <= address;
end if;
end process;
dataOut <= sys_RAM( to_integer( unsigned( read_address )));
end Behavioral;
| mit | 0f2dd8a58f1d415c38d11f8c3578d8d2 | 0.444876 | 2.267814 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml605/svga2ch7301c.vhd | 1 | 7,595 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk100 : in std_ulogic;
clk125 : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
clkvga : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, vgaclk, clk40, clk65, clk50, clk25 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
signal clkval40 : std_logic_vector(1 downto 0);
signal clkval65 : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
clkvga <= vgaclk;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25 when clksel = "00" else clk40 when clksel = "01"
else clk50 when clksel = "10" else clk65;
-- Generate clocks
clkdiv : process(clk100, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk100) then
clkval <= clkval + 1;
end if;
end process;
clkdiv65 : process(clk125, rstn)
begin
if rstn = '0' then clkval65 <= "00"; clkval40 <= "00";
elsif rising_edge(clk125) then
clkval65 <= clkval65 + 1;
if clkval40 = "10" then clkval40 <= "00";
else clkval40 <= clkval40 + 1; end if;
end if;
end process;
clk25 <= clkval(1);
clk50 <= clkval(0);
clk40 <= clkval40(1);
clk65 <= clkval65(0);
end rtl;
| gpl-2.0 | 0ba6d520ef141fba551551f0e4a3d345 | 0.560105 | 3.630497 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/ahbdpram.vhd | 1 | 5,264 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahdpbram
-- File: ahbdpram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB DP ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbdpram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end;
architecture rtl of ahbdpram is
--constant abits : integer := log2(kbytes) + 8;
constant kbytes : integer := 2**(abits - 8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDPRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal bwrite : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
signal hwdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
bwrite <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ahbdrivedata(ramdata);
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
hwdata <= ahbreadword(ahbsi.hwdata, r.addr(4 downto 2));
bw : if bytewrite = 1 generate
ra : for i in 0 to 3 generate
aram : syncram_dp generic map (tech, abits, 8) port map (
clk, ramaddr, hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, bwrite(3-i),
clkdp, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable, write(3-i)
);
end generate;
end generate;
nobw : if bytewrite = 0 generate
aram : syncram_dp generic map (tech, abits, 32) port map (
clk, ramaddr, hwdata(31 downto 0), ramdata, ramsel, r.hwrite,
clkdp, address, datain, dataout, enable, write(0)
);
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdpram" & tost(hindex) &
": AHB DP SRAM Module, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 | 658f7e6047dd1c34e9377c4e1ee20b14 | 0.605813 | 3.372197 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/ddrram.vhd | 1 | 20,380 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrram
-- File: ddrram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR SDRAM (JESD79E)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddrram is
generic (
width: integer := 32;
abits: integer range 12 to 14 := 12;
colbits: integer range 8 to 13 := 8;
rowbits: integer range 1 to 14 := 12;
implbanks: integer range 1 to 4 := 1;
fname: string;
lddelay: time := (0 ns);
speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A
density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip
igndqs: integer range 0 to 1 := 0
);
port (
ck: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of ddrram is
type moderegs is record
-- Mode register (0)
opmode: std_logic_vector(6 downto 0);
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register (1)
opmode1: std_logic_vector(10 downto 0);
res1: std_ulogic;
ds: std_ulogic;
dlldis: std_ulogic;
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal hcmode: boolean := false; -- Shift DQS/read data one cycle for CL=1.5/2.5
signal hcread_en: boolean := false; -- One cycle earlier for half-cycle mode read preamble gen
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
type timetab is array (0 to 5) of time;
constant tRAS : timetab := (50 ns, 45 ns, 42 ns, 40 ns, 40 ns, 40 ns);
constant tRP : timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRCD: timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRRD: timetab := (15 ns, 15 ns, 12 ns, 10 ns, 10 ns, 10 ns);
constant tRFC_lt1G: timetab := (80 ns, 75 ns, 72 ns, 70 ns, 70 ns, 70 ns); --Assuming<1Gb
constant tRFC_mt1G: time := 120 ns;
function tRFC return time is
begin
if density < 3 then return tRFC_lt1G(speedbin);
else return tRFC_mt1G; end if;
end tRFC;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr : integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
a10,a8,a0: std_ulogic) is
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba) and (a10='-' or a10=a(10)) and (a8='-' or a8=a(8)) and
(a0='-' or a0=a(0))
report "Wrong command during init sequence" severity warning;
end checkcmd;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
-- EMRS enable DLL
checkcmd('0','0','0',"01",'-','-','0');
-- MRS reset DLL
checkcmd('0','0','0',"00",'-','1','-');
cyctr := 0;
-- 200 cycle NOP
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
assert cyctr >= 200
report "Command issued too quickly after DLL reset" severity warning;
-- 2 x auto refresh
checkcmd('0','0','1',"--",'-','-','-');
checkcmd('0','0','1',"--",'-','-','-');
-- MRS !reset DLL
checkcmd('0','0','0',"00",'-','0','-');
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs := ((others => '0'), "UUU", 'U', "UUU", (others => '0'), '0', '0', '0');
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
autopch: integer;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(3 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, -1));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Main command handler
cmd := rasn & casn & wen;
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC, true, "tRFC");
end if;
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 3 loop
checktime(now-banks(x).opentime, tRRD(speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime, tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
-- Xilinx V4 MIG controller issues multiple overlapping load commands
-- during calibration, therefore this assertion is bypassed before
-- load-delay has passed.
assert (not accpipe(x).r and not accpipe(x).w) or (now < lddelay);
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "001" => blen := 2;
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := blen/2;
else
banks(bank).autopch := 1+blen/2 + (tWR-deltat+(re-prev_re))/(re-prev_re);
end if;
end if;
when "110" => -- Burst terminate
assert not accpipe(3).w
report "Burst terminate on write burst!" severity warning;
assert banks(accpipe(3).bank).autopch<0
report "Burst terminate on read with auto-precharge!" severity warning;
assert accpipe(3).r
report "Burst terminate with no effect!" severity warning;
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
when "010" => -- Precharge
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
for x in 0 to 3 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,2)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged" severity note;
assert a(10)='1' or banks(x).openrow>=0
report "Precharging single bank that is in idle state" severity note;
banks(x).autopch := 0; -- Handled below
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 3 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 3 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
case ba is
when "00" =>
vmr.opmode(a'high-7 downto 0) := a(a'high downto 7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when "01" =>
vmr.opmode1(a'high-3 downto 0) := a(a'high downto 3);
vmr.res1 := a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge
for x in 0 to 3 loop
if banks(x).autopch=0 then
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now then
load_srec;
loaded := true;
end if;
case vmr.caslat is
when "010" => i := 2; b:=false; -- CL2
when "011" => i := 3; b:=false; -- CL3
when "101" => i := 2; b:=true; -- CL1.5
when "110" => i := 3; b:=true; -- CL2.5
when others => i := 1;
end case;
hcmode <= b;
if b then hcread_en <= accpipe(1+i).r; else hcread_en <= false; end if;
if accpipe(2+i).r then
assert i>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+i).col(0)) & memdata(accpipe(2+i).col(1));
else
read_en <= false;
end if;
write_en <= accpipe(3).w or accpipe(4).w;
if accpipe(5).w and write_mask/=(write_mask'range => '1') then
assert not is_x(write_mask) report "Write error";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(5).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(5).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
wait until (hcmode and hcread_en) or read_en or write_en;
assert not ((read_en or hcread_en) and write_en);
if (read_en or hcread_en) then
if hcmode then
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
if not hcmode then
wait until rising_edge(ck);
end if;
dqs <= (others => '1');
dq <= rdata(2*width-1 downto width);
if hcmode then
wait until rising_edge(ck);
else
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
dq <= rdata(width-1 downto 0);
if hcmode then
wait until falling_edge(ck);
end if;
end loop;
if not hcmode then
wait until rising_edge(ck);
end if;
else
wait until falling_edge(ck);
assert to_X01(dqs)=(dqs'range => '0') or igndqs/=0;
while write_en loop
prevdqs := to_X01(dqs);
if igndqs /= 0 then
wait on ck,write_en;
else
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
end if;
if rising_edge(ck) then
-- Just to make sure missing DQS is not undetected
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if (igndqs=0 and prevdqs(x)='0' and to_X01(dqs(x))='1') or (igndqs/=0 and rising_edge(ck)) then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif (igndqs=0 and prevdqs(x)='1' and to_X01(dqs(x))='0') or (igndqs/=0 and falling_edge(ck)) then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | c3babcdbf80f05077d557669b814c055 | 0.532385 | 3.742196 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_0/sim/zqynq_lab_1_design_axi_timer_0_0.vhd | 1 | 8,558 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0_15;
USE axi_timer_v2_0_15.axi_timer;
ENTITY zqynq_lab_1_design_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END zqynq_lab_1_design_axi_timer_0_0;
ARCHITECTURE zqynq_lab_1_design_axi_timer_0_0_arch OF zqynq_lab_1_design_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END zqynq_lab_1_design_axi_timer_0_0_arch;
| mit | 72351305027d529a445eeb1319ac7ea2 | 0.685791 | 3.326079 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/stratixii/stratixii_ddr_phy.vhd | 1 | 39,095 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0)
);
END altdqs_stxii;
ARCHITECTURE RTL OF altdqs_stxii IS
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "none";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
SIGNAL dqs_busout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
TYPE periodtype IS ARRAY(10 TO 20) of STRING(1 TO 6);
CONSTANT period : periodtype := (
"9999ps", "9090ps", "8333ps", "7692ps", -- 100-130 MHz
"7143ps", "6667ps", "6250ps", "5882ps", -- 140-170 MHz
"5556ps", "5263ps", "5000ps"); -- 180-200 MHz
FUNCTION buffer_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "high"; ELSE RETURN "low"; END IF;
END buffer_mode;
FUNCTION out_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "delay_chain4";
ELSE RETURN "delay_chain3"; END IF;
END out_mode;
FUNCTION chain_length(MHz : INTEGER) RETURN INTEGER IS
BEGIN
IF MHz > 175 THEN RETURN 16; ELSE RETURN 12; END IF;
END chain_length;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
subtype v4 is std_logic_vector(3 downto 0);
type vv4 is array (width-1 downto 0) of v4;
signal dqslocal : vv4;
signal gnd : std_logic;
BEGIN
gnd <= '0';
dqinclk <= not dqs_busout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => buffer_mode(MHz),
DELAY_CHAIN_LENGTH => chain_length(MHz),
INPUT_FREQUENCY => period(MHz/10),
OFFSETCTRLOUT_MODE => "static",
DELAYCTRLOUT_MODE => "normal",
JITTER_REDUCTION => "false",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => delay_ctrl
);
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "false",
DQS_DELAY_BUFFER_MODE => buffer_mode(MHz),
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period(MHz/10),
DQS_OFFSETCTRL_ENABLE => "false",
DQS_OUT_MODE => out_mode(MHz),
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "true",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 36,
SIM_DQS_INTRINSIC_DELAY => 900,
SIM_DQS_OFFSET_INCREMENT => 0,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
datain => dqs_datain_h(i),
ddiodatain => dqs_datain_l(i),
delayctrlin => delay_ctrl,
dqsbusout => dqs_busout(i),
oe => oe(i),
outclk => outclk(i),
padio => dqs_padio(i)
);
-- clkbuf : global
-- port map (a_in => dqsbusout(i), a_out => dqs_busout(i));
-- dqslocal(i) <= "000" & dqsbusout(i);
-- clkbuf : stratixii_clkctrl generic map (clock_type => "global clock")
-- port map (inclk => dqslocal(i), outclk => dqs_busout(i));
END GENERATE loop0;
END RTL; --altdqs_stxii
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdq_stxii IS
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END altdq_stxii;
ARCHITECTURE RTL OF altdq_stxii IS
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO width-1 GENERATE
dq_ioa : stratixii_io
GENERIC MAP (
DDIO_MODE => "bidir",
DDIOINCLK_INPUT => "negated_inclk",
EXTEND_OE_DISABLE => "false",
-- INCLK_INPUT => "dqs_bus",
INPUT_ASYNC_RESET => "none",
INPUT_POWER_UP => "low",
INPUT_REGISTER_MODE => "register",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register"
)
PORT MAP (
datain => datain_h(i),
ddiodatain => datain_l(i),
ddioregout => dataout_l(i),
inclk => inclock,
oe => oe,
outclk => outclock,
padio => padio(i),
regout => dataout_h(i)
);
END GENERATE loop0;
END RTL; --altdq_stxii
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera;
library altera_mf;
--pragma translate_off
use altera_mf.altpll;
use altera_mf.altddio_out;
use altera_mf.altddio_bidir;
--pragma translate_on
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altdqs_stxii
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk0r, dataout => ddr_csb);
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk0r, dataout => ddr_cke);
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba, datain_l => ba, oe => vcc,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk90r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsnv <= (others => oe);
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
--library stratixii;
use altera_mf.altera_mf_components.all;
--use stratixii.stratixii_pll;
------------------------------------------------------------------
-- STRATIX2 DDR2 PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr2_phy is
signal vcc, gnd : std_logic;
signal ckel, odtl : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_120r, clk_180r, clk_270r : std_ulogic;
signal locked, lockl, vlockl : std_ulogic;
signal clk5 : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal gndv : std_logic_vector (dbits/8-1 downto 0);
signal dqsnv : std_logic_vector (dbits/8-1 downto 0);
signal dqsoe : std_logic_vector (dbits/8-1 downto 0);
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinl : std_logic_vector (dbits*2-1 downto 0);
signal dqoe : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; Mhz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
component altdq_stxii
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
type phasevec is array (1 to 4) of string(1 to 4);
type phasevecarr is array (13 to 20) of phasevec;
constant phasearr : phasevecarr := (
("1923", "2564", "3846", "5769"), -- 130 MHz
("1786", "2381", "3571", "5357"), -- 140 MHz
("1667", "2222", "3333", "5000"), -- 150 MHz
("1562", "2083", "3125", "4687"), -- 160 MHz
("1471", "1961", "2941", "4412"), -- 160 MHz
("1389", "1852", "2778", "4167"), -- 180 MHz
("1316", "1754", "2632", "3947"), -- 190 MHz
("1250", "1667", "2500", "3750")); -- 200 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
begin
clkout <= clk_0r;
vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk4_phase_shift => phasearr(DDR_FREQ/10)(4),
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => clk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_120r, clk(3) => clk_180r,
clk(4) => clk_270r, clk(5) => clk5, locked => lockl);
rstdel : process (clk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(clk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_180r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_180r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
odtl(i) <= odt(i) and locked;
end generate;
dqsreg : process (clk_180r)
begin
if rising_edge(clk_180r) then
dqsoe <= (others => not dqsoen);
dqsnv <= (others => not oen);
end if;
end process;
dqinreg : process (clk_120r)
begin
if rising_edge(clk_120r) then
dqin <= dqinl;
end if;
end process;
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clkb(i));
end generate;
-- Control signal pads
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk_180r, dataout => ddr_cke);
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk_180r, dataout => ddr_csb);
odtpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => odtl, datain_l => odtl, oe => vcc,
outclock => clk_180r, dataout => ddr_odt);
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_web);
bapads : altddio_out generic map (width => 2+eightbanks,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba(1+eightbanks downto 0),
datain_l => ba(1+eightbanks downto 0),
oe => vcc,
outclock => clk_180r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk_180r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk_0r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk_0r, oe => dqsoe, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqoe <= not oen;
dqgen : for i in 0 to dbits/8-1 generate
altdq : altdq_stxii generic map (width => 8)
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i),
outclock => clk_270r, oe => dqoe,
dataout_h => dqinl(i*8+7 downto i*8),
dataout_l => dqinl(i*8+7+dbits downto dbits+i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
-- Data mask
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/4-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk_270r, dataout => ddr_dm
);
end;
| gpl-2.0 | c1ae45582ab42e8c5e364b176ee153cb | 0.580509 | 3.128351 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/svgactrl.vhd | 1 | 27,545 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: svgactrl
-- File: svgactrl.vhd
-- Author: Hans Soderlund
-- Modified: Jiri Gaisler, Edvin Catovic, Jan Andersson
-- Contact: [email protected]
-- Description: SVGA Controller core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity svgactrl is
generic(
length : integer := 384; -- FIFO length in 32-bit words
part : integer := 128; -- FIFO-part length in 32-bit words
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0 -- Enable async. reset of VGA CD
);
port (
rst : in std_logic; -- Synchronous reset
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1' -- Asynchronous reset
);
end ;
architecture rtl of svgactrl is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
-- Calculates the required number of address bits for 32 bit buffer
function addrbits return integer is
begin
for i in 1 to 30 loop
if (2**i >= length) then return(i);
end if;
end loop;
return(30);
end function addrbits;
constant WPAC : integer := ahbaccsz/32; -- Words Per AHB Access.
constant FIFO_DW : integer := ahbaccsz; -- FIFO data width
constant FIFOCNTR : integer := log2(WPAC);
constant ABITS : integer := addrbits - FIFOCNTR; -- FIFO address bits
constant FIFOCNTL : integer := addrbits - 1;
subtype FIFO_CNT_R is natural range FIFOCNTL downto FIFOCNTR;
constant BURSTL : integer := burstlen + 1;
constant BURSTR : integer := log2(ahbaccsz/8);
type register_type is array (1 to 5) of std_logic_vector(31 downto 0);
type state_type is (running, not_running, reset);
type read_type is record
read_pointer : std_logic_vector(FIFOCNTL downto 0);
read_pointer_out : std_logic_vector(FIFOCNTL downto 0);
sync : std_logic_vector(2 downto 0);
data_out : std_logic_vector(23 downto 0);
lock : std_logic;
index : std_logic_vector(1 downto 0);
read_pointer_clut : std_logic_vector(7 downto 0);
hcounter : std_logic_vector(15 downto 0);
vcounter : std_logic_vector(15 downto 0);
fifo_ren : std_logic;
fifo_en : std_logic;
hsync : std_logic ;
vsync : std_logic ;
csync : std_logic ;
blank : std_logic ;
hsync2 : std_logic ;
vsync2 : std_logic ;
csync2 : std_logic ;
blank2 : std_logic ;
end record;
type control_type is record
int_reg : register_type;
state : state_type;
enable : std_logic;
reset : std_logic;
sync_c : std_logic_vector(2 downto 0);
sync_w : std_logic_vector(2 downto 0);
write_pointer_clut : std_logic_vector(7 downto 0);
datain_clut : std_logic_vector(23 downto 0);
write_en_clut : std_logic;
address : std_logic_vector(31 downto 0);
start : std_logic;
write_pointer : integer range 0 to length/WPAC;
ram_address : integer range 0 to length/WPAC;
data : std_logic_vector(FIFO_DW-1 downto 0);
level : integer range 0 to part/WPAC + 1;
status : integer range 0 to 3;
hpolarity : std_ulogic;
vpolarity : std_ulogic;
func : std_logic_vector(1 downto 0);
clk_sel : std_logic_vector(1 downto 0);
end record;
type sync_regs is record
s1 : std_logic_vector(2 downto 0);
s2 : std_logic_vector(2 downto 0);
s3 : std_logic_vector(2 downto 0);
end record;
signal t,tin : read_type;
signal r,rin : control_type;
signal sync_w : sync_regs;
signal sync_ra : sync_regs;
signal sync_rb : sync_regs;
signal sync_c : sync_regs;
signal read_status : std_logic_vector(2 downto 0);
signal write_status : std_logic_vector(2 downto 0);
signal write_en : std_logic;
signal res_mod :std_logic;
signal en_mod : std_logic;
signal fifo_en : std_logic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal equal : std_logic;
signal hmax : std_logic_vector(15 downto 0);
signal hfporch : std_logic_vector(15 downto 0);
signal hsyncpulse : std_logic_vector(15 downto 0);
signal hvideo : std_logic_vector(15 downto 0);
signal vmax : std_logic_vector(15 downto 0);
signal vfporch : std_logic_vector(15 downto 0);
signal vsyncpulse : std_logic_vector(15 downto 0);
signal vvideo : std_logic_vector(15 downto 0);
signal write_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal write_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal datain_clut : std_logic_vector(23 downto 0);
signal dataout_clut : std_logic_vector(23 downto 0);
signal dataout_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal datain_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal write_en_clut, read_en_clut : std_logic;
signal vcc : std_logic;
signal read_en_fifo, write_en_fifo : std_logic;
begin
vcc <= '1';
ram0 : syncram_2p
generic map (
tech => memtech,
abits => ABITS,
dbits => FIFO_DW,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_fifo,
raddress => read_pointer_fifo,
dataout => dataout_fifo,
wclk => clk,
write => write_en_fifo,
waddress => write_pointer_fifo,
datain => datain_fifo);
clutram : syncram_2p
generic map (
tech => memtech,
abits => 8,
dbits => 24,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_clut,
raddress => read_pointer_clut,
dataout => dataout_clut,
wclk => clk,
write => write_en_clut,
waddress => write_pointer_clut,
datain => datain_clut);
ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER,
GAISLER_SVGACTRL, 0, 3, 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod,sync_w)
variable v : control_type;
variable apbrdata : std_logic_vector(31 downto 0);
variable apbwrite : std_logic;
variable we_fifo : std_logic;
begin
v := r; v.write_en_clut := '0'; apbrdata := (others =>'0'); we_fifo := '0';
---------------------------------------------------------------------------
-- Control. Handles the APB accesses and stores the internal registers
---------------------------------------------------------------------------
apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
case apbi.paddr(5 downto 2) is
when "0000" =>
-- Status register
if apbwrite = '1' then
v.enable := apbi.pwdata(0);
v.reset := apbi.pwdata(1);
v.hpolarity := apbi.pwdata(8);
v.vpolarity := apbi.pwdata(9);
v.func := apbi.pwdata(5 downto 4);
v.clk_sel := apbi.pwdata(7 downto 6);
end if;
apbrdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel &
r.func & fifo_en & '0' & r.reset & r.enable;
when "1010" =>
-- CLUT access register
if apbwrite = '1' then
v.datain_clut := apbi.pwdata(23 downto 0);
v.write_pointer_clut := apbi.pwdata(31 downto 24);
v.write_en_clut := '1';
end if;
when "0001" =>
-- Video length register
if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if;
apbrdata := r.int_reg(1);
when "0010" =>
-- Front porch register
if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if;
apbrdata := r.int_reg(2);
when "0011" =>
-- Sync length register
if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if;
apbrdata := r.int_reg(3);
when "0100" =>
-- Line length register
if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if;
apbrdata := r.int_reg(4);
when "0101" =>
-- Framebuffer memory position register
if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if;
apbrdata := r.int_reg(5);
-- Dynamic clock registers 0 - 3
when "0110" => apbrdata := conv_std_logic_vector(clk0,32);
when "0111" => apbrdata := conv_std_logic_vector(clk1,32);
when "1000" => apbrdata := conv_std_logic_vector(clk2,32);
when "1001" => apbrdata := conv_std_logic_vector(clk3,32);
when others =>
end case;
---------------------------------------------------------------------------
-- Control state machine
---------------------------------------------------------------------------
case r.state is
when running =>
if r.enable = '0' then
v.sync_c := "011";
v.state := not_running;
end if;
when not_running =>
if r.enable = '1' then
v.sync_c := "001";
v.state := reset;
end if;
when reset =>
if sync_c.s3 = "001" then
v.sync_c := "010";
v.state := running;
end if;
end case;
---------------------------------------------------------------------------
-- Control reset
---------------------------------------------------------------------------
if r.reset = '1' or rst = '0' then
v.state := not_running;
v.enable := '0';
v.int_reg := (others => (others => '0'));
v.sync_c := "011";
v.reset := '0';
v.clk_sel := "00";
end if;
---------------------------------------------------------------------------
-- Write part. This part reads from the memory framebuffer and places the
-- data in the designated fifo specified from the generic.
---------------------------------------------------------------------------
v.start := '0';
if write_en = '0' then
if (r.start or not dmao.active) = '1' then v.start := '1'; end if;
-- AHB access and FIFO write
if dmao.ready = '1' then
v.data := ahbreaddata(dmao.rdata, r.address(4 downto 2),
conv_std_logic_vector(log2(FIFO_DW/8), 3));
v.ram_address := v.write_pointer;
v.write_pointer := v.write_pointer + 1; we_fifo := '1';
if v.write_pointer = length/WPAC then
v.write_pointer := 0;
end if;
v.level := v.level + 1;
if dmao.haddr = (9 downto 0 => '0') then
v.address := (v.address(31 downto 10) + 1) & dmao.haddr;
else
v.address := v.address(31 downto 10) & dmao.haddr;
end if;
if (dmao.haddr(BURSTL downto 0) =
((BURSTL downto BURSTR => '1') & zero32(BURSTR-1 downto 0))) then
v.start := '0';
end if;
end if;
-- FIFO sync
v.sync_w := v.sync_w and read_status;
if v.level >= (part/WPAC-1) then
if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part/WPAC then
v.level := 0;
if r.status = 0 then
v.sync_w(2) := '1';
else
v.sync_w(r.status -1) := '1';
end if;
v.status := v.status + 1;
if v.status = 3 then
v.status := 0;
end if;
else
v.start := '0';
end if;
end if;
end if;
---------------------------------------------------------------------------
--- Write reset part
---------------------------------------------------------------------------
if res_mod = '0' or write_en = '1' then
if dmao.active = '0' then v.address := r.int_reg(5); end if;
v.start := '0';
v.sync_w := "000";
v.status := 1;
v.ram_address := 0;
v.write_pointer := 0;
v.level := 0;
end if;
if (r.start and dmao.active and not dmao.ready) = '1' then
v.start := '1';
end if;
---------------------------------------------------------------------------
-- Drive process outputs
---------------------------------------------------------------------------
rin <= v;
sync_c.s1 <= v.sync_c;
sync_w.s1 <= r.sync_w;
res_mod <= sync_c.s3(1);
en_mod <= sync_c.s3(0);
write_status <= sync_w.s3;
hvideo <= r.int_reg(1)(15 downto 0);
vvideo <= r.int_reg(1)(31 downto 16);
hfporch <= r.int_reg(2)(15 downto 0);
vfporch <= r.int_reg(2)(31 downto 16);
hsyncpulse <= r.int_reg(3)(15 downto 0);
vsyncpulse <= r.int_reg(3)(31 downto 16);
hmax <= r.int_reg(4)(15 downto 0);
vmax <= r.int_reg(4)(31 downto 16);
apbo.prdata <= apbrdata;
dmai.wdata <= (others => '0');
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= conv_std_logic_vector(log2(ahbaccsz/8), 3);
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= r.start and r.enable;
dmai.address <= r.address;
write_pointer_fifo <= conv_std_logic_vector(v.ram_address, ABITS);
write_pointer_clut <= r.write_pointer_clut;
datain_fifo <= v.data;
datain_clut <= r.datain_clut;
write_en_clut <= r.write_en_clut;
clk_sel <= r.clk_sel;
write_en_fifo <= we_fifo;
end process;
read_proc : process(t, res_mod, en_mod, write_status, dataout_fifo, sync_rb,
dataout_clut, vmax, hmax, hvideo, hfporch, hsyncpulse,
vvideo, vfporch, vsyncpulse, sync_ra, r)
variable v : read_type;
variable inc_pointer : std_logic;
variable fifo_word : std_logic_vector(31 downto 0);
variable rpo1 : std_logic_vector(1 downto 0);
variable rpo2 : std_logic_vector(2 downto 0);
begin
v := t; fifo_word := (others => '0');
rpo1 := (others => '0'); rpo2 := (others => '0');
v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync;
v.blank2 := t.blank;
---------------------------------------------------------------------------
-- Sync signals generation
---------------------------------------------------------------------------
if en_mod = '0' then
-- vertical counter
if (t.vcounter = vmax ) and (t.hcounter = hmax ) then
v.vcounter := (others => '0');
elsif t.hcounter = hmax then
v.vcounter := t.vcounter + 1;
end if;
-- horizontal counter
if t.hcounter < hmax then v.hcounter := t.hcounter + 1;
else v.hcounter := (others => '0'); end if;
-- generate hsync
if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch-1)) then
v.hsync := r.hpolarity;
else v.hsync := not r.hpolarity; end if;
-- generate vsync
if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then
v.vsync := r.vpolarity;
else v.vsync := not r.vpolarity; end if;
--generate csync & blank signal
v.csync := not (v.hsync xor v.vsync);
v.blank := not t.fifo_ren;
--generate fifo_ren signal
if (t.hcounter = (hmax-1) and t.vcounter = vmax) or
(t.hcounter = (hmax-1) and t.vcounter < vvideo) then
v.fifo_ren := '0';
elsif t.hcounter = (hvideo-1) and t.vcounter <= vvideo then
v.fifo_ren := '1';
end if;
--generate fifo_en signal
if t.vcounter = vmax then
v.fifo_en := '0';
elsif t.vcounter = vvideo and t.hcounter = (hvideo-1) then
v.fifo_en := '1';
end if;
else
-- Prevent uninitialized fifo_en signal that leads to uninitialized
-- bit in APB status register
v.fifo_en := '1';
end if;
if r.func /= "01" then -- do not delay strobes when not using CLUT
v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync;
v.blank2 := v.blank;
end if;
---------------------------------------------------------------------------
-- Sync reset
---------------------------------------------------------------------------
if res_mod = '0' then
v.hcounter := hmax;
v.vcounter := vmax - 1;
v.hsync := r.hpolarity;
v.vsync := r.vpolarity;
v.blank := '0';
v.fifo_ren := '1';
v.fifo_en := '1';
end if;
---------------------------------------------------------------------------
-- Read from fifo.
---------------------------------------------------------------------------
inc_pointer := '0';
if t.fifo_en = '0' then
-- Fifo sync
if ((t.read_pointer_out = zero32(t.read_pointer_out'range) or
t.read_pointer_out = conv_std_logic_vector(part, FIFOCNTL+1) or
t.read_pointer_out = conv_std_logic_vector(2*part, FIFOCNTL+1)) and
t.fifo_ren = '0' and v.index = "00") then
case t.sync is
when "111" | "011" =>
if write_status(0) = '1' then
v.sync := "110"; v.lock := '0';
else v.lock := '1'; end if;
when "110" =>
if write_status(1) = '1' then
v.sync := "101"; v.lock := '0';
else v.lock := '1'; end if;
when "101" =>
if write_status(2) = '1' then
v.sync := "011"; v.lock := '0';
else v.lock := '1'; end if;
when others => null;
end case;
end if;
-------------------------------------------------------------------------
-- FIFO read and CLUT access
-------------------------------------------------------------------------
if t.fifo_ren = '0' and v.lock = '0' then
if FIFO_DW = 32 then
fifo_word(FIFO_DW-1 downto 0) := dataout_fifo(FIFO_DW-1 downto 0);
elsif FIFO_DW = 64 then
if t.read_pointer_out(0) = '0' then
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto FIFO_DW/2);
else
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW/2-1 downto 0);
end if;
elsif FIFO_DW = 128 then
rpo1 := t.read_pointer_out(1 downto 0);
case rpo1 is
when "00" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 3*(FIFO_DW/4));
when "01" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/4)-1 downto 2*(FIFO_DW/4));
when "10" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/4)-1 downto 1*(FIFO_DW/4));
when others =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo((FIFO_DW/4)-1 downto 0);
end case;
elsif FIFO_DW = 256 then
rpo2 := t.read_pointer_out(2 downto 0);
case rpo2 is
when "000" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 7*(FIFO_DW/8));
when "001" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(7*(FIFO_DW/8)-1 downto 6*(FIFO_DW/8));
when "010" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(6*(FIFO_DW/8)-1 downto 5*(FIFO_DW/8));
when "011" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(5*(FIFO_DW/8)-1 downto 4*(FIFO_DW/8));
when "100" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(4*(FIFO_DW/8)-1 downto 3*(FIFO_DW/8));
when "101" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/8)-1 downto 2*(FIFO_DW/8));
when "110" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/8)-1 downto 1*(FIFO_DW/8));
when others =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo((FIFO_DW/8)-1 downto 0);
end case;
end if;
case r.func is
when "01" =>
if t.index = "00" then
v.read_pointer_clut := fifo_word(31 downto 24);
v.index := "01";
elsif t.index = "01" then
v.read_pointer_clut := fifo_word(23 downto 16);
v.index := "10";
elsif t.index = "10" then
v.read_pointer_clut := fifo_word(15 downto 8);
v.index := "11";
else
v.read_pointer_clut := fifo_word(7 downto 0);
v.index := "00"; inc_pointer := '1';
end if;
v.data_out := dataout_clut;
when "10" =>
if t.index = "00" then
v.data_out := fifo_word(31 downto 27) & "000" &
fifo_word(26 downto 21) & "00" &
fifo_word(20 downto 16) & "000";
v.index := "01";
else
v.data_out := fifo_word(15 downto 11) & "000" &
fifo_word(10 downto 5) & "00" &
fifo_word(4 downto 0) & "000";
v.index := "00"; inc_pointer := '1';
end if;
when "11" =>
v.data_out := fifo_word(23 downto 0);
v.index := "00"; inc_pointer := '1';
when others =>
v.data_out := (23 downto 0 => '1');
v.index := "00"; inc_pointer := '1';
end case;
else
v.data_out := (others => '0');
end if;
if inc_pointer = '1' then
v.read_pointer_out := t.read_pointer;
v.read_pointer := t.read_pointer + 1;
if v.read_pointer(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer := (others => '0');
end if;
if v.read_pointer_out(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer_out := (others => '0');
end if;
end if;
else
v.data_out := (others => '0');
end if;
---------------------------------------------------------------------------
-- FIFO read reset
---------------------------------------------------------------------------
if res_mod = '0' or t.fifo_en = '1' then
v.sync := "111";
v.read_pointer_out := (others => '0');
v.read_pointer := conv_std_logic_vector(1, ABITS+FIFOCNTR);
v.data_out := (others => '0');
v.lock := '1';
v.index := "00";
v.read_pointer_clut := (others => '0');
end if;
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
tin <= v;
sync_ra.s1 <= t.sync;
sync_rb.s1 <= t.fifo_en & "00";
read_status <= sync_ra.s3;
write_en <= sync_rb.s3(2);
fifo_en <= t.fifo_en;
read_pointer_clut <= v.read_pointer_clut;
read_pointer_fifo <= v.read_pointer_out(FIFO_CNT_R);
read_en_fifo <= not v.fifo_ren;
read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0);
vgao.video_out_r <= t.data_out(23 downto 16);
vgao.video_out_g <= t.data_out(15 downto 8);
vgao.video_out_b <= t.data_out(7 downto 0);
vgao.hsync <= t.hsync2;
vgao.vsync <= t.vsync2;
vgao.comp_sync <= t.csync2;
vgao.blank <= t.blank2;
vgao.bitdepth <= r.func;
end process;
-----------------------------------------------------------------------------
-- Registers in system clock domain
-----------------------------------------------------------------------------
proc_clk : process(clk)
begin
if rising_edge(clk) then
r <= rin; -- Control
sync_ra.s2 <= sync_ra.s1; -- Write
sync_ra.s3 <= sync_ra.s2; -- Write
sync_rb.s2 <= sync_rb.s1; -- Write
sync_rb.s3 <= sync_rb.s2; -- Write
end if;
end process;
-----------------------------------------------------------------------------
-- Registers in video clock domain
-----------------------------------------------------------------------------
proc_vgaclk : process(arst, vgaclk)
begin
if asyncrst = 1 and arst = '0' then
t.fifo_en <= '1';
sync_c.s2 <= "011";
sync_c.s3 <= "011";
elsif rising_edge(vgaclk) then
t <= tin; -- Read
sync_c.s2 <= sync_c.s1; -- Control
sync_c.s3 <= sync_c.s2; -- Control
sync_w.s2 <= sync_w.s1; -- Read
sync_w.s3 <= sync_w.s2; -- Read
end if;
end process;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"svgactrl" & tost(pindex) & ": SVGA controller rev " &
tost(REVISION) & ", FIFO length: " & tost(length) &
", FIFO part length: " & tost(part) &
", FIFO address bits: " & tost(ABITS) &
", AHB access size: " & tost(ahbaccsz) & " bits");
-- pragma translate_on
end;
| gpl-2.0 | d79d3e4c9046791a2830dbbde20a467b | 0.481939 | 3.68495 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/grsysmon.vhd | 1 | 16,851 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grsysmon
-- File: grsysmon.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Description: Provides GRLIB AMBA AHB slave interface to Xilinx SYSMON
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
entity grsysmon is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end grsysmon;
architecture rtl of grsysmon is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRSYSMON, 0, REVISION, hirq),
4 => ahb_iobar(caddr, cmask), 5 => ahb_iobar(saddr, smask),
others => zero32);
-- BANKs
constant CONF_BANK : integer := 0;
constant SYSMON_BANK : integer := 1;
-- Registers
constant CONF_REG_OFF : std_ulogic := '0';
constant STAT_REG_OFF : std_ulogic := '1';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sysmon_out_type is record
alm : std_logic_vector(2 downto 0);
busy : std_ulogic;
channel : std_logic_vector(4 downto 0);
do : std_logic_vector(15 downto 0);
drdy : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
jtagbusy : std_ulogic;
jtaglocked : std_ulogic;
jtagmodified : std_ulogic;
ot : std_ulogic;
end record;
type sysmon_in_type is record
daddr : std_logic_vector(6 downto 0);
den : std_ulogic;
di : std_logic_vector(15 downto 0);
dwe : std_ulogic;
end record;
type grsysmon_conf_reg_type is record
ot_ien : std_ulogic;
alm_ien : std_logic_vector(2 downto 0);
convst : std_ulogic;
eos_ien : std_ulogic;
eoc_ien : std_ulogic;
busy_ien : std_ulogic;
jb_ien : std_ulogic;
jl_ien : std_ulogic;
jm_ien : std_ulogic;
end record;
type grsysmon_reg_type is record
cfgreg : grsysmon_conf_reg_type;
-- SYSMON
den : std_ulogic; -- System monitor data enable
sma : std_ulogic; -- System monitor access
smr : std_ulogic; -- System monitor access ready
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
srdata : std_logic_vector(15 downto 0); -- SYSMON response data
rrdata : std_logic_vector(12 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : grsysmon_reg_type;
signal syso : sysmon_out_type;
signal sysi : sysmon_in_type;
signal sysmon_rst : std_ulogic;
signal lconvst : std_ulogic;
begin -- rtl
sysmon_rst <= not rstn;
convstint: if extconvst = 0 generate
lconvst <= r.cfgreg.convst;
end generate convstint;
convstext: if extconvst /= 0 generate
lconvst <= sysmoni.convst;
end generate convstext;
-----------------------------------------------------------------------------
-- System monitor
-----------------------------------------------------------------------------
macro0 : system_monitor
generic map (tech => tech,
INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => syso.alm, busy => syso.busy, channel => syso.channel,
do => syso.do, drdy => syso.drdy, eoc => syso.eoc,
eos => syso.eos, jtagbusy => syso.jtagbusy,
jtaglocked => syso.jtaglocked, jtagmodified => syso.jtagmodified,
ot => syso.ot, convst => lconvst, convstclk => sysmoni.convstclk,
daddr => sysi.daddr, dclk => clk, den => sysi.den,
di => sysi.di, dwe => sysi.dwe, reset => sysmon_rst,
vauxn => sysmoni.vauxn, vauxp => sysmoni.vauxp,
vn => sysmoni.vn, vp => sysmoni.vp);
-----------------------------------------------------------------------------
-- AMBA and control i/f
-----------------------------------------------------------------------------
comb: process (r, rstn, ahbsi, syso)
variable v : grsysmon_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable addr : std_logic_vector(7 downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable regaddr : std_ulogic;
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; v.den := '0';
regaddr := r.haddr(1-wrdalign); hsplit := (others => '0');
v.cfgreg.convst := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not r.sma or ahbsi.hmbsel(CONF_BANK) or
ahbsi.hmastlock) = '1' then
v.hready := ahbsi.hmbsel(CONF_BANK) and ahbsi.hwrite;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr((7+wrdalign) downto (1+wrdalign));
v.hsel := '1';
if ahbsi.hmbsel(SYSMON_BANK) = '1' then
v.den := not r.insplit; v.sma := '1';
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to sysmon
-- registers. Respond with SPLIT or insert wait states
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to conf registers
if (r.hsel and r.hmbsel(CONF_BANK)) = '1' then
v.rrdata := (others => '0');
if r.hwrite = '0' then
v.hready := '1';
v.hsel := '0';
end if;
case regaddr is
when CONF_REG_OFF =>
v.rrdata(12) := r.cfgreg.ot_ien;
v.rrdata(11 downto 9) := r.cfgreg.alm_ien;
if extconvst = 0 then
v.rrdata(6) := r.cfgreg.convst;
end if;
v.rrdata(5) := r.cfgreg.eos_ien;
v.rrdata(4) := r.cfgreg.eoc_ien;
v.rrdata(3) := r.cfgreg.busy_ien;
v.rrdata(2) := r.cfgreg.jb_ien;
v.rrdata(1) := r.cfgreg.jl_ien;
v.rrdata(0) := r.cfgreg.jm_ien;
if r.hwrite = '1' then
v.cfgreg.ot_ien := hwdata(12);
v.cfgreg.alm_ien := hwdata(11 downto 9);
if extconvst = 0 then
v.cfgreg.convst := hwdata(6);
end if;
v.cfgreg.eos_ien := hwdata(5);
v.cfgreg.eoc_ien := hwdata(4);
v.cfgreg.busy_ien := hwdata(3);
v.cfgreg.jb_ien := hwdata(2);
v.cfgreg.jl_ien := hwdata(1);
v.cfgreg.jm_ien := hwdata(0);
end if;
when STAT_REG_OFF =>
v.rrdata(12) := syso.ot;
v.rrdata(11 downto 9) := syso.alm;
v.rrdata(8 downto 4) := syso.channel;
v.rrdata(3) := syso.busy;
v.rrdata(2) := syso.jtagbusy;
v.rrdata(1) := syso.jtaglocked;
v.rrdata(0) := syso.jtagmodified;
when others => null;
end case;
end if;
-- SYSMON access finished
if syso.drdy = '1' then
v.srdata := syso.do;
v.smr := '1';
end if;
if (syso.drdy or r.smr) = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
-- (((split = 0 or r.insplit = '0') and r.hmbsel(SYSMON_BANK) = '1') or
-- (split = 1 and ahbsi.hmbsel(SYSMON_BANK) = '1')) and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.smr := '0';
v.sma := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.den := '1'; v.smr := '0';
v.ahbcancel := '0';
end if;
end if;
-- Interrupts
if (syso.ot and v.cfgreg.ot_ien) = '1' then
v.irq := '1';
v.cfgreg.ot_ien := '0';
end if;
for i in r.cfgreg.alm_ien'range loop
if (syso.alm(i) and r.cfgreg.alm_ien(i)) = '1' then
v.irq := '1';
v.cfgreg.alm_ien(i) := '0';
end if;
end loop; -- i
if (syso.eos and v.cfgreg.eos_ien) = '1' then
v.irq := '1';
v.cfgreg.eos_ien := '0';
end if;
if (syso.eoc and v.cfgreg.eoc_ien) = '1' then
v.irq := '1';
v.cfgreg.eoc_ien := '0';
end if;
if (syso.busy and v.cfgreg.busy_ien) = '1' then
v.irq := '1';
v.cfgreg.busy_ien := '0';
end if;
if (syso.jtagbusy and v.cfgreg.jb_ien) = '1' then
v.irq := '1';
v.cfgreg.jb_ien := '0';
end if;
if (syso.jtaglocked and v.cfgreg.jl_ien) = '1' then
v.irq := '1';
v.cfgreg.jl_ien := '0';
end if;
if (syso.jtagmodified and v.cfgreg.jm_ien) = '1' then
v.irq := '1';
v.cfgreg.jm_ien := '0';
end if;
-- Reset
if rstn = '0' then
v.cfgreg.ot_ien := '0';
v.cfgreg.alm_ien := (others => '0');
v.cfgreg.eos_ien := '0';
v.cfgreg.eoc_ien := '0';
v.cfgreg.busy_ien := '0';
v.cfgreg.jb_ien := '0';
v.cfgreg.jl_ien := '0';
v.cfgreg.jm_ien := '0';
v.sma := '0';
v.smr := '0';
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CONF_BANK) = '1' then
if wrdalign = 0 then hrdata := zero32(31 downto 13) & r.rrdata;
else hrdata := '1' & zero32(30 downto 13) & r.rrdata; end if;
else
if wrdalign = 0 then hrdata := r.srdata & r.srdata;
else hrdata := zero32(31 downto 16) & r.srdata;
end if;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- Signals to system monitor
sysi.daddr <= r.haddr;
sysi.den <= r.den;
sysi.dwe <= r.hwrite;
if wrdalign = 0 then
if r.haddr(0) = '0' then sysi.di <= hwdata(31 downto 16);
else sysi.di <= hwdata(15 downto 0); end if;
else
sysi.di <= hwdata(15 downto 0);
end if;
-- Signals from system monitor to core outputs
sysmono.alm <= syso.alm;
sysmono.ot <= syso.ot;
sysmono.eoc <= syso.eoc;
sysmono.eos <= syso.eos;
sysmono.channel <= syso.channel;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"grsysmon" & tost(hindex) & ": AMBA wrapper for System Monitor, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-2.0 | 5d22eebf6d988f4f811bc13024a0ef3c | 0.50632 | 3.599103 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/ec/ddr_ec.vhd | 1 | 2,040 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
| gpl-2.0 | 35fd0c84840607bb86a3d7679cbbbce2 | 0.538725 | 4.112903 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/TestBeanch.vhd | 1 | 766 | entity ODD_PARITY_TB is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture
OP_TB_ARCH of ODD_PARITY_TB is
component Parity_Generator1
port(
input_stream : in input;
clk : in std_logic;
parity : out bit);
end component;
signal input_stream : input;
signal clk :std_logic;
signal parity :bit ;
begin
U1: Parity_Generator1 port map (input_stream, clk, parity => parity );
input1 : process (clk)
begin
if clk <= 'U' then clk <= '0' after 1 ns;
else clk <= not clk after 1 ns;
end if;
end process;
input2: process (input_stream)
begin
input_stream <= "10100110" after 1 ns,
"01111100" after 2 ns;
end process;
end OP_TB_ARCH;
configuration cfg_op of ODD_PARITY_TB is
for OP_TB_ARCH
end for;
end cfg_op; | mit | 85f973048f6264d78e7bd43b5acae2ad | 0.671018 | 2.641379 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/7GFLOPs/syn/vhdl/convolve_kernel.vhd | 1 | 921,145 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
bufw_0_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_0_EN_A : OUT STD_LOGIC;
bufw_0_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_0_Clk_A : OUT STD_LOGIC;
bufw_0_0_Rst_A : OUT STD_LOGIC;
bufw_0_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_1_EN_A : OUT STD_LOGIC;
bufw_0_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_1_Clk_A : OUT STD_LOGIC;
bufw_0_1_Rst_A : OUT STD_LOGIC;
bufw_0_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_2_EN_A : OUT STD_LOGIC;
bufw_0_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_2_Clk_A : OUT STD_LOGIC;
bufw_0_2_Rst_A : OUT STD_LOGIC;
bufw_0_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_3_EN_A : OUT STD_LOGIC;
bufw_0_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_3_Clk_A : OUT STD_LOGIC;
bufw_0_3_Rst_A : OUT STD_LOGIC;
bufw_0_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_4_EN_A : OUT STD_LOGIC;
bufw_0_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_4_Clk_A : OUT STD_LOGIC;
bufw_0_4_Rst_A : OUT STD_LOGIC;
bufw_1_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_0_EN_A : OUT STD_LOGIC;
bufw_1_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_0_Clk_A : OUT STD_LOGIC;
bufw_1_0_Rst_A : OUT STD_LOGIC;
bufw_1_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_1_EN_A : OUT STD_LOGIC;
bufw_1_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_1_Clk_A : OUT STD_LOGIC;
bufw_1_1_Rst_A : OUT STD_LOGIC;
bufw_1_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_2_EN_A : OUT STD_LOGIC;
bufw_1_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_2_Clk_A : OUT STD_LOGIC;
bufw_1_2_Rst_A : OUT STD_LOGIC;
bufw_1_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_3_EN_A : OUT STD_LOGIC;
bufw_1_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_3_Clk_A : OUT STD_LOGIC;
bufw_1_3_Rst_A : OUT STD_LOGIC;
bufw_1_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_4_EN_A : OUT STD_LOGIC;
bufw_1_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_4_Clk_A : OUT STD_LOGIC;
bufw_1_4_Rst_A : OUT STD_LOGIC;
bufw_2_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_0_EN_A : OUT STD_LOGIC;
bufw_2_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_0_Clk_A : OUT STD_LOGIC;
bufw_2_0_Rst_A : OUT STD_LOGIC;
bufw_2_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_1_EN_A : OUT STD_LOGIC;
bufw_2_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_1_Clk_A : OUT STD_LOGIC;
bufw_2_1_Rst_A : OUT STD_LOGIC;
bufw_2_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_2_EN_A : OUT STD_LOGIC;
bufw_2_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_2_Clk_A : OUT STD_LOGIC;
bufw_2_2_Rst_A : OUT STD_LOGIC;
bufw_2_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_3_EN_A : OUT STD_LOGIC;
bufw_2_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_3_Clk_A : OUT STD_LOGIC;
bufw_2_3_Rst_A : OUT STD_LOGIC;
bufw_2_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_4_EN_A : OUT STD_LOGIC;
bufw_2_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_4_Clk_A : OUT STD_LOGIC;
bufw_2_4_Rst_A : OUT STD_LOGIC;
bufw_3_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_0_EN_A : OUT STD_LOGIC;
bufw_3_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_0_Clk_A : OUT STD_LOGIC;
bufw_3_0_Rst_A : OUT STD_LOGIC;
bufw_3_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_1_EN_A : OUT STD_LOGIC;
bufw_3_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_1_Clk_A : OUT STD_LOGIC;
bufw_3_1_Rst_A : OUT STD_LOGIC;
bufw_3_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_2_EN_A : OUT STD_LOGIC;
bufw_3_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_2_Clk_A : OUT STD_LOGIC;
bufw_3_2_Rst_A : OUT STD_LOGIC;
bufw_3_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_3_EN_A : OUT STD_LOGIC;
bufw_3_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_3_Clk_A : OUT STD_LOGIC;
bufw_3_3_Rst_A : OUT STD_LOGIC;
bufw_3_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_4_EN_A : OUT STD_LOGIC;
bufw_3_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_4_Clk_A : OUT STD_LOGIC;
bufw_3_4_Rst_A : OUT STD_LOGIC;
bufw_4_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_0_EN_A : OUT STD_LOGIC;
bufw_4_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_0_Clk_A : OUT STD_LOGIC;
bufw_4_0_Rst_A : OUT STD_LOGIC;
bufw_4_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_1_EN_A : OUT STD_LOGIC;
bufw_4_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_1_Clk_A : OUT STD_LOGIC;
bufw_4_1_Rst_A : OUT STD_LOGIC;
bufw_4_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_2_EN_A : OUT STD_LOGIC;
bufw_4_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_2_Clk_A : OUT STD_LOGIC;
bufw_4_2_Rst_A : OUT STD_LOGIC;
bufw_4_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_3_EN_A : OUT STD_LOGIC;
bufw_4_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_3_Clk_A : OUT STD_LOGIC;
bufw_4_3_Rst_A : OUT STD_LOGIC;
bufw_4_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_4_EN_A : OUT STD_LOGIC;
bufw_4_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_4_Clk_A : OUT STD_LOGIC;
bufw_4_4_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_A : OUT STD_LOGIC;
bufi_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_A : OUT STD_LOGIC;
bufi_0_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_B : OUT STD_LOGIC;
bufi_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_B : OUT STD_LOGIC;
bufi_0_Rst_B : OUT STD_LOGIC;
bufi_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_A : OUT STD_LOGIC;
bufi_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_A : OUT STD_LOGIC;
bufi_1_Rst_A : OUT STD_LOGIC;
bufi_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_B : OUT STD_LOGIC;
bufi_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_B : OUT STD_LOGIC;
bufi_1_Rst_B : OUT STD_LOGIC;
bufi_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_A : OUT STD_LOGIC;
bufi_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_A : OUT STD_LOGIC;
bufi_2_Rst_A : OUT STD_LOGIC;
bufi_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_B : OUT STD_LOGIC;
bufi_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_B : OUT STD_LOGIC;
bufi_2_Rst_B : OUT STD_LOGIC;
bufi_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_EN_A : OUT STD_LOGIC;
bufi_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Clk_A : OUT STD_LOGIC;
bufi_3_Rst_A : OUT STD_LOGIC;
bufi_3_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_EN_B : OUT STD_LOGIC;
bufi_3_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_3_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_3_Clk_B : OUT STD_LOGIC;
bufi_3_Rst_B : OUT STD_LOGIC;
bufi_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_EN_A : OUT STD_LOGIC;
bufi_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Clk_A : OUT STD_LOGIC;
bufi_4_Rst_A : OUT STD_LOGIC;
bufi_4_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_EN_B : OUT STD_LOGIC;
bufi_4_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_4_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_4_Clk_B : OUT STD_LOGIC;
bufi_4_Rst_B : OUT STD_LOGIC;
bufi_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_EN_A : OUT STD_LOGIC;
bufi_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Clk_A : OUT STD_LOGIC;
bufi_5_Rst_A : OUT STD_LOGIC;
bufi_5_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_EN_B : OUT STD_LOGIC;
bufi_5_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_5_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_5_Clk_B : OUT STD_LOGIC;
bufi_5_Rst_B : OUT STD_LOGIC;
bufi_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_EN_A : OUT STD_LOGIC;
bufi_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Clk_A : OUT STD_LOGIC;
bufi_6_Rst_A : OUT STD_LOGIC;
bufi_6_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_EN_B : OUT STD_LOGIC;
bufi_6_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_6_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_6_Clk_B : OUT STD_LOGIC;
bufi_6_Rst_B : OUT STD_LOGIC;
bufo_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_EN_A : OUT STD_LOGIC;
bufo_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Clk_A : OUT STD_LOGIC;
bufo_0_Rst_A : OUT STD_LOGIC;
bufo_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_EN_B : OUT STD_LOGIC;
bufo_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_0_Clk_B : OUT STD_LOGIC;
bufo_0_Rst_B : OUT STD_LOGIC;
bufo_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_EN_A : OUT STD_LOGIC;
bufo_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Clk_A : OUT STD_LOGIC;
bufo_1_Rst_A : OUT STD_LOGIC;
bufo_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_EN_B : OUT STD_LOGIC;
bufo_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_1_Clk_B : OUT STD_LOGIC;
bufo_1_Rst_B : OUT STD_LOGIC;
bufo_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_EN_A : OUT STD_LOGIC;
bufo_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Clk_A : OUT STD_LOGIC;
bufo_2_Rst_A : OUT STD_LOGIC;
bufo_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_EN_B : OUT STD_LOGIC;
bufo_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_2_Clk_B : OUT STD_LOGIC;
bufo_2_Rst_B : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=811,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=125,HLS_SYN_FF=23835,HLS_SYN_LUT=25571}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state239 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv8_C0 : STD_LOGIC_VECTOR (7 downto 0) := "11000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal indvar_flatten_reg_810 : STD_LOGIC_VECTOR (7 downto 0);
signal p_s_reg_821 : STD_LOGIC_VECTOR (6 downto 0);
signal p_1_reg_833 : STD_LOGIC_VECTOR (1 downto 0);
signal exitcond_flatten_fu_1044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state17_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state20_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state23_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state29_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state32_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state35_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state38_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state41_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state44_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state47_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter16 : BOOLEAN;
signal ap_block_state53_pp0_stage0_iter17 : BOOLEAN;
signal ap_block_state56_pp0_stage0_iter18 : BOOLEAN;
signal ap_block_state59_pp0_stage0_iter19 : BOOLEAN;
signal ap_block_state62_pp0_stage0_iter20 : BOOLEAN;
signal ap_block_state65_pp0_stage0_iter21 : BOOLEAN;
signal ap_block_state68_pp0_stage0_iter22 : BOOLEAN;
signal ap_block_state71_pp0_stage0_iter23 : BOOLEAN;
signal ap_block_state74_pp0_stage0_iter24 : BOOLEAN;
signal ap_block_state77_pp0_stage0_iter25 : BOOLEAN;
signal ap_block_state80_pp0_stage0_iter26 : BOOLEAN;
signal ap_block_state83_pp0_stage0_iter27 : BOOLEAN;
signal ap_block_state86_pp0_stage0_iter28 : BOOLEAN;
signal ap_block_state89_pp0_stage0_iter29 : BOOLEAN;
signal ap_block_state92_pp0_stage0_iter30 : BOOLEAN;
signal ap_block_state95_pp0_stage0_iter31 : BOOLEAN;
signal ap_block_state98_pp0_stage0_iter32 : BOOLEAN;
signal ap_block_state101_pp0_stage0_iter33 : BOOLEAN;
signal ap_block_state104_pp0_stage0_iter34 : BOOLEAN;
signal ap_block_state107_pp0_stage0_iter35 : BOOLEAN;
signal ap_block_state110_pp0_stage0_iter36 : BOOLEAN;
signal ap_block_state113_pp0_stage0_iter37 : BOOLEAN;
signal ap_block_state116_pp0_stage0_iter38 : BOOLEAN;
signal ap_block_state119_pp0_stage0_iter39 : BOOLEAN;
signal ap_block_state122_pp0_stage0_iter40 : BOOLEAN;
signal ap_block_state125_pp0_stage0_iter41 : BOOLEAN;
signal ap_block_state128_pp0_stage0_iter42 : BOOLEAN;
signal ap_block_state131_pp0_stage0_iter43 : BOOLEAN;
signal ap_block_state134_pp0_stage0_iter44 : BOOLEAN;
signal ap_block_state137_pp0_stage0_iter45 : BOOLEAN;
signal ap_block_state140_pp0_stage0_iter46 : BOOLEAN;
signal ap_block_state143_pp0_stage0_iter47 : BOOLEAN;
signal ap_block_state146_pp0_stage0_iter48 : BOOLEAN;
signal ap_block_state149_pp0_stage0_iter49 : BOOLEAN;
signal ap_block_state152_pp0_stage0_iter50 : BOOLEAN;
signal ap_block_state155_pp0_stage0_iter51 : BOOLEAN;
signal ap_block_state158_pp0_stage0_iter52 : BOOLEAN;
signal ap_block_state161_pp0_stage0_iter53 : BOOLEAN;
signal ap_block_state164_pp0_stage0_iter54 : BOOLEAN;
signal ap_block_state167_pp0_stage0_iter55 : BOOLEAN;
signal ap_block_state170_pp0_stage0_iter56 : BOOLEAN;
signal ap_block_state173_pp0_stage0_iter57 : BOOLEAN;
signal ap_block_state176_pp0_stage0_iter58 : BOOLEAN;
signal ap_block_state179_pp0_stage0_iter59 : BOOLEAN;
signal ap_block_state182_pp0_stage0_iter60 : BOOLEAN;
signal ap_block_state185_pp0_stage0_iter61 : BOOLEAN;
signal ap_block_state188_pp0_stage0_iter62 : BOOLEAN;
signal ap_block_state191_pp0_stage0_iter63 : BOOLEAN;
signal ap_block_state194_pp0_stage0_iter64 : BOOLEAN;
signal ap_block_state197_pp0_stage0_iter65 : BOOLEAN;
signal ap_block_state200_pp0_stage0_iter66 : BOOLEAN;
signal ap_block_state203_pp0_stage0_iter67 : BOOLEAN;
signal ap_block_state206_pp0_stage0_iter68 : BOOLEAN;
signal ap_block_state209_pp0_stage0_iter69 : BOOLEAN;
signal ap_block_state212_pp0_stage0_iter70 : BOOLEAN;
signal ap_block_state215_pp0_stage0_iter71 : BOOLEAN;
signal ap_block_state218_pp0_stage0_iter72 : BOOLEAN;
signal ap_block_state221_pp0_stage0_iter73 : BOOLEAN;
signal ap_block_state224_pp0_stage0_iter74 : BOOLEAN;
signal ap_block_state227_pp0_stage0_iter75 : BOOLEAN;
signal ap_block_state230_pp0_stage0_iter76 : BOOLEAN;
signal ap_block_state233_pp0_stage0_iter77 : BOOLEAN;
signal ap_block_state236_pp0_stage0_iter78 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter28_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter29_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter30_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter31_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter32_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter33_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter34_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter35_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter36_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter37_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter38_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter39_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter40_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter41_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter42_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter43_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter44_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter45_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter46_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter47_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter48_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter49_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter50_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter51_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter52_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter53_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter54_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter55_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter56_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter57_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter58_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter59_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter60_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter61_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter62_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter63_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter64_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter65_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter66_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter67_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter68_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter69_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter70_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter71_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter72_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter73_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter74_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter75_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter76_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter77_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter78_exitcond_flatten_reg_1202 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next_fu_1050_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_next_reg_1206 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal to_b_V_fu_1056_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal to_b_V_reg_1211 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_1_fu_1062_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1216 : STD_LOGIC_VECTOR (0 downto 0);
signal p_1_mid2_fu_1068_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal p_1_mid2_reg_1221 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_pp0_iter1_p_1_mid2_reg_1221 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_mid2_v_fu_1076_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_mid2_v_reg_1230 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state6_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state9_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state12_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state15_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state18_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state21_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state24_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state27_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state30_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_state33_pp0_stage1_iter10 : BOOLEAN;
signal ap_block_state36_pp0_stage1_iter11 : BOOLEAN;
signal ap_block_state39_pp0_stage1_iter12 : BOOLEAN;
signal ap_block_state42_pp0_stage1_iter13 : BOOLEAN;
signal ap_block_state45_pp0_stage1_iter14 : BOOLEAN;
signal ap_block_state48_pp0_stage1_iter15 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter16 : BOOLEAN;
signal ap_block_state54_pp0_stage1_iter17 : BOOLEAN;
signal ap_block_state57_pp0_stage1_iter18 : BOOLEAN;
signal ap_block_state60_pp0_stage1_iter19 : BOOLEAN;
signal ap_block_state63_pp0_stage1_iter20 : BOOLEAN;
signal ap_block_state66_pp0_stage1_iter21 : BOOLEAN;
signal ap_block_state69_pp0_stage1_iter22 : BOOLEAN;
signal ap_block_state72_pp0_stage1_iter23 : BOOLEAN;
signal ap_block_state75_pp0_stage1_iter24 : BOOLEAN;
signal ap_block_state78_pp0_stage1_iter25 : BOOLEAN;
signal ap_block_state81_pp0_stage1_iter26 : BOOLEAN;
signal ap_block_state84_pp0_stage1_iter27 : BOOLEAN;
signal ap_block_state87_pp0_stage1_iter28 : BOOLEAN;
signal ap_block_state90_pp0_stage1_iter29 : BOOLEAN;
signal ap_block_state93_pp0_stage1_iter30 : BOOLEAN;
signal ap_block_state96_pp0_stage1_iter31 : BOOLEAN;
signal ap_block_state99_pp0_stage1_iter32 : BOOLEAN;
signal ap_block_state102_pp0_stage1_iter33 : BOOLEAN;
signal ap_block_state105_pp0_stage1_iter34 : BOOLEAN;
signal ap_block_state108_pp0_stage1_iter35 : BOOLEAN;
signal ap_block_state111_pp0_stage1_iter36 : BOOLEAN;
signal ap_block_state114_pp0_stage1_iter37 : BOOLEAN;
signal ap_block_state117_pp0_stage1_iter38 : BOOLEAN;
signal ap_block_state120_pp0_stage1_iter39 : BOOLEAN;
signal ap_block_state123_pp0_stage1_iter40 : BOOLEAN;
signal ap_block_state126_pp0_stage1_iter41 : BOOLEAN;
signal ap_block_state129_pp0_stage1_iter42 : BOOLEAN;
signal ap_block_state132_pp0_stage1_iter43 : BOOLEAN;
signal ap_block_state135_pp0_stage1_iter44 : BOOLEAN;
signal ap_block_state138_pp0_stage1_iter45 : BOOLEAN;
signal ap_block_state141_pp0_stage1_iter46 : BOOLEAN;
signal ap_block_state144_pp0_stage1_iter47 : BOOLEAN;
signal ap_block_state147_pp0_stage1_iter48 : BOOLEAN;
signal ap_block_state150_pp0_stage1_iter49 : BOOLEAN;
signal ap_block_state153_pp0_stage1_iter50 : BOOLEAN;
signal ap_block_state156_pp0_stage1_iter51 : BOOLEAN;
signal ap_block_state159_pp0_stage1_iter52 : BOOLEAN;
signal ap_block_state162_pp0_stage1_iter53 : BOOLEAN;
signal ap_block_state165_pp0_stage1_iter54 : BOOLEAN;
signal ap_block_state168_pp0_stage1_iter55 : BOOLEAN;
signal ap_block_state171_pp0_stage1_iter56 : BOOLEAN;
signal ap_block_state174_pp0_stage1_iter57 : BOOLEAN;
signal ap_block_state177_pp0_stage1_iter58 : BOOLEAN;
signal ap_block_state180_pp0_stage1_iter59 : BOOLEAN;
signal ap_block_state183_pp0_stage1_iter60 : BOOLEAN;
signal ap_block_state186_pp0_stage1_iter61 : BOOLEAN;
signal ap_block_state189_pp0_stage1_iter62 : BOOLEAN;
signal ap_block_state192_pp0_stage1_iter63 : BOOLEAN;
signal ap_block_state195_pp0_stage1_iter64 : BOOLEAN;
signal ap_block_state198_pp0_stage1_iter65 : BOOLEAN;
signal ap_block_state201_pp0_stage1_iter66 : BOOLEAN;
signal ap_block_state204_pp0_stage1_iter67 : BOOLEAN;
signal ap_block_state207_pp0_stage1_iter68 : BOOLEAN;
signal ap_block_state210_pp0_stage1_iter69 : BOOLEAN;
signal ap_block_state213_pp0_stage1_iter70 : BOOLEAN;
signal ap_block_state216_pp0_stage1_iter71 : BOOLEAN;
signal ap_block_state219_pp0_stage1_iter72 : BOOLEAN;
signal ap_block_state222_pp0_stage1_iter73 : BOOLEAN;
signal ap_block_state225_pp0_stage1_iter74 : BOOLEAN;
signal ap_block_state228_pp0_stage1_iter75 : BOOLEAN;
signal ap_block_state231_pp0_stage1_iter76 : BOOLEAN;
signal ap_block_state234_pp0_stage1_iter77 : BOOLEAN;
signal ap_block_state237_pp0_stage1_iter78 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_mid2_v_reg_1230 : STD_LOGIC_VECTOR (6 downto 0);
signal lhs_V_cast1_fu_1092_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal lhs_V_cast1_reg_1273 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_V_fu_1095_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal row_b_V_reg_1278 : STD_LOGIC_VECTOR (1 downto 0);
signal r_V_1_0_2_fu_1100_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal r_V_1_0_2_reg_1284 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_mid2_fu_1106_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_mid2_reg_1289 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state7_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state10_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state13_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state16_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state19_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state22_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state25_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state28_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_state31_pp0_stage2_iter9 : BOOLEAN;
signal ap_block_state34_pp0_stage2_iter10 : BOOLEAN;
signal ap_block_state37_pp0_stage2_iter11 : BOOLEAN;
signal ap_block_state40_pp0_stage2_iter12 : BOOLEAN;
signal ap_block_state43_pp0_stage2_iter13 : BOOLEAN;
signal ap_block_state46_pp0_stage2_iter14 : BOOLEAN;
signal ap_block_state49_pp0_stage2_iter15 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter16 : BOOLEAN;
signal ap_block_state55_pp0_stage2_iter17 : BOOLEAN;
signal ap_block_state58_pp0_stage2_iter18 : BOOLEAN;
signal ap_block_state61_pp0_stage2_iter19 : BOOLEAN;
signal ap_block_state64_pp0_stage2_iter20 : BOOLEAN;
signal ap_block_state67_pp0_stage2_iter21 : BOOLEAN;
signal ap_block_state70_pp0_stage2_iter22 : BOOLEAN;
signal ap_block_state73_pp0_stage2_iter23 : BOOLEAN;
signal ap_block_state76_pp0_stage2_iter24 : BOOLEAN;
signal ap_block_state79_pp0_stage2_iter25 : BOOLEAN;
signal ap_block_state82_pp0_stage2_iter26 : BOOLEAN;
signal ap_block_state85_pp0_stage2_iter27 : BOOLEAN;
signal ap_block_state88_pp0_stage2_iter28 : BOOLEAN;
signal ap_block_state91_pp0_stage2_iter29 : BOOLEAN;
signal ap_block_state94_pp0_stage2_iter30 : BOOLEAN;
signal ap_block_state97_pp0_stage2_iter31 : BOOLEAN;
signal ap_block_state100_pp0_stage2_iter32 : BOOLEAN;
signal ap_block_state103_pp0_stage2_iter33 : BOOLEAN;
signal ap_block_state106_pp0_stage2_iter34 : BOOLEAN;
signal ap_block_state109_pp0_stage2_iter35 : BOOLEAN;
signal ap_block_state112_pp0_stage2_iter36 : BOOLEAN;
signal ap_block_state115_pp0_stage2_iter37 : BOOLEAN;
signal ap_block_state118_pp0_stage2_iter38 : BOOLEAN;
signal ap_block_state121_pp0_stage2_iter39 : BOOLEAN;
signal ap_block_state124_pp0_stage2_iter40 : BOOLEAN;
signal ap_block_state127_pp0_stage2_iter41 : BOOLEAN;
signal ap_block_state130_pp0_stage2_iter42 : BOOLEAN;
signal ap_block_state133_pp0_stage2_iter43 : BOOLEAN;
signal ap_block_state136_pp0_stage2_iter44 : BOOLEAN;
signal ap_block_state139_pp0_stage2_iter45 : BOOLEAN;
signal ap_block_state142_pp0_stage2_iter46 : BOOLEAN;
signal ap_block_state145_pp0_stage2_iter47 : BOOLEAN;
signal ap_block_state148_pp0_stage2_iter48 : BOOLEAN;
signal ap_block_state151_pp0_stage2_iter49 : BOOLEAN;
signal ap_block_state154_pp0_stage2_iter50 : BOOLEAN;
signal ap_block_state157_pp0_stage2_iter51 : BOOLEAN;
signal ap_block_state160_pp0_stage2_iter52 : BOOLEAN;
signal ap_block_state163_pp0_stage2_iter53 : BOOLEAN;
signal ap_block_state166_pp0_stage2_iter54 : BOOLEAN;
signal ap_block_state169_pp0_stage2_iter55 : BOOLEAN;
signal ap_block_state172_pp0_stage2_iter56 : BOOLEAN;
signal ap_block_state175_pp0_stage2_iter57 : BOOLEAN;
signal ap_block_state178_pp0_stage2_iter58 : BOOLEAN;
signal ap_block_state181_pp0_stage2_iter59 : BOOLEAN;
signal ap_block_state184_pp0_stage2_iter60 : BOOLEAN;
signal ap_block_state187_pp0_stage2_iter61 : BOOLEAN;
signal ap_block_state190_pp0_stage2_iter62 : BOOLEAN;
signal ap_block_state193_pp0_stage2_iter63 : BOOLEAN;
signal ap_block_state196_pp0_stage2_iter64 : BOOLEAN;
signal ap_block_state199_pp0_stage2_iter65 : BOOLEAN;
signal ap_block_state202_pp0_stage2_iter66 : BOOLEAN;
signal ap_block_state205_pp0_stage2_iter67 : BOOLEAN;
signal ap_block_state208_pp0_stage2_iter68 : BOOLEAN;
signal ap_block_state211_pp0_stage2_iter69 : BOOLEAN;
signal ap_block_state214_pp0_stage2_iter70 : BOOLEAN;
signal ap_block_state217_pp0_stage2_iter71 : BOOLEAN;
signal ap_block_state220_pp0_stage2_iter72 : BOOLEAN;
signal ap_block_state223_pp0_stage2_iter73 : BOOLEAN;
signal ap_block_state226_pp0_stage2_iter74 : BOOLEAN;
signal ap_block_state229_pp0_stage2_iter75 : BOOLEAN;
signal ap_block_state232_pp0_stage2_iter76 : BOOLEAN;
signal ap_block_state235_pp0_stage2_iter77 : BOOLEAN;
signal ap_block_state238_pp0_stage2_iter78 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal bufi_0_load_reg_1354 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_reg_1359 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_reg_1365 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_load_reg_1372 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_reg_1379 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_1_0_3_fu_1138_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal r_V_1_0_3_reg_1456 : STD_LOGIC_VECTOR (2 downto 0);
signal bufi_5_load_reg_1461 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_reg_1467 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_0_load_reg_1512 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_1_load_reg_1519 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_2_load_reg_1526 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_3_load_reg_1533 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_4_load_reg_1540 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_0_load_reg_1547 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_1_reg_1554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal bufw_1_1_load_reg_1559 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_1_reg_1566 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_2_load_reg_1572 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_1_reg_1579 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_3_load_reg_1586 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_load_1_reg_1592 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_1_reg_1599 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_2_reg_1606 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_2_reg_1611 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_2_reg_1617 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_load_2_reg_1624 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_2_reg_1631 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_load_1_reg_1673 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_load_2_reg_1679 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_1_reg_1685 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_2_reg_1690 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_4_load_reg_1735 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_0_load_reg_1742 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_1_load_reg_1749 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_2_load_reg_1756 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_3_load_reg_1763 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_4_load_reg_1770 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_0_load_reg_1777 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_3_reg_1784 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_1_load_reg_1789 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_3_reg_1795 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_3_reg_1801 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_load_3_reg_1808 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_3_reg_1815 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_load_3_reg_1857 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_3_reg_1863 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_2_load_reg_1868 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_3_load_reg_1875 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_4_load_reg_1882 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_0_load_reg_1889 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_4_reg_1896 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_1_load_reg_1901 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_4_reg_1908 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_2_load_reg_1914 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_4_reg_1921 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_3_load_reg_1928 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_load_4_reg_1935 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_4_load_reg_1942 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_load_4_reg_1949 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_load_4_reg_1956 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_load_4_reg_1962 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_1190_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_reg_1967 : STD_LOGIC_VECTOR (8 downto 0);
signal bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter24_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter25_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter26_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter27_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter28_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter29_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter30_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter31_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter32_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter33_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter34_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter35_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter36_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter37_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter38_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter39_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter40_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter41_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter42_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter43_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter44_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter45_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter46_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter47_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter48_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter49_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter50_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter51_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter52_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter53_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter54_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter55_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter56_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter57_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter58_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter59_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter60_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter61_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter62_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter63_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter64_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter65_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter66_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter67_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter68_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter69_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter70_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter71_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter72_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter73_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter74_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter75_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter76_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter77_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter78_bufo_0_addr_reg_1972 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter24_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter25_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter26_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter27_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter28_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter29_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter30_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter31_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter32_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter33_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter34_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter35_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter36_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter37_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter38_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter39_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter40_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter41_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter42_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter43_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter44_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter45_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter46_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter47_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter48_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter49_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter50_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter51_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter52_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter53_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter54_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter55_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter56_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter57_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter58_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter59_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter60_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter61_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter62_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter63_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter64_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter65_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter66_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter67_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter68_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter69_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter70_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter71_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter72_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter73_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter74_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter75_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter76_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter77_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter78_bufo_1_addr_reg_1978 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter24_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter25_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter26_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter27_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter28_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter29_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter30_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter31_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter32_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter33_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter34_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter35_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter36_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter37_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter38_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter39_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter40_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter41_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter42_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter43_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter44_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter45_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter46_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter47_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter48_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter49_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter50_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter51_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter52_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter53_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter54_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter55_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter56_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter57_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter58_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter59_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter60_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter61_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter62_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter63_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter64_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter65_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter66_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter67_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter68_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter69_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter70_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter71_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter72_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter73_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter74_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter75_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter76_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter77_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter78_bufo_2_addr_reg_1984 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_0_load_reg_1990 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal grp_fu_944_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_reg_1995 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_948_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_0_1_reg_2000 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_952_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_956_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_960_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_964_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_1_reg_2020 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_968_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_972_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_976_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_load_reg_2040 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_980_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_reg_2045 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_984_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_0_1_reg_2050 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_988_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_992_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_996_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1000_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_1_reg_2070 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1004_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1008_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_load_reg_2085 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1012_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_reg_2090 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1016_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_0_1_reg_2095 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1020_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1024_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1028_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1032_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_1_reg_2115 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1036_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1040_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_2_reg_2135 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_3_reg_2160 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_2_reg_2180 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_3_reg_2205 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_2_reg_2225 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_3_reg_2250 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_0_4_reg_2270 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_1_4_reg_2310 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_2_4_reg_2355 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_844_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_reg_2380 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal grp_fu_848_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_reg_2385 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_852_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_reg_2390 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_856_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_0_1_reg_2395 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal grp_fu_860_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_0_1_reg_2400 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_864_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_0_1_reg_2405 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_868_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_0_2_reg_2410 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal grp_fu_872_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_0_2_reg_2415 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_876_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_0_2_reg_2420 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_880_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_0_3_reg_2425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal grp_fu_884_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_0_3_reg_2430 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_888_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_0_3_reg_2435 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_892_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_0_4_reg_2440 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
signal grp_fu_896_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_0_4_reg_2445 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_900_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_0_4_reg_2450 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_904_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_1_reg_2455 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
signal grp_fu_908_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_1_reg_2460 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_912_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_1_reg_2465 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_916_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_1_1_reg_2470 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
signal grp_fu_920_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_1_1_reg_2475 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_924_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_1_1_reg_2480 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_928_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_1_2_reg_2485 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter26 : STD_LOGIC := '0';
signal grp_fu_932_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_1_1_2_reg_2490 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_936_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_1_2_reg_2495 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_940_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_1_3_reg_2500 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter29 : STD_LOGIC := '0';
signal temp_2_1_1_3_reg_2505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter30 : STD_LOGIC := '0';
signal temp_2_2_1_3_reg_2510 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_1_4_reg_2515 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter33 : STD_LOGIC := '0';
signal temp_2_1_1_4_reg_2520 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_1_4_reg_2525 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_2_reg_2530 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter36 : STD_LOGIC := '0';
signal temp_2_1_2_reg_2535 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_2_reg_2540 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_2_1_reg_2545 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter39 : STD_LOGIC := '0';
signal temp_2_1_2_1_reg_2550 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_2_1_reg_2555 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_2_2_reg_2560 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter42 : STD_LOGIC := '0';
signal temp_2_1_2_2_reg_2565 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_2_2_reg_2570 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_2_3_reg_2575 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter45 : STD_LOGIC := '0';
signal temp_2_1_2_3_reg_2580 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_2_3_reg_2585 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_2_4_reg_2590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter48 : STD_LOGIC := '0';
signal temp_2_1_2_4_reg_2595 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_2_4_reg_2600 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_3_reg_2605 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter51 : STD_LOGIC := '0';
signal temp_2_1_3_reg_2610 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_3_reg_2615 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_3_1_reg_2620 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter54 : STD_LOGIC := '0';
signal temp_2_1_3_1_reg_2625 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_3_1_reg_2630 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_3_2_reg_2635 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter57 : STD_LOGIC := '0';
signal temp_2_1_3_2_reg_2640 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_3_2_reg_2645 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_3_3_reg_2650 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter60 : STD_LOGIC := '0';
signal temp_2_1_3_3_reg_2655 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_3_3_reg_2660 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_3_4_reg_2665 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter63 : STD_LOGIC := '0';
signal temp_2_1_3_4_reg_2670 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_3_4_reg_2675 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_4_reg_2680 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter66 : STD_LOGIC := '0';
signal temp_2_1_4_reg_2685 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_4_reg_2690 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_4_1_reg_2695 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter69 : STD_LOGIC := '0';
signal temp_2_1_4_1_reg_2700 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_4_1_reg_2705 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_4_2_reg_2710 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter72 : STD_LOGIC := '0';
signal temp_2_1_4_2_reg_2715 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_4_2_reg_2720 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_4_3_reg_2725 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter75 : STD_LOGIC := '0';
signal temp_2_1_4_3_reg_2730 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_4_3_reg_2735 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_0_4_4_reg_2740 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter78 : STD_LOGIC := '0';
signal temp_2_1_4_4_reg_2745 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_2_4_4_reg_2750 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter25 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter27 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter28 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter31 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter32 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter34 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter35 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter37 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter38 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter40 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter41 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter43 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter44 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter46 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter47 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter49 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter50 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter52 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter53 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter55 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter56 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter58 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter59 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter61 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter62 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter64 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter65 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter67 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter68 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter70 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter71 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter73 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter74 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter76 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter77 : STD_LOGIC := '0';
signal indvar_flatten_phi_fu_814_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal p_s_phi_fu_825_p4 : STD_LOGIC_VECTOR (6 downto 0);
signal p_1_phi_fu_837_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_3_fu_1082_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal tmp_2_0_1_fu_1118_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_0_2_fu_1128_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_0_3_fu_1143_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_0_4_fu_1160_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_cast_fu_1196_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal bufi_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_3_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_4_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_5_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_6_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_844_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_844_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_848_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_848_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_852_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_852_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_856_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_856_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_860_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_860_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_864_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_868_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_868_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_872_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_872_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_876_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_880_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_880_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_884_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_884_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_888_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_892_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_892_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_896_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_900_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_900_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_904_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_904_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_908_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_912_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_912_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_916_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_916_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_920_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_920_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_924_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_924_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_928_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_928_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_932_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_932_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_936_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_936_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_940_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_940_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_944_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_944_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_948_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_948_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_952_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_956_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_956_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_960_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_960_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_964_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_968_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_968_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_972_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_972_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_976_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_976_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_980_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_980_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_984_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_984_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_988_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_988_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_992_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_996_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_996_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1000_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1000_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1004_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1004_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1008_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1008_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1012_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1012_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1016_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1016_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1020_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1020_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1024_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1024_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1028_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1028_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1032_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1032_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1036_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1040_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1040_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_1_0_s_fu_1153_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_fu_1174_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_mid2_cast_fu_1171_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_fu_1181_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_cast_fu_1187_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state239 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state239 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_844_p0,
din1 => grp_fu_844_p1,
ce => ap_const_logic_1,
dout => grp_fu_844_p2);
convolve_kernel_fbkb_U2 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_848_p0,
din1 => grp_fu_848_p1,
ce => ap_const_logic_1,
dout => grp_fu_848_p2);
convolve_kernel_fbkb_U3 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_852_p0,
din1 => grp_fu_852_p1,
ce => ap_const_logic_1,
dout => grp_fu_852_p2);
convolve_kernel_fbkb_U4 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_856_p0,
din1 => grp_fu_856_p1,
ce => ap_const_logic_1,
dout => grp_fu_856_p2);
convolve_kernel_fbkb_U5 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_860_p0,
din1 => grp_fu_860_p1,
ce => ap_const_logic_1,
dout => grp_fu_860_p2);
convolve_kernel_fbkb_U6 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_864_p0,
din1 => grp_fu_864_p1,
ce => ap_const_logic_1,
dout => grp_fu_864_p2);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_868_p0,
din1 => grp_fu_868_p1,
ce => ap_const_logic_1,
dout => grp_fu_868_p2);
convolve_kernel_fbkb_U8 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_872_p0,
din1 => grp_fu_872_p1,
ce => ap_const_logic_1,
dout => grp_fu_872_p2);
convolve_kernel_fbkb_U9 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_876_p0,
din1 => grp_fu_876_p1,
ce => ap_const_logic_1,
dout => grp_fu_876_p2);
convolve_kernel_fbkb_U10 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_880_p0,
din1 => grp_fu_880_p1,
ce => ap_const_logic_1,
dout => grp_fu_880_p2);
convolve_kernel_fbkb_U11 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_884_p0,
din1 => grp_fu_884_p1,
ce => ap_const_logic_1,
dout => grp_fu_884_p2);
convolve_kernel_fbkb_U12 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_888_p0,
din1 => grp_fu_888_p1,
ce => ap_const_logic_1,
dout => grp_fu_888_p2);
convolve_kernel_fbkb_U13 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_892_p0,
din1 => grp_fu_892_p1,
ce => ap_const_logic_1,
dout => grp_fu_892_p2);
convolve_kernel_fbkb_U14 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_896_p0,
din1 => grp_fu_896_p1,
ce => ap_const_logic_1,
dout => grp_fu_896_p2);
convolve_kernel_fbkb_U15 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_900_p0,
din1 => grp_fu_900_p1,
ce => ap_const_logic_1,
dout => grp_fu_900_p2);
convolve_kernel_fbkb_U16 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_904_p0,
din1 => grp_fu_904_p1,
ce => ap_const_logic_1,
dout => grp_fu_904_p2);
convolve_kernel_fbkb_U17 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_908_p0,
din1 => grp_fu_908_p1,
ce => ap_const_logic_1,
dout => grp_fu_908_p2);
convolve_kernel_fbkb_U18 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_912_p0,
din1 => grp_fu_912_p1,
ce => ap_const_logic_1,
dout => grp_fu_912_p2);
convolve_kernel_fbkb_U19 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_916_p0,
din1 => grp_fu_916_p1,
ce => ap_const_logic_1,
dout => grp_fu_916_p2);
convolve_kernel_fbkb_U20 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_920_p0,
din1 => grp_fu_920_p1,
ce => ap_const_logic_1,
dout => grp_fu_920_p2);
convolve_kernel_fbkb_U21 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_924_p0,
din1 => grp_fu_924_p1,
ce => ap_const_logic_1,
dout => grp_fu_924_p2);
convolve_kernel_fbkb_U22 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_928_p0,
din1 => grp_fu_928_p1,
ce => ap_const_logic_1,
dout => grp_fu_928_p2);
convolve_kernel_fbkb_U23 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_932_p0,
din1 => grp_fu_932_p1,
ce => ap_const_logic_1,
dout => grp_fu_932_p2);
convolve_kernel_fbkb_U24 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_936_p0,
din1 => grp_fu_936_p1,
ce => ap_const_logic_1,
dout => grp_fu_936_p2);
convolve_kernel_fbkb_U25 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_940_p0,
din1 => grp_fu_940_p1,
ce => ap_const_logic_1,
dout => grp_fu_940_p2);
convolve_kernel_fcud_U26 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_944_p0,
din1 => grp_fu_944_p1,
ce => ap_const_logic_1,
dout => grp_fu_944_p2);
convolve_kernel_fcud_U27 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_948_p0,
din1 => grp_fu_948_p1,
ce => ap_const_logic_1,
dout => grp_fu_948_p2);
convolve_kernel_fcud_U28 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_952_p0,
din1 => grp_fu_952_p1,
ce => ap_const_logic_1,
dout => grp_fu_952_p2);
convolve_kernel_fcud_U29 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_956_p0,
din1 => grp_fu_956_p1,
ce => ap_const_logic_1,
dout => grp_fu_956_p2);
convolve_kernel_fcud_U30 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_960_p0,
din1 => grp_fu_960_p1,
ce => ap_const_logic_1,
dout => grp_fu_960_p2);
convolve_kernel_fcud_U31 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_964_p0,
din1 => grp_fu_964_p1,
ce => ap_const_logic_1,
dout => grp_fu_964_p2);
convolve_kernel_fcud_U32 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_968_p0,
din1 => grp_fu_968_p1,
ce => ap_const_logic_1,
dout => grp_fu_968_p2);
convolve_kernel_fcud_U33 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_972_p0,
din1 => grp_fu_972_p1,
ce => ap_const_logic_1,
dout => grp_fu_972_p2);
convolve_kernel_fcud_U34 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_976_p0,
din1 => grp_fu_976_p1,
ce => ap_const_logic_1,
dout => grp_fu_976_p2);
convolve_kernel_fcud_U35 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_980_p0,
din1 => grp_fu_980_p1,
ce => ap_const_logic_1,
dout => grp_fu_980_p2);
convolve_kernel_fcud_U36 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_984_p0,
din1 => grp_fu_984_p1,
ce => ap_const_logic_1,
dout => grp_fu_984_p2);
convolve_kernel_fcud_U37 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_988_p0,
din1 => grp_fu_988_p1,
ce => ap_const_logic_1,
dout => grp_fu_988_p2);
convolve_kernel_fcud_U38 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_992_p0,
din1 => grp_fu_992_p1,
ce => ap_const_logic_1,
dout => grp_fu_992_p2);
convolve_kernel_fcud_U39 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_996_p0,
din1 => grp_fu_996_p1,
ce => ap_const_logic_1,
dout => grp_fu_996_p2);
convolve_kernel_fcud_U40 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1000_p0,
din1 => grp_fu_1000_p1,
ce => ap_const_logic_1,
dout => grp_fu_1000_p2);
convolve_kernel_fcud_U41 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1004_p0,
din1 => grp_fu_1004_p1,
ce => ap_const_logic_1,
dout => grp_fu_1004_p2);
convolve_kernel_fcud_U42 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1008_p0,
din1 => grp_fu_1008_p1,
ce => ap_const_logic_1,
dout => grp_fu_1008_p2);
convolve_kernel_fcud_U43 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1012_p0,
din1 => grp_fu_1012_p1,
ce => ap_const_logic_1,
dout => grp_fu_1012_p2);
convolve_kernel_fcud_U44 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1016_p0,
din1 => grp_fu_1016_p1,
ce => ap_const_logic_1,
dout => grp_fu_1016_p2);
convolve_kernel_fcud_U45 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1020_p0,
din1 => grp_fu_1020_p1,
ce => ap_const_logic_1,
dout => grp_fu_1020_p2);
convolve_kernel_fcud_U46 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1024_p0,
din1 => grp_fu_1024_p1,
ce => ap_const_logic_1,
dout => grp_fu_1024_p2);
convolve_kernel_fcud_U47 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1028_p0,
din1 => grp_fu_1028_p1,
ce => ap_const_logic_1,
dout => grp_fu_1028_p2);
convolve_kernel_fcud_U48 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1032_p0,
din1 => grp_fu_1032_p1,
ce => ap_const_logic_1,
dout => grp_fu_1032_p2);
convolve_kernel_fcud_U49 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1036_p0,
din1 => grp_fu_1036_p1,
ce => ap_const_logic_1,
dout => grp_fu_1036_p2);
convolve_kernel_fcud_U50 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1040_p0,
din1 => grp_fu_1040_p1,
ce => ap_const_logic_1,
dout => grp_fu_1040_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter25 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter26 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter27 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter28 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter29 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter30 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter31 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter32 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter33 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter34 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter34 <= ap_enable_reg_pp0_iter33;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter35 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter35 <= ap_enable_reg_pp0_iter34;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter36 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter36 <= ap_enable_reg_pp0_iter35;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter37 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter37 <= ap_enable_reg_pp0_iter36;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter38 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter38 <= ap_enable_reg_pp0_iter37;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter39 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter39 <= ap_enable_reg_pp0_iter38;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter40 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter40 <= ap_enable_reg_pp0_iter39;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter41 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter41 <= ap_enable_reg_pp0_iter40;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter42 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter42 <= ap_enable_reg_pp0_iter41;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter43 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter42;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter44 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter44 <= ap_enable_reg_pp0_iter43;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter45 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter45 <= ap_enable_reg_pp0_iter44;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter46 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter46 <= ap_enable_reg_pp0_iter45;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter47 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter47 <= ap_enable_reg_pp0_iter46;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter48 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter48 <= ap_enable_reg_pp0_iter47;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter49 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter49 <= ap_enable_reg_pp0_iter48;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter50 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter50 <= ap_enable_reg_pp0_iter49;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter51 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter51 <= ap_enable_reg_pp0_iter50;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter52 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter52 <= ap_enable_reg_pp0_iter51;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter53_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter53 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter53 <= ap_enable_reg_pp0_iter52;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter54_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter54 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter54 <= ap_enable_reg_pp0_iter53;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter55_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter55 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter55 <= ap_enable_reg_pp0_iter54;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter56_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter56 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter56 <= ap_enable_reg_pp0_iter55;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter57_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter57 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter57 <= ap_enable_reg_pp0_iter56;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter58_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter58 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter58 <= ap_enable_reg_pp0_iter57;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter59_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter59 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter59 <= ap_enable_reg_pp0_iter58;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter60_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter60 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter60 <= ap_enable_reg_pp0_iter59;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter61_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter61 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter61 <= ap_enable_reg_pp0_iter60;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter62_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter62 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter62 <= ap_enable_reg_pp0_iter61;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter63_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter63 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter63 <= ap_enable_reg_pp0_iter62;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter64_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter64 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter64 <= ap_enable_reg_pp0_iter63;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter65_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter65 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter65 <= ap_enable_reg_pp0_iter64;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter66_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter66 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter66 <= ap_enable_reg_pp0_iter65;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter67_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter67 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter67 <= ap_enable_reg_pp0_iter66;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter68_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter68 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter68 <= ap_enable_reg_pp0_iter67;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter69_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter69 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter69 <= ap_enable_reg_pp0_iter68;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter70_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter70 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter70 <= ap_enable_reg_pp0_iter69;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter71_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter71 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter71 <= ap_enable_reg_pp0_iter70;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter72_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter72 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter72 <= ap_enable_reg_pp0_iter71;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter73_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter73 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter73 <= ap_enable_reg_pp0_iter72;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter74_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter74 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter74 <= ap_enable_reg_pp0_iter73;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter75_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter75 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter75 <= ap_enable_reg_pp0_iter74;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter76_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter76 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter76 <= ap_enable_reg_pp0_iter75;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter77_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter77 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter77 <= ap_enable_reg_pp0_iter76;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter78_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter78 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter78 <= ap_enable_reg_pp0_iter77;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter78 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
indvar_flatten_reg_810_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
indvar_flatten_reg_810 <= indvar_flatten_next_reg_1206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_810 <= ap_const_lv8_0;
end if;
end if;
end process;
p_1_reg_833_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
p_1_reg_833 <= row_b_V_reg_1278;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_1_reg_833 <= ap_const_lv2_0;
end if;
end if;
end process;
p_s_reg_821_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
p_s_reg_821 <= tmp_mid2_v_reg_1230;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_s_reg_821 <= ap_const_lv7_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter9_bufo_0_addr_reg_1972;
ap_reg_pp0_iter10_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter9_bufo_1_addr_reg_1978;
ap_reg_pp0_iter10_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter9_bufo_2_addr_reg_1984;
ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter10_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter9_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter10_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter9_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter10_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter9_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter11_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter10_bufo_0_addr_reg_1972;
ap_reg_pp0_iter11_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter10_bufo_1_addr_reg_1978;
ap_reg_pp0_iter11_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter10_bufo_2_addr_reg_1984;
ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter11_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter10_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter11_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter10_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter11_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter10_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter12_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter11_bufo_0_addr_reg_1972;
ap_reg_pp0_iter12_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter11_bufo_1_addr_reg_1978;
ap_reg_pp0_iter12_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter11_bufo_2_addr_reg_1984;
ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter12_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter11_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter12_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter11_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter12_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter11_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter13_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter12_bufo_0_addr_reg_1972;
ap_reg_pp0_iter13_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter12_bufo_1_addr_reg_1978;
ap_reg_pp0_iter13_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter12_bufo_2_addr_reg_1984;
ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter13_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter12_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter13_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter12_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter13_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter12_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter14_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter13_bufo_0_addr_reg_1972;
ap_reg_pp0_iter14_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter13_bufo_1_addr_reg_1978;
ap_reg_pp0_iter14_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter13_bufo_2_addr_reg_1984;
ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter14_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter13_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter14_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter13_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter14_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter13_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter15_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter14_bufo_0_addr_reg_1972;
ap_reg_pp0_iter15_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter14_bufo_1_addr_reg_1978;
ap_reg_pp0_iter15_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter14_bufo_2_addr_reg_1984;
ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter15_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter14_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter15_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter14_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter15_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter14_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter16_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter15_bufo_0_addr_reg_1972;
ap_reg_pp0_iter16_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter15_bufo_1_addr_reg_1978;
ap_reg_pp0_iter16_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter15_bufo_2_addr_reg_1984;
ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter16_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter15_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter16_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter15_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter16_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter15_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter17_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter16_bufo_0_addr_reg_1972;
ap_reg_pp0_iter17_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter16_bufo_1_addr_reg_1978;
ap_reg_pp0_iter17_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter16_bufo_2_addr_reg_1984;
ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter17_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter16_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter17_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter16_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter17_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter16_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter18_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter17_bufo_0_addr_reg_1972;
ap_reg_pp0_iter18_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter17_bufo_1_addr_reg_1978;
ap_reg_pp0_iter18_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter17_bufo_2_addr_reg_1984;
ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter18_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter17_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter18_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter17_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter18_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter17_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter19_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter18_bufo_0_addr_reg_1972;
ap_reg_pp0_iter19_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter18_bufo_1_addr_reg_1978;
ap_reg_pp0_iter19_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter18_bufo_2_addr_reg_1984;
ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter19_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter18_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter19_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter18_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter19_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter18_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter1_tmp_mid2_v_reg_1230 <= tmp_mid2_v_reg_1230;
ap_reg_pp0_iter20_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter19_bufo_0_addr_reg_1972;
ap_reg_pp0_iter20_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter19_bufo_1_addr_reg_1978;
ap_reg_pp0_iter20_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter19_bufo_2_addr_reg_1984;
ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter20_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter19_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter20_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter19_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter20_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter19_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter21_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter20_bufo_0_addr_reg_1972;
ap_reg_pp0_iter21_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter20_bufo_1_addr_reg_1978;
ap_reg_pp0_iter21_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter20_bufo_2_addr_reg_1984;
ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter21_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter20_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter21_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter20_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter21_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter20_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter22_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter21_bufo_0_addr_reg_1972;
ap_reg_pp0_iter22_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter21_bufo_1_addr_reg_1978;
ap_reg_pp0_iter22_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter21_bufo_2_addr_reg_1984;
ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter22_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter21_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter22_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter21_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter22_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter21_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter23_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter22_bufo_0_addr_reg_1972;
ap_reg_pp0_iter23_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter22_bufo_1_addr_reg_1978;
ap_reg_pp0_iter23_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter22_bufo_2_addr_reg_1984;
ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter23_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter22_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter23_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter22_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter23_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter22_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter24_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter23_bufo_0_addr_reg_1972;
ap_reg_pp0_iter24_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter23_bufo_1_addr_reg_1978;
ap_reg_pp0_iter24_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter23_bufo_2_addr_reg_1984;
ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter24_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter23_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter24_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter23_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter24_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter23_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter25_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter24_bufo_0_addr_reg_1972;
ap_reg_pp0_iter25_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter24_bufo_1_addr_reg_1978;
ap_reg_pp0_iter25_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter24_bufo_2_addr_reg_1984;
ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter25_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter24_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter25_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter24_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter25_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter24_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter26_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter25_bufo_0_addr_reg_1972;
ap_reg_pp0_iter26_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter25_bufo_1_addr_reg_1978;
ap_reg_pp0_iter26_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter25_bufo_2_addr_reg_1984;
ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter26_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter25_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter26_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter25_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter26_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter25_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter27_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter26_bufo_0_addr_reg_1972;
ap_reg_pp0_iter27_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter26_bufo_1_addr_reg_1978;
ap_reg_pp0_iter27_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter26_bufo_2_addr_reg_1984;
ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter27_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter26_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter27_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter26_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter27_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter26_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter28_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter27_bufo_0_addr_reg_1972;
ap_reg_pp0_iter28_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter27_bufo_1_addr_reg_1978;
ap_reg_pp0_iter28_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter27_bufo_2_addr_reg_1984;
ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter28_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter27_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter28_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter27_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter28_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter27_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter29_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter28_bufo_0_addr_reg_1972;
ap_reg_pp0_iter29_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter28_bufo_1_addr_reg_1978;
ap_reg_pp0_iter29_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter28_bufo_2_addr_reg_1984;
ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter29_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter28_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter29_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter28_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter29_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter28_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter30_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter29_bufo_0_addr_reg_1972;
ap_reg_pp0_iter30_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter29_bufo_1_addr_reg_1978;
ap_reg_pp0_iter30_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter29_bufo_2_addr_reg_1984;
ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter30_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter29_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter30_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter29_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter30_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter29_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter31_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter30_bufo_0_addr_reg_1972;
ap_reg_pp0_iter31_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter30_bufo_1_addr_reg_1978;
ap_reg_pp0_iter31_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter30_bufo_2_addr_reg_1984;
ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter31_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter30_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter31_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter30_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter31_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter30_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter32_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter31_bufo_0_addr_reg_1972;
ap_reg_pp0_iter32_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter31_bufo_1_addr_reg_1978;
ap_reg_pp0_iter32_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter31_bufo_2_addr_reg_1984;
ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter32_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter31_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter32_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter31_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter32_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter31_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter33_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter32_bufo_0_addr_reg_1972;
ap_reg_pp0_iter33_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter32_bufo_1_addr_reg_1978;
ap_reg_pp0_iter33_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter32_bufo_2_addr_reg_1984;
ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter33_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter32_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter33_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter32_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter33_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter32_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter34_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter33_bufo_0_addr_reg_1972;
ap_reg_pp0_iter34_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter33_bufo_1_addr_reg_1978;
ap_reg_pp0_iter34_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter33_bufo_2_addr_reg_1984;
ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter34_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter33_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter34_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter33_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter34_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter33_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter35_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter34_bufo_0_addr_reg_1972;
ap_reg_pp0_iter35_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter34_bufo_1_addr_reg_1978;
ap_reg_pp0_iter35_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter34_bufo_2_addr_reg_1984;
ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter35_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter34_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter35_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter34_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter35_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter34_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter36_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter35_bufo_0_addr_reg_1972;
ap_reg_pp0_iter36_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter35_bufo_1_addr_reg_1978;
ap_reg_pp0_iter36_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter35_bufo_2_addr_reg_1984;
ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter36_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter35_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter36_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter35_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter36_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter35_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter37_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter36_bufo_0_addr_reg_1972;
ap_reg_pp0_iter37_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter36_bufo_1_addr_reg_1978;
ap_reg_pp0_iter37_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter36_bufo_2_addr_reg_1984;
ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter37_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter36_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter37_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter36_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter37_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter36_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter38_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter37_bufo_0_addr_reg_1972;
ap_reg_pp0_iter38_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter37_bufo_1_addr_reg_1978;
ap_reg_pp0_iter38_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter37_bufo_2_addr_reg_1984;
ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter38_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter37_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter38_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter37_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter38_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter37_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter39_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter38_bufo_0_addr_reg_1972;
ap_reg_pp0_iter39_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter38_bufo_1_addr_reg_1978;
ap_reg_pp0_iter39_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter38_bufo_2_addr_reg_1984;
ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter39_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter38_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter39_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter38_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter39_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter38_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter3_bufo_0_addr_reg_1972 <= bufo_0_addr_reg_1972;
ap_reg_pp0_iter3_bufo_1_addr_reg_1978 <= bufo_1_addr_reg_1978;
ap_reg_pp0_iter3_bufo_2_addr_reg_1984 <= bufo_2_addr_reg_1984;
ap_reg_pp0_iter40_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter39_bufo_0_addr_reg_1972;
ap_reg_pp0_iter40_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter39_bufo_1_addr_reg_1978;
ap_reg_pp0_iter40_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter39_bufo_2_addr_reg_1984;
ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter40_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter39_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter40_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter39_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter40_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter39_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter41_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter40_bufo_0_addr_reg_1972;
ap_reg_pp0_iter41_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter40_bufo_1_addr_reg_1978;
ap_reg_pp0_iter41_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter40_bufo_2_addr_reg_1984;
ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter41_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter40_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter41_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter40_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter41_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter40_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter42_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter41_bufo_0_addr_reg_1972;
ap_reg_pp0_iter42_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter41_bufo_1_addr_reg_1978;
ap_reg_pp0_iter42_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter41_bufo_2_addr_reg_1984;
ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter42_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter41_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter42_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter41_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter42_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter41_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter43_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter42_bufo_0_addr_reg_1972;
ap_reg_pp0_iter43_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter42_bufo_1_addr_reg_1978;
ap_reg_pp0_iter43_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter42_bufo_2_addr_reg_1984;
ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter43_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter42_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter43_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter42_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter43_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter42_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter44_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter43_bufo_0_addr_reg_1972;
ap_reg_pp0_iter44_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter43_bufo_1_addr_reg_1978;
ap_reg_pp0_iter44_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter43_bufo_2_addr_reg_1984;
ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter44_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter43_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter44_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter43_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter44_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter43_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter45_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter44_bufo_0_addr_reg_1972;
ap_reg_pp0_iter45_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter44_bufo_1_addr_reg_1978;
ap_reg_pp0_iter45_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter44_bufo_2_addr_reg_1984;
ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter45_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter44_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter45_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter44_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter45_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter44_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter46_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter45_bufo_0_addr_reg_1972;
ap_reg_pp0_iter46_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter45_bufo_1_addr_reg_1978;
ap_reg_pp0_iter46_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter45_bufo_2_addr_reg_1984;
ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter46_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter45_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter46_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter45_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter46_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter45_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter47_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter46_bufo_0_addr_reg_1972;
ap_reg_pp0_iter47_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter46_bufo_1_addr_reg_1978;
ap_reg_pp0_iter47_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter46_bufo_2_addr_reg_1984;
ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter47_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter46_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter47_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter46_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter47_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter46_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter48_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter47_bufo_0_addr_reg_1972;
ap_reg_pp0_iter48_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter47_bufo_1_addr_reg_1978;
ap_reg_pp0_iter48_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter47_bufo_2_addr_reg_1984;
ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter48_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter47_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter48_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter47_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter48_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter47_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter49_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter48_bufo_0_addr_reg_1972;
ap_reg_pp0_iter49_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter48_bufo_1_addr_reg_1978;
ap_reg_pp0_iter49_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter48_bufo_2_addr_reg_1984;
ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter49_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter48_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter49_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter48_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter49_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter48_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter4_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter3_bufo_0_addr_reg_1972;
ap_reg_pp0_iter4_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter3_bufo_1_addr_reg_1978;
ap_reg_pp0_iter4_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter3_bufo_2_addr_reg_1984;
ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255 <= tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260 <= tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265 <= tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275 <= tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280 <= tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285 <= tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290 <= tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter4_tmp_10_0_4_reg_2270 <= tmp_10_0_4_reg_2270;
ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295 <= tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300 <= tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305 <= tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315 <= tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320 <= tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325 <= tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330 <= tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter4_tmp_10_1_4_reg_2310 <= tmp_10_1_4_reg_2310;
ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335 <= tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340 <= tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345 <= tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350 <= tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360 <= tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365 <= tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370 <= tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375 <= tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter4_tmp_10_2_4_reg_2355 <= tmp_10_2_4_reg_2355;
ap_reg_pp0_iter50_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter49_bufo_0_addr_reg_1972;
ap_reg_pp0_iter50_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter49_bufo_1_addr_reg_1978;
ap_reg_pp0_iter50_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter49_bufo_2_addr_reg_1984;
ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter50_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter49_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter50_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter49_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter50_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter49_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter51_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter50_bufo_0_addr_reg_1972;
ap_reg_pp0_iter51_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter50_bufo_1_addr_reg_1978;
ap_reg_pp0_iter51_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter50_bufo_2_addr_reg_1984;
ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter51_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter50_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter51_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter50_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter51_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter50_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter52_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter51_bufo_0_addr_reg_1972;
ap_reg_pp0_iter52_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter51_bufo_1_addr_reg_1978;
ap_reg_pp0_iter52_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter51_bufo_2_addr_reg_1984;
ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter52_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter51_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter52_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter51_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter52_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter51_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter53_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter52_bufo_0_addr_reg_1972;
ap_reg_pp0_iter53_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter52_bufo_1_addr_reg_1978;
ap_reg_pp0_iter53_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter52_bufo_2_addr_reg_1984;
ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter53_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter52_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter53_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter52_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter53_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter52_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter54_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter53_bufo_0_addr_reg_1972;
ap_reg_pp0_iter54_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter53_bufo_1_addr_reg_1978;
ap_reg_pp0_iter54_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter53_bufo_2_addr_reg_1984;
ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter54_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter53_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter54_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter53_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter54_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter53_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter55_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter54_bufo_0_addr_reg_1972;
ap_reg_pp0_iter55_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter54_bufo_1_addr_reg_1978;
ap_reg_pp0_iter55_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter54_bufo_2_addr_reg_1984;
ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter55_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter54_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter55_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter54_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter55_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter54_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter56_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter55_bufo_0_addr_reg_1972;
ap_reg_pp0_iter56_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter55_bufo_1_addr_reg_1978;
ap_reg_pp0_iter56_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter55_bufo_2_addr_reg_1984;
ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter56_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter55_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter56_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter55_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter56_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter55_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter57_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter56_bufo_0_addr_reg_1972;
ap_reg_pp0_iter57_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter56_bufo_1_addr_reg_1978;
ap_reg_pp0_iter57_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter56_bufo_2_addr_reg_1984;
ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter57_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter56_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter57_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter56_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter57_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter56_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter58_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter57_bufo_0_addr_reg_1972;
ap_reg_pp0_iter58_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter57_bufo_1_addr_reg_1978;
ap_reg_pp0_iter58_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter57_bufo_2_addr_reg_1984;
ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter58_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter57_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter58_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter57_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter58_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter57_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter59_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter58_bufo_0_addr_reg_1972;
ap_reg_pp0_iter59_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter58_bufo_1_addr_reg_1978;
ap_reg_pp0_iter59_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter58_bufo_2_addr_reg_1984;
ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter59_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter58_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter59_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter58_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter59_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter58_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter5_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter4_bufo_0_addr_reg_1972;
ap_reg_pp0_iter5_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter4_bufo_1_addr_reg_1978;
ap_reg_pp0_iter5_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter4_bufo_2_addr_reg_1984;
ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter5_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter4_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter5_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter4_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter5_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter4_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter60_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter59_bufo_0_addr_reg_1972;
ap_reg_pp0_iter60_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter59_bufo_1_addr_reg_1978;
ap_reg_pp0_iter60_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter59_bufo_2_addr_reg_1984;
ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter60_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter59_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter60_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter59_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter60_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter59_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter61_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter60_bufo_0_addr_reg_1972;
ap_reg_pp0_iter61_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter60_bufo_1_addr_reg_1978;
ap_reg_pp0_iter61_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter60_bufo_2_addr_reg_1984;
ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter61_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter60_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter61_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter60_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter61_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter60_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter62_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter61_bufo_0_addr_reg_1972;
ap_reg_pp0_iter62_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter61_bufo_1_addr_reg_1978;
ap_reg_pp0_iter62_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter61_bufo_2_addr_reg_1984;
ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter62_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter61_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter62_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter61_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter62_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter61_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter63_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter62_bufo_0_addr_reg_1972;
ap_reg_pp0_iter63_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter62_bufo_1_addr_reg_1978;
ap_reg_pp0_iter63_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter62_bufo_2_addr_reg_1984;
ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter63_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter62_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter63_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter62_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter63_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter62_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter64_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter63_bufo_0_addr_reg_1972;
ap_reg_pp0_iter64_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter63_bufo_1_addr_reg_1978;
ap_reg_pp0_iter64_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter63_bufo_2_addr_reg_1984;
ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter65_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter64_bufo_0_addr_reg_1972;
ap_reg_pp0_iter65_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter64_bufo_1_addr_reg_1978;
ap_reg_pp0_iter65_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter64_bufo_2_addr_reg_1984;
ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter66_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter65_bufo_0_addr_reg_1972;
ap_reg_pp0_iter66_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter65_bufo_1_addr_reg_1978;
ap_reg_pp0_iter66_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter65_bufo_2_addr_reg_1984;
ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter67_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter66_bufo_0_addr_reg_1972;
ap_reg_pp0_iter67_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter66_bufo_1_addr_reg_1978;
ap_reg_pp0_iter67_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter66_bufo_2_addr_reg_1984;
ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter68_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter67_bufo_0_addr_reg_1972;
ap_reg_pp0_iter68_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter67_bufo_1_addr_reg_1978;
ap_reg_pp0_iter68_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter67_bufo_2_addr_reg_1984;
ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter69_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter68_bufo_0_addr_reg_1972;
ap_reg_pp0_iter69_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter68_bufo_1_addr_reg_1978;
ap_reg_pp0_iter69_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter68_bufo_2_addr_reg_1984;
ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter6_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter5_bufo_0_addr_reg_1972;
ap_reg_pp0_iter6_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter5_bufo_1_addr_reg_1978;
ap_reg_pp0_iter6_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter5_bufo_2_addr_reg_1984;
ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter6_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter5_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter6_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter5_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter6_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter5_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter70_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter69_bufo_0_addr_reg_1972;
ap_reg_pp0_iter70_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter69_bufo_1_addr_reg_1978;
ap_reg_pp0_iter70_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter69_bufo_2_addr_reg_1984;
ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter71_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter70_bufo_0_addr_reg_1972;
ap_reg_pp0_iter71_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter70_bufo_1_addr_reg_1978;
ap_reg_pp0_iter71_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter70_bufo_2_addr_reg_1984;
ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter72_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter71_bufo_0_addr_reg_1972;
ap_reg_pp0_iter72_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter71_bufo_1_addr_reg_1978;
ap_reg_pp0_iter72_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter71_bufo_2_addr_reg_1984;
ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter73_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter72_bufo_0_addr_reg_1972;
ap_reg_pp0_iter73_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter72_bufo_1_addr_reg_1978;
ap_reg_pp0_iter73_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter72_bufo_2_addr_reg_1984;
ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter74_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter73_bufo_0_addr_reg_1972;
ap_reg_pp0_iter74_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter73_bufo_1_addr_reg_1978;
ap_reg_pp0_iter74_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter73_bufo_2_addr_reg_1984;
ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter75_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter74_bufo_0_addr_reg_1972;
ap_reg_pp0_iter75_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter74_bufo_1_addr_reg_1978;
ap_reg_pp0_iter75_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter74_bufo_2_addr_reg_1984;
ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter76_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter75_bufo_0_addr_reg_1972;
ap_reg_pp0_iter76_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter75_bufo_1_addr_reg_1978;
ap_reg_pp0_iter76_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter75_bufo_2_addr_reg_1984;
ap_reg_pp0_iter77_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter76_bufo_0_addr_reg_1972;
ap_reg_pp0_iter77_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter76_bufo_1_addr_reg_1978;
ap_reg_pp0_iter77_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter76_bufo_2_addr_reg_1984;
ap_reg_pp0_iter78_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter77_bufo_0_addr_reg_1972;
ap_reg_pp0_iter78_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter77_bufo_1_addr_reg_1978;
ap_reg_pp0_iter78_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter77_bufo_2_addr_reg_1984;
ap_reg_pp0_iter7_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter6_bufo_0_addr_reg_1972;
ap_reg_pp0_iter7_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter6_bufo_1_addr_reg_1978;
ap_reg_pp0_iter7_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter6_bufo_2_addr_reg_1984;
ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter7_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter6_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter7_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter6_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter7_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter6_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter8_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter7_bufo_0_addr_reg_1972;
ap_reg_pp0_iter8_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter7_bufo_1_addr_reg_1978;
ap_reg_pp0_iter8_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter7_bufo_2_addr_reg_1984;
ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter8_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter7_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter8_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter7_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter8_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter7_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter9_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter8_bufo_0_addr_reg_1972;
ap_reg_pp0_iter9_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter8_bufo_1_addr_reg_1978;
ap_reg_pp0_iter9_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter8_bufo_2_addr_reg_1984;
ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter9_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter8_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter9_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter8_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter9_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter8_tmp_10_2_4_reg_2355;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter9_exitcond_flatten_reg_1202;
ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter10_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter9_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter10_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter9_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter10_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter9_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter10_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter9_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter10_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter9_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter10_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter9_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter11_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter10_exitcond_flatten_reg_1202;
ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter11_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter10_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter11_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter10_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter11_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter10_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter11_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter10_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter11_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter10_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter11_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter10_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter12_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter11_exitcond_flatten_reg_1202;
ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter12_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter11_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter12_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter11_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter12_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter11_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter12_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter11_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter12_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter11_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter12_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter11_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter13_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter12_exitcond_flatten_reg_1202;
ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter13_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter12_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter13_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter12_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter13_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter12_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter13_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter12_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter13_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter12_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter13_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter12_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter14_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter13_exitcond_flatten_reg_1202;
ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter14_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter13_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter14_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter13_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter14_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter13_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter14_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter13_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter14_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter13_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter14_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter13_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter15_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter14_exitcond_flatten_reg_1202;
ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter15_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter14_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter15_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter14_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter15_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter14_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter15_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter14_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter15_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter14_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter15_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter14_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter16_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter15_exitcond_flatten_reg_1202;
ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter16_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter15_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter16_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter15_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter16_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter15_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter16_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter15_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter16_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter15_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter16_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter15_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter17_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter16_exitcond_flatten_reg_1202;
ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter17_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter16_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter17_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter16_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter17_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter16_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter17_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter16_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter17_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter16_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter17_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter16_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter18_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter17_exitcond_flatten_reg_1202;
ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter18_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter17_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter18_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter17_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter18_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter17_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter18_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter17_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter18_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter17_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter18_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter17_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter19_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter18_exitcond_flatten_reg_1202;
ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter19_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter18_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter19_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter18_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter19_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter18_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter19_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter18_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter19_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter18_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter19_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter18_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter1_exitcond_flatten_reg_1202 <= exitcond_flatten_reg_1202;
ap_reg_pp0_iter1_p_1_mid2_reg_1221 <= p_1_mid2_reg_1221;
ap_reg_pp0_iter20_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter19_exitcond_flatten_reg_1202;
ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter20_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter19_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter20_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter19_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter20_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter19_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter20_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter19_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter20_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter19_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter20_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter19_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter21_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter20_exitcond_flatten_reg_1202;
ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter21_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter20_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter21_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter20_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter21_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter20_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter21_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter20_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter21_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter20_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter21_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter20_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter22_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter21_exitcond_flatten_reg_1202;
ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter22_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter21_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter22_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter21_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter22_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter21_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter22_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter21_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter22_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter21_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter22_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter21_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter23_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter22_exitcond_flatten_reg_1202;
ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter23_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter22_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter23_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter22_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter23_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter22_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter23_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter22_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter23_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter22_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter23_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter22_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter24_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter23_exitcond_flatten_reg_1202;
ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter24_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter23_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter24_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter23_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter24_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter23_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter24_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter23_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter24_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter23_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter24_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter23_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter25_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter24_exitcond_flatten_reg_1202;
ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter25_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter24_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter25_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter24_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter25_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter24_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter25_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter24_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter25_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter24_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter25_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter24_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter26_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter25_exitcond_flatten_reg_1202;
ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter26_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter25_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter26_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter25_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter26_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter25_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter26_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter25_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter26_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter25_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter26_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter25_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter27_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter26_exitcond_flatten_reg_1202;
ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter27_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter26_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter27_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter26_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter27_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter26_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter27_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter26_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter27_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter26_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter27_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter26_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter28_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter27_exitcond_flatten_reg_1202;
ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter28_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter27_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter28_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter27_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter28_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter27_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter28_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter27_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter28_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter27_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter28_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter27_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter29_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter28_exitcond_flatten_reg_1202;
ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter29_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter28_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter29_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter28_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter29_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter28_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter29_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter28_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter29_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter28_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter29_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter28_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter2_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter1_exitcond_flatten_reg_1202;
ap_reg_pp0_iter30_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter29_exitcond_flatten_reg_1202;
ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter30_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter29_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter30_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter29_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter30_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter29_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter30_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter29_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter30_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter29_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter30_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter29_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter31_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter30_exitcond_flatten_reg_1202;
ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter31_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter30_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter31_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter30_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter31_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter30_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter31_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter30_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter31_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter30_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter31_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter30_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter32_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter31_exitcond_flatten_reg_1202;
ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter32_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter31_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter32_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter31_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter32_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter31_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter32_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter31_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter32_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter31_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter32_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter31_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter33_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter32_exitcond_flatten_reg_1202;
ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter33_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter32_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter33_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter32_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter33_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter32_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter33_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter32_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter33_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter32_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter33_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter32_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter34_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter33_exitcond_flatten_reg_1202;
ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter34_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter33_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter34_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter33_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter34_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter33_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter35_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter34_exitcond_flatten_reg_1202;
ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter35_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter34_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter35_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter34_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter35_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter34_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter36_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter35_exitcond_flatten_reg_1202;
ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter36_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter35_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter36_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter35_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter36_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter35_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter37_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter36_exitcond_flatten_reg_1202;
ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter37_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter36_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter37_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter36_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter37_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter36_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter38_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter37_exitcond_flatten_reg_1202;
ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter38_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter37_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter38_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter37_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter38_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter37_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter39_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter38_exitcond_flatten_reg_1202;
ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter39_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter38_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter39_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter38_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter39_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter38_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter3_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter2_exitcond_flatten_reg_1202;
ap_reg_pp0_iter40_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter39_exitcond_flatten_reg_1202;
ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter40_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter39_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter40_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter39_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter40_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter39_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter41_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter40_exitcond_flatten_reg_1202;
ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter41_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter40_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter41_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter40_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter41_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter40_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter42_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter41_exitcond_flatten_reg_1202;
ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter42_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter41_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter42_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter41_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter42_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter41_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter43_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter42_exitcond_flatten_reg_1202;
ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter43_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter42_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter43_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter42_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter43_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter42_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter44_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter43_exitcond_flatten_reg_1202;
ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter44_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter43_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter44_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter43_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter44_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter43_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter45_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter44_exitcond_flatten_reg_1202;
ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter45_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter44_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter45_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter44_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter45_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter44_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter46_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter45_exitcond_flatten_reg_1202;
ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter46_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter45_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter46_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter45_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter46_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter45_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter47_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter46_exitcond_flatten_reg_1202;
ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter47_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter46_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter47_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter46_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter47_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter46_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter48_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter47_exitcond_flatten_reg_1202;
ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter48_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter47_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter48_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter47_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter48_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter47_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter49_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter48_exitcond_flatten_reg_1202;
ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter4_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter3_exitcond_flatten_reg_1202;
ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130 <= tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140 <= tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145 <= tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150 <= tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155 <= tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter4_tmp_10_0_2_reg_2135 <= tmp_10_0_2_reg_2135;
ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165 <= tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter4_tmp_10_0_3_reg_2160 <= tmp_10_0_3_reg_2160;
ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170 <= tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175 <= tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185 <= tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190 <= tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195 <= tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200 <= tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter4_tmp_10_1_2_reg_2180 <= tmp_10_1_2_reg_2180;
ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210 <= tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter4_tmp_10_1_3_reg_2205 <= tmp_10_1_3_reg_2205;
ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215 <= tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220 <= tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230 <= tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235 <= tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240 <= tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245 <= tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter4_tmp_10_2_2_reg_2225 <= tmp_10_2_2_reg_2225;
ap_reg_pp0_iter4_tmp_10_2_3_reg_2250 <= tmp_10_2_3_reg_2250;
ap_reg_pp0_iter50_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter49_exitcond_flatten_reg_1202;
ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter51_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter50_exitcond_flatten_reg_1202;
ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter52_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter51_exitcond_flatten_reg_1202;
ap_reg_pp0_iter53_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter52_exitcond_flatten_reg_1202;
ap_reg_pp0_iter54_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter53_exitcond_flatten_reg_1202;
ap_reg_pp0_iter55_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter54_exitcond_flatten_reg_1202;
ap_reg_pp0_iter56_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter55_exitcond_flatten_reg_1202;
ap_reg_pp0_iter57_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter56_exitcond_flatten_reg_1202;
ap_reg_pp0_iter58_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter57_exitcond_flatten_reg_1202;
ap_reg_pp0_iter59_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter58_exitcond_flatten_reg_1202;
ap_reg_pp0_iter5_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter4_exitcond_flatten_reg_1202;
ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter5_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter4_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter5_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter4_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter5_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter4_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter5_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter4_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter5_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter4_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter5_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter4_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter60_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter59_exitcond_flatten_reg_1202;
ap_reg_pp0_iter61_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter60_exitcond_flatten_reg_1202;
ap_reg_pp0_iter62_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter61_exitcond_flatten_reg_1202;
ap_reg_pp0_iter63_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter62_exitcond_flatten_reg_1202;
ap_reg_pp0_iter64_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter63_exitcond_flatten_reg_1202;
ap_reg_pp0_iter65_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter64_exitcond_flatten_reg_1202;
ap_reg_pp0_iter66_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter65_exitcond_flatten_reg_1202;
ap_reg_pp0_iter67_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter66_exitcond_flatten_reg_1202;
ap_reg_pp0_iter68_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter67_exitcond_flatten_reg_1202;
ap_reg_pp0_iter69_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter68_exitcond_flatten_reg_1202;
ap_reg_pp0_iter6_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter5_exitcond_flatten_reg_1202;
ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter6_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter5_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter6_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter5_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter6_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter5_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter6_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter5_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter6_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter5_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter6_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter5_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter70_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter69_exitcond_flatten_reg_1202;
ap_reg_pp0_iter71_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter70_exitcond_flatten_reg_1202;
ap_reg_pp0_iter72_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter71_exitcond_flatten_reg_1202;
ap_reg_pp0_iter73_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter72_exitcond_flatten_reg_1202;
ap_reg_pp0_iter74_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter73_exitcond_flatten_reg_1202;
ap_reg_pp0_iter75_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter74_exitcond_flatten_reg_1202;
ap_reg_pp0_iter76_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter75_exitcond_flatten_reg_1202;
ap_reg_pp0_iter77_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter76_exitcond_flatten_reg_1202;
ap_reg_pp0_iter78_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter77_exitcond_flatten_reg_1202;
ap_reg_pp0_iter7_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter6_exitcond_flatten_reg_1202;
ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter7_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter6_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter7_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter6_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter7_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter6_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter7_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter6_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter7_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter6_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter7_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter6_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter8_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter7_exitcond_flatten_reg_1202;
ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter8_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter7_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter8_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter7_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter8_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter7_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter8_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter7_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter8_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter7_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter8_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter7_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter9_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter8_exitcond_flatten_reg_1202;
ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter9_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter8_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter9_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter8_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter9_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter8_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter9_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter8_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter9_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter8_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter9_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter8_tmp_10_2_3_reg_2250;
exitcond_flatten_reg_1202 <= exitcond_flatten_fu_1044_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter10_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter9_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter10_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter9_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter10_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter9_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter11_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter10_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter11_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter10_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter11_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter10_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter12_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter11_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter12_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter11_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter12_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter11_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter13_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter12_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter13_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter12_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter13_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter12_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter14_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter13_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter14_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter13_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter14_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter13_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter15_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter14_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter15_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter14_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter15_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter14_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter16_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter15_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter16_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter15_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter16_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter15_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter17_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter16_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter17_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter16_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter17_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter16_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000 <= tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005 <= tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010 <= tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015 <= tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025 <= tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030 <= tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035 <= tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter3_tmp_10_0_1_reg_2020 <= tmp_10_0_1_reg_2020;
ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050 <= tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055 <= tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060 <= tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065 <= tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075 <= tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080 <= tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter3_tmp_10_1_1_reg_2070 <= tmp_10_1_1_reg_2070;
ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095 <= tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100 <= tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105 <= tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110 <= tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120 <= tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125 <= tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter3_tmp_10_2_1_reg_2115 <= tmp_10_2_1_reg_2115;
ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000 <= ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter4_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter3_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050 <= ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter4_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter3_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095 <= ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter4_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter3_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000 <= ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter5_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter4_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050 <= ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter5_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter4_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095 <= ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter5_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter4_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter6_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter5_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter6_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter5_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter6_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter5_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter7_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter6_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter7_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter6_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter7_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter6_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter8_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter7_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter8_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter7_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter8_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter7_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter9_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter8_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter9_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter8_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter9_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter8_tmp_10_2_1_reg_2115;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufi_0_load_1_reg_1554 <= bufi_0_Dout_B;
bufi_0_load_2_reg_1606 <= bufi_0_Dout_A;
bufi_1_load_1_reg_1566 <= bufi_1_Dout_B;
bufi_1_load_2_reg_1611 <= bufi_1_Dout_A;
bufi_2_load_1_reg_1579 <= bufi_2_Dout_B;
bufi_2_load_2_reg_1617 <= bufi_2_Dout_A;
bufi_3_load_1_reg_1592 <= bufi_3_Dout_B;
bufi_3_load_2_reg_1624 <= bufi_3_Dout_A;
bufi_4_load_1_reg_1599 <= bufi_4_Dout_B;
bufi_4_load_2_reg_1631 <= bufi_4_Dout_A;
bufi_5_load_1_reg_1673 <= bufi_5_Dout_B;
bufi_5_load_2_reg_1679 <= bufi_5_Dout_A;
bufi_6_load_1_reg_1685 <= bufi_6_Dout_B;
bufi_6_load_2_reg_1690 <= bufi_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufi_0_load_3_reg_1784 <= bufi_0_Dout_A;
bufi_1_load_3_reg_1795 <= bufi_1_Dout_A;
bufi_2_load_3_reg_1801 <= bufi_2_Dout_A;
bufi_3_load_3_reg_1808 <= bufi_3_Dout_A;
bufi_4_load_3_reg_1815 <= bufi_4_Dout_A;
bufi_5_load_3_reg_1857 <= bufi_5_Dout_A;
bufi_6_load_3_reg_1863 <= bufi_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufi_0_load_4_reg_1896 <= bufi_0_Dout_B;
bufi_1_load_4_reg_1908 <= bufi_1_Dout_B;
bufi_2_load_4_reg_1921 <= bufi_2_Dout_B;
bufi_3_load_4_reg_1935 <= bufi_3_Dout_B;
bufi_4_load_4_reg_1949 <= bufi_4_Dout_B;
bufi_5_load_4_reg_1956 <= bufi_5_Dout_B;
bufi_6_load_4_reg_1962 <= bufi_6_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufi_0_load_reg_1354 <= bufi_0_Dout_A;
bufi_1_load_reg_1359 <= bufi_1_Dout_A;
bufi_2_load_reg_1365 <= bufi_2_Dout_A;
bufi_3_load_reg_1372 <= bufi_3_Dout_A;
bufi_4_load_reg_1379 <= bufi_4_Dout_A;
bufi_5_load_reg_1461 <= bufi_5_Dout_A;
bufi_6_load_reg_1467 <= bufi_6_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufo_0_addr_reg_1972 <= tmp_4_cast_fu_1196_p1(8 - 1 downto 0);
bufo_1_addr_reg_1978 <= tmp_4_cast_fu_1196_p1(8 - 1 downto 0);
bufo_2_addr_reg_1984 <= tmp_4_cast_fu_1196_p1(8 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
bufo_0_load_reg_1990 <= bufo_0_Dout_A;
bufo_1_load_reg_2040 <= bufo_1_Dout_A;
bufo_2_load_reg_2085 <= bufo_2_Dout_A;
tmp_10_0_0_1_reg_2000 <= grp_fu_948_p2;
tmp_10_0_0_2_reg_2005 <= grp_fu_952_p2;
tmp_10_0_0_3_reg_2010 <= grp_fu_956_p2;
tmp_10_0_0_4_reg_2015 <= grp_fu_960_p2;
tmp_10_0_1_1_reg_2025 <= grp_fu_968_p2;
tmp_10_0_1_2_reg_2030 <= grp_fu_972_p2;
tmp_10_0_1_3_reg_2035 <= grp_fu_976_p2;
tmp_10_0_1_reg_2020 <= grp_fu_964_p2;
tmp_10_1_0_1_reg_2050 <= grp_fu_984_p2;
tmp_10_1_0_2_reg_2055 <= grp_fu_988_p2;
tmp_10_1_0_3_reg_2060 <= grp_fu_992_p2;
tmp_10_1_0_4_reg_2065 <= grp_fu_996_p2;
tmp_10_1_1_1_reg_2075 <= grp_fu_1004_p2;
tmp_10_1_1_2_reg_2080 <= grp_fu_1008_p2;
tmp_10_1_1_reg_2070 <= grp_fu_1000_p2;
tmp_10_1_reg_2045 <= grp_fu_980_p2;
tmp_10_2_0_1_reg_2095 <= grp_fu_1016_p2;
tmp_10_2_0_2_reg_2100 <= grp_fu_1020_p2;
tmp_10_2_0_3_reg_2105 <= grp_fu_1024_p2;
tmp_10_2_0_4_reg_2110 <= grp_fu_1028_p2;
tmp_10_2_1_1_reg_2120 <= grp_fu_1036_p2;
tmp_10_2_1_2_reg_2125 <= grp_fu_1040_p2;
tmp_10_2_1_reg_2115 <= grp_fu_1032_p2;
tmp_10_2_reg_2090 <= grp_fu_1012_p2;
tmp_s_reg_1995 <= grp_fu_944_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufw_0_0_load_reg_1512 <= bufw_0_0_Dout_A;
bufw_0_1_load_reg_1519 <= bufw_0_1_Dout_A;
bufw_0_2_load_reg_1526 <= bufw_0_2_Dout_A;
bufw_0_3_load_reg_1533 <= bufw_0_3_Dout_A;
bufw_0_4_load_reg_1540 <= bufw_0_4_Dout_A;
bufw_1_0_load_reg_1547 <= bufw_1_0_Dout_A;
bufw_1_1_load_reg_1559 <= bufw_1_1_Dout_A;
bufw_1_2_load_reg_1572 <= bufw_1_2_Dout_A;
bufw_1_3_load_reg_1586 <= bufw_1_3_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufw_1_4_load_reg_1735 <= bufw_1_4_Dout_A;
bufw_2_0_load_reg_1742 <= bufw_2_0_Dout_A;
bufw_2_1_load_reg_1749 <= bufw_2_1_Dout_A;
bufw_2_2_load_reg_1756 <= bufw_2_2_Dout_A;
bufw_2_3_load_reg_1763 <= bufw_2_3_Dout_A;
bufw_2_4_load_reg_1770 <= bufw_2_4_Dout_A;
bufw_3_0_load_reg_1777 <= bufw_3_0_Dout_A;
bufw_3_1_load_reg_1789 <= bufw_3_1_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufw_3_2_load_reg_1868 <= bufw_3_2_Dout_A;
bufw_3_3_load_reg_1875 <= bufw_3_3_Dout_A;
bufw_3_4_load_reg_1882 <= bufw_3_4_Dout_A;
bufw_4_0_load_reg_1889 <= bufw_4_0_Dout_A;
bufw_4_1_load_reg_1901 <= bufw_4_1_Dout_A;
bufw_4_2_load_reg_1914 <= bufw_4_2_Dout_A;
bufw_4_3_load_reg_1928 <= bufw_4_3_Dout_A;
bufw_4_4_load_reg_1942 <= bufw_4_4_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next_reg_1206 <= indvar_flatten_next_fu_1050_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
lhs_V_cast1_reg_1273(1 downto 0) <= lhs_V_cast1_fu_1092_p1(1 downto 0);
r_V_1_0_2_reg_1284 <= r_V_1_0_2_fu_1100_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_fu_1044_p2 = ap_const_lv1_0))) then
p_1_mid2_reg_1221 <= p_1_mid2_fu_1068_p3;
tmp_1_reg_1216 <= tmp_1_fu_1062_p2;
to_b_V_reg_1211 <= to_b_V_fu_1056_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
r_V_1_0_3_reg_1456 <= r_V_1_0_3_fu_1138_p2;
tmp_mid2_reg_1289(6 downto 0) <= tmp_mid2_fu_1106_p1(6 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
row_b_V_reg_1278 <= row_b_V_fu_1095_p2;
tmp_mid2_v_reg_1230 <= tmp_mid2_v_fu_1076_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_reg_pp0_iter8_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_0_1_reg_2395 <= grp_fu_856_p2;
temp_2_1_0_1_reg_2400 <= grp_fu_860_p2;
temp_2_2_0_1_reg_2405 <= grp_fu_864_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter11) and (ap_reg_pp0_iter11_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_0_2_reg_2410 <= grp_fu_868_p2;
temp_2_1_0_2_reg_2415 <= grp_fu_872_p2;
temp_2_2_0_2_reg_2420 <= grp_fu_876_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter14) and (ap_reg_pp0_iter14_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_0_3_reg_2425 <= grp_fu_880_p2;
temp_2_1_0_3_reg_2430 <= grp_fu_884_p2;
temp_2_2_0_3_reg_2435 <= grp_fu_888_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter17) and (ap_reg_pp0_iter17_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_0_4_reg_2440 <= grp_fu_892_p2;
temp_2_1_0_4_reg_2445 <= grp_fu_896_p2;
temp_2_2_0_4_reg_2450 <= grp_fu_900_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter23) and (ap_reg_pp0_iter23_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_1_1_reg_2470 <= grp_fu_916_p2;
temp_2_1_1_1_reg_2475 <= grp_fu_920_p2;
temp_2_2_1_1_reg_2480 <= grp_fu_924_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter26) and (ap_reg_pp0_iter26_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_1_2_reg_2485 <= grp_fu_928_p2;
temp_2_1_1_2_reg_2490 <= grp_fu_932_p2;
temp_2_2_1_2_reg_2495 <= grp_fu_936_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter29) and (ap_reg_pp0_iter29_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_1_3_reg_2500 <= grp_fu_940_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_reg_pp0_iter32_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_1_4_reg_2515 <= grp_fu_852_p2;
temp_2_1_1_4_reg_2520 <= grp_fu_856_p2;
temp_2_2_1_4_reg_2525 <= grp_fu_860_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter20) and (ap_reg_pp0_iter20_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_1_reg_2455 <= grp_fu_904_p2;
temp_2_1_1_reg_2460 <= grp_fu_908_p2;
temp_2_2_1_reg_2465 <= grp_fu_912_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_reg_pp0_iter38_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_2_1_reg_2545 <= grp_fu_876_p2;
temp_2_1_2_1_reg_2550 <= grp_fu_880_p2;
temp_2_2_2_1_reg_2555 <= grp_fu_884_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_reg_pp0_iter41_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_2_2_reg_2560 <= grp_fu_888_p2;
temp_2_1_2_2_reg_2565 <= grp_fu_892_p2;
temp_2_2_2_2_reg_2570 <= grp_fu_896_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_reg_pp0_iter44_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_2_3_reg_2575 <= grp_fu_900_p2;
temp_2_1_2_3_reg_2580 <= grp_fu_904_p2;
temp_2_2_2_3_reg_2585 <= grp_fu_908_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_reg_pp0_iter47_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_2_4_reg_2590 <= grp_fu_912_p2;
temp_2_1_2_4_reg_2595 <= grp_fu_916_p2;
temp_2_2_2_4_reg_2600 <= grp_fu_920_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_reg_pp0_iter35_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_2_reg_2530 <= grp_fu_864_p2;
temp_2_1_2_reg_2535 <= grp_fu_868_p2;
temp_2_2_2_reg_2540 <= grp_fu_872_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_reg_pp0_iter53_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_3_1_reg_2620 <= grp_fu_936_p2;
temp_2_1_3_1_reg_2625 <= grp_fu_940_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_reg_pp0_iter57_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_3_2_reg_2635 <= grp_fu_848_p2;
temp_2_1_3_2_reg_2640 <= grp_fu_852_p2;
temp_2_2_3_2_reg_2645 <= grp_fu_856_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_reg_pp0_iter60_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_3_3_reg_2650 <= grp_fu_860_p2;
temp_2_1_3_3_reg_2655 <= grp_fu_864_p2;
temp_2_2_3_3_reg_2660 <= grp_fu_868_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_reg_pp0_iter63_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_3_4_reg_2665 <= grp_fu_872_p2;
temp_2_1_3_4_reg_2670 <= grp_fu_876_p2;
temp_2_2_3_4_reg_2675 <= grp_fu_880_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_reg_pp0_iter50_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_3_reg_2605 <= grp_fu_924_p2;
temp_2_1_3_reg_2610 <= grp_fu_928_p2;
temp_2_2_3_reg_2615 <= grp_fu_932_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_reg_pp0_iter69_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_4_1_reg_2695 <= grp_fu_896_p2;
temp_2_1_4_1_reg_2700 <= grp_fu_900_p2;
temp_2_2_4_1_reg_2705 <= grp_fu_904_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_reg_pp0_iter72_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_4_2_reg_2710 <= grp_fu_908_p2;
temp_2_1_4_2_reg_2715 <= grp_fu_912_p2;
temp_2_2_4_2_reg_2720 <= grp_fu_916_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_reg_pp0_iter75_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_4_3_reg_2725 <= grp_fu_920_p2;
temp_2_1_4_3_reg_2730 <= grp_fu_924_p2;
temp_2_2_4_3_reg_2735 <= grp_fu_928_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_4_4_reg_2740 <= grp_fu_932_p2;
temp_2_1_4_4_reg_2745 <= grp_fu_936_p2;
temp_2_2_4_4_reg_2750 <= grp_fu_940_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_reg_pp0_iter66_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_0_4_reg_2680 <= grp_fu_884_p2;
temp_2_1_4_reg_2685 <= grp_fu_888_p2;
temp_2_2_4_reg_2690 <= grp_fu_892_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter29_exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30))) then
temp_2_1_1_3_reg_2505 <= grp_fu_844_p2;
temp_2_2_1_3_reg_2510 <= grp_fu_848_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5) and (ap_reg_pp0_iter5_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_1_reg_2385 <= grp_fu_848_p2;
temp_2_2_reg_2390 <= grp_fu_852_p2;
temp_2_reg_2380 <= grp_fu_844_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_reg_pp0_iter54_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
temp_2_2_3_1_reg_2630 <= grp_fu_844_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_10_0_1_4_reg_2130 <= grp_fu_944_p2;
tmp_10_0_2_1_reg_2140 <= grp_fu_952_p2;
tmp_10_0_2_2_reg_2145 <= grp_fu_956_p2;
tmp_10_0_2_3_reg_2150 <= grp_fu_960_p2;
tmp_10_0_2_4_reg_2155 <= grp_fu_964_p2;
tmp_10_0_2_reg_2135 <= grp_fu_948_p2;
tmp_10_0_3_1_reg_2165 <= grp_fu_972_p2;
tmp_10_0_3_reg_2160 <= grp_fu_968_p2;
tmp_10_1_1_3_reg_2170 <= grp_fu_976_p2;
tmp_10_1_1_4_reg_2175 <= grp_fu_980_p2;
tmp_10_1_2_1_reg_2185 <= grp_fu_988_p2;
tmp_10_1_2_2_reg_2190 <= grp_fu_992_p2;
tmp_10_1_2_3_reg_2195 <= grp_fu_996_p2;
tmp_10_1_2_4_reg_2200 <= grp_fu_1000_p2;
tmp_10_1_2_reg_2180 <= grp_fu_984_p2;
tmp_10_1_3_1_reg_2210 <= grp_fu_1008_p2;
tmp_10_1_3_reg_2205 <= grp_fu_1004_p2;
tmp_10_2_1_3_reg_2215 <= grp_fu_1012_p2;
tmp_10_2_1_4_reg_2220 <= grp_fu_1016_p2;
tmp_10_2_2_1_reg_2230 <= grp_fu_1024_p2;
tmp_10_2_2_2_reg_2235 <= grp_fu_1028_p2;
tmp_10_2_2_3_reg_2240 <= grp_fu_1032_p2;
tmp_10_2_2_4_reg_2245 <= grp_fu_1036_p2;
tmp_10_2_2_reg_2225 <= grp_fu_1020_p2;
tmp_10_2_3_reg_2250 <= grp_fu_1040_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_reg_pp0_iter3_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
tmp_10_0_3_2_reg_2255 <= grp_fu_944_p2;
tmp_10_0_3_3_reg_2260 <= grp_fu_948_p2;
tmp_10_0_3_4_reg_2265 <= grp_fu_952_p2;
tmp_10_0_4_1_reg_2275 <= grp_fu_960_p2;
tmp_10_0_4_2_reg_2280 <= grp_fu_964_p2;
tmp_10_0_4_3_reg_2285 <= grp_fu_968_p2;
tmp_10_0_4_4_reg_2290 <= grp_fu_972_p2;
tmp_10_0_4_reg_2270 <= grp_fu_956_p2;
tmp_10_1_3_2_reg_2295 <= grp_fu_976_p2;
tmp_10_1_3_3_reg_2300 <= grp_fu_980_p2;
tmp_10_1_3_4_reg_2305 <= grp_fu_984_p2;
tmp_10_1_4_1_reg_2315 <= grp_fu_992_p2;
tmp_10_1_4_2_reg_2320 <= grp_fu_996_p2;
tmp_10_1_4_3_reg_2325 <= grp_fu_1000_p2;
tmp_10_1_4_4_reg_2330 <= grp_fu_1004_p2;
tmp_10_1_4_reg_2310 <= grp_fu_988_p2;
tmp_10_2_3_1_reg_2335 <= grp_fu_1008_p2;
tmp_10_2_3_2_reg_2340 <= grp_fu_1012_p2;
tmp_10_2_3_3_reg_2345 <= grp_fu_1016_p2;
tmp_10_2_3_4_reg_2350 <= grp_fu_1020_p2;
tmp_10_2_4_1_reg_2360 <= grp_fu_1028_p2;
tmp_10_2_4_2_reg_2365 <= grp_fu_1032_p2;
tmp_10_2_4_3_reg_2370 <= grp_fu_1036_p2;
tmp_10_2_4_4_reg_2375 <= grp_fu_1040_p2;
tmp_10_2_4_reg_2355 <= grp_fu_1024_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
tmp_4_reg_1967 <= tmp_4_fu_1190_p2;
end if;
end if;
end process;
lhs_V_cast1_reg_1273(2) <= '0';
tmp_mid2_reg_1289(63 downto 7) <= "000000000000000000000000000000000000000000000000000000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten_fu_1044_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter78, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage2_flag00011011, ap_enable_reg_pp0_iter77, ap_block_pp0_stage1_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_1044_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_1044_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state239;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if (((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter77 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter77 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state239;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_state239 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state239 <= ap_CS_fsm(4);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state100_pp0_stage2_iter32 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state101_pp0_stage0_iter33 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state102_pp0_stage1_iter33 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state103_pp0_stage2_iter33 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state104_pp0_stage0_iter34 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state105_pp0_stage1_iter34 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state106_pp0_stage2_iter34 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state107_pp0_stage0_iter35 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state108_pp0_stage1_iter35 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state109_pp0_stage2_iter35 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state110_pp0_stage0_iter36 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state111_pp0_stage1_iter36 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state112_pp0_stage2_iter36 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state113_pp0_stage0_iter37 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state114_pp0_stage1_iter37 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state115_pp0_stage2_iter37 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state116_pp0_stage0_iter38 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state117_pp0_stage1_iter38 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state118_pp0_stage2_iter38 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state119_pp0_stage0_iter39 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state120_pp0_stage1_iter39 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state121_pp0_stage2_iter39 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state122_pp0_stage0_iter40 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state123_pp0_stage1_iter40 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state124_pp0_stage2_iter40 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state125_pp0_stage0_iter41 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state126_pp0_stage1_iter41 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state127_pp0_stage2_iter41 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state128_pp0_stage0_iter42 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state129_pp0_stage1_iter42 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state130_pp0_stage2_iter42 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state131_pp0_stage0_iter43 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state132_pp0_stage1_iter43 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state133_pp0_stage2_iter43 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state134_pp0_stage0_iter44 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state135_pp0_stage1_iter44 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state136_pp0_stage2_iter44 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state137_pp0_stage0_iter45 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state138_pp0_stage1_iter45 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state139_pp0_stage2_iter45 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state140_pp0_stage0_iter46 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state141_pp0_stage1_iter46 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state142_pp0_stage2_iter46 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state143_pp0_stage0_iter47 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state144_pp0_stage1_iter47 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state145_pp0_stage2_iter47 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state146_pp0_stage0_iter48 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state147_pp0_stage1_iter48 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state148_pp0_stage2_iter48 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state149_pp0_stage0_iter49 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state150_pp0_stage1_iter49 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state151_pp0_stage2_iter49 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state152_pp0_stage0_iter50 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state153_pp0_stage1_iter50 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state154_pp0_stage2_iter50 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state155_pp0_stage0_iter51 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state156_pp0_stage1_iter51 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state157_pp0_stage2_iter51 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state158_pp0_stage0_iter52 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state159_pp0_stage1_iter52 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state160_pp0_stage2_iter52 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state161_pp0_stage0_iter53 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state162_pp0_stage1_iter53 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state163_pp0_stage2_iter53 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state164_pp0_stage0_iter54 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state165_pp0_stage1_iter54 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state166_pp0_stage2_iter54 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state167_pp0_stage0_iter55 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state168_pp0_stage1_iter55 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state169_pp0_stage2_iter55 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state170_pp0_stage0_iter56 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state171_pp0_stage1_iter56 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state172_pp0_stage2_iter56 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state173_pp0_stage0_iter57 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state174_pp0_stage1_iter57 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state175_pp0_stage2_iter57 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state176_pp0_stage0_iter58 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state177_pp0_stage1_iter58 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state178_pp0_stage2_iter58 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state179_pp0_stage0_iter59 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state180_pp0_stage1_iter59 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state181_pp0_stage2_iter59 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state182_pp0_stage0_iter60 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state183_pp0_stage1_iter60 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state184_pp0_stage2_iter60 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state185_pp0_stage0_iter61 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state186_pp0_stage1_iter61 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state187_pp0_stage2_iter61 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state188_pp0_stage0_iter62 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state189_pp0_stage1_iter62 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state190_pp0_stage2_iter62 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state191_pp0_stage0_iter63 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state192_pp0_stage1_iter63 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state193_pp0_stage2_iter63 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state194_pp0_stage0_iter64 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state195_pp0_stage1_iter64 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state196_pp0_stage2_iter64 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state197_pp0_stage0_iter65 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state198_pp0_stage1_iter65 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state199_pp0_stage2_iter65 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state200_pp0_stage0_iter66 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state201_pp0_stage1_iter66 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state202_pp0_stage2_iter66 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state203_pp0_stage0_iter67 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state204_pp0_stage1_iter67 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state205_pp0_stage2_iter67 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state206_pp0_stage0_iter68 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state207_pp0_stage1_iter68 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state208_pp0_stage2_iter68 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state209_pp0_stage0_iter69 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state210_pp0_stage1_iter69 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state211_pp0_stage2_iter69 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state212_pp0_stage0_iter70 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state213_pp0_stage1_iter70 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state214_pp0_stage2_iter70 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state215_pp0_stage0_iter71 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state216_pp0_stage1_iter71 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state217_pp0_stage2_iter71 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state218_pp0_stage0_iter72 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state219_pp0_stage1_iter72 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state220_pp0_stage2_iter72 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state221_pp0_stage0_iter73 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state222_pp0_stage1_iter73 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state223_pp0_stage2_iter73 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state224_pp0_stage0_iter74 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state225_pp0_stage1_iter74 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state226_pp0_stage2_iter74 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state227_pp0_stage0_iter75 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state228_pp0_stage1_iter75 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state229_pp0_stage2_iter75 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state230_pp0_stage0_iter76 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state231_pp0_stage1_iter76 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state232_pp0_stage2_iter76 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state233_pp0_stage0_iter77 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state234_pp0_stage1_iter77 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state235_pp0_stage2_iter77 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state236_pp0_stage0_iter78 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state237_pp0_stage1_iter78 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state238_pp0_stage2_iter78 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage2_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage1_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage2_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage1_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage2_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage1_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage2_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage1_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage2_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage1_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage2_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage1_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage2_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage0_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage1_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage2_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage0_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage1_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage2_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage0_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage1_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage2_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage0_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage1_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage2_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage0_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage1_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage2_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage0_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage1_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage2_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage0_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage1_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage2_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage0_iter24 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage1_iter24 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state76_pp0_stage2_iter24 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state77_pp0_stage0_iter25 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state78_pp0_stage1_iter25 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state79_pp0_stage2_iter25 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state80_pp0_stage0_iter26 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state81_pp0_stage1_iter26 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state82_pp0_stage2_iter26 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state83_pp0_stage0_iter27 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state84_pp0_stage1_iter27 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state85_pp0_stage2_iter27 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state86_pp0_stage0_iter28 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state87_pp0_stage1_iter28 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state88_pp0_stage2_iter28 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state89_pp0_stage0_iter29 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state90_pp0_stage1_iter29 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state91_pp0_stage2_iter29 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state92_pp0_stage0_iter30 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state93_pp0_stage1_iter30 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state94_pp0_stage2_iter30 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state95_pp0_stage0_iter31 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state96_pp0_stage1_iter31 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state97_pp0_stage2_iter31 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state98_pp0_stage0_iter32 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state99_pp0_stage1_iter32 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten_fu_1044_p2)
begin
if ((exitcond_flatten_fu_1044_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state239)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state239)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter14, ap_enable_reg_pp0_iter17, ap_enable_reg_pp0_iter20, ap_enable_reg_pp0_iter23, ap_enable_reg_pp0_iter26, ap_enable_reg_pp0_iter29, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter51, ap_enable_reg_pp0_iter54, ap_enable_reg_pp0_iter57, ap_enable_reg_pp0_iter60, ap_enable_reg_pp0_iter63, ap_enable_reg_pp0_iter66, ap_enable_reg_pp0_iter69, ap_enable_reg_pp0_iter72, ap_enable_reg_pp0_iter75, ap_enable_reg_pp0_iter78, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter16, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter21, ap_enable_reg_pp0_iter22, ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter25, ap_enable_reg_pp0_iter27, ap_enable_reg_pp0_iter28, ap_enable_reg_pp0_iter31, ap_enable_reg_pp0_iter32, ap_enable_reg_pp0_iter34, ap_enable_reg_pp0_iter35, ap_enable_reg_pp0_iter37, ap_enable_reg_pp0_iter38, ap_enable_reg_pp0_iter40, ap_enable_reg_pp0_iter41, ap_enable_reg_pp0_iter43, ap_enable_reg_pp0_iter44, ap_enable_reg_pp0_iter46, ap_enable_reg_pp0_iter47, ap_enable_reg_pp0_iter49, ap_enable_reg_pp0_iter50, ap_enable_reg_pp0_iter52, ap_enable_reg_pp0_iter53, ap_enable_reg_pp0_iter55, ap_enable_reg_pp0_iter56, ap_enable_reg_pp0_iter58, ap_enable_reg_pp0_iter59, ap_enable_reg_pp0_iter61, ap_enable_reg_pp0_iter62, ap_enable_reg_pp0_iter64, ap_enable_reg_pp0_iter65, ap_enable_reg_pp0_iter67, ap_enable_reg_pp0_iter68, ap_enable_reg_pp0_iter70, ap_enable_reg_pp0_iter71, ap_enable_reg_pp0_iter73, ap_enable_reg_pp0_iter74, ap_enable_reg_pp0_iter76, ap_enable_reg_pp0_iter77)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter10) and (ap_const_logic_0 = ap_enable_reg_pp0_iter11) and (ap_const_logic_0 = ap_enable_reg_pp0_iter12) and (ap_const_logic_0 = ap_enable_reg_pp0_iter13) and (ap_const_logic_0 = ap_enable_reg_pp0_iter14) and (ap_const_logic_0 = ap_enable_reg_pp0_iter15) and (ap_const_logic_0 = ap_enable_reg_pp0_iter16) and (ap_const_logic_0 = ap_enable_reg_pp0_iter17) and (ap_const_logic_0 = ap_enable_reg_pp0_iter18) and (ap_const_logic_0 = ap_enable_reg_pp0_iter19) and (ap_const_logic_0 = ap_enable_reg_pp0_iter20) and (ap_const_logic_0 = ap_enable_reg_pp0_iter21) and (ap_const_logic_0 = ap_enable_reg_pp0_iter22) and (ap_const_logic_0 = ap_enable_reg_pp0_iter23) and (ap_const_logic_0 = ap_enable_reg_pp0_iter24) and (ap_const_logic_0 = ap_enable_reg_pp0_iter25) and (ap_const_logic_0 = ap_enable_reg_pp0_iter26) and (ap_const_logic_0 = ap_enable_reg_pp0_iter27) and (ap_const_logic_0 = ap_enable_reg_pp0_iter28) and (ap_const_logic_0 = ap_enable_reg_pp0_iter29) and (ap_const_logic_0 = ap_enable_reg_pp0_iter30) and (ap_const_logic_0 = ap_enable_reg_pp0_iter31) and (ap_const_logic_0 = ap_enable_reg_pp0_iter32) and (ap_const_logic_0 = ap_enable_reg_pp0_iter33) and (ap_const_logic_0 = ap_enable_reg_pp0_iter34) and (ap_const_logic_0 = ap_enable_reg_pp0_iter35) and (ap_const_logic_0 = ap_enable_reg_pp0_iter36) and (ap_const_logic_0 = ap_enable_reg_pp0_iter37) and (ap_const_logic_0 = ap_enable_reg_pp0_iter38) and (ap_const_logic_0 = ap_enable_reg_pp0_iter39) and (ap_const_logic_0 = ap_enable_reg_pp0_iter40) and (ap_const_logic_0 = ap_enable_reg_pp0_iter41) and (ap_const_logic_0 = ap_enable_reg_pp0_iter42) and (ap_const_logic_0 = ap_enable_reg_pp0_iter43) and (ap_const_logic_0 = ap_enable_reg_pp0_iter44) and (ap_const_logic_0 = ap_enable_reg_pp0_iter45) and (ap_const_logic_0 = ap_enable_reg_pp0_iter46) and (ap_const_logic_0 = ap_enable_reg_pp0_iter47) and (ap_const_logic_0 = ap_enable_reg_pp0_iter48) and (ap_const_logic_0 = ap_enable_reg_pp0_iter49) and (ap_const_logic_0 = ap_enable_reg_pp0_iter50) and (ap_const_logic_0 = ap_enable_reg_pp0_iter51) and (ap_const_logic_0 = ap_enable_reg_pp0_iter52) and (ap_const_logic_0 = ap_enable_reg_pp0_iter53) and (ap_const_logic_0 = ap_enable_reg_pp0_iter54) and (ap_const_logic_0 = ap_enable_reg_pp0_iter55) and (ap_const_logic_0 = ap_enable_reg_pp0_iter56) and (ap_const_logic_0 = ap_enable_reg_pp0_iter57) and (ap_const_logic_0 = ap_enable_reg_pp0_iter58) and (ap_const_logic_0 = ap_enable_reg_pp0_iter59) and (ap_const_logic_0 = ap_enable_reg_pp0_iter60) and (ap_const_logic_0 = ap_enable_reg_pp0_iter61) and (ap_const_logic_0 = ap_enable_reg_pp0_iter62) and (ap_const_logic_0 = ap_enable_reg_pp0_iter63) and (ap_const_logic_0 = ap_enable_reg_pp0_iter64) and (ap_const_logic_0 = ap_enable_reg_pp0_iter65) and (ap_const_logic_0 = ap_enable_reg_pp0_iter66) and (ap_const_logic_0 = ap_enable_reg_pp0_iter67) and (ap_const_logic_0 = ap_enable_reg_pp0_iter68) and (ap_const_logic_0 = ap_enable_reg_pp0_iter69) and (ap_const_logic_0 = ap_enable_reg_pp0_iter70) and (ap_const_logic_0 = ap_enable_reg_pp0_iter71) and (ap_const_logic_0 = ap_enable_reg_pp0_iter72) and (ap_const_logic_0 = ap_enable_reg_pp0_iter73) and (ap_const_logic_0 = ap_enable_reg_pp0_iter74) and (ap_const_logic_0 = ap_enable_reg_pp0_iter75) and (ap_const_logic_0 = ap_enable_reg_pp0_iter76) and (ap_const_logic_0 = ap_enable_reg_pp0_iter77) and (ap_const_logic_0 = ap_enable_reg_pp0_iter78))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state239)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state239)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
bufi_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_0_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_0_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_0_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_0_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_0_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_0_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Clk_A <= ap_clk;
bufi_0_Clk_B <= ap_clk;
bufi_0_Din_A <= ap_const_lv32_0;
bufi_0_Din_B <= ap_const_lv32_0;
bufi_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_0_EN_A <= ap_const_logic_1;
else
bufi_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_0_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_0_EN_B <= ap_const_logic_1;
else
bufi_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_0_Rst_A <= ap_rst;
bufi_0_Rst_B <= ap_rst;
bufi_0_WEN_A <= ap_const_lv4_0;
bufi_0_WEN_B <= ap_const_lv4_0;
bufi_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_1_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_1_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_1_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_1_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_1_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_1_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Clk_A <= ap_clk;
bufi_1_Clk_B <= ap_clk;
bufi_1_Din_A <= ap_const_lv32_0;
bufi_1_Din_B <= ap_const_lv32_0;
bufi_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_1_EN_A <= ap_const_logic_1;
else
bufi_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_1_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_1_EN_B <= ap_const_logic_1;
else
bufi_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_1_Rst_A <= ap_rst;
bufi_1_Rst_B <= ap_rst;
bufi_1_WEN_A <= ap_const_lv4_0;
bufi_1_WEN_B <= ap_const_lv4_0;
bufi_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_2_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_2_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_2_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_2_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_2_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_2_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Clk_A <= ap_clk;
bufi_2_Clk_B <= ap_clk;
bufi_2_Din_A <= ap_const_lv32_0;
bufi_2_Din_B <= ap_const_lv32_0;
bufi_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_2_EN_A <= ap_const_logic_1;
else
bufi_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_2_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_2_EN_B <= ap_const_logic_1;
else
bufi_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_2_Rst_A <= ap_rst;
bufi_2_Rst_B <= ap_rst;
bufi_2_WEN_A <= ap_const_lv4_0;
bufi_2_WEN_B <= ap_const_lv4_0;
bufi_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_3_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_3_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_3_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_3_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_3_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_3_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_3_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_3_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_3_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_3_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_3_Clk_A <= ap_clk;
bufi_3_Clk_B <= ap_clk;
bufi_3_Din_A <= ap_const_lv32_0;
bufi_3_Din_B <= ap_const_lv32_0;
bufi_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_3_EN_A <= ap_const_logic_1;
else
bufi_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_3_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_3_EN_B <= ap_const_logic_1;
else
bufi_3_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_3_Rst_A <= ap_rst;
bufi_3_Rst_B <= ap_rst;
bufi_3_WEN_A <= ap_const_lv4_0;
bufi_3_WEN_B <= ap_const_lv4_0;
bufi_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_4_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_4_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_4_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_4_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_4_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_4_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_4_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_4_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_4_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_4_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_4_Clk_A <= ap_clk;
bufi_4_Clk_B <= ap_clk;
bufi_4_Din_A <= ap_const_lv32_0;
bufi_4_Din_B <= ap_const_lv32_0;
bufi_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_4_EN_A <= ap_const_logic_1;
else
bufi_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_4_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_4_EN_B <= ap_const_logic_1;
else
bufi_4_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_4_Rst_A <= ap_rst;
bufi_4_Rst_B <= ap_rst;
bufi_4_WEN_A <= ap_const_lv4_0;
bufi_4_WEN_B <= ap_const_lv4_0;
bufi_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_5_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_5_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_5_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_5_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_5_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_5_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_5_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_5_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_5_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_5_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_5_Clk_A <= ap_clk;
bufi_5_Clk_B <= ap_clk;
bufi_5_Din_A <= ap_const_lv32_0;
bufi_5_Din_B <= ap_const_lv32_0;
bufi_5_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_5_EN_A <= ap_const_logic_1;
else
bufi_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_5_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_5_EN_B <= ap_const_logic_1;
else
bufi_5_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_5_Rst_A <= ap_rst;
bufi_5_Rst_B <= ap_rst;
bufi_5_WEN_A <= ap_const_lv4_0;
bufi_5_WEN_B <= ap_const_lv4_0;
bufi_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_6_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_3_fu_1082_p1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_2_fu_1128_p1, tmp_2_0_3_fu_1143_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
bufi_6_Addr_A_orig <= tmp_2_0_3_fu_1143_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_6_Addr_A_orig <= tmp_2_0_2_fu_1128_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_6_Addr_A_orig <= tmp_3_fu_1082_p1(32 - 1 downto 0);
else
bufi_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_6_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_6_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_6_Addr_B_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, tmp_2_0_1_fu_1118_p1, tmp_2_0_4_fu_1160_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
bufi_6_Addr_B_orig <= tmp_2_0_4_fu_1160_p1(32 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
bufi_6_Addr_B_orig <= tmp_2_0_1_fu_1118_p1(32 - 1 downto 0);
else
bufi_6_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_6_Clk_A <= ap_clk;
bufi_6_Clk_B <= ap_clk;
bufi_6_Din_A <= ap_const_lv32_0;
bufi_6_Din_B <= ap_const_lv32_0;
bufi_6_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_6_EN_A <= ap_const_logic_1;
else
bufi_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_6_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
bufi_6_EN_B <= ap_const_logic_1;
else
bufi_6_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_6_Rst_A <= ap_rst;
bufi_6_Rst_B <= ap_rst;
bufi_6_WEN_A <= ap_const_lv4_0;
bufi_6_WEN_B <= ap_const_lv4_0;
bufo_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_0_Addr_A_orig <= tmp_4_cast_fu_1196_p1(32 - 1 downto 0);
bufo_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_0_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter78_bufo_0_addr_reg_1972),32));
bufo_0_Clk_A <= ap_clk;
bufo_0_Clk_B <= ap_clk;
bufo_0_Din_A <= ap_const_lv32_0;
bufo_0_Din_B <= temp_2_0_4_4_reg_2740;
bufo_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
bufo_0_EN_A <= ap_const_logic_1;
else
bufo_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_0_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78))) then
bufo_0_EN_B <= ap_const_logic_1;
else
bufo_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_0_Rst_A <= ap_rst;
bufo_0_Rst_B <= ap_rst;
bufo_0_WEN_A <= ap_const_lv4_0;
bufo_0_WEN_B_assign_proc : process(ap_reg_pp0_iter78_exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufo_0_WEN_B <= ap_const_lv4_F;
else
bufo_0_WEN_B <= ap_const_lv4_0;
end if;
end process;
bufo_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_1_Addr_A_orig <= tmp_4_cast_fu_1196_p1(32 - 1 downto 0);
bufo_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_1_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter78_bufo_1_addr_reg_1978),32));
bufo_1_Clk_A <= ap_clk;
bufo_1_Clk_B <= ap_clk;
bufo_1_Din_A <= ap_const_lv32_0;
bufo_1_Din_B <= temp_2_1_4_4_reg_2745;
bufo_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
bufo_1_EN_A <= ap_const_logic_1;
else
bufo_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_1_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78))) then
bufo_1_EN_B <= ap_const_logic_1;
else
bufo_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_1_Rst_A <= ap_rst;
bufo_1_Rst_B <= ap_rst;
bufo_1_WEN_A <= ap_const_lv4_0;
bufo_1_WEN_B_assign_proc : process(ap_reg_pp0_iter78_exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufo_1_WEN_B <= ap_const_lv4_F;
else
bufo_1_WEN_B <= ap_const_lv4_0;
end if;
end process;
bufo_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_2_Addr_A_orig <= tmp_4_cast_fu_1196_p1(32 - 1 downto 0);
bufo_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_2_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter78_bufo_2_addr_reg_1984),32));
bufo_2_Clk_A <= ap_clk;
bufo_2_Clk_B <= ap_clk;
bufo_2_Din_A <= ap_const_lv32_0;
bufo_2_Din_B <= temp_2_2_4_4_reg_2750;
bufo_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
bufo_2_EN_A <= ap_const_logic_1;
else
bufo_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_2_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78))) then
bufo_2_EN_B <= ap_const_logic_1;
else
bufo_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_2_Rst_A <= ap_rst;
bufo_2_Rst_B <= ap_rst;
bufo_2_WEN_A <= ap_const_lv4_0;
bufo_2_WEN_B_assign_proc : process(ap_reg_pp0_iter78_exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_enable_reg_pp0_iter78)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter78) and (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 = ap_const_lv1_0))) then
bufo_2_WEN_B <= ap_const_lv4_F;
else
bufo_2_WEN_B <= ap_const_lv4_0;
end if;
end process;
bufw_0_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_0_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_0_0_Clk_A <= ap_clk;
bufw_0_0_Din_A <= ap_const_lv32_0;
bufw_0_0_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_0_0_EN_A <= ap_const_logic_1;
else
bufw_0_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_0_Rst_A <= ap_rst;
bufw_0_0_WEN_A <= ap_const_lv4_0;
bufw_0_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_1_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_0_1_Clk_A <= ap_clk;
bufw_0_1_Din_A <= ap_const_lv32_0;
bufw_0_1_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_0_1_EN_A <= ap_const_logic_1;
else
bufw_0_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_1_Rst_A <= ap_rst;
bufw_0_1_WEN_A <= ap_const_lv4_0;
bufw_0_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_2_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_0_2_Clk_A <= ap_clk;
bufw_0_2_Din_A <= ap_const_lv32_0;
bufw_0_2_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_0_2_EN_A <= ap_const_logic_1;
else
bufw_0_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_2_Rst_A <= ap_rst;
bufw_0_2_WEN_A <= ap_const_lv4_0;
bufw_0_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_3_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_0_3_Clk_A <= ap_clk;
bufw_0_3_Din_A <= ap_const_lv32_0;
bufw_0_3_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_0_3_EN_A <= ap_const_logic_1;
else
bufw_0_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_3_Rst_A <= ap_rst;
bufw_0_3_WEN_A <= ap_const_lv4_0;
bufw_0_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_4_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_0_4_Clk_A <= ap_clk;
bufw_0_4_Din_A <= ap_const_lv32_0;
bufw_0_4_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_0_4_EN_A <= ap_const_logic_1;
else
bufw_0_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_4_Rst_A <= ap_rst;
bufw_0_4_WEN_A <= ap_const_lv4_0;
bufw_1_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_0_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_1_0_Clk_A <= ap_clk;
bufw_1_0_Din_A <= ap_const_lv32_0;
bufw_1_0_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_1_0_EN_A <= ap_const_logic_1;
else
bufw_1_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_0_Rst_A <= ap_rst;
bufw_1_0_WEN_A <= ap_const_lv4_0;
bufw_1_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_1_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_1_1_Clk_A <= ap_clk;
bufw_1_1_Din_A <= ap_const_lv32_0;
bufw_1_1_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_1_1_EN_A <= ap_const_logic_1;
else
bufw_1_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_1_Rst_A <= ap_rst;
bufw_1_1_WEN_A <= ap_const_lv4_0;
bufw_1_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_2_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_1_2_Clk_A <= ap_clk;
bufw_1_2_Din_A <= ap_const_lv32_0;
bufw_1_2_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_1_2_EN_A <= ap_const_logic_1;
else
bufw_1_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_2_Rst_A <= ap_rst;
bufw_1_2_WEN_A <= ap_const_lv4_0;
bufw_1_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_3_Addr_A_orig <= tmp_mid2_fu_1106_p1(32 - 1 downto 0);
bufw_1_3_Clk_A <= ap_clk;
bufw_1_3_Din_A <= ap_const_lv32_0;
bufw_1_3_EN_A_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
bufw_1_3_EN_A <= ap_const_logic_1;
else
bufw_1_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_3_Rst_A <= ap_rst;
bufw_1_3_WEN_A <= ap_const_lv4_0;
bufw_1_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_4_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_1_4_Clk_A <= ap_clk;
bufw_1_4_Din_A <= ap_const_lv32_0;
bufw_1_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_1_4_EN_A <= ap_const_logic_1;
else
bufw_1_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_4_Rst_A <= ap_rst;
bufw_1_4_WEN_A <= ap_const_lv4_0;
bufw_2_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_0_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_2_0_Clk_A <= ap_clk;
bufw_2_0_Din_A <= ap_const_lv32_0;
bufw_2_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_2_0_EN_A <= ap_const_logic_1;
else
bufw_2_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_0_Rst_A <= ap_rst;
bufw_2_0_WEN_A <= ap_const_lv4_0;
bufw_2_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_1_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_2_1_Clk_A <= ap_clk;
bufw_2_1_Din_A <= ap_const_lv32_0;
bufw_2_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_2_1_EN_A <= ap_const_logic_1;
else
bufw_2_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_1_Rst_A <= ap_rst;
bufw_2_1_WEN_A <= ap_const_lv4_0;
bufw_2_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_2_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_2_2_Clk_A <= ap_clk;
bufw_2_2_Din_A <= ap_const_lv32_0;
bufw_2_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_2_2_EN_A <= ap_const_logic_1;
else
bufw_2_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_2_Rst_A <= ap_rst;
bufw_2_2_WEN_A <= ap_const_lv4_0;
bufw_2_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_3_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_2_3_Clk_A <= ap_clk;
bufw_2_3_Din_A <= ap_const_lv32_0;
bufw_2_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_2_3_EN_A <= ap_const_logic_1;
else
bufw_2_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_3_Rst_A <= ap_rst;
bufw_2_3_WEN_A <= ap_const_lv4_0;
bufw_2_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_4_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_2_4_Clk_A <= ap_clk;
bufw_2_4_Din_A <= ap_const_lv32_0;
bufw_2_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_2_4_EN_A <= ap_const_logic_1;
else
bufw_2_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_4_Rst_A <= ap_rst;
bufw_2_4_WEN_A <= ap_const_lv4_0;
bufw_3_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_0_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_3_0_Clk_A <= ap_clk;
bufw_3_0_Din_A <= ap_const_lv32_0;
bufw_3_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_3_0_EN_A <= ap_const_logic_1;
else
bufw_3_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_0_Rst_A <= ap_rst;
bufw_3_0_WEN_A <= ap_const_lv4_0;
bufw_3_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_1_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_3_1_Clk_A <= ap_clk;
bufw_3_1_Din_A <= ap_const_lv32_0;
bufw_3_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_3_1_EN_A <= ap_const_logic_1;
else
bufw_3_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_1_Rst_A <= ap_rst;
bufw_3_1_WEN_A <= ap_const_lv4_0;
bufw_3_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_2_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_3_2_Clk_A <= ap_clk;
bufw_3_2_Din_A <= ap_const_lv32_0;
bufw_3_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_3_2_EN_A <= ap_const_logic_1;
else
bufw_3_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_2_Rst_A <= ap_rst;
bufw_3_2_WEN_A <= ap_const_lv4_0;
bufw_3_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_3_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_3_3_Clk_A <= ap_clk;
bufw_3_3_Din_A <= ap_const_lv32_0;
bufw_3_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_3_3_EN_A <= ap_const_logic_1;
else
bufw_3_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_3_Rst_A <= ap_rst;
bufw_3_3_WEN_A <= ap_const_lv4_0;
bufw_3_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_4_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_3_4_Clk_A <= ap_clk;
bufw_3_4_Din_A <= ap_const_lv32_0;
bufw_3_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_3_4_EN_A <= ap_const_logic_1;
else
bufw_3_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_4_Rst_A <= ap_rst;
bufw_3_4_WEN_A <= ap_const_lv4_0;
bufw_4_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_0_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_4_0_Clk_A <= ap_clk;
bufw_4_0_Din_A <= ap_const_lv32_0;
bufw_4_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_4_0_EN_A <= ap_const_logic_1;
else
bufw_4_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_0_Rst_A <= ap_rst;
bufw_4_0_WEN_A <= ap_const_lv4_0;
bufw_4_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_1_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_4_1_Clk_A <= ap_clk;
bufw_4_1_Din_A <= ap_const_lv32_0;
bufw_4_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_4_1_EN_A <= ap_const_logic_1;
else
bufw_4_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_1_Rst_A <= ap_rst;
bufw_4_1_WEN_A <= ap_const_lv4_0;
bufw_4_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_2_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_4_2_Clk_A <= ap_clk;
bufw_4_2_Din_A <= ap_const_lv32_0;
bufw_4_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_4_2_EN_A <= ap_const_logic_1;
else
bufw_4_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_2_Rst_A <= ap_rst;
bufw_4_2_WEN_A <= ap_const_lv4_0;
bufw_4_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_3_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_4_3_Clk_A <= ap_clk;
bufw_4_3_Din_A <= ap_const_lv32_0;
bufw_4_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_4_3_EN_A <= ap_const_logic_1;
else
bufw_4_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_3_Rst_A <= ap_rst;
bufw_4_3_WEN_A <= ap_const_lv4_0;
bufw_4_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_4_Addr_A_orig <= tmp_mid2_reg_1289(32 - 1 downto 0);
bufw_4_4_Clk_A <= ap_clk;
bufw_4_4_Din_A <= ap_const_lv32_0;
bufw_4_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
bufw_4_4_EN_A <= ap_const_logic_1;
else
bufw_4_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_4_Rst_A <= ap_rst;
bufw_4_4_WEN_A <= ap_const_lv4_0;
exitcond_flatten_fu_1044_p2 <= "1" when (indvar_flatten_phi_fu_814_p4 = ap_const_lv8_C0) else "0";
grp_fu_1000_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_1_0_load_reg_1547, ap_enable_reg_pp0_iter1, bufw_2_4_load_reg_1770, bufw_4_3_load_reg_1928, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p0 <= bufw_4_3_load_reg_1928;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p0 <= bufw_2_4_load_reg_1770;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p0 <= bufw_1_0_load_reg_1547;
else
grp_fu_1000_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1000_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_1_load_1_reg_1566, bufi_5_load_2_reg_1679, bufi_4_load_4_reg_1949, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p1 <= bufi_4_load_4_reg_1949;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p1 <= bufi_5_load_2_reg_1679;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1000_p1 <= bufi_1_load_1_reg_1566;
else
grp_fu_1000_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1004_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_1_load_reg_1559, bufw_3_0_load_reg_1777, bufw_4_4_load_reg_1942, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p0 <= bufw_4_4_load_reg_1942;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p0 <= bufw_3_0_load_reg_1777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p0 <= bufw_1_1_load_reg_1559;
else
grp_fu_1004_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1004_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_2_load_1_reg_1579, bufi_1_load_3_reg_1795, bufi_5_load_4_reg_1956, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p1 <= bufi_5_load_4_reg_1956;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p1 <= bufi_1_load_3_reg_1795;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1004_p1 <= bufi_2_load_1_reg_1579;
else
grp_fu_1004_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1008_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_2_load_reg_1572, bufw_3_1_load_reg_1789, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then
grp_fu_1008_p0 <= bufw_3_1_load_reg_1789;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1008_p0 <= bufw_1_2_load_reg_1572;
else
grp_fu_1008_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1008_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_3_load_1_reg_1592, bufi_2_load_3_reg_1801, bufi_3_load_3_reg_1808, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1008_p1 <= bufi_3_load_3_reg_1808;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1008_p1 <= bufi_2_load_3_reg_1801;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1008_p1 <= bufi_3_load_1_reg_1592;
else
grp_fu_1008_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1012_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_0_load_reg_1512, ap_enable_reg_pp0_iter1, bufw_1_3_load_reg_1586, bufw_3_2_load_reg_1868, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p0 <= bufw_3_2_load_reg_1868;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p0 <= bufw_1_3_load_reg_1586;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p0 <= bufw_0_0_load_reg_1512;
else
grp_fu_1012_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1012_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_2_load_reg_1365, ap_enable_reg_pp0_iter1, bufi_5_load_1_reg_1673, bufi_4_load_3_reg_1815, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p1 <= bufi_4_load_3_reg_1815;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p1 <= bufi_5_load_1_reg_1673;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1012_p1 <= bufi_2_load_reg_1365;
else
grp_fu_1012_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1016_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_1_load_reg_1519, ap_enable_reg_pp0_iter1, bufw_1_4_load_reg_1735, bufw_3_3_load_reg_1875, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p0 <= bufw_3_3_load_reg_1875;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p0 <= bufw_1_4_load_reg_1735;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p0 <= bufw_0_1_load_reg_1519;
else
grp_fu_1016_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1016_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_3_load_reg_1372, ap_enable_reg_pp0_iter1, bufi_6_load_1_reg_1685, bufi_5_load_3_reg_1857, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p1 <= bufi_5_load_3_reg_1857;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p1 <= bufi_6_load_1_reg_1685;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1016_p1 <= bufi_3_load_reg_1372;
else
grp_fu_1016_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1020_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_2_load_reg_1526, ap_enable_reg_pp0_iter1, bufw_2_0_load_reg_1742, bufw_3_4_load_reg_1882, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p0 <= bufw_3_4_load_reg_1882;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p0 <= bufw_2_0_load_reg_1742;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p0 <= bufw_0_2_load_reg_1526;
else
grp_fu_1020_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1020_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_4_load_reg_1379, ap_enable_reg_pp0_iter1, bufi_2_load_2_reg_1617, bufi_6_load_3_reg_1863, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p1 <= bufi_6_load_3_reg_1863;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p1 <= bufi_2_load_2_reg_1617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1020_p1 <= bufi_4_load_reg_1379;
else
grp_fu_1020_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1024_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_3_load_reg_1533, ap_enable_reg_pp0_iter1, bufw_2_1_load_reg_1749, bufw_4_0_load_reg_1889, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p0 <= bufw_4_0_load_reg_1889;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p0 <= bufw_2_1_load_reg_1749;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p0 <= bufw_0_3_load_reg_1533;
else
grp_fu_1024_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1024_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_5_load_reg_1461, ap_enable_reg_pp0_iter1, bufi_3_load_2_reg_1624, bufi_2_load_4_reg_1921, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p1 <= bufi_2_load_4_reg_1921;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p1 <= bufi_3_load_2_reg_1624;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1024_p1 <= bufi_5_load_reg_1461;
else
grp_fu_1024_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1028_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_4_load_reg_1540, ap_enable_reg_pp0_iter1, bufw_2_2_load_reg_1756, bufw_4_1_load_reg_1901, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p0 <= bufw_4_1_load_reg_1901;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p0 <= bufw_2_2_load_reg_1756;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p0 <= bufw_0_4_load_reg_1540;
else
grp_fu_1028_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1028_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_6_load_reg_1467, ap_enable_reg_pp0_iter1, bufi_4_load_2_reg_1631, bufi_3_load_4_reg_1935, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p1 <= bufi_3_load_4_reg_1935;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p1 <= bufi_4_load_2_reg_1631;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1028_p1 <= bufi_6_load_reg_1467;
else
grp_fu_1028_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1032_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_1_0_load_reg_1547, ap_enable_reg_pp0_iter1, bufw_2_3_load_reg_1763, bufw_4_2_load_reg_1914, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p0 <= bufw_4_2_load_reg_1914;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p0 <= bufw_2_3_load_reg_1763;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p0 <= bufw_1_0_load_reg_1547;
else
grp_fu_1032_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1032_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_2_load_1_reg_1579, bufi_5_load_2_reg_1679, bufi_4_load_4_reg_1949, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p1 <= bufi_4_load_4_reg_1949;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p1 <= bufi_5_load_2_reg_1679;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1032_p1 <= bufi_2_load_1_reg_1579;
else
grp_fu_1032_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1036_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_1_load_reg_1559, bufw_2_4_load_reg_1770, bufw_4_3_load_reg_1928, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p0 <= bufw_4_3_load_reg_1928;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p0 <= bufw_2_4_load_reg_1770;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p0 <= bufw_1_1_load_reg_1559;
else
grp_fu_1036_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1036_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_3_load_1_reg_1592, bufi_6_load_2_reg_1690, bufi_5_load_4_reg_1956, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p1 <= bufi_5_load_4_reg_1956;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p1 <= bufi_6_load_2_reg_1690;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1036_p1 <= bufi_3_load_1_reg_1592;
else
grp_fu_1036_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1040_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_2_load_reg_1572, bufw_3_0_load_reg_1777, bufw_4_4_load_reg_1942, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p0 <= bufw_4_4_load_reg_1942;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p0 <= bufw_3_0_load_reg_1777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p0 <= bufw_1_2_load_reg_1572;
else
grp_fu_1040_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1040_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_4_load_1_reg_1599, bufi_2_load_3_reg_1801, bufi_6_load_4_reg_1962, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p1 <= bufi_6_load_4_reg_1962;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p1 <= bufi_2_load_3_reg_1801;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_1040_p1 <= bufi_4_load_1_reg_1599;
else
grp_fu_1040_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_844_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufo_0_load_reg_1990, ap_enable_reg_pp0_iter3, temp_2_1_1_2_reg_2490, ap_enable_reg_pp0_iter51, temp_2_2_3_reg_2615, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_844_p0 <= temp_2_2_3_reg_2615;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_844_p0 <= temp_2_1_1_2_reg_2490;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_844_p0 <= bufo_0_load_reg_1990;
else
grp_fu_844_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_844_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, tmp_s_reg_1995, ap_enable_reg_pp0_iter3, ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170, ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335, ap_enable_reg_pp0_iter51, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_844_p1 <= ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_844_p1 <= ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_844_p1 <= tmp_s_reg_1995;
else
grp_fu_844_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_848_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufo_1_load_reg_2040, ap_enable_reg_pp0_iter3, temp_2_2_1_2_reg_2495, temp_2_0_3_1_reg_2620, ap_enable_reg_pp0_iter54, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_848_p0 <= temp_2_0_3_1_reg_2620;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_848_p0 <= temp_2_2_1_2_reg_2495;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_848_p0 <= bufo_1_load_reg_2040;
else
grp_fu_848_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_848_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, tmp_10_1_reg_2045, ap_enable_reg_pp0_iter3, ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215, ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255, ap_enable_reg_pp0_iter54, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_848_p1 <= ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_848_p1 <= ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_848_p1 <= tmp_10_1_reg_2045;
else
grp_fu_848_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_852_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufo_2_load_reg_2085, ap_enable_reg_pp0_iter3, temp_2_0_1_3_reg_2500, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter54, temp_2_1_3_1_reg_2625, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p0 <= temp_2_1_3_1_reg_2625;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p0 <= temp_2_0_1_3_reg_2500;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p0 <= bufo_2_load_reg_2085;
else
grp_fu_852_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_852_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, tmp_10_2_reg_2090, ap_enable_reg_pp0_iter3, ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130, ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter54, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p1 <= ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p1 <= ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_852_p1 <= tmp_10_2_reg_2090;
else
grp_fu_852_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_856_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_reg_2380, temp_2_1_1_3_reg_2505, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter54, temp_2_2_3_1_reg_2630, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_856_p0 <= temp_2_2_3_1_reg_2630;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_856_p0 <= temp_2_1_1_3_reg_2505;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_856_p0 <= temp_2_reg_2380;
else
grp_fu_856_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_856_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000, ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175, ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter54, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter54) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_856_p1 <= ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_856_p1 <= ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_856_p1 <= ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000;
else
grp_fu_856_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_860_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_reg_2385, ap_enable_reg_pp0_iter30, temp_2_2_1_3_reg_2510, temp_2_0_3_2_reg_2635, ap_enable_reg_pp0_iter57, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_860_p0 <= temp_2_0_3_2_reg_2635;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_860_p0 <= temp_2_2_1_3_reg_2510;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_860_p0 <= temp_2_1_reg_2385;
else
grp_fu_860_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_860_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050, ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220, ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter57, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_860_p1 <= ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter30) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_860_p1 <= ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_860_p1 <= ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050;
else
grp_fu_860_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_864_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_reg_2390, temp_2_0_1_4_reg_2515, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter57, temp_2_1_3_2_reg_2640, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_864_p0 <= temp_2_1_3_2_reg_2640;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_864_p0 <= temp_2_0_1_4_reg_2515;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_864_p0 <= temp_2_2_reg_2390;
else
grp_fu_864_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_864_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095, ap_reg_pp0_iter33_tmp_10_0_2_reg_2135, ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter57, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_864_p1 <= ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_864_p1 <= ap_reg_pp0_iter33_tmp_10_0_2_reg_2135;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_864_p1 <= ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095;
else
grp_fu_864_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_868_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_0_1_reg_2395, ap_enable_reg_pp0_iter33, temp_2_1_1_4_reg_2520, ap_enable_reg_pp0_iter57, temp_2_2_3_2_reg_2645, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_868_p0 <= temp_2_2_3_2_reg_2645;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_868_p0 <= temp_2_1_1_4_reg_2520;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_868_p0 <= temp_2_0_0_1_reg_2395;
else
grp_fu_868_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_868_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005, ap_reg_pp0_iter33_tmp_10_1_2_reg_2180, ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter57, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter57) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_868_p1 <= ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_868_p1 <= ap_reg_pp0_iter33_tmp_10_1_2_reg_2180;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_868_p1 <= ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005;
else
grp_fu_868_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_872_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_0_1_reg_2400, ap_enable_reg_pp0_iter33, temp_2_2_1_4_reg_2525, temp_2_0_3_3_reg_2650, ap_enable_reg_pp0_iter60, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_872_p0 <= temp_2_0_3_3_reg_2650;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_872_p0 <= temp_2_2_1_4_reg_2525;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_872_p0 <= temp_2_1_0_1_reg_2400;
else
grp_fu_872_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_872_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055, ap_reg_pp0_iter33_tmp_10_2_2_reg_2225, ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter60, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_872_p1 <= ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter33) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_872_p1 <= ap_reg_pp0_iter33_tmp_10_2_2_reg_2225;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_872_p1 <= ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055;
else
grp_fu_872_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_876_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_0_1_reg_2405, temp_2_0_2_reg_2530, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter60, temp_2_1_3_3_reg_2655, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_876_p0 <= temp_2_1_3_3_reg_2655;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_876_p0 <= temp_2_0_2_reg_2530;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_876_p0 <= temp_2_2_0_1_reg_2405;
else
grp_fu_876_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_876_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100, ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140, ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter60, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_876_p1 <= ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_876_p1 <= ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
grp_fu_876_p1 <= ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100;
else
grp_fu_876_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_880_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_0_2_reg_2410, ap_enable_reg_pp0_iter36, temp_2_1_2_reg_2535, ap_enable_reg_pp0_iter60, temp_2_2_3_3_reg_2660, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_880_p0 <= temp_2_2_3_3_reg_2660;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_880_p0 <= temp_2_1_2_reg_2535;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_880_p0 <= temp_2_0_0_2_reg_2410;
else
grp_fu_880_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_880_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010, ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185, ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter60, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter60) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_880_p1 <= ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_880_p1 <= ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_880_p1 <= ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010;
else
grp_fu_880_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_884_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_0_2_reg_2415, ap_enable_reg_pp0_iter36, temp_2_2_2_reg_2540, temp_2_0_3_4_reg_2665, ap_enable_reg_pp0_iter63, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_884_p0 <= temp_2_0_3_4_reg_2665;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_884_p0 <= temp_2_2_2_reg_2540;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_884_p0 <= temp_2_1_0_2_reg_2415;
else
grp_fu_884_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_884_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060, ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230, ap_reg_pp0_iter63_tmp_10_0_4_reg_2270, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter63, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_884_p1 <= ap_reg_pp0_iter63_tmp_10_0_4_reg_2270;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter36) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_884_p1 <= ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_884_p1 <= ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060;
else
grp_fu_884_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_888_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_0_2_reg_2420, temp_2_0_2_1_reg_2545, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter63, temp_2_1_3_4_reg_2670, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_888_p0 <= temp_2_1_3_4_reg_2670;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_888_p0 <= temp_2_0_2_1_reg_2545;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_888_p0 <= temp_2_2_0_2_reg_2420;
else
grp_fu_888_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_888_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105, ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145, ap_reg_pp0_iter63_tmp_10_1_4_reg_2310, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter63, ap_enable_reg_pp0_iter12, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_888_p1 <= ap_reg_pp0_iter63_tmp_10_1_4_reg_2310;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_888_p1 <= ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter12))) then
grp_fu_888_p1 <= ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105;
else
grp_fu_888_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_892_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_0_3_reg_2425, ap_enable_reg_pp0_iter39, temp_2_1_2_1_reg_2550, ap_enable_reg_pp0_iter63, temp_2_2_3_4_reg_2675, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_892_p0 <= temp_2_2_3_4_reg_2675;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_892_p0 <= temp_2_1_2_1_reg_2550;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_892_p0 <= temp_2_0_0_3_reg_2425;
else
grp_fu_892_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_892_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015, ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190, ap_reg_pp0_iter63_tmp_10_2_4_reg_2355, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter63, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter63) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_892_p1 <= ap_reg_pp0_iter63_tmp_10_2_4_reg_2355;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_892_p1 <= ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_892_p1 <= ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015;
else
grp_fu_892_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_896_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_0_3_reg_2430, ap_enable_reg_pp0_iter39, temp_2_2_2_1_reg_2555, temp_2_0_4_reg_2680, ap_enable_reg_pp0_iter66, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_896_p0 <= temp_2_0_4_reg_2680;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_896_p0 <= temp_2_2_2_1_reg_2555;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_896_p0 <= temp_2_1_0_3_reg_2430;
else
grp_fu_896_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_896_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065, ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235, ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter66, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_896_p1 <= ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter39) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_896_p1 <= ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_896_p1 <= ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065;
else
grp_fu_896_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_900_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_0_3_reg_2435, temp_2_0_2_2_reg_2560, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter66, temp_2_1_4_reg_2685, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_900_p0 <= temp_2_1_4_reg_2685;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_900_p0 <= temp_2_0_2_2_reg_2560;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_900_p0 <= temp_2_2_0_3_reg_2435;
else
grp_fu_900_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_900_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110, ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150, ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter66, ap_enable_reg_pp0_iter15, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_900_p1 <= ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_900_p1 <= ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter15))) then
grp_fu_900_p1 <= ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110;
else
grp_fu_900_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_904_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_0_4_reg_2440, ap_enable_reg_pp0_iter42, temp_2_1_2_2_reg_2565, ap_enable_reg_pp0_iter66, temp_2_2_4_reg_2690, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_904_p0 <= temp_2_2_4_reg_2690;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_904_p0 <= temp_2_1_2_2_reg_2565;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_904_p0 <= temp_2_0_0_4_reg_2440;
else
grp_fu_904_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_904_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter17_tmp_10_0_1_reg_2020, ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195, ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter66, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter66) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_904_p1 <= ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_904_p1 <= ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_904_p1 <= ap_reg_pp0_iter17_tmp_10_0_1_reg_2020;
else
grp_fu_904_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_908_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_0_4_reg_2445, ap_enable_reg_pp0_iter42, temp_2_2_2_2_reg_2570, temp_2_0_4_1_reg_2695, ap_enable_reg_pp0_iter69, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_908_p0 <= temp_2_0_4_1_reg_2695;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_908_p0 <= temp_2_2_2_2_reg_2570;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_908_p0 <= temp_2_1_0_4_reg_2445;
else
grp_fu_908_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_908_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter17_tmp_10_1_1_reg_2070, ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240, ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter69, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_908_p1 <= ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter42) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_908_p1 <= ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_908_p1 <= ap_reg_pp0_iter17_tmp_10_1_1_reg_2070;
else
grp_fu_908_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_912_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_0_4_reg_2450, temp_2_0_2_3_reg_2575, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter69, temp_2_1_4_1_reg_2700, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_912_p0 <= temp_2_1_4_1_reg_2700;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_912_p0 <= temp_2_0_2_3_reg_2575;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_912_p0 <= temp_2_2_0_4_reg_2450;
else
grp_fu_912_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_912_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter17_tmp_10_2_1_reg_2115, ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155, ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter69, ap_enable_reg_pp0_iter18, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_912_p1 <= ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_912_p1 <= ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter18))) then
grp_fu_912_p1 <= ap_reg_pp0_iter17_tmp_10_2_1_reg_2115;
else
grp_fu_912_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_916_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_1_reg_2455, ap_enable_reg_pp0_iter45, temp_2_1_2_3_reg_2580, ap_enable_reg_pp0_iter69, temp_2_2_4_1_reg_2705, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_916_p0 <= temp_2_2_4_1_reg_2705;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_916_p0 <= temp_2_1_2_3_reg_2580;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_916_p0 <= temp_2_0_1_reg_2455;
else
grp_fu_916_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_916_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025, ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200, ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter69, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter69) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_916_p1 <= ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_916_p1 <= ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_916_p1 <= ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025;
else
grp_fu_916_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_920_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_1_reg_2460, ap_enable_reg_pp0_iter45, temp_2_2_2_3_reg_2585, temp_2_0_4_2_reg_2710, ap_enable_reg_pp0_iter72, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_920_p0 <= temp_2_0_4_2_reg_2710;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_920_p0 <= temp_2_2_2_3_reg_2585;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_920_p0 <= temp_2_1_1_reg_2460;
else
grp_fu_920_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_920_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075, ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245, ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter72, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_920_p1 <= ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter45) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_920_p1 <= ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_920_p1 <= ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075;
else
grp_fu_920_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_924_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_1_reg_2465, temp_2_0_2_4_reg_2590, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter72, temp_2_1_4_2_reg_2715, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_924_p0 <= temp_2_1_4_2_reg_2715;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_924_p0 <= temp_2_0_2_4_reg_2590;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_924_p0 <= temp_2_2_1_reg_2465;
else
grp_fu_924_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_924_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120, ap_reg_pp0_iter48_tmp_10_0_3_reg_2160, ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter72, ap_enable_reg_pp0_iter21, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_924_p1 <= ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_924_p1 <= ap_reg_pp0_iter48_tmp_10_0_3_reg_2160;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter21))) then
grp_fu_924_p1 <= ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120;
else
grp_fu_924_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_928_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_1_1_reg_2470, ap_enable_reg_pp0_iter48, temp_2_1_2_4_reg_2595, ap_enable_reg_pp0_iter72, temp_2_2_4_2_reg_2720, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_928_p0 <= temp_2_2_4_2_reg_2720;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_928_p0 <= temp_2_1_2_4_reg_2595;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_928_p0 <= temp_2_0_1_1_reg_2470;
else
grp_fu_928_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_928_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030, ap_reg_pp0_iter48_tmp_10_1_3_reg_2205, ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter72, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter72) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_928_p1 <= ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_928_p1 <= ap_reg_pp0_iter48_tmp_10_1_3_reg_2205;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_928_p1 <= ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030;
else
grp_fu_928_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_932_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_1_1_1_reg_2475, ap_enable_reg_pp0_iter48, temp_2_2_2_4_reg_2600, temp_2_0_4_3_reg_2725, ap_enable_reg_pp0_iter75, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_932_p0 <= temp_2_0_4_3_reg_2725;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_932_p0 <= temp_2_2_2_4_reg_2600;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_932_p0 <= temp_2_1_1_1_reg_2475;
else
grp_fu_932_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_932_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080, ap_reg_pp0_iter48_tmp_10_2_3_reg_2250, ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter75, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_932_p1 <= ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter48) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_932_p1 <= ap_reg_pp0_iter48_tmp_10_2_3_reg_2250;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_932_p1 <= ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080;
else
grp_fu_932_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_936_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_2_1_1_reg_2480, temp_2_0_3_reg_2605, ap_enable_reg_pp0_iter51, ap_enable_reg_pp0_iter75, temp_2_1_4_3_reg_2730, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_936_p0 <= temp_2_1_4_3_reg_2730;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_936_p0 <= temp_2_0_3_reg_2605;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_936_p0 <= temp_2_2_1_1_reg_2480;
else
grp_fu_936_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_936_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125, ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165, ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330, ap_enable_reg_pp0_iter51, ap_enable_reg_pp0_iter75, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_936_p1 <= ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_936_p1 <= ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter24))) then
grp_fu_936_p1 <= ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125;
else
grp_fu_936_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_940_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, temp_2_0_1_2_reg_2485, ap_enable_reg_pp0_iter51, temp_2_1_3_reg_2610, ap_enable_reg_pp0_iter75, temp_2_2_4_3_reg_2735, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_940_p0 <= temp_2_2_4_3_reg_2735;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_940_p0 <= temp_2_1_3_reg_2610;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_940_p0 <= temp_2_0_1_2_reg_2485;
else
grp_fu_940_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_940_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035, ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210, ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375, ap_enable_reg_pp0_iter51, ap_enable_reg_pp0_iter75, ap_enable_reg_pp0_iter27, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter75) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_940_p1 <= ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter51) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_940_p1 <= ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter27))) then
grp_fu_940_p1 <= ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035;
else
grp_fu_940_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_944_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_0_load_reg_1512, ap_enable_reg_pp0_iter1, bufw_1_4_load_reg_1735, bufw_3_2_load_reg_1868, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p0 <= bufw_3_2_load_reg_1868;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p0 <= bufw_1_4_load_reg_1735;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p0 <= bufw_0_0_load_reg_1512;
else
grp_fu_944_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_944_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_0_load_reg_1354, ap_enable_reg_pp0_iter1, bufi_4_load_1_reg_1599, bufi_2_load_3_reg_1801, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p1 <= bufi_2_load_3_reg_1801;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p1 <= bufi_4_load_1_reg_1599;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_944_p1 <= bufi_0_load_reg_1354;
else
grp_fu_944_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_948_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_1_load_reg_1519, ap_enable_reg_pp0_iter1, bufw_2_0_load_reg_1742, bufw_3_3_load_reg_1875, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p0 <= bufw_3_3_load_reg_1875;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p0 <= bufw_2_0_load_reg_1742;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p0 <= bufw_0_1_load_reg_1519;
else
grp_fu_948_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_948_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_1_load_reg_1359, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_1606, bufi_3_load_3_reg_1808, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p1 <= bufi_3_load_3_reg_1808;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p1 <= bufi_0_load_2_reg_1606;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_948_p1 <= bufi_1_load_reg_1359;
else
grp_fu_948_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_952_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_2_load_reg_1526, ap_enable_reg_pp0_iter1, bufw_2_1_load_reg_1749, bufw_3_4_load_reg_1882, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p0 <= bufw_3_4_load_reg_1882;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p0 <= bufw_2_1_load_reg_1749;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p0 <= bufw_0_2_load_reg_1526;
else
grp_fu_952_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_952_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_2_load_reg_1365, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_1611, bufi_4_load_3_reg_1815, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p1 <= bufi_4_load_3_reg_1815;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p1 <= bufi_1_load_2_reg_1611;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_952_p1 <= bufi_2_load_reg_1365;
else
grp_fu_952_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_956_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_3_load_reg_1533, ap_enable_reg_pp0_iter1, bufw_2_2_load_reg_1756, bufw_4_0_load_reg_1889, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p0 <= bufw_4_0_load_reg_1889;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p0 <= bufw_2_2_load_reg_1756;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p0 <= bufw_0_3_load_reg_1533;
else
grp_fu_956_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_956_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_3_load_reg_1372, ap_enable_reg_pp0_iter1, bufi_2_load_2_reg_1617, bufi_0_load_4_reg_1896, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p1 <= bufi_0_load_4_reg_1896;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p1 <= bufi_2_load_2_reg_1617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_956_p1 <= bufi_3_load_reg_1372;
else
grp_fu_956_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_960_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_4_load_reg_1540, ap_enable_reg_pp0_iter1, bufw_2_3_load_reg_1763, bufw_4_1_load_reg_1901, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p0 <= bufw_4_1_load_reg_1901;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p0 <= bufw_2_3_load_reg_1763;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p0 <= bufw_0_4_load_reg_1540;
else
grp_fu_960_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_960_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_4_load_reg_1379, ap_enable_reg_pp0_iter1, bufi_3_load_2_reg_1624, bufi_1_load_4_reg_1908, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p1 <= bufi_1_load_4_reg_1908;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p1 <= bufi_3_load_2_reg_1624;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_960_p1 <= bufi_4_load_reg_1379;
else
grp_fu_960_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_964_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_1_0_load_reg_1547, ap_enable_reg_pp0_iter1, bufw_2_4_load_reg_1770, bufw_4_2_load_reg_1914, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p0 <= bufw_4_2_load_reg_1914;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p0 <= bufw_2_4_load_reg_1770;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p0 <= bufw_1_0_load_reg_1547;
else
grp_fu_964_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_964_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_0_load_1_reg_1554, ap_enable_reg_pp0_iter1, bufi_4_load_2_reg_1631, bufi_2_load_4_reg_1921, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p1 <= bufi_2_load_4_reg_1921;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p1 <= bufi_4_load_2_reg_1631;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_964_p1 <= bufi_0_load_1_reg_1554;
else
grp_fu_964_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_968_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_1_load_reg_1559, bufw_3_0_load_reg_1777, bufw_4_3_load_reg_1928, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p0 <= bufw_4_3_load_reg_1928;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p0 <= bufw_3_0_load_reg_1777;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p0 <= bufw_1_1_load_reg_1559;
else
grp_fu_968_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_968_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_1_load_1_reg_1566, bufi_0_load_3_reg_1784, bufi_3_load_4_reg_1935, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p1 <= bufi_3_load_4_reg_1935;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p1 <= bufi_0_load_3_reg_1784;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_968_p1 <= bufi_1_load_1_reg_1566;
else
grp_fu_968_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_972_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_2_load_reg_1572, bufw_3_1_load_reg_1789, bufw_4_4_load_reg_1942, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p0 <= bufw_4_4_load_reg_1942;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p0 <= bufw_3_1_load_reg_1789;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p0 <= bufw_1_2_load_reg_1572;
else
grp_fu_972_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_972_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_2_load_1_reg_1579, bufi_1_load_3_reg_1795, bufi_4_load_4_reg_1949, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p1 <= bufi_4_load_4_reg_1949;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p1 <= bufi_1_load_3_reg_1795;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_972_p1 <= bufi_2_load_1_reg_1579;
else
grp_fu_972_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_976_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufw_1_3_load_reg_1586, bufw_3_2_load_reg_1868, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_976_p0 <= bufw_3_2_load_reg_1868;
elsif ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)))) then
grp_fu_976_p0 <= bufw_1_3_load_reg_1586;
else
grp_fu_976_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_976_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter1, bufi_3_load_1_reg_1592, bufi_4_load_1_reg_1599, bufi_3_load_3_reg_1808, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_976_p1 <= bufi_3_load_3_reg_1808;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_976_p1 <= bufi_4_load_1_reg_1599;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_976_p1 <= bufi_3_load_1_reg_1592;
else
grp_fu_976_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_980_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_0_load_reg_1512, ap_enable_reg_pp0_iter1, bufw_1_4_load_reg_1735, bufw_3_3_load_reg_1875, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p0 <= bufw_3_3_load_reg_1875;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p0 <= bufw_1_4_load_reg_1735;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p0 <= bufw_0_0_load_reg_1512;
else
grp_fu_980_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_980_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_1_load_reg_1359, ap_enable_reg_pp0_iter1, bufi_5_load_1_reg_1673, bufi_4_load_3_reg_1815, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p1 <= bufi_4_load_3_reg_1815;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p1 <= bufi_5_load_1_reg_1673;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_980_p1 <= bufi_1_load_reg_1359;
else
grp_fu_980_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_984_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_1_load_reg_1519, ap_enable_reg_pp0_iter1, bufw_2_0_load_reg_1742, bufw_3_4_load_reg_1882, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p0 <= bufw_3_4_load_reg_1882;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p0 <= bufw_2_0_load_reg_1742;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p0 <= bufw_0_1_load_reg_1519;
else
grp_fu_984_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_984_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_2_load_reg_1365, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_1611, bufi_5_load_3_reg_1857, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p1 <= bufi_5_load_3_reg_1857;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p1 <= bufi_1_load_2_reg_1611;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_984_p1 <= bufi_2_load_reg_1365;
else
grp_fu_984_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_988_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_2_load_reg_1526, ap_enable_reg_pp0_iter1, bufw_2_1_load_reg_1749, bufw_4_0_load_reg_1889, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p0 <= bufw_4_0_load_reg_1889;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p0 <= bufw_2_1_load_reg_1749;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p0 <= bufw_0_2_load_reg_1526;
else
grp_fu_988_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_988_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_3_load_reg_1372, ap_enable_reg_pp0_iter1, bufi_2_load_2_reg_1617, bufi_1_load_4_reg_1908, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p1 <= bufi_1_load_4_reg_1908;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p1 <= bufi_2_load_2_reg_1617;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_988_p1 <= bufi_3_load_reg_1372;
else
grp_fu_988_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_992_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_3_load_reg_1533, ap_enable_reg_pp0_iter1, bufw_2_2_load_reg_1756, bufw_4_1_load_reg_1901, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p0 <= bufw_4_1_load_reg_1901;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p0 <= bufw_2_2_load_reg_1756;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p0 <= bufw_0_3_load_reg_1533;
else
grp_fu_992_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_992_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_4_load_reg_1379, ap_enable_reg_pp0_iter1, bufi_3_load_2_reg_1624, bufi_2_load_4_reg_1921, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p1 <= bufi_2_load_4_reg_1921;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p1 <= bufi_3_load_2_reg_1624;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_992_p1 <= bufi_4_load_reg_1379;
else
grp_fu_992_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_996_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufw_0_4_load_reg_1540, ap_enable_reg_pp0_iter1, bufw_2_3_load_reg_1763, bufw_4_2_load_reg_1914, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p0 <= bufw_4_2_load_reg_1914;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p0 <= bufw_2_3_load_reg_1763;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p0 <= bufw_0_4_load_reg_1540;
else
grp_fu_996_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_996_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, bufi_5_load_reg_1461, ap_enable_reg_pp0_iter1, bufi_4_load_2_reg_1631, bufi_3_load_4_reg_1935, ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p1 <= bufi_3_load_4_reg_1935;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p1 <= bufi_4_load_2_reg_1631;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_996_p1 <= bufi_5_load_reg_1461;
else
grp_fu_996_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
indvar_flatten_next_fu_1050_p2 <= std_logic_vector(unsigned(indvar_flatten_phi_fu_814_p4) + unsigned(ap_const_lv8_1));
indvar_flatten_phi_fu_814_p4_assign_proc : process(indvar_flatten_reg_810, exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage0, indvar_flatten_next_reg_1206, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
indvar_flatten_phi_fu_814_p4 <= indvar_flatten_next_reg_1206;
else
indvar_flatten_phi_fu_814_p4 <= indvar_flatten_reg_810;
end if;
end process;
lhs_V_cast1_fu_1092_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_1_mid2_reg_1221),3));
p_1_mid2_fu_1068_p3 <=
ap_const_lv2_0 when (tmp_1_fu_1062_p2(0) = '1') else
p_1_phi_fu_837_p4;
p_1_phi_fu_837_p4_assign_proc : process(p_1_reg_833, exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage0, row_b_V_reg_1278, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
p_1_phi_fu_837_p4 <= row_b_V_reg_1278;
else
p_1_phi_fu_837_p4 <= p_1_reg_833;
end if;
end process;
p_s_phi_fu_825_p4_assign_proc : process(p_s_reg_821, exitcond_flatten_reg_1202, ap_CS_fsm_pp0_stage0, tmp_mid2_v_reg_1230, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_1202 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
p_s_phi_fu_825_p4 <= tmp_mid2_v_reg_1230;
else
p_s_phi_fu_825_p4 <= p_s_reg_821;
end if;
end process;
r_V_1_0_2_fu_1100_p2 <= std_logic_vector(unsigned(lhs_V_cast1_fu_1092_p1) + unsigned(ap_const_lv3_2));
r_V_1_0_3_fu_1138_p2 <= std_logic_vector(unsigned(lhs_V_cast1_reg_1273) + unsigned(ap_const_lv3_3));
r_V_1_0_s_fu_1153_p3 <= (ap_const_lv1_1 & ap_reg_pp0_iter1_p_1_mid2_reg_1221);
row_b_V_fu_1095_p2 <= std_logic_vector(unsigned(p_1_mid2_reg_1221) + unsigned(ap_const_lv2_1));
tmp_1_fu_1062_p2 <= "1" when (p_1_phi_fu_837_p4 = ap_const_lv2_3) else "0";
tmp_2_0_1_fu_1118_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_V_reg_1278),64));
tmp_2_0_2_fu_1128_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_1_0_2_reg_1284),64));
tmp_2_0_3_fu_1143_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_1_0_3_reg_1456),64));
tmp_2_0_4_fu_1160_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_1_0_s_fu_1153_p3),64));
tmp_2_fu_1181_p2 <= std_logic_vector(unsigned(tmp_fu_1174_p3) - unsigned(tmp_mid2_cast_fu_1171_p1));
tmp_3_cast_fu_1187_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter1_p_1_mid2_reg_1221),9));
tmp_3_fu_1082_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_1_mid2_reg_1221),64));
tmp_4_cast_fu_1196_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_4_reg_1967),64));
tmp_4_fu_1190_p2 <= std_logic_vector(unsigned(tmp_2_fu_1181_p2) + unsigned(tmp_3_cast_fu_1187_p1));
tmp_fu_1174_p3 <= (ap_reg_pp0_iter1_tmp_mid2_v_reg_1230 & ap_const_lv2_0);
tmp_mid2_cast_fu_1171_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter1_tmp_mid2_v_reg_1230),9));
tmp_mid2_fu_1106_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_mid2_v_reg_1230),64));
tmp_mid2_v_fu_1076_p3 <=
to_b_V_reg_1211 when (tmp_1_reg_1216(0) = '1') else
p_s_reg_821;
to_b_V_fu_1056_p2 <= std_logic_vector(unsigned(p_s_phi_fu_825_p4) + unsigned(ap_const_lv7_1));
end behav;
| mit | da089cd2f790df755f7f5a2ca7e2017c | 0.626521 | 2.362274 | false | false | false | false |
kloboves/sicxe | vhdl/computer_interface.vhd | 1 | 12,811 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity computer_interface is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
serial_i : in std_logic;
serial_o : out std_logic;
control_signals_o : out std_logic_vector(3 downto 0);
memory_read_o : out std_logic;
memory_write_o : out std_logic;
memory_address_o : out std_logic_vector(19 downto 0);
memory_data_in_i : in std_logic_vector(7 downto 0);
memory_data_out_o : out std_logic_vector(7 downto 0);
memory_done_i : in std_logic
);
end computer_interface;
architecture behavioral of computer_interface is
component rs232_in
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
data_o : out std_logic_vector(7 downto 0);
receive_o : out std_logic
);
end component;
component rs232_out
Port (
clock_i : in std_logic;
reset_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
send_i : in std_logic;
output_o : out std_logic;
ready_o : out std_logic
);
end component;
-- serial port signals
signal in_data : std_logic_vector(7 downto 0);
signal in_receive : std_logic;
signal out_data : std_logic_vector(7 downto 0);
signal out_ready : std_logic;
signal out_send : std_logic;
-- registers
signal reg_command : std_logic_vector(7 downto 0);
signal reg_command_write : std_logic;
signal reg_address : std_logic_vector(19 downto 0);
signal reg_address_write_byte2 : std_logic;
signal reg_address_write_byte1 : std_logic;
signal reg_address_write_byte0 : std_logic;
signal reg_address_increment : std_logic;
signal reg_data : std_logic_vector(7 downto 0);
signal reg_data_write_in : std_logic;
signal reg_data_write_mem : std_logic;
signal reg_count : std_logic_vector(15 downto 0);
signal reg_count_write_byte1 : std_logic;
signal reg_count_write_byte0 : std_logic;
signal reg_count_decrement : std_logic;
signal reg_control_signals : std_logic_vector(3 downto 0);
signal control_signals : std_logic_vector(3 downto 0);
-- FSM
type state_type is (LOCKED, PROTO_ERROR, KEY_GET1, KEY_GET2, KEY_GET3, KEY_GET4,
KEY_SEND1, KEY_SEND2, KEY_SEND3, UNLOCKED, COMMAND_ACCEPT,
GET_ADDR0, GET_ADDR1, GET_ADDR2, GET_COUNT0, GET_COUNT1,
WRITE_START, WRITE_IN, WRITE_MEM, READ_START, READ_MEM,
READ_OUT);
signal state : state_type;
signal next_state : state_type;
begin
-- output connections
memory_address_o <= reg_address;
memory_data_out_o <= reg_data;
control_signals_o <= reg_control_signals;
-- rs232 components
rs232_in_cmpt : rs232_in
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => serial_i,
data_o => in_data,
receive_o => in_receive
);
rs232_out_cmpt : rs232_out
port map (
clock_i => clock_i,
reset_i => reset_i,
data_i => out_data,
send_i => out_send,
output_o => serial_o,
ready_o => out_ready
);
-- registers
reg_command_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_command <= (others => '0');
else
if (reg_command_write = '1') then
reg_command <= in_data;
else
reg_command <= reg_command;
end if;
end if;
end if;
end process;
reg_address_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_address <= (others => '0');
else
reg_address <= reg_address;
if (reg_address_write_byte2 = '1') then
reg_address(19 downto 16) <= in_data(3 downto 0);
elsif (reg_address_write_byte1 = '1') then
reg_address(15 downto 8) <= in_data;
elsif (reg_address_write_byte0 = '1') then
reg_address(7 downto 0) <= in_data;
elsif (reg_address_increment = '1') then
reg_address <= reg_address + 1;
end if;
end if;
end if;
end process;
reg_data_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_data <= (others => '0');
else
if (reg_data_write_in = '1') then
reg_data <= in_data;
elsif (reg_data_write_mem = '1') then
reg_data <= memory_data_in_i;
else
reg_data <= reg_data;
end if;
end if;
end if;
end process;
reg_count_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_count <= (others => '0');
else
reg_count <= reg_count;
if (reg_count_write_byte1 = '1') then
reg_count(15 downto 8) <= in_data;
elsif (reg_count_write_byte0 = '1') then
reg_count(7 downto 0) <= in_data;
elsif (reg_count_decrement = '1') then
reg_count <= reg_count - 1;
end if;
end if;
end if;
end process;
control_signals_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_control_signals <= (others => '0');
else
reg_control_signals <= control_signals;
end if;
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
state <= LOCKED;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, in_receive, in_data, out_ready, reg_command, reg_count,
memory_done_i)
begin
next_state <= state;
case (state) is
when PROTO_ERROR =>
if (out_ready = '1') then
next_state <= LOCKED;
end if;
when LOCKED =>
if (in_receive = '1') then
if (in_data = x"53") then
next_state <= KEY_GET1;
else
next_state <= PROTO_ERROR;
end if;
end if;
when KEY_GET1 =>
if (in_receive = '1') then
if (in_data = x"49") then
next_state <= KEY_GET2;
else
next_state <= PROTO_ERROR;
end if;
end if;
when KEY_GET2 =>
if (in_receive = '1') then
if (in_data = x"43") then
next_state <= KEY_GET3;
else
next_state <= PROTO_ERROR;
end if;
end if;
when KEY_GET3 =>
if (in_receive = '1') then
if (in_data = x"58") then
next_state <= KEY_GET4;
else
next_state <= PROTO_ERROR;
end if;
end if;
when KEY_GET4 =>
if (in_receive = '1') then
if (in_data = x"45") then
next_state <= KEY_SEND1;
else
next_state <= PROTO_ERROR;
end if;
end if;
when KEY_SEND1 =>
if (out_ready = '1') then
next_state <= KEY_SEND2;
end if;
when KEY_SEND2 =>
if (out_ready = '1') then
next_state <= KEY_SEND3;
end if;
when KEY_SEND3 =>
if (out_ready = '1') then
next_state <= UNLOCKED;
end if;
when UNLOCKED =>
if (in_receive = '1') then
if (in_data = x"00" or in_data = x"01" or in_data = x"02" or
in_data = x"10" or in_data = x"11" or in_data = x"12" or
in_data = x"13" or in_data = x"ff") then
next_state <= COMMAND_ACCEPT;
else
next_state <= PROTO_ERROR;
end if;
end if;
when COMMAND_ACCEPT =>
if (out_ready = '1') then
if (reg_command = x"ff") then -- end session
next_state <= LOCKED;
elsif (reg_command = x"01" or reg_command = x"02") then
next_state <= GET_ADDR0;
else
next_state <= UNLOCKED;
end if;
end if;
when GET_ADDR0 =>
if (in_receive = '1') then
next_state <= GET_ADDR1;
end if;
when GET_ADDR1 =>
if (in_receive = '1') then
next_state <= GET_ADDR2;
end if;
when GET_ADDR2 =>
if (in_receive = '1') then
next_state <= GET_COUNT0;
end if;
when GET_COUNT0 =>
if (in_receive = '1') then
next_state <= GET_COUNT1;
end if;
when GET_COUNT1 =>
if (in_receive = '1') then
if (reg_command = x"02") then
next_state <= WRITE_START;
else
next_state <= READ_START;
end if;
end if;
when WRITE_START =>
if (reg_count = x"0000") then
next_state <= UNLOCKED;
else
next_state <= WRITE_IN;
end if;
when WRITE_IN =>
if (in_receive = '1') then
next_state <= WRITE_MEM;
end if;
when WRITE_MEM =>
if (memory_done_i = '1') then
next_state <= WRITE_START;
end if;
when READ_START =>
if (reg_count = x"0000") then
next_state <= UNLOCKED;
else
next_state <= READ_MEM;
end if;
when READ_MEM =>
if (memory_done_i = '1') then
next_state <= READ_OUT;
end if;
when READ_OUT =>
if (out_ready = '1') then
next_state <= READ_START;
end if;
when others =>
end case;
end process;
output_proc : process(state, in_receive, in_data, out_ready, reg_command, reg_data,
memory_done_i)
begin
memory_read_o <= '0';
memory_write_o <= '0';
out_data <= (others => '0');
out_send <= '0';
reg_address_write_byte2 <= '0';
reg_address_write_byte1 <= '0';
reg_address_write_byte0 <= '0';
reg_address_increment <= '0';
reg_data_write_in <= '0';
reg_data_write_mem <= '0';
reg_count_write_byte1 <= '0';
reg_count_write_byte0 <= '0';
reg_count_decrement <= '0';
reg_command_write <= '0';
control_signals <= (others => '0');
case (state) is
when PROTO_ERROR =>
if (out_ready = '1') then
out_data <= x"58";
out_send <= '1';
end if;
when LOCKED | KEY_GET1 | KEY_GET2 | KEY_GET3 | KEY_GET4 =>
when KEY_SEND1 =>
if (out_ready = '1') then
out_data <= x"41";
out_send <= '1';
end if;
when KEY_SEND2 =>
if (out_ready = '1') then
out_data <= x"43";
out_send <= '1';
end if;
when KEY_SEND3 =>
if (out_ready = '1') then
out_data <= x"4b";
out_send <= '1';
end if;
when UNLOCKED =>
if (in_receive = '1'and
(in_data = x"00" or in_data = x"01" or in_data = x"02" or
in_data = x"10" or in_data = x"11" or in_data = x"12" or
in_data = x"13" or in_data = x"ff")) then
reg_command_write <= '1';
end if;
when COMMAND_ACCEPT =>
if (out_ready = '1') then
out_data <= x"4B";
out_send <= '1';
if (reg_command = x"10") then
control_signals(0) <= '1';
elsif (reg_command = x"11") then
control_signals(1) <= '1';
elsif (reg_command = x"12") then
control_signals(2) <= '1';
elsif (reg_command = x"13") then
control_signals(3) <= '1';
end if;
end if;
when GET_ADDR0 =>
if (in_receive = '1') then
reg_address_write_byte0 <= '1';
end if;
when GET_ADDR1 =>
if (in_receive = '1') then
reg_address_write_byte1 <= '1';
end if;
when GET_ADDR2 =>
if (in_receive = '1') then
reg_address_write_byte2 <= '1';
end if;
when GET_COUNT0 =>
if (in_receive = '1') then
reg_count_write_byte0 <= '1';
end if;
when GET_COUNT1 =>
if (in_receive = '1') then
reg_count_write_byte1 <= '1';
end if;
when WRITE_START =>
when WRITE_IN =>
if (in_receive = '1') then
reg_data_write_in <= '1';
end if;
when WRITE_MEM =>
memory_write_o <= '1';
if (memory_done_i = '1') then
reg_count_decrement <= '1';
reg_address_increment <= '1';
end if;
when READ_START =>
when READ_MEM =>
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_data_write_mem <= '1';
end if;
when READ_OUT =>
if (out_ready = '1') then
out_data <= reg_data;
out_send <= '1';
reg_count_decrement <= '1';
reg_address_increment <= '1';
end if;
when others =>
end case;
end process;
end behavioral;
| mit | 63ec31d8771fcacf81fee4127e70bd47 | 0.512528 | 3.364233 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/core.vhd | 1 | 45,844 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity core is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
keyPad : in STD_LOGIC_VECTOR (15 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
cpu_state : out STD_LOGIC_VECTOR( 7 downto 0 );
t_PC : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_I : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_addr : out STD_LOGIC_VECTOR ( 11 downto 0 );
t_n, t_x, t_y : out STD_LOGIC_VECTOR ( 3 downto 0 );
t_kk : out STD_LOGIC_VECTOR ( 7 downto 0 );
t_SP : out STD_LOGIC_VECTOR ( 7 downto 0 );
t_STACK_0, t_STACK_1, t_STACK_2, t_STACK_3,
t_STACK_4, t_STACK_5, t_STACK_6, t_STACK_7,
t_STACK_8, t_STACK_9, t_STACK_A, t_STACK_B,
t_STACK_C, t_STACK_D, t_STACK_E, t_STACK_F
: out STD_LOGIC_VECTOR (15 downto 0);
t_REG_0, t_REG_1, t_REG_2, t_REG_3,
t_REG_4, t_REG_5, t_REG_6, t_REG_7,
t_REG_8, t_REG_9, t_REG_A, t_REG_B,
t_REG_C, t_REG_D, t_REG_E, t_REG_F
: out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
active : out STD_LOGIC;
err_code : out STD_LOGIC_VECTOR( 2 downto 0 ) );
end core;
architecture Behavioral of core is
constant DT_ADDRESS : std_logic_vector(11 downto 0):= "000000000000";
constant ST_ADDRESS : std_logic_vector(11 downto 0):= "000000000001";
constant INVALID_OP : std_logic_vector(2 downto 0):= "001";
constant STACK_OVER : std_logic_vector(2 downto 0):= "010";
constant STACK_UNDER : std_logic_vector(2 downto 0):= "011";
type state is ( initA, error, fetchA, fetchB, delay,
memA, memB, Decode,
readKey0, readKey1, readKey2, readKey3,
readKey4, readKey5, readKey6, readKey7,
readDelay0, readDelay1, readDelay2,
O_NOP, O_CLEAR, O_RET, O_JUMP, O_CALL,
O_SNI_X_EQ_KK, O_SNI_X_NE_KK, O_SNI_X_EQ_Y, O_LD_X_KK, O_ADD_X_KK,
O_LD_X_Y, O_OR_X_Y, O_AND_X_Y, O_XOR_X_Y, O_ADC_X_Y,
O_SUB_X_Y, O_SHR_X_Y, O_SUBN_X_Y, O_SHL_X_Y, O_SNI_X_NE_Y,
O_LD_I_ADDR, O_JMP_V0_ADDR, O_RND, O_DRW, O_SNI_KEY_X,
O_SNI_KEY_NX, O_LD_X_DT, O_LD_X_KEY, O_LD_DT_X, O_LD_ST_X,
O_ADD_I_X, O_LD_F_X, O_LD_B_X, O_LD_I_X, O_LD_X_I,
CLEAR_A, getSprite, grab_graphicsA, grab_graphicsB,
drawSprite, drawSpriteA, drawSpriteB, getDT,
BCD_hundreds, BCD_tens, BCD_ones, pull_reg );
signal current_state : state;
signal tmp_err_code : STD_LOGIC_VECTOR( 2 downto 0 );
signal mem_ret_state : state;
signal tmp_mem_write : STD_LOGIC;
signal mem_ret_data : STD_LOGIC_VECTOR (7 downto 0);
signal PC : STD_LOGIC_VECTOR ( 11 downto 0 );
signal instruction_high : STD_LOGIC_VECTOR ( 7 downto 0 );
signal addr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal n, x, y : STD_LOGIC_VECTOR ( 3 downto 0 );
signal kk : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SP : STD_LOGIC_VECTOR ( 7 downto 0 );
type STACK is array( 15 downto 0 ) of STD_LOGIC_VECTOR (15 downto 0);
signal cpu_STACK : STACK;
type REG is array( 15 downto 0 ) of STD_LOGIC_VECTOR (7 downto 0);
signal cpu_REG : REG;
type POINTER_TABLE is array( 15 downto 0 ) of STD_LOGIC_VECTOR (11 downto 0);
signal hex_digits : POINTER_TABLE;
signal I : STD_LOGIC_VECTOR ( 11 downto 0 );
--- poor man's RNG, since a human will let up on the reset,
--- should start at a random point at least.
signal RAND : STD_LOGIC_VECTOR ( 15 downto 0 ) := "1010101010101010";
signal multi_address : STD_LOGIC_VECTOR ( 11 downto 0 );
signal multi_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal graphic_addressA : STD_LOGIC_VECTOR ( 11 downto 0 );
signal graphic_addressB : STD_LOGIC_VECTOR ( 11 downto 0 );
signal graphic_bufferA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal graphic_bufferB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal sprite_buffer : STD_LOGIC_VECTOR ( 7 downto 0 );
signal sprite_buffer_flip : STD_LOGIC_VECTOR ( 7 downto 0 );
signal graphic_offset : STD_LOGIC_VECTOR ( 2 downto 0 );
signal graphic_collision : STD_LOGIC;
signal key_counter : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BCD_total : STD_LOGIC_VECTOR ( 7 downto 0 );
signal BCD_left : STD_LOGIC_VECTOR ( 7 downto 0 );
signal reg_copy_num : STD_LOGIC_VECTOR ( 3 downto 0 );
signal instruction_delay : STD_LOGIC_VECTOR ( 23 downto 0 );
signal current_delay : STD_LOGIC_VECTOR ( 23 downto 0 );
signal s_keyPad : STD_LOGIC_VECTOR (15 downto 0);
type KEY is array( 15 downto 0 ) of STD_LOGIC_VECTOR (3 downto 0);
signal map_KEY : KEY;
begin
mem_write <= tmp_mem_write;
err_code <= tmp_err_code;
s_keyPad( 0) <= keyPad(to_integer( unsigned (map_KEY( 0 ))) );
s_keyPad( 1) <= keyPad(to_integer( unsigned (map_KEY( 1 ))) );
s_keyPad( 2) <= keyPad(to_integer( unsigned (map_KEY( 2 ))) );
s_keyPad( 3) <= keyPad(to_integer( unsigned (map_KEY( 3 ))) );
s_keyPad( 4) <= keyPad(to_integer( unsigned (map_KEY( 4 ))) );
s_keyPad( 5) <= keyPad(to_integer( unsigned (map_KEY( 5 ))) );
s_keyPad( 6) <= keyPad(to_integer( unsigned (map_KEY( 6 ))) );
s_keyPad( 7) <= keyPad(to_integer( unsigned (map_KEY( 7 ))) );
s_keyPad( 8) <= keyPad(to_integer( unsigned (map_KEY( 8 ))) );
s_keyPad( 9) <= keyPad(to_integer( unsigned (map_KEY( 9 ))) );
s_keyPad(10) <= keyPad(to_integer( unsigned (map_KEY( 10 ))) );
s_keyPad(11) <= keyPad(to_integer( unsigned (map_KEY( 11 ))) );
s_keyPad(12) <= keyPad(to_integer( unsigned (map_KEY( 12 ))) );
s_keyPad(13) <= keyPad(to_integer( unsigned (map_KEY( 13 ))) );
s_keyPad(14) <= keyPad(to_integer( unsigned (map_KEY( 14 ))) );
s_keyPad(15) <= keyPad(to_integer( unsigned (map_KEY( 15 ))) );
t_PC <= PC;
t_I <= I;
t_addr <= addr;
t_n <= n;
t_x <= x;
t_y <= y;
t_kk <= kk;
t_SP <= SP;
t_STACK_0 <= cpu_STACK( 0); t_STACK_1 <= cpu_STACK( 1); t_STACK_2 <= cpu_STACK( 2); t_STACK_3 <= cpu_STACK( 3);
t_STACK_4 <= cpu_STACK( 4); t_STACK_5 <= cpu_STACK( 5); t_STACK_6 <= cpu_STACK( 6); t_STACK_7 <= cpu_STACK( 7);
t_STACK_8 <= cpu_STACK( 8); t_STACK_9 <= cpu_STACK( 9); t_STACK_A <= cpu_STACK(10); t_STACK_B <= cpu_STACK(11);
t_STACK_C <= cpu_STACK(12); t_STACK_D <= cpu_STACK(13); t_STACK_E <= cpu_STACK(14); t_STACK_F <= cpu_STACK(15);
t_REG_0 <= cpu_REG( 0); t_REG_1 <= cpu_REG( 1); t_REG_2 <= cpu_REG( 2); t_REG_3 <= cpu_REG( 3);
t_REG_4 <= cpu_REG( 4); t_REG_5 <= cpu_REG( 5); t_REG_6 <= cpu_REG( 6); t_REG_7 <= cpu_REG( 7);
t_REG_8 <= cpu_REG( 8); t_REG_9 <= cpu_REG( 9); t_REG_A <= cpu_REG(10); t_REG_B <= cpu_REG(11);
t_REG_C <= cpu_REG(12); t_REG_D <= cpu_REG(13); t_REG_E <= cpu_REG(14); t_REG_F <= cpu_REG(15);
process( clk, reset )
variable instruction : STD_LOGIC_VECTOR ( 15 downto 0 );
variable tmp_SP : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_8 : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_8x : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_8y : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_8A : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_8B : STD_LOGIC_VECTOR ( 7 downto 0 );
variable tmp_4 : STD_LOGIC_VECTOR ( 3 downto 0 );
variable tmp_12 : STD_LOGIC_VECTOR ( 11 downto 0 );
variable tmp_12A : STD_LOGIC_VECTOR ( 11 downto 0 );
variable tmp_12B : STD_LOGIC_VECTOR ( 11 downto 0 );
variable key_num : STD_LOGIC_VECTOR ( 3 downto 0 );
variable key_mask : STD_LOGIC_VECTOR ( 15 downto 0 );
variable math_buf : STD_LOGIC_VECTOR ( 8 downto 0 );
begin
if( reset = '1' ) then
current_state <= initA;
memWrite <= "00000000";
memAddress <= x"000";
mem_valid <= '0';
tmp_mem_write <= '0';
mem_hold <= '0';
tmp_err_code <= "000";
cpu_state <= x"01";
active <= '0';
if ( rising_edge( clk ) ) then
RAND <= ( RAND(0) xor RAND(2) xor RAND(3) xor RAND(5) ) & RAND( 15 downto 1);
end if;
elsif ( rising_edge( clk ) ) then
RAND <= ( RAND(0) xor RAND(2) xor RAND(3) xor RAND(5) ) & RAND( 15 downto 1);
current_state <= current_state;
case current_state is
when error =>
cpu_state <= x"00";
when initA =>
cpu_state <= x"02";
active <= '1';
PC <= x"200";
I <= "000000000000";
SP <= "00000000";
cpu_REG( 0) <= "00000000"; cpu_REG( 8) <= "00000000";
cpu_REG( 1) <= "00000000"; cpu_REG( 9) <= "00000000";
cpu_REG( 2) <= "00000000"; cpu_REG(10) <= "00000000";
cpu_REG( 3) <= "00000000"; cpu_REG(11) <= "00000000";
cpu_REG( 4) <= "00000000"; cpu_REG(12) <= "00000000";
cpu_REG( 5) <= "00000000"; cpu_REG(13) <= "00000000";
cpu_REG( 6) <= "00000000"; cpu_REG(14) <= "00000000";
cpu_REG( 7) <= "00000000"; cpu_REG(15) <= "00000000";
key_counter <= "0000";
hex_digits( 0) <= "000000000010"; hex_digits( 8) <= "000000101010";
hex_digits( 1) <= "000000000111"; hex_digits( 9) <= "000000101111";
hex_digits( 2) <= "000000001100"; hex_digits(10) <= "000000110100";
hex_digits( 3) <= "000000010001"; hex_digits(11) <= "000000111001";
hex_digits( 4) <= "000000010110"; hex_digits(12) <= "000000111110";
hex_digits( 5) <= "000000011011"; hex_digits(13) <= "000001000011";
hex_digits( 6) <= "000000100000"; hex_digits(14) <= "000001001000";
hex_digits( 7) <= "000000100101"; hex_digits(15) <= "000001001101";
instruction_delay <= x"002000";
memAddress <= x"080";
tmp_mem_write <= '0';
mem_hold <= '0';
mem_ret_state <= readKey0;
current_state <= memA;
when readKey0 =>
map_KEY(0) <= mem_ret_data( 7 downto 4 );
map_KEY(1) <= mem_ret_data( 3 downto 0 );
memAddress <= x"081";
mem_ret_state <= readKey1;
current_state <= memA;
when readKey1 =>
map_KEY(2) <= mem_ret_data( 7 downto 4 );
map_KEY(3) <= mem_ret_data( 3 downto 0 );
memAddress <= x"082";
mem_ret_state <= readKey2;
current_state <= memA;
when readKey2 =>
map_KEY(4) <= mem_ret_data( 7 downto 4 );
map_KEY(5) <= mem_ret_data( 3 downto 0 );
memAddress <= x"083";
mem_ret_state <= readKey3;
current_state <= memA;
when readKey3 =>
map_KEY(6) <= mem_ret_data( 7 downto 4 );
map_KEY(7) <= mem_ret_data( 3 downto 0 );
memAddress <= x"084";
mem_ret_state <= readKey4;
current_state <= memA;
when readKey4 =>
map_KEY(8) <= mem_ret_data( 7 downto 4 );
map_KEY(9) <= mem_ret_data( 3 downto 0 );
memAddress <= x"085";
mem_ret_state <= readKey5;
current_state <= memA;
when readKey5 =>
map_KEY(10) <= mem_ret_data( 7 downto 4 );
map_KEY(11) <= mem_ret_data( 3 downto 0 );
memAddress <= x"086";
mem_ret_state <= readKey6;
current_state <= memA;
when readKey6 =>
map_KEY(12) <= mem_ret_data( 7 downto 4 );
map_KEY(13) <= mem_ret_data( 3 downto 0 );
memAddress <= x"087";
mem_ret_state <= readKey7;
current_state <= memA;
when readKey7 =>
map_KEY(14) <= mem_ret_data( 7 downto 4 );
map_KEY(15) <= mem_ret_data( 3 downto 0 );
memAddress <= x"088";
mem_ret_state <= readDelay0;
current_state <= memA;
when readDelay0 =>
instruction_delay( 23 downto 16) <= mem_ret_data;
memAddress <= x"089";
mem_ret_state <= readDelay1;
current_state <= memA;
when readDelay1 =>
instruction_delay( 15 downto 8) <= mem_ret_data;
memAddress <= x"08A";
mem_ret_state <= readDelay2;
current_state <= memA;
when readDelay2 =>
instruction_delay( 7 downto 0) <= mem_ret_data;
current_state <= fetchA;
when fetchA =>
cpu_state <= x"03";
memAddress <= PC;
PC <= PC + x"001";
tmp_mem_write <= '0';
mem_hold <= '0';
mem_ret_state <= delay;
current_delay <= x"000000";
current_state <= memA;
when delay =>
current_delay <= current_delay + x"000001";
if( current_delay = instruction_delay ) then
current_state <= fetchB;
end if;
when fetchB =>
cpu_state <= x"04";
instruction_high <= mem_ret_data;
memAddress <= PC;
PC <= PC + x"001";
mem_ret_state <= Decode;
current_state <= memA;
when memA =>
cpu_state <= x"05";
if ( mem_done = '0' ) then
mem_valid <= '1';
current_state <= memB;
end if;
when memB =>
cpu_state <= x"06";
if( mem_done = '1' ) then
if ( tmp_mem_write = '0' ) then
mem_ret_data <= memRead;
end if;
mem_valid <= '0';
current_state <= mem_ret_state;
end if;
when Decode =>
cpu_state <= x"07";
instruction := instruction_high & mem_ret_data;
case instruction( 15 downto 12 ) is
when "0000" =>
if ( instruction = "0000000011100000" ) then
current_state <= O_CLEAR;
elsif ( instruction = "0000000011101110" ) then
current_state <= O_RET;
else
current_state <= O_NOP;
end if;
when "0001" =>
addr <= instruction( 11 downto 0 );
current_state <= O_JUMP;
when "0010" =>
addr <= instruction( 11 downto 0 );
current_state <= O_CALL;
when "0011" =>
x <= instruction( 11 downto 8 );
kk <= instruction( 7 downto 0 );
current_state <= O_SNI_X_EQ_KK;
when "0100" =>
x <= instruction( 11 downto 8 );
kk <= instruction( 7 downto 0 );
current_state <= O_SNI_X_NE_KK;
when "0101" =>
x <= instruction( 11 downto 8 );
y <= instruction( 7 downto 4 );
current_state <= O_SNI_X_EQ_Y;
when "0110" =>
x <= instruction( 11 downto 8 );
kk <= instruction( 7 downto 0 );
current_state <= O_LD_X_KK;
when "0111" =>
x <= instruction( 11 downto 8 );
kk <= instruction( 7 downto 0 );
current_state <= O_ADD_X_KK;
when "1000" =>
x <= instruction( 11 downto 8 );
y <= instruction( 7 downto 4 );
case instruction( 3 downto 0 ) is
when "0000" =>
current_state <= O_LD_X_Y;
when "0001" =>
current_state <= O_OR_X_Y;
when "0010" =>
current_state <= O_AND_X_Y;
when "0011" =>
current_state <= O_XOR_X_Y;
when "0100" =>
current_state <= O_ADC_X_Y;
when "0101" =>
current_state <= O_SUB_X_Y;
when "0110" =>
current_state <= O_SHR_X_Y;
when "0111" =>
current_state <= O_SUBN_X_Y;
when "1110" =>
current_state <= O_SHL_X_Y;
when others =>
tmp_err_code <= INVALID_OP;
current_state <= error;
end case;
when "1001" =>
x <= instruction( 11 downto 8 );
y <= instruction( 7 downto 4 );
current_state <= O_SNI_X_NE_Y;
when "1010" =>
addr <= instruction( 11 downto 0 );
current_state <= O_LD_I_ADDR;
when "1011" =>
addr <= instruction( 11 downto 0 );
current_state <= O_JMP_V0_ADDR;
when "1100" =>
x <= instruction( 11 downto 8 );
kk <= instruction( 7 downto 0 );
current_state <= O_RND;
when "1101" =>
x <= instruction( 11 downto 8 );
y <= instruction( 7 downto 4 );
n <= instruction( 3 downto 0 );
current_state <= O_DRW;
when "1110" =>
x <= instruction( 11 downto 8 );
if ( instruction( 7 downto 0 ) = "10011110" ) then
current_state <= O_SNI_KEY_X;
elsif ( instruction( 7 downto 0 ) = "10100001" ) then
current_state <= O_SNI_KEY_NX;
else
tmp_err_code <= INVALID_OP;
current_state <= error;
end if;
when "1111" =>
x <= instruction( 11 downto 8 );
case instruction( 7 downto 0 ) is
when x"07" =>
current_state <= O_LD_X_DT;
when x"0A" =>
current_state <= O_LD_X_KEY;
when x"15" =>
current_state <= O_LD_DT_X;
when x"18" =>
current_state <= O_LD_ST_X;
when x"1E" =>
current_state <= O_ADD_I_X;
when x"29" =>
current_state <= O_LD_F_X;
when x"33" =>
current_state <= O_LD_B_X;
when x"55" =>
current_state <= O_LD_I_X;
when x"65" =>
current_state <= O_LD_X_I;
when others =>
tmp_err_code <= INVALID_OP;
current_state <= error;
end case;
when others =>
tmp_err_code <= INVALID_OP;
current_state <= error;
end case;
when O_NOP =>
cpu_state <= x"08";
current_state <= fetchA;
when O_CLEAR =>
cpu_state <= x"09";
multi_address <= "111100000000"; -- 0xF00
multi_count <= "100000000"; -- 256
current_state <= CLEAR_A;
when CLEAR_A =>
cpu_state <= x"0A";
if ( multi_count = "000000000" ) then
current_state <= fetchA;
else
memAddress <= multi_address;
tmp_mem_write <= '1';
mem_hold <= '0';
mem_ret_state <= CLEAR_A;
memWrite <= "00000000";
current_state <= memA;
multi_address <= multi_address + "000000000001";
multi_count <= multi_count - "000000001";
end if;
when O_RET =>
cpu_state <= x"0B";
tmp_SP := SP;
tmp_SP := tmp_SP - "00000001";
if( tmp_SP = "11111111" ) then
tmp_err_code <= STACK_UNDER;
current_state <= error;
else
PC <= cpu_STACK( to_integer( unsigned ( tmp_SP ) ))( 11 downto 0 );
SP <= tmp_SP;
current_state <= fetchA;
end if;
when O_JUMP =>
cpu_state <= x"0C";
PC <= addr;
current_state <= fetchA;
when O_CALL =>
cpu_state <= x"0D";
tmp_SP := SP;
if( tmp_SP = "00010000" ) then -- 16 is to much
tmp_err_code <= STACK_OVER;
current_state <= error;
else
cpu_STACK( to_integer( unsigned ( tmp_SP ) )) <= "0000" & PC;
tmp_SP := tmp_SP + "00000001";
SP <= tmp_SP;
PC <= addr;
current_state <= fetchA;
end if;
when O_SNI_X_EQ_KK =>
cpu_state <= x"0E";
if ( cpu_REG( to_integer( unsigned ( x ) ) ) = kk ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_SNI_X_NE_KK =>
cpu_state <= x"0F";
if ( cpu_REG( to_integer( unsigned ( x ) ) ) /= kk ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_SNI_X_EQ_Y =>
cpu_state <= x"10";
if ( cpu_REG( to_integer( unsigned ( x ) ) )
=
cpu_REG( to_integer( unsigned ( y ) ) ) ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_LD_X_KK =>
cpu_state <= x"11";
cpu_REG(to_integer(unsigned( x ))) <= kk;
current_state <= fetchA;
when O_ADD_X_KK =>
cpu_state <= x"12";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( x ))) + kk;
current_state <= fetchA;
when O_LD_X_Y =>
cpu_state <= x"13";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( y )));
current_state <= fetchA;
when O_OR_X_Y =>
cpu_state <= x"14";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( x )))
or
cpu_REG(to_integer(unsigned( y )));
current_state <= fetchA;
when O_AND_X_Y =>
cpu_state <= x"15";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( x )))
and
cpu_REG(to_integer(unsigned( y )));
current_state <= fetchA;
when O_XOR_X_Y =>
cpu_state <= x"16";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( x )))
xor
cpu_REG(to_integer(unsigned( y )));
current_state <= fetchA;
when O_ADC_X_Y =>
cpu_state <= x"17";
math_buf :=
( '0' & cpu_REG(to_integer(unsigned( x ))) )
+
( '0' & cpu_REG(to_integer(unsigned( y ))) );
cpu_REG(to_integer(unsigned( x ))) <= math_buf( 7 downto 0 );
cpu_REG( 15 ) <= "0000000" & math_buf( 8 );
current_state <= fetchA;
when O_SUB_X_Y =>
cpu_state <= x"18";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( x )))
-
cpu_REG(to_integer(unsigned( y )));
---- not sure about this, think documentation might have a typo.
if ( cpu_REG(to_integer(unsigned( x )))
>=
cpu_REG(to_integer(unsigned( y ))) ) then
cpu_REG( 15 ) <= "00000001";
else
cpu_REG( 15 ) <= "00000000";
end if;
current_state <= fetchA;
---- is the doc right on this one? You don't use the Y?????
when O_SHR_X_Y =>
cpu_state <= x"19";
cpu_REG(to_integer(unsigned( x ))) <= '0' &
cpu_REG(to_integer(unsigned( y )))( 7 downto 1 );
cpu_REG( 15 ) <= "0000000" &
cpu_REG(to_integer(unsigned( y )))(0);
current_state <= fetchA;
when O_SUBN_X_Y =>
cpu_state <= x"1A";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( y )))
-
cpu_REG(to_integer(unsigned( x )));
if ( cpu_REG(to_integer(unsigned( y )))
>=
cpu_REG(to_integer(unsigned( x ))) ) then
cpu_REG( 15 ) <= "00000001";
else
cpu_REG( 15 ) <= "00000000";
end if;
current_state <= fetchA;
when O_SHL_X_Y =>
cpu_state <= x"1B";
cpu_REG(to_integer(unsigned( x ))) <=
cpu_REG(to_integer(unsigned( y )))( 6 downto 0 ) & '0';
cpu_REG( 15 ) <= "0000000" &
cpu_REG(to_integer(unsigned( y )))(7);
current_state <= fetchA;
when O_SNI_X_NE_Y =>
cpu_state <= x"1C";
if ( cpu_REG( to_integer( unsigned ( x ) ) )
/=
cpu_REG( to_integer( unsigned ( y ) ) ) ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_LD_I_ADDR =>
cpu_state <= x"1D";
I <= addr;
current_state <= fetchA;
when O_JMP_V0_ADDR =>
cpu_state <= x"1E";
PC <= addr + ( "0000" & cpu_REG(0) );
current_state <= fetchA;
when O_RND =>
cpu_state <= x"1F";
tmp_8 := RAND( 7 downto 0 );
tmp_8 := tmp_8 and kk;
cpu_REG( to_integer( unsigned ( x ) ) ) <= tmp_8;
current_state <= fetchA;
when O_DRW =>
cpu_state <= x"20";
tmp_8x := "00" & cpu_REG( to_integer( unsigned ( x ) ) )(5 downto 0);
tmp_8y := "000" & cpu_REG( to_integer( unsigned ( y ) ) )( 4 downto 0);
-- address = 0xF00 + ( y << 3 ) + ( x >> 3 )
tmp_12 := "1111" & tmp_8y( 4 downto 0 ) & tmp_8x( 5 downto 3);
graphic_addressA <= tmp_12;
-- address + 1 = address + 1, but roll over on 8 byte boundary
tmp_12 := tmp_12( 11 downto 3 ) & ( tmp_12( 2 downto 0 ) + "001");
graphic_addressB <= tmp_12;
graphic_offset <= tmp_8x( 2 downto 0 );
graphic_collision <= '0';
multi_address <= I;
current_state <= getSprite;
when getSprite =>
cpu_state <= x"21";
-- when n gets to 0 we are done, if there was a collision set VF
if( n = "0000" ) then
if ( graphic_collision = '1' ) then
cpu_REG( 15 ) <= "00000001";
else
cpu_REG( 15 ) <= "00000000";
end if;
current_state <= fetchA;
else
-- we have more to do, n--
n <= n - "0001";
-- readAddress = spriteAddress++
memAddress <= multi_address;
multi_address <= multi_address + "000000000001";
-- read, do not hold memory
tmp_mem_write <= '0';
mem_hold <= '0';
mem_ret_state <= grab_graphicsA;
current_state <= memA;
end if;
when grab_graphicsA =>
cpu_state <= x"22";
-- grab the value
sprite_buffer_flip <= mem_ret_data;
-- get old info from video buffer low byte
memAddress <= graphic_addressA;
mem_ret_state <= grab_graphicsB;
current_state <= memA;
when grab_graphicsB =>
cpu_state <= x"23";
-- flip the sprite bits because bit 7 drawn at 0, 0
-- should be pixel 0 if that makes sense?
sprite_buffer(0) <= sprite_buffer_flip(7);
sprite_buffer(1) <= sprite_buffer_flip(6);
sprite_buffer(2) <= sprite_buffer_flip(5);
sprite_buffer(3) <= sprite_buffer_flip(4);
sprite_buffer(4) <= sprite_buffer_flip(3);
sprite_buffer(5) <= sprite_buffer_flip(2);
sprite_buffer(6) <= sprite_buffer_flip(1);
sprite_buffer(7) <= sprite_buffer_flip(0);
-- grab the value
graphic_bufferA <= mem_ret_data;
-- get old info from video buffer high byte
memAddress <= graphic_addressB;
mem_ret_state <= drawSprite;
current_state <= memA;
when drawSprite =>
cpu_state <= x"24";
-- xor the new data into highByte::lowByte at the corret offset
tmp_8A := graphic_bufferA;
tmp_8B := mem_ret_data;
if( graphic_offset = "000" ) then
tmp_8A := tmp_8A xor sprite_buffer;
elsif ( graphic_offset = "001" ) then
tmp_8B := tmp_8B xor ( "0000000" & sprite_buffer(7) );
tmp_8A := tmp_8A xor ( sprite_buffer( 6 downto 0 ) & "0");
elsif ( graphic_offset = "010" ) then
tmp_8B := tmp_8B xor ( "000000" & sprite_buffer(7 downto 6) );
tmp_8A := tmp_8A xor ( sprite_buffer( 5 downto 0 ) & "00");
elsif ( graphic_offset = "011" ) then
tmp_8B := tmp_8B xor ( "00000" & sprite_buffer(7 downto 5) );
tmp_8A := tmp_8A xor ( sprite_buffer( 4 downto 0 ) & "000");
elsif ( graphic_offset = "100" ) then
tmp_8B := tmp_8B xor ( "0000" & sprite_buffer(7 downto 4) );
tmp_8A := tmp_8A xor ( sprite_buffer( 3 downto 0 ) & "0000");
elsif ( graphic_offset = "101" ) then
tmp_8B := tmp_8B xor ( "000" & sprite_buffer(7 downto 3) );
tmp_8A := tmp_8A xor ( sprite_buffer( 2 downto 0 ) & "00000");
elsif ( graphic_offset = "110" ) then
tmp_8B := tmp_8B xor ( "00" & sprite_buffer(7 downto 2) );
tmp_8A := tmp_8A xor ( sprite_buffer( 1 downto 0 ) & "000000");
elsif ( graphic_offset = "111" ) then
tmp_8B := tmp_8B xor ( "0" & sprite_buffer(7 downto 1) );
tmp_8A := tmp_8A xor ( sprite_buffer( 0 ) & "0000000");
end if;
-- collision if the old bits are gone
if( ( graphic_bufferA and tmp_8A ) /= graphic_bufferA ) then
graphic_collision <= '1';
elsif ( ( mem_ret_data and tmp_8B ) /= mem_ret_data ) then
graphic_collision <= '1';
end if;
-- store this here to remember we cannot use it this state, whoops!!
graphic_bufferB <= tmp_8B;
-- writeAddress = videoLowByte++8 to increment to the next row.
memAddress <= graphic_addressA;
graphic_addressA <= graphic_addressA + "00000001000";
-- we are writing the new xored video data here
tmp_mem_write <= '1';
memWrite <= tmp_8A;
mem_ret_state <= drawSpriteA;
current_state <= memA;
when drawSpriteA =>
cpu_state <= x"25";
-- writeAddress = videoHighByte++8 to increment to the next row.
memAddress <= graphic_addressB;
graphic_addressB <= graphic_addressB + "00000001000";
-- write the rest of the video update
memWrite <= graphic_bufferB;
mem_ret_state <= drawSpriteB;
current_state <= memA;
when drawSpriteB =>
cpu_state <= x"26";
-- if the addresses rolled off the bottom of the screen,
-- then put them back up at the top of the buffer instead of top of memory
if( graphic_addressA( 11 downto 8 ) = "0000" ) then
graphic_addressA <= graphic_addressA or x"F00";
graphic_addressB <= graphic_addressB or x"F00";
end if;
-- get the next sprite line.
current_state <= getSprite;
when O_SNI_KEY_X =>
cpu_state <= x"27";
key_num := cpu_REG( to_integer( unsigned ( x ) ) )( 3 downto 0 );
key_mask := "0000000000000001";
key_mask := std_logic_vector( shift_left( unsigned( key_mask ), to_integer( unsigned ( key_num ) ) ) );
if( ( key_mask and s_keyPad ) = key_mask ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_SNI_KEY_NX =>
cpu_state <= x"28";
key_num := cpu_REG( to_integer( unsigned ( x ) ) )( 3 downto 0 );
key_mask := "0000000000000001";
key_mask := std_logic_vector( shift_left( unsigned( key_mask ), to_integer( unsigned ( key_num ) ) ) );
if( ( key_mask and s_keyPad ) /= key_mask ) then
PC <= PC + "000000000010";
end if;
current_state <= fetchA;
when O_LD_X_DT =>
cpu_state <= x"29";
memAddress <= DT_ADDRESS;
tmp_mem_write <= '0';
mem_hold <= '0';
mem_ret_state <= getDT;
current_state <= memA;
when getDT =>
cpu_state <= x"2A";
cpu_REG( to_integer( unsigned ( x ) ) ) <= mem_ret_data;
current_state <= fetchA;
when O_LD_X_KEY =>
cpu_state <= x"2B";
-- keep rolling through all 15 keys until we find one that is down.
key_num := key_counter;
key_mask := "0000000000000001";
key_counter <= key_counter + 1;
key_mask := std_logic_vector( shift_left( unsigned( key_mask ), to_integer( unsigned ( key_num ) ) ) );
if( ( key_mask and s_keyPad ) = key_mask ) then
cpu_REG( to_integer( unsigned ( x ) ) ) <= "0000" & key_num;
current_state <= fetchA;
end if;
when O_LD_DT_X =>
cpu_state <= x"2C";
memAddress <= DT_ADDRESS;
tmp_mem_write <= '1';
mem_hold <= '0';
mem_ret_state <= fetchA;
memWrite <= cpu_REG( to_integer( unsigned ( x ) ) );
current_state <= memA;
when O_LD_ST_X =>
cpu_state <= x"2D";
memAddress <= ST_ADDRESS;
tmp_mem_write <= '1';
mem_hold <= '0';
mem_ret_state <= fetchA;
memWrite <= cpu_REG( to_integer( unsigned ( x ) ) );
current_state <= memA;
when O_ADD_I_X =>
cpu_state <= x"2E";
I <= I + ( "0000" & cpu_REG(to_integer(unsigned( x ))) );
current_state <= fetchA;
when O_LD_F_X =>
cpu_state <= x"2F";
tmp_4 := cpu_REG(to_integer(unsigned( x )))( 3 downto 0 );
I <= hex_digits( to_integer(unsigned( tmp_4 )));
current_state <= fetchA;
when O_LD_B_X =>
cpu_state <= x"30";
BCD_left <= cpu_REG(to_integer(unsigned( x )));
BCD_total <= "00000000";
current_state <= BCD_hundreds;
when BCD_hundreds =>
cpu_state <= x"31";
if ( BCD_left < "01100100" ) then -- if < 100
memAddress <= I;
tmp_mem_write <= '1';
mem_hold <= '0';
mem_ret_state <= BCD_tens;
memWrite <= BCD_total;
BCD_total <= "00000000";
current_state <= memA;
else
BCD_left <= BCD_left - "01100100"; -- BCD_left -= 100
BCD_total <= BCD_total + "00000001"; -- total++
end if;
when BCD_tens =>
cpu_state <= x"32";
if ( BCD_left < "00001010" ) then -- if < 10
memAddress <= I + "000000000001";
mem_ret_state <= BCD_ones;
memWrite <= BCD_total;
BCD_total <= "00000000";
current_state <= memA;
else
BCD_left <= BCD_left - "00001010"; -- BCD_left -= 10
BCD_total <= BCD_total + "00000001"; -- total++
end if;
when BCD_ones =>
cpu_state <= x"33";
if ( BCD_left = "00000000" ) then
memAddress <= I + "000000000010";
mem_ret_state <= fetchA;
memWrite <= BCD_total;
BCD_total <= "00000000";
current_state <= memA;
else
BCD_left <= BCD_left - "00000001"; -- BCD_left -= 1
BCD_total <= BCD_total + "00000001"; -- total++
end if;
when O_LD_I_X =>
cpu_state <= x"34";
memAddress <= I + ( "00000000" & x );
tmp_mem_write <= '1';
mem_hold <= '0';
memWrite <= cpu_REG(to_integer(unsigned( x )));
x <= x - "0001";
current_state <= memA;
if( x = "0000" ) then
mem_ret_state <= fetchA;
else
mem_ret_state <= O_LD_I_X;
end if;
when O_LD_X_I =>
cpu_state <= x"35";
reg_copy_num <= "0000";
multi_address <= I + "000000000001";
memAddress <= I;
tmp_mem_write <= '0';
mem_hold <= '0';
mem_ret_state <= pull_reg;
current_state <= memA;
when pull_reg =>
cpu_state <= x"36";
cpu_REG( to_integer( unsigned ( reg_copy_num ) ) ) <= mem_ret_data;
memAddress <= multi_address;
multi_address <= multi_address + "000000000001";
reg_copy_num <= reg_copy_num + "0001";
if ( reg_copy_num = x ) then
current_state <= fetchA;
else
mem_ret_state <= pull_reg;
current_state <= memA;
end if;
when others =>
cpu_state <= x"37";
tmp_err_code <= INVALID_OP;
current_state <= error;
end case;
end if;
end process;
end Behavioral;
| mit | ce7c2d84b1d2a6856f15475b13ea4f30 | 0.392156 | 4.344579 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution1/syn/vhdl/fir.vhd | 9 | 14,661 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.714000,HLS_SYN_LAT=45,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=329,HLS_SYN_LUT=214}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_187 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_134_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_123_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_206 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_211 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal acc_1_fu_167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal acc_reg_89 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_106_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_102 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_123_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
acc_reg_89_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
acc_reg_89 <= acc_1_fu_167_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
acc_reg_89 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0))) then
data1_reg_114 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
data1_reg_114 <= x;
end if;
end if;
end process;
i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_reg_102 <= i_1_reg_206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_102 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_206 <= grp_fu_123_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_178 <= i_cast_fu_130_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0))) then
tmp_1_reg_187 <= tmp_1_fu_142_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_6_reg_211 <= tmp_6_fu_161_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_134_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
acc_1_fu_167_p2 <= std_logic_vector(unsigned(tmp_6_reg_211) + unsigned(acc_reg_89));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_157_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_123_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_106_p4, i_reg_102)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_123_p0 <= i_reg_102;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_123_p0 <= i_phi_fu_106_p4;
else
grp_fu_123_p0 <= "XXXXX";
end if;
end process;
grp_fu_123_p2 <= std_logic_vector(unsigned(grp_fu_123_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_130_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_102),32));
i_phi_fu_106_p4 <= i_reg_102;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3, tmp_3_fu_148_p1, tmp_4_fu_153_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_148_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_1_reg_187, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_142_p2 <= "1" when (i_reg_102 = ap_const_lv5_0) else "0";
tmp_3_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_123_p2),64));
tmp_4_fu_153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_5_fu_157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_6_fu_161_p0 <= c_q0;
tmp_6_fu_161_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(tmp_6_fu_161_p0) * signed(data1_reg_114))), 32));
tmp_fu_134_p3 <= i_reg_102(4 downto 4);
y <= acc_reg_89;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
| mit | 77c90ab248d482c300bfeee959fd004c | 0.574108 | 2.861241 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_frontend.vhd | 1 | 43,678 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_frontend.vhd
--!
--! @brief fpgaMSP430 Instruction fetch and decode unit
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_frontend is
generic (
CPUOFF_EN : boolean := false; --! Wakeup condition from DMA interface
DMA_IF_EN : boolean := false; --! Wakeup condition from DMA interface
IRQ_nr : integer := 16 --! Number of IRQs
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
cpu_en_s : in std_logic; --! Enable CPU code execution (synchronous)
cpu_halt_cmd : in std_logic; --! Halt CPU command
cpuoff : in std_logic; --! Turns off the CPU
dbg_reg_sel : in std_logic_vector(3 downto 0); --! Debug selected register for rd/wr access
dma_en : in std_logic; --! Direct Memory Access enable (high active)
fe_pmem_wait : in std_logic; --! Frontend wait for Instruction fetch
gie : in std_logic; --! General interrupt enable
irq : in std_logic_vector((IRQ_nr-3) downto 0); --! Maskable interrupts
mdb_in : in std_logic_vector(15 downto 0); --! Frontend Memory data bus input
nmi_pnd : in std_logic; --! Non-maskable interrupt pending
nmi_wkup : in std_logic; --! NMI Wakeup
pc_sw : in std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : in std_logic; --! Program counter software write
wdt_irq : in std_logic; --! Watchdog-timer interrupt
wdt_wkup : in std_logic; --! Watchdog Wakeup
--! OUTPUTs
cpu_halt_st : out std_logic; --! Halt/Run status from CPU
decode_noirq : out std_logic; --! Frontend decode instruction
e_state : out std_logic_vector(3 downto 0); --! Execution state
exec_done : out std_logic; --! Execution completed
inst_ad : out std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : out std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : out std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : out std_logic; --! Decoded Inst: byte width
inst_dest : out std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : out std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : out std_logic; --! Decoded Inst: Reset interrupt
inst_jmp : out std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : out std_logic; --! Decoded Inst: mov instruction
inst_sext : out std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : out std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : out std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : out std_logic_vector(2 downto 0); --! Decoded Instruction type
irq_acc : out std_logic_vector(13 downto 0); --! Interrupt request accepted (one-hot signal)
mab : out std_logic_vector(15 downto 0); --! Frontend Memory address bus
mb_en : out std_logic; --! Frontend Memory bus enable
-- mclk_dma_enable : out std_logic; --! DMA Sub-System Clock enable
-- mclk_dma_wkup : out std_logic; --! DMA Sub-System Clock wake-up (asynchronous)
-- mclk_enable : out std_logic; --! Main System Clock enable
-- mclk_wkup : out std_logic; --! Main System Clock wake-up (asynchronous)
nmi_acc : out std_logic; --! Non-Maskable interrupt request accepted
pc : out std_logic_vector(15 downto 0); --! Program counter
pc_nxt : out std_logic_vector(15 downto 0) --! Next PC value (for CALL & IRQ)
);
end entity fmsp_frontend;
architecture RTL of fmsp_frontend is
-- constant SUMEXT_D : std_logic_vector(3 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(SUMEXT,3));
--! Instructions type
constant C_INST_SO : integer := 0;
constant C_INST_JMP : integer := 1;
constant C_INST_TO : integer := 2;
--! Single-operand arithmetic
constant C_RRC : integer := 0;
constant C_SWPB : integer := 1;
constant C_RRA : integer := 2;
constant C_SXT : integer := 3;
constant C_PUSH : integer := 4;
constant C_CALL : integer := 5;
constant C_RETI : integer := 6;
constant C_IRQ : integer := 7;
--! Conditional jump
constant C_JNE : integer := 0;
constant C_JEQ : integer := 1;
constant C_JNC : integer := 2;
constant C_JC : integer := 3;
constant C_JN : integer := 4;
constant C_JGE : integer := 5;
constant C_JL : integer := 6;
constant C_JMP : integer := 7;
--! Two-operand arithmetic
constant C_MOV : integer := 0;
constant C_ADD : integer := 1;
constant C_ADDC : integer := 2;
constant C_SUBC : integer := 3;
constant C_SUB : integer := 4;
constant C_CMP : integer := 5;
constant C_DADD : integer := 6;
constant C_BIT : integer := 7;
constant C_BIC : integer := 8;
constant C_BIS : integer := 9;
constant C_XOR : integer := 10;
constant C_AND : integer := 11;
--! Addressing modes
constant C_DIR : integer := 0;
constant C_IDX : integer := 1;
constant C_INDIR : integer := 2;
constant C_INDIR_I : integer := 3;
constant C_SYMB : integer := 4;
constant C_IMM : integer := 5;
constant C_ABS : integer := 6;
constant C_CONST : integer := 7;
type fmsp_frontend_in_type is record
cpu_en_s : std_logic; --! Enable CPU code execution (synchronous)
cpu_halt_cmd : std_logic; --! Halt CPU command
cpuoff : std_logic; --! Turns off the CPU
dbg_reg_sel : std_logic_vector(3 downto 0); --! Debug selected register for rd/wr access
dma_en : std_logic; --! Direct Memory Access enable (high active)
fe_pmem_wait : std_logic; --! Frontend wait for Instruction fetch
gie : std_logic; --! General interrupt enable
irq : std_logic_vector((IRQ_nr-3) downto 0); --! Maskable interrupts
mdb_in : std_logic_vector(15 downto 0); --! Frontend Memory data bus input
nmi_pnd : std_logic; --! Non-maskable interrupt pending
nmi_wkup : std_logic; --! NMI Wakeup
pc_sw : std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : std_logic; --! Program counter software write
wdt_irq : std_logic; --! Watchdog-timer interrupt
wdt_wkup : std_logic; --! Watchdog Wakeup
end record;
type reg_type is record
i_state : std_logic_vector(2 downto 0);
i_state_nxt : std_logic_vector(2 downto 0);
inst_sz : std_logic_vector(1 downto 0);
sconst_nxt : std_logic_vector(15 downto 0);
e_state_nxt : std_logic_vector(3 downto 0);
cpu_halt_st : std_logic; --! Debug interface cpu status
inst_nmi : std_logic; --! Detect nmi interrupt
inst_irq_rst : std_logic; --! Detect reset interrupt
irq_num : std_logic_vector(5 downto 0); --! Select interrupt vector
pc : std_logic_vector(15 downto 0); --! Program counter
pmem_busy : std_logic; --! Check if ROM has been busy in order to retry ROM access
inst_sext : std_logic_vector(15 downto 0); --! Store source extension word
inst_dext : std_logic_vector(15 downto 0); --! Store destination extension word
inst_type : std_logic_vector(2 downto 0);
inst_so : std_logic_vector(7 downto 0);
inst_jmp_bin : std_logic_vector(2 downto 0);
inst_mov : std_logic;
inst_dest_bin : std_logic_vector(3 downto 0); --! Destination register
inst_src_bin : std_logic_vector(3 downto 0); --! Source register
inst_as_nxt : std_logic_vector(12 downto 0);
inst_as : std_logic_vector(7 downto 0);
inst_ad_nxt : std_logic_vector(7 downto 0);
inst_ad : std_logic_vector(7 downto 0);
inst_bw : std_logic; --! Operation size
e_state : std_logic_vector(3 downto 0); --! State machine registers
exec_jmp : std_logic;
exec_dst_wr : std_logic;
exec_src_wr : std_logic;
exec_dext_rdy : std_logic;
inst_alu : std_logic_vector(11 downto 0);
end record;
signal d : fmsp_frontend_in_type;
signal r : reg_type := ( i_state => "000",
i_state_nxt => "000",
inst_sz => "00",
sconst_nxt => x"0000",
e_state_nxt => "0000",
cpu_halt_st => '0', --! Debug interface cpu status
inst_nmi => '0', --! Detect nmi interrupt
inst_irq_rst => '1', --! Detect reset interrupt
irq_num => "111111", --! Select interrupt vector
pc => x"0000", --! Program counter
pmem_busy => '0', --! Check if ROM has been busy in order to retry ROM access
inst_sext => x"0000", --! Store source extension word
inst_dext => x"0000", --! Store destination extension word
inst_type => "000",
inst_so => x"00",
inst_jmp_bin => "000",
inst_mov => '0',
inst_dest_bin => "0000", --! Destination register
inst_src_bin => "0000", --! Source register
inst_as_nxt => "0000000000000",
inst_as => x"00",
inst_ad_nxt => x"00",
inst_ad => x"00",
inst_bw => '0', --! Operation size
e_state => "0000", --! State machine registers
exec_jmp => '0',
exec_dst_wr => '0',
exec_src_wr => '0',
exec_dext_rdy => '0',
inst_alu => x"000"
);
signal rin : reg_type;
begin
d.cpu_en_s <= cpu_en_s;
d.cpu_halt_cmd <= cpu_halt_cmd;
d.cpuoff <= cpuoff;
d.dbg_reg_sel <= dbg_reg_sel;
d.dma_en <= dma_en;
d.fe_pmem_wait <= fe_pmem_wait;
d.gie <= gie;
d.irq <= irq;
d.mdb_in <= mdb_in;
d.nmi_pnd <= nmi_pnd;
d.nmi_wkup <= nmi_wkup;
d.pc_sw <= pc_sw;
d.pc_sw_wr <= pc_sw_wr;
d.wdt_irq <= wdt_irq;
d.wdt_wkup <= wdt_wkup;
COMB : process (d, r)
variable v : reg_type;
variable v_ir : std_logic_vector(15 downto 0);
variable v_inst_sz_nxt : std_logic_vector(1 downto 0);
variable v_irq_detect : std_logic;
variable v_inst_type_nxt : std_logic_vector(2 downto 0);
variable v_is_const : std_logic;
variable v_cpu_halt_req : std_logic;
--! Utility signals
variable v_decode_noirq : std_logic;
variable v_decode : std_logic;
variable v_fetch : std_logic;
variable v_irq_addr : std_logic_vector(15 downto 0);
--! Interrupt request accepted
variable v_irq_all : std_logic_vector(62 downto 0);
variable v_irq_acc_all : std_logic_vector(63 downto 0);
variable v_irq_acc : std_logic_vector((IRQ_nr-3) downto 0);--! is v_irq_acc_all(13 downto 0);
variable v_nmi_acc : std_logic;--! is v_irq_acc_all(14);
--! Compute next PC value
variable v_pc_incr : std_logic_vector(15 downto 0);
variable v_pc_nxt : std_logic_vector(15 downto 0);
--! Memory interface
variable v_mab : std_logic_vector(15 downto 0);
variable v_mb_en : std_logic;
--! Instruction register
--variable v_ir : std_logic_vector(15 downto 0);
--! Detect if source extension word is required
variable v_is_sext : std_logic;
--! Detect if destination extension word is required
-- variable v_is_dext : std_logic;
--! For the Symbolic addressing mode, add -2 to the extension word in order to make up for the PC address
variable v_ext_incr : std_logic_vector(15 downto 0);
--! Source extension word is ready
variable v_inst_sext_rdy : std_logic;
--! Destination extension word is ready
variable v_inst_dext_rdy : std_logic;
variable v_inst_so_nxt : std_logic_vector(7 downto 0);
variable v_inst_jmp : std_logic_vector(7 downto 0);
variable v_inst_to_1hot : std_logic_vector(15 downto 0);
variable v_inst_to_nxt : std_logic_vector(11 downto 0);
variable v_inst_dest : std_logic_vector(15 downto 0);
variable v_inst_src : std_logic_vector(15 downto 0);
variable v_src_reg : std_logic_vector(3 downto 0);
variable v_dest_reg : std_logic_vector(3 downto 0);
variable v_src_acalc_pre : std_logic;
variable v_src_rd_pre : std_logic;
variable v_dst_acalc_pre : std_logic;
variable v_dst_acalc : std_logic;
variable v_dst_rd_pre : std_logic;
variable v_dst_rd : std_logic;
variable v_inst_branch : std_logic;
--! Execution first state
variable v_e_first_state : std_logic_vector(3 downto 0);
variable v_exec_done : std_logic;
variable v_alu_src_inv : std_logic;
variable v_alu_inc : std_logic;
variable v_alu_inc_c : std_logic;
variable v_alu_add : std_logic;
variable v_alu_and : std_logic;
variable v_alu_or : std_logic;
variable v_alu_xor : std_logic;
variable v_alu_dadd : std_logic;
variable v_alu_stat_7 : std_logic;
variable v_alu_stat_f : std_logic;
variable v_alu_shift : std_logic;
variable v_exec_no_wr : std_logic;
-- --! 3) FRONTEND STATE MACHINE
-- --! The variable v_"conv" is used as state bits to calculate the next response
-- variable v_inst_sz_nxt : std_logic_vector(1 downto 0);
-- variable v_irq_detect : std_logic;
-- variable v_inst_type_nxt : std_logic_vector(2 downto 0);
-- variable v_is_const : std_logic;
-- --! CPU on/off through the debug interface or cpu_en port
-- variable v_cpu_halt_req : std_logic;
-- --! Utility signals
-- variable v_decode_noirq : std_logic;
-- variable v_decode : std_logic;
-- variable v_fetch : std_logic;
-- --! 4) INTERRUPT HANDLING
-- variable v_irq_addr : std_logic_vector(15 downto 0);
-- --! Interrupt request accepted
-- variable v_irq_acc_all : std_logic_vector(15 downto 0);
-- alias v_irq_acc : std_logic_vector(13 downto 0) is irq_acc_all(13 downto 0);
-- alias v_nmi_acc : std_logic is irq_acc_all(14);
-- --! Compute next PC value
-- variable v_pc_incr : std_logic_vector(15 downto 0);
-- variable v_pc_nxt : std_logic_vector(15 downto 0);
-- --! Memory interface
-- alias v_mab : std_logic_vector(15 downto 0) is v_pc_nxtr(15 downto 0);
-- variable v_mb_en : std_logic;
-- --! 5.2) INSTRUCTION REGISTER
-- --! Instruction register
-- alias v_ir : std_logic_vector(15 downto 0) is d.mdb_in(15 downto 0);
-- --! Detect if source extension word is required
-- variable v_is_sext : std_logic;
-- --! Detect if destination extension word is required
-- variable v_is_dext : std_logic;
-- --! For the Symbolic addressing mode, add -2 to the extension word in order to make up for the PC address
-- variable v_ext_incr : std_logic_vector(15 downto 0);
variable v_ext_nxt : std_logic_vector(15 downto 0);
-- --! Source extension word is ready
-- variable v_inst_sext_rdy : std_logic;
-- --! Destination extension word is ready
-- variable v_inst_dext_rdy : std_logic;
-- variable v_inst_so_nxt : std_logic_vector(7 downto 0);
-- variable v_inst_jmp : std_logic_vector(7 downto 0);
-- variable v_inst_to_1hot : std_logic_vector(15 downto 0);
-- alias v_inst_to_nxt : std_logic_vector(11 downto 0) is v_inst_to_1hot(15 downto 0);
-- variable v_inst_dest : std_logic_vector(15 downto 0);
-- variable v_inst_src : std_logic_vector(15 downto 0);
-- variable v_src_reg : std_logic_vector(3 downto 0);
-- variable v_dest_reg : std_logic_vector(3 downto 0);
-- variable v_src_acalc_pre : std_logic;
-- variable v_src_rd_pre : std_logic;
-- variable v_dst_acalc_pre : std_logic;
-- variable v_dst_acalc : std_logic;
-- variable v_dst_rd_pre : std_logic;
-- variable v_dst_rd : std_logic;
-- variable v_inst_branch : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
--! The wire "conv" is used as state bits to calculate the next response
--! CPU on/off through the debug interface or cpu_en port
v_cpu_halt_req := d.cpu_halt_cmd or not(d.cpu_en_s);
--! States Transitions
case(r.i_state) is
when I_IDLE =>
if ( (v_irq_detect = '1') and (v_cpu_halt_req = '0') ) then
v.i_state_nxt := I_IRQ_FETCH;
elsif ( (d.cpuoff = '0') and (v_cpu_halt_req = '0') ) then
v.i_state_nxt := I_DEC;
else
v.i_state_nxt := I_IDLE;
end if;
when I_IRQ_FETCH =>
v.i_state_nxt := I_IRQ_DONE;
when I_IRQ_DONE =>
v.i_state_nxt := I_DEC;
when I_DEC =>
if (v_irq_detect = '1') then
v.i_state_nxt := I_IRQ_FETCH;
elsif ( ((d.cpuoff or v_cpu_halt_req) and exec_done) = '1' ) then
v.i_state_nxt := I_IDLE;
elsif ( (v_cpu_halt_req = '1') and (e_state=E_IDLE) ) then
v.i_state_nxt := I_IDLE;
elsif (d.pc_sw_wr = '1') then
v.i_state_nxt := I_DEC;
elsif ( (d.pc_sw_wr = '0') and (e_state/=E_IDLE) ) then
v.i_state_nxt := I_DEC;
elsif (r.inst_sz /= "00") then
v.i_state_nxt := I_EXT1;
else
v.i_state_nxt := I_DEC;
end if;
when I_EXT1 =>
if (d.pc_sw_wr = '1') then
v.i_state_nxt := I_DEC;
elsif (r.inst_sz /= "01") then
v.i_state_nxt := I_EXT2;
else
v.i_state_nxt := I_DEC;
end if;
when I_EXT2 =>
v.i_state_nxt := I_DEC;
when others =>
v.i_state_nxt := I_IRQ_FETCH;
end case;
--! State machine
v.i_state := r.i_state_nxt;
--! Utility signals
if ( (r.i_state=I_DEC) and ((v_exec_done = '1') or (r.e_state=E_IDLE)) ) then
v_decode_noirq := '1';
else
v_decode_noirq := '0';
end if;
v_decode := v_decode_noirq or v_irq_detect;
--! Debug interface cpu status
if ( not( (r.i_state=I_DEC) and not((v_exec_done = '1') or (r.e_state=E_IDLE)) ) and (r.e_state_nxt/=E_IDLE) ) then
v_fetch := '1';
else
v_fetch := '0';
end if;
--! Debug interface cpu status
if ( (r.i_state_nxt=I_IDLE) and (v_cpu_halt_req = '1') ) then
v.cpu_halt_st := '1';
else
v.cpu_halt_st := '0';
end if;
--=============================================================================
--! 4) INTERRUPT HANDLING & SYSTEM WAKEUP
--=============================================================================
--
--! 4.1) INTERRUPT HANDLING
-------------------------------------------
-- --! Detect nmi interrupt
-- if (d.nmi_evt = '1') then
-- v.inst_nmi :='1';
-- elsif (r.i_state=I_IRQ_DONE) then
-- v.inst_nmi :='0';
-- end if;
--! Detect reset interrupt
if (v_exec_done = '1') then
v.inst_irq_rst :='0';
end if;
--! Detect other interrupts
if ( ( (d.nmi_pnd = '1')
or ( ( (d.irq /= "00000000000000") or (d.wdt_irq = '1') ) and (d.gie = '1') ) )
and (v_cpu_halt_req = '0')
and (r.cpu_halt_st = '0')
and ( (v_exec_done = '1') or (r.i_state=I_IDLE) ) ) then
v_irq_detect := '1';
else
v_irq_detect := '0';
end if;
--! Combine all IRQs
v_irq_all := STD_LOGIC_VECTOR(TO_UNSIGNED(0,63));
v_irq_all(62) := d.nmi_pnd;
v_irq_all(61 downto (64-IRQ_nr)) := d.irq;
v_irq_all(59) := d.wdt_irq or v_irq_all(59);
--! Select highest priority IRQ
if (v_irq_detect ='1') then
v.irq_num := get_irq_num(v_irq_all);
end if;
--! Generate selected IRQ vector address
v_irq_addr := "111111111" & r.irq_num & '0';
--! Interrupt request accepted
if (r.i_state=I_IRQ_FETCH) then
v_irq_acc_all := one_hot64(r.irq_num);
else
v_irq_acc_all := x"0000000000000000";
end if;
v_irq_acc := v_irq_acc_all(61 downto (64-IRQ_nr));
v_nmi_acc := v_irq_acc_all(62);
--=============================================================================
--! 5) FETCH INSTRUCTION
--=============================================================================
--
--! 5.1) PROGRAM COUNTER & MEMORY INTERFACE
-------------------------------------------
--! Compute next PC value
--------v_pc_incr := r.pc + ("00000000000000" & v_fetch & '0');
if (v_fetch = '1') then
v_pc_incr := STD_LOGIC_VECTOR(UNSIGNED(r.pc) + TO_UNSIGNED(2,16));
else
v_pc_incr := r.pc;
end if;
if (d.pc_sw_wr = '1') then
v_pc_nxt := d.pc_sw;
elsif (r.i_state=I_IRQ_FETCH) then
v_pc_nxt := v_irq_addr;
elsif (r.i_state=I_IRQ_DONE) then
v_pc_nxt := d.mdb_in;
else
v_pc_nxt := v_pc_incr;
end if;
v.pc := v_pc_nxt;
--! Check if ROM has been busy in order to retry ROM access
v.pmem_busy := d.fe_pmem_wait;
--! Memory interface
v_mab := v_pc_nxt;
if ( (v_fetch = '1')
or (r.i_state=I_IRQ_FETCH)
or (d.pc_sw_wr = '1')
or (r.pmem_busy = '1')
or ((r.cpu_halt_st and not(v_cpu_halt_req)) = '1') ) then
v_mb_en := '1';
else
v_mb_en := '0';
end if;
--
--! 5.2) INSTRUCTION REGISTER
----------------------------------
--! Instruction register
v_ir := d.mdb_in;
--! Detect if source extension word is required
v_is_sext := r.inst_as(C_IDX) or r.inst_as(C_SYMB) or r.inst_as(C_ABS) or r.inst_as(C_IMM);
--! Detect if destination extension word is required
-- v_is_dext := r.inst_ad(C_IDX) or r.inst_ad(C_SYMB) or r.inst_ad(C_ABS);
--! For the Symbolic addressing mode, add -2 to the extension word in order
--! to make up for the PC address
if ( ( (r.i_state=I_EXT1) and (r.inst_as(C_SYMB) = '1') )
or ( (r.i_state=I_EXT2) and (r.inst_ad(C_SYMB) = '1') )
or ( (r.i_state=I_EXT1) and (r.inst_as(C_SYMB) = '0')
and (r.i_state/=I_EXT2) and (r.inst_ad(C_SYMB) = '1') ) ) then
v_ext_incr := x"FFFE";
else
v_ext_incr := x"0000";
end if;
v_ext_nxt := STD_LOGIC_VECTOR(UNSIGNED(v_ir) + UNSIGNED(v_ext_incr));
--! Store source extension word
if ( (v_decode = '1') and (v_is_const = '1') ) then
v.inst_sext := r.sconst_nxt;
elsif ( (v_decode = '1') and (v_inst_type_nxt(C_INST_JMP) = '1') ) then
v.inst_sext := v_ir(9) & v_ir(9) & v_ir(9) & v_ir(9) & v_ir(9) & v_ir(9 downto 0) & '0';
elsif ( (r.i_state=I_EXT1) and (v_is_sext = '1') ) then
v.inst_sext := v_ext_nxt;
end if;
--! Source extension word is ready
if ( (r.i_state=I_EXT1) and (v_is_sext = '1') ) then
v_inst_sext_rdy := '1';
else
v_inst_sext_rdy := '0';
end if;
--! Store destination extension word
if ( (r.i_state=I_EXT1) and (v_is_sext = '0') ) then
v.inst_dext := v_ext_nxt;
elsif (r.i_state=I_EXT2) then
v.inst_dext := v_ext_nxt;
end if;
--! Destination extension word is ready
if ( ((r.i_state=I_EXT1) and (v_is_sext = '0')) or (r.i_state=I_EXT2) ) then
v_inst_dext_rdy := '1';
else
v_inst_dext_rdy := '0';
end if;
--=============================================================================
--! 6) DECODE INSTRUCTION
--=============================================================================
--
--! 6.1) OPCODE: INSTRUCTION TYPE
------------------------------------------
--! Instructions type is encoded in a one hot fashion as following:
--
--! 3'b001: Single-operand arithmetic
--! 3'b010: Conditional jump
--! 3'b100: Two-operand arithmetic
v_inst_type_nxt := ( ( v_ir(15) or v_ir(14) ) and not(v_irq_detect) )
& ( (not(v_ir(15)) and not(v_ir(14)) and v_ir(13) ) and not(v_irq_detect) )
& ( (not(v_ir(15)) and not(v_ir(14)) and not(v_ir(13))) and not(v_irq_detect) );
if (v_decode = '1') then
v.inst_type := v_inst_type_nxt;
end if;
--
--! 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC
------------------------------------------
--! Instructions are encoded in a one hot fashion as following:
--
--! 8'b00000001: RRC
--! 8'b00000010: SWPB
--! 8'b00000100: RRA
--! 8'b00001000: SXT
--! 8'b00010000: PUSH
--! 8'b00100000: CALL
--! 8'b01000000: RETI
--! 8'b10000000: IRQ
if (v_irq_detect = '1') then
v_inst_so_nxt := x"80";
elsif (v_inst_type_nxt(C_INST_SO) = '1') then
v_inst_so_nxt := one_hot8(v_ir(9 downto 7));
else
v_inst_so_nxt := x"00";
end if;
if (v_decode = '1') then
v.inst_so := v_inst_so_nxt;
end if;
--
--! 6.3) OPCODE: CONDITIONAL JUMP
----------------------------------
--! Instructions are encoded in a one hot fashion as following:
--
--! 8'b00000001: JNE/JNZ
--! 8'b00000010: JEQ/JZ
--! 8'b00000100: JNC/JLO
--! 8'b00001000: JC/JHS
--! 8'b00010000: JN
--! 8'b00100000: JGE
--! 8'b01000000: JL
--! 8'b10000000: JMP
if (v_decode = '1') then
v.inst_jmp_bin := v_ir(12 downto 10);
end if;
if (r.inst_type(C_INST_JMP) = '1') then
v_inst_jmp := one_hot8(r.inst_jmp_bin);
else
v_inst_jmp := x"00";
end if;
--
--! 6.4) OPCODE: TWO-OPERAND ARITHMETIC
---------------------------------------
--! Instructions are encoded in a one hot fashion as following:
--
--! 12'b000000000001: MOV
--! 12'b000000000010: ADD
--! 12'b000000000100: ADDC
--! 12'b000000001000: SUBC
--! 12'b000000010000: SUB
--! 12'b000000100000: CMP
--! 12'b000001000000: DADD
--! 12'b000010000000: BIT
--! 12'b000100000000: BIC
--! 12'b001000000000: BIS
--! 12'b010000000000: XOR
--! 12'b100000000000: AND
if (v_inst_type_nxt(C_INST_TO) = '1') then
v_inst_to_1hot := one_hot16(v_ir(15 downto 12));
else
v_inst_to_1hot := x"0000";
end if;
v_inst_to_nxt := v_inst_to_1hot(15 downto 4);
if (v_decode = '1') then
v.inst_mov := v_inst_to_nxt(C_MOV);
end if;
--
--! 6.5) SOURCE AND DESTINATION REGISTERS
-----------------------------------------
--! Destination register
v.inst_dest_bin := v_ir(3 downto 0);
if (cpu_halt_st = '1') then
v_inst_dest := one_hot16(d.dbg_reg_sel);
elsif (r.inst_type(C_INST_JMP) = '1') then
v_inst_dest := x"0001";
elsif ( ( r.inst_so(C_IRQ) or r.inst_so(C_PUSH) or r.inst_so(C_CALL) ) = '1' ) then
v_inst_dest := x"0002";
else
v_inst_dest := one_hot16(r.inst_dest_bin);
end if;
--! Source register
v.inst_src_bin := v_ir(11 downto 8);
if (r.inst_type(C_INST_TO) = '1') then
v_inst_src := one_hot16(r.inst_src_bin);
elsif (r.inst_so(C_RETI) = '1') then
v_inst_src := x"0002";
elsif (r.inst_so(C_IRQ) = '1') then
v_inst_src := x"0001";
elsif (r.inst_so(C_IRQ) = '1') then
v_inst_src := one_hot16(r.inst_dest_bin);
else
v_inst_src := x"0000";
end if;
--
--! 6.6) SOURCE ADDRESSING MODES
----------------------------------
--! Source addressing modes are encoded in a one hot fashion as following:
--
--! 13'b0000000000001: Register direct.
--! 13'b0000000000010: Register indexed.
--! 13'b0000000000100: Register indirect.
--! 13'b0000000001000: Register indirect autoincrement.
--! 13'b0000000010000: Symbolic (operand is in memory at address PC+x).
--! 13'b0000000100000: Immediate (operand is next word in the instruction stream).
--! 13'b0000001000000: Absolute (operand is in memory at address x).
--! 13'b0000010000000: Constant 4.
--! 13'b0000100000000: Constant 8.
--! 13'b0001000000000: Constant 0.
--! 13'b0010000000000: Constant 1.
--! 13'b0100000000000: Constant 2.
--! 13'b1000000000000: Constant -1.
if (v_inst_type_nxt(C_INST_TO) = '1') then
v_src_reg := v_ir(3 downto 0);
else
v_src_reg := v_ir(11 downto 8);
end if;
if (v_inst_type_nxt(C_INST_JMP) = '1') then
v.inst_as_nxt := "0000000000001";
elsif (v_src_reg = x"3") then--! Addressing mode using R3
case (v_ir(5 downto 4)) is
when "11" =>
v.inst_as_nxt := "1000000000000";
when "10" =>
v.inst_as_nxt := "0100000000000";
when "01" =>
v.inst_as_nxt := "0010000000000";
when others =>
v.inst_as_nxt := "0001000000000";
end case;
elsif (v_src_reg = x"2") then--! Addressing mode using R2
case (v_ir(5 downto 4)) is
when "11" =>
v.inst_as_nxt := "0000100000000";
when "10" =>
v.inst_as_nxt := "0000010000000";
when "01" =>
v.inst_as_nxt := "0000001000000";
when others =>
v.inst_as_nxt := "0000000000001";
end case;
elsif (v_src_reg = x"0") then--! Addressing mode using R0
case (v_ir(5 downto 4)) is
when "11" =>
v.inst_as_nxt := "0000000100000";
when "10" =>
v.inst_as_nxt := "0000000000100";
when "01" =>
v.inst_as_nxt := "0000000010000";
when others =>
v.inst_as_nxt := "0000000000001";
end case;
else --! General Addressing mode
case (v_ir(5 downto 4)) is
when "11" =>
v.inst_as_nxt := "0000000001000";
when "10" =>
v.inst_as_nxt := "0000000000100";
when "01" =>
v.inst_as_nxt := "0000000000010";
when others =>
v.inst_as_nxt := "0000000000001";
end case;
end if;
v_is_const := r.inst_as_nxt(12) or r.inst_as_nxt(11) or r.inst_as_nxt(10) or r.inst_as_nxt(9) or r.inst_as_nxt(8) or r.inst_as_nxt(7);
v.inst_as := v_is_const & r.inst_as_nxt(6 downto 0);
--! 13'b0000010000000: Constant 4.
--! 13'b0000100000000: Constant 8.
--! 13'b0001000000000: Constant 0.
--! 13'b0010000000000: Constant 1.
--! 13'b0100000000000: Constant 2.
--! 13'b1000000000000: Constant -1.
if (r.inst_as_nxt(7) = '1') then
v.sconst_nxt := x"0004";
elsif (r.inst_as_nxt(8) = '1') then
v.sconst_nxt := x"0008";
elsif (r.inst_as_nxt(9) = '1') then
v.sconst_nxt := x"0000";
elsif (r.inst_as_nxt(10) = '1') then
v.sconst_nxt := x"0001";
elsif (r.inst_as_nxt(11) = '1') then
v.sconst_nxt := x"0002";
elsif (r.inst_as_nxt(12) = '1') then
v.sconst_nxt := x"FFFF";
else
v.sconst_nxt := x"0000";
end if;
--
--! 6.7) DESTINATION ADDRESSING MODES
-------------------------------------
--! Destination addressing modes are encoded in a one hot fashion as following:
--
--! 8'b00000001: Register direct.
--! 8'b00000010: Register indexed.
--! 8'b00010000: Symbolic (operand is in memory at address PC+x).
--! 8'b01000000: Absolute (operand is in memory at address x).
v_dest_reg := v_ir(3 downto 0);
if (v_inst_type_nxt(C_INST_TO) = '0') then
v.inst_ad_nxt := "00000000";
elsif (v_dest_reg = x"2") then --! Addressing mode using R2
if (v_ir(7) = '1') then
v.inst_ad_nxt := "01000000";
else
v.inst_ad_nxt := "00000001";
end if;
elsif (v_dest_reg=x"0") then --! Addressing mode using R0
if (v_ir(7) = '1') then
v.inst_ad_nxt := "00010000";
else
v.inst_ad_nxt := "00000001";
end if;
else --! General Addressing mode
if (v_ir(7) = '1') then
v.inst_ad_nxt := "00000010";
else
v.inst_ad_nxt := "00000001";
end if;
end if;
v.inst_ad := r.inst_ad_nxt;
--
--! 6.8) REMAINING INSTRUCTION DECODING
---------------------------------------
--! Operation size
if (v_decode = '1') then
v.inst_bw := v_ir(6) and not(v_inst_type_nxt(C_INST_JMP)) and not(v_irq_detect) and not(v_cpu_halt_req);
end if;
--! Extended instruction size
-- v_inst_sz_nxt := STD_LOGIC_VECTOR( UNSIGNED( '0' & (r.inst_as_nxt(C_IDX) or r.inst_as_nxt(C_SYMB) or r.inst_as_nxt(C_ABS) or r.inst_as_nxt(C_IMM)) )
-- + UNSIGNED( '0' & ((r.inst_ad_nxt(C_IDX) or r.inst_ad_nxt(C_SYMB) or r.inst_ad_nxt(C_ABS)) and not(v_inst_type_nxt(C_INST_SO))) ) );
if ( ( (r.inst_as_nxt(C_IDX) or r.inst_as_nxt(C_SYMB) or r.inst_as_nxt(C_ABS) or r.inst_as_nxt(C_IMM)) = '0' )
and ( ((r.inst_ad_nxt(C_IDX) or r.inst_ad_nxt(C_SYMB) or r.inst_ad_nxt(C_ABS)) and not(v_inst_type_nxt(C_INST_SO))) = '0' ) ) then
v_inst_sz_nxt := "00";
elsif ( ( (r.inst_as_nxt(C_IDX) or r.inst_as_nxt(C_SYMB) or r.inst_as_nxt(C_ABS) or r.inst_as_nxt(C_IMM)) = '1' )
and ( ((r.inst_ad_nxt(C_IDX) or r.inst_ad_nxt(C_SYMB) or r.inst_ad_nxt(C_ABS)) and not(v_inst_type_nxt(C_INST_SO))) = '1' ) ) then
v_inst_sz_nxt := "10";
else
v_inst_sz_nxt := "01";
end if;
if (v_decode = '1') then
v.inst_sz := v_inst_sz_nxt;
end if;
--=============================================================================
--! 7) EXECUTION-UNIT STATE MACHINE
--=============================================================================
--! State machine control signals
----------------------------------
v_src_acalc_pre := r.inst_as_nxt(C_IDX) or r.inst_as_nxt(C_SYMB) or r.inst_as_nxt(C_ABS);
v_src_rd_pre := r.inst_as_nxt(C_INDIR) or r.inst_as_nxt(C_INDIR_I) or r.inst_as_nxt(C_IMM) or v_inst_so_nxt(C_RETI);
v_dst_acalc_pre := r.inst_ad_nxt(C_IDX) or r.inst_ad_nxt(C_SYMB) or r.inst_ad_nxt(C_ABS);
v_dst_acalc := inst_ad(C_IDX) or inst_ad(C_SYMB) or inst_ad(C_ABS);
v_dst_rd_pre := r.inst_ad_nxt(C_IDX) or v_inst_so_nxt(C_PUSH) or v_inst_so_nxt(C_CALL) or v_inst_so_nxt(C_RETI);
v_dst_rd := inst_ad(C_IDX) or inst_so(C_PUSH) or inst_so(C_CALL) or inst_so(C_RETI);
if ( ((r.inst_ad_nxt(C_DIR) = '1') and (v_ir(3 downto 0) = "0000")) or (v_inst_type_nxt(C_INST_JMP) = '1') or (v_inst_so_nxt(C_RETI) = '1') ) then
v_inst_branch := '1';
else
v_inst_branch := '0';
end if;
if ( (v_inst_branch = '1') and (v_decode = '1') ) then
v.exec_jmp := '1';
elsif (e_state = E_JUMP) then
v.exec_jmp := '0';
end if;
if (r.e_state = E_DST_RD) then
v.exec_dst_wr := '1';
elsif (e_state = E_DST_WR) then
v.exec_dst_wr := '0';
end if;
if ( (inst_type(C_INST_SO) = '1') and (r.e_state = E_SRC_RD) ) then
v.exec_src_wr := '1';
elsif ( (r.e_state = E_SRC_WR) or (r.e_state = E_DST_WR) ) then
v.exec_src_wr := '0';
end if;
if (r.e_state=E_DST_RD) then
v.exec_dext_rdy := '0';
elsif (v_inst_dext_rdy = '1') then
v.exec_dext_rdy := '1';
end if;
--! Execution first state
if ( (r.cpu_halt_st = '0') and (v_inst_so_nxt(C_IRQ) = '1') ) then
v_e_first_state := E_IRQ_0;
elsif ( (v_cpu_halt_req = '1') or (r.i_state = I_IDLE) ) then
v_e_first_state := E_IDLE;
elsif (d.cpuoff = '1') then
v_e_first_state := E_IDLE;
elsif (v_src_acalc_pre = '1') then
v_e_first_state := E_SRC_AD;
elsif (v_src_rd_pre = '1') then
v_e_first_state := E_SRC_RD;
elsif (v_dst_acalc_pre = '1') then
v_e_first_state := E_DST_AD;
elsif (v_dst_rd_pre = '1') then
v_e_first_state := E_DST_RD;
else
v_e_first_state := E_EXEC;
end if;
--! State machine
----------------------------------
--! States Transitions
case(r.e_state) is
when E_IDLE =>
v.e_state_nxt := v_e_first_state;
when E_IRQ_0 =>
v.e_state_nxt := E_IRQ_1;
when E_IRQ_1 =>
v.e_state_nxt := E_IRQ_2;
when E_IRQ_2 =>
v.e_state_nxt := E_IRQ_3;
when E_IRQ_3 =>
v.e_state_nxt := E_IRQ_4;
when E_IRQ_4 =>
v.e_state_nxt := E_EXEC;
when E_SRC_AD =>
if (v_inst_sext_rdy = '1') then
v.e_state_nxt := E_SRC_RD;
else
v.e_state_nxt := E_SRC_AD;
end if;
when E_SRC_RD =>
if (v_dst_acalc = '1') then
v.e_state_nxt := E_DST_AD;
elsif (v_dst_rd = '1') then
v.e_state_nxt := E_DST_RD;
else
v.e_state_nxt := E_EXEC;
end if;
when E_DST_AD =>
if ( (v_inst_dext_rdy = '1') or (r.exec_dext_rdy = '1') )then
v.e_state_nxt := E_DST_RD;
else
v.e_state_nxt := E_DST_AD;
end if;
when E_DST_RD =>
v.e_state_nxt := E_EXEC;
when E_EXEC =>
if (r.exec_dst_wr = '1') then
v.e_state_nxt := E_DST_WR;
elsif (r.exec_jmp = '1') then
v.e_state_nxt := E_JUMP;
elsif (r.exec_src_wr = '1') then
v.e_state_nxt := E_SRC_WR;
else
v.e_state_nxt := v_e_first_state;
end if;
when E_JUMP =>
v.e_state_nxt := v_e_first_state;
when E_DST_WR =>
if (r.exec_jmp = '1') then
v.e_state_nxt := E_JUMP;
else
v.e_state_nxt := v_e_first_state;
end if;
when E_SRC_WR =>
v.e_state_nxt := v_e_first_state;
when others =>
v.e_state_nxt := E_IRQ_0;
end case;
--! State machine
v.e_state := r.e_state_nxt;
--! Frontend State machine control signals
------------------------------------------
if (r.exec_jmp = '1') then
if (r.e_state = E_JUMP) then
v_exec_done := '1';
else
v_exec_done := '0';
end if;
elsif (r.exec_dst_wr = '1') then
if (r.e_state = E_DST_WR) then
v_exec_done := '1';
else
v_exec_done := '0';
end if;
elsif (r.exec_src_wr = '1') then
if (r.e_state = E_SRC_WR) then
v_exec_done := '1';
else
v_exec_done := '0';
end if;
else
if (r.e_state = E_EXEC) then
v_exec_done := '1';
else
v_exec_done := '0';
end if;
end if;
--=============================================================================
--! 8) EXECUTION-UNIT STATE CONTROL
--=============================================================================
--
--! 8.1) ALU CONTROL SIGNALS
---------------------------------------
--
--! 12'b000000000001: Enable ALU source inverter
--! 12'b000000000010: Enable Incrementer
--! 12'b000000000100: Enable Incrementer on carry bit
--! 12'b000000001000: Select Adder
--! 12'b000000010000: Select AND
--! 12'b000000100000: Select OR
--! 12'b000001000000: Select XOR
--! 12'b000010000000: Select DADD
--! 12'b000100000000: Update N, Z & C (C=~Z)
--! 12'b001000000000: Update all status bits
--! 12'b010000000000: Update status bit for XOR instruction
--! 12'b100000000000: Don't write to destination
v_alu_src_inv := v_inst_to_nxt(C_SUB) or v_inst_to_nxt(C_SUBC)
or v_inst_to_nxt(C_CMP) or v_inst_to_nxt(C_BIC) ;
v_alu_inc := v_inst_to_nxt(C_SUB) or v_inst_to_nxt(C_CMP);
v_alu_inc_c := v_inst_to_nxt(C_ADDC) or v_inst_to_nxt(C_DADD)
or v_inst_to_nxt(C_SUBC);
v_alu_add := v_inst_to_nxt(C_ADD) or v_inst_to_nxt(C_ADDC)
or v_inst_to_nxt(C_SUB) or v_inst_to_nxt(C_SUBC)
or v_inst_to_nxt(C_CMP) or v_inst_type_nxt(C_INST_JMP)
or v_inst_so_nxt(C_RETI);
v_alu_and := v_inst_to_nxt(C_AND) or v_inst_to_nxt(C_BIC)
or v_inst_to_nxt(C_BIT);
v_alu_or := v_inst_to_nxt(C_BIS);
v_alu_xor := v_inst_to_nxt(C_XOR);
v_alu_dadd := v_inst_to_nxt(C_DADD);
v_alu_stat_7 := v_inst_to_nxt(C_BIT) or v_inst_to_nxt(C_AND)
or v_inst_so_nxt(C_SXT);
v_alu_stat_f := v_inst_to_nxt(C_ADD) or v_inst_to_nxt(C_ADDC)
or v_inst_to_nxt(C_SUB) or v_inst_to_nxt(C_SUBC)
or v_inst_to_nxt(C_CMP) or v_inst_to_nxt(C_DADD)
or v_inst_to_nxt(C_BIT) or v_inst_to_nxt(C_XOR)
or v_inst_to_nxt(C_AND)
or v_inst_so_nxt(C_RRC) or v_inst_so_nxt(C_RRA)
or v_inst_so_nxt(C_SXT);
v_alu_shift := v_inst_so_nxt(C_RRC) or v_inst_so_nxt(C_RRA);
v_exec_no_wr := v_inst_to_nxt(C_CMP) or v_inst_to_nxt(C_BIT);
if (v_decode = '1') then
v.inst_alu := v_exec_no_wr
& v_alu_shift
& v_alu_stat_f
& v_alu_stat_7
& v_alu_dadd
& v_alu_xor
& v_alu_or
& v_alu_and
& v_alu_add
& v_alu_inc_c
& v_alu_inc
& v_alu_src_inv;
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
cpu_halt_st <= r.cpu_halt_st; --! Halt/Run status from CPU
decode_noirq <= v_decode_noirq; --! Frontend v_decode instruction
e_state <= r.e_state; --! Execution state
exec_done <= v_exec_done; --! Execution completed
inst_ad <= r.inst_ad; --! Decoded Inst: destination addressing mode
inst_as <= r.inst_as; --! Decoded Inst: source addressing mode
inst_alu <= r.inst_alu; --! ALU control signals
inst_bw <= r.inst_bw; --! Decoded Inst: byte width
inst_dest <= v_inst_dest; --! Decoded Inst: destination (one hot)
inst_dext <= r.inst_dext; --! Decoded Inst: destination extended instruction word
inst_irq_rst <= r.inst_irq_rst; --! Decoded Inst: Reset interrupt
inst_jmp <= v_inst_jmp; --! Decoded Inst: Conditional jump
inst_mov <= r.inst_mov; --! Decoded Inst: mov instruction
inst_sext <= r.inst_sext; --! Decoded Inst: source extended instruction word
inst_so <= r.inst_so; --! Decoded Inst: Single-operand arithmetic
inst_src <= v_inst_src; --! Decoded Inst: source (one hot)
inst_type <= r.inst_type; --! Decoded Instruction type
irq_acc <= v_irq_acc; --! Interrupt request accepted (one-hot signal)
mab <= v_mab; --! Frontend Memory address bus
mb_en <= v_mb_en; --! Frontend Memory bus enable
nmi_acc <= v_nmi_acc; --! Non-Maskable interrupt request accepted
pc <= r.pc; --! Program counter
pc_nxt <= v_pc_nxt; --! Next PC value (for CALL & IRQ)
end process COMB;
REGS : process (mclk, mrst)
begin
if (mrst = '1') then
r <= ( i_state => "000",
i_state_nxt => "000",
inst_sz => "00",
sconst_nxt => x"0000",
e_state_nxt => "0000",
cpu_halt_st => '0', --! Debug interface cpu status
inst_nmi => '0', --! Detect nmi interrupt
inst_irq_rst => '1', --! Detect reset interrupt
irq_num => "111111", --! Select interrupt vector
pc => x"0000", --! Program counter
pmem_busy => '0', --! Check if ROM has been busy in order to retry ROM access
inst_sext => x"0000", --! Store source extension word
inst_dext => x"0000", --! Store destination extension word
inst_type => "000",
inst_so => x"00",
inst_jmp_bin => "000",
inst_mov => '0',
inst_dest_bin => "0000", --! Destination register
inst_src_bin => "0000", --! Source register
inst_as_nxt => "0000000000000",
inst_as => x"00",
inst_ad_nxt => x"00",
inst_ad => x"00",
inst_bw => '0', --! Operation size
e_state => "0001", --! State machine registers
exec_jmp => '0',
exec_dst_wr => '0',
exec_src_wr => '0',
exec_dext_rdy => '0',
inst_alu => x"000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
end RTL; | bsd-3-clause | 0afe6a6a2b609fc03214327d460dd8fd | 0.569761 | 2.649399 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/cmod_a7_15/tx/bsp.vhd | 2 | 14,973 | -------------------------------------------------------------------------------
---
--- FPGA TX - FPGA Based Radio Transmitter
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | >-------> RF OUT
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +-------------+ +--------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity bsp is
port(
clk_in : in std_logic;
rst : in std_logic;
rf_out : out std_logic;
leds : out std_logic_vector(7 downto 0);
gps_tx : in std_logic;
gps_rx : out std_logic;
pps : in std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic;
ld1 : out std_logic;
--rs232 interface
rs232_rx : in std_logic;
rs232_tx : out std_logic
);
end entity bsp;
architecture rtl of bsp is
component transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end component transmitter;
component user_design is
port(
clk : in std_logic;
rst : in std_logic;
output_tx_freq : out std_logic_vector(31 downto 0);
output_tx_freq_stb : out std_logic;
output_tx_freq_ack : in std_logic;
output_tx_am : out std_logic_vector(31 downto 0);
output_tx_am_stb : out std_logic;
output_tx_am_ack : in std_logic;
output_tx_ctl : out std_logic_vector(31 downto 0);
output_tx_ctl_stb : out std_logic;
output_tx_ctl_ack : in std_logic;
output_leds : out std_logic_vector(31 downto 0);
output_leds_stb : out std_logic;
output_leds_ack : in std_logic;
--gps pps count
input_gps_count : in std_logic_vector(31 downto 0);
input_gps_count_stb : in std_logic;
input_gps_count_ack : out std_logic;
--gps rx stream
input_gps_rx : in std_logic_vector(31 downto 0);
input_gps_rx_stb : in std_logic;
input_gps_rx_ack : out std_logic;
--gps tx stream
output_gps_tx : out std_logic_vector(31 downto 0);
output_gps_tx_stb : out std_logic;
output_gps_tx_ack : in std_logic;
--rs232 rx stream
input_rs232_rx : in std_logic_vector(31 downto 0);
input_rs232_rx_stb : in std_logic;
input_rs232_rx_ack : out std_logic;
--rs232 tx stream
output_rs232_tx : out std_logic_vector(31 downto 0);
output_rs232_tx_stb : out std_logic;
output_rs232_tx_ack : in std_logic
);
end component;
component serial_input is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
rx : in std_logic;
out1 : out std_logic_vector(7 downto 0);
out1_stb : out std_logic;
out1_ack : in std_logic
);
end component serial_input;
component serial_output is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
tx : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in1_stb : in std_logic;
in1_ack : out std_logic
);
end component serial_output;
component gps_pps
port(
clk : in std_logic;
pps : in std_logic;
pps_count : out std_logic_vector(31 downto 0);
pps_count_stb : out std_logic;
pps_count_ack : in std_logic);
end component gps_pps;
--clock tree signals
signal clk : std_logic;
signal clkin1 : std_logic;
signal clkfb : std_logic;
signal clkfbout : std_logic;
signal clk100 : std_logic;
signal locked_internal : std_logic;
signal not_locked : std_logic;
signal internal_rst : std_logic;
--tx interface
signal output_tx_freq : std_logic_vector(31 downto 0);
signal output_tx_freq_stb : std_logic;
signal output_tx_freq_ack : std_logic;
signal output_tx_am : std_logic_vector(31 downto 0);
signal output_tx_am_stb : std_logic;
signal output_tx_am_ack : std_logic;
signal output_tx_ctl : std_logic_vector(31 downto 0);
signal output_tx_ctl_stb : std_logic;
signal output_tx_ctl_ack : std_logic;
signal input_gps_count : std_logic_vector(31 downto 0);
signal input_gps_count_stb : std_logic;
signal input_gps_count_ack : std_logic;
--rs232 rx stream
signal input_rs232_rx : std_logic_vector(31 downto 0);
signal input_rs232_rx_stb : std_logic;
signal input_rs232_rx_ack : std_logic;
--rs232 tx stream
signal output_rs232_tx : std_logic_vector(31 downto 0);
signal output_rs232_tx_stb : std_logic;
signal output_rs232_tx_ack : std_logic;
--gps rx stream
signal input_gps_rx : std_logic_vector(31 downto 0);
signal input_gps_rx_stb : std_logic;
signal input_gps_rx_ack : std_logic;
--gps tx stream
signal output_gps_tx : std_logic_vector(31 downto 0);
signal output_gps_tx_stb : std_logic;
signal output_gps_tx_ack : std_logic;
signal s_test_1 : std_logic := '0';
signal s_test_2 : std_logic := '0';
signal output_leds : std_logic_vector(31 downto 0);
signal output_leds_stb : std_logic;
signal output_leds_ack : std_logic;
begin
ld1 <= '1';
transmitter_inst_1 : transmitter port map(
clk => clk,
rst => internal_rst,
frequency => output_tx_freq,
frequency_stb => output_tx_freq_stb,
frequency_ack => output_tx_freq_ack,
control => output_tx_ctl,
control_stb => output_tx_ctl_stb,
control_ack => output_tx_ctl_ack,
amplitude => output_tx_am,
amplitude_stb => output_tx_am_stb,
amplitude_ack => output_tx_am_ack,
tx_rx => tx_rx,
tx_pa => tx_pa,
rf => rf_out
);
process
begin
wait until rising_edge(clk);
if output_tx_freq_stb = '1' then
s_test_1 <= not s_test_1;
end if;
if output_tx_am_stb = '1' then
s_test_2 <= not s_test_2;
end if;
end process;
user_design_inst_1 : user_design port map(
clk => clk,
rst => internal_rst,
--rs232 rx stream
input_rs232_rx => input_rs232_rx,
input_rs232_rx_stb => input_rs232_rx_stb,
input_rs232_rx_ack => input_rs232_rx_ack,
--rs232 tx stream
output_rs232_tx => output_rs232_tx,
output_rs232_tx_stb => output_rs232_tx_stb,
output_rs232_tx_ack => output_rs232_tx_ack,
--gps rx stream
input_gps_rx => input_gps_rx,
input_gps_rx_stb => input_gps_rx_stb,
input_gps_rx_ack => input_gps_rx_ack,
--gps tx stream
output_gps_tx => output_gps_tx,
output_gps_tx_stb => output_gps_tx_stb,
output_gps_tx_ack => output_gps_tx_ack,
input_gps_count => input_gps_count,
input_gps_count_stb => input_gps_count_stb,
input_gps_count_ack => input_gps_count_ack,
output_leds => output_leds,
output_leds_stb => output_leds_stb,
output_leds_ack => output_leds_ack,
--transmit interface
output_tx_freq => output_tx_freq,
output_tx_freq_stb => output_tx_freq_stb,
output_tx_freq_ack => output_tx_freq_ack,
output_tx_am => output_tx_am,
output_tx_am_stb => output_tx_am_stb,
output_tx_am_ack => output_tx_am_ack,
output_tx_ctl => output_tx_ctl,
output_tx_ctl_stb => output_tx_ctl_stb,
output_tx_ctl_ack => output_tx_ctl_ack
);
pps1 : gps_pps port map(
clk => clk,
pps => pps,
pps_count => input_gps_count,
pps_count_stb => input_gps_count_stb,
pps_count_ack => input_gps_count_ack
);
serial_output_inst_1 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 12000000
)port map(
clk => clk,
rst => internal_rst,
tx => rs232_tx,
in1 => output_rs232_tx(7 downto 0),
in1_stb => output_rs232_tx_stb,
in1_ack => output_rs232_tx_ack
);
serial_input_inst_1 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 12000000
) port map (
clk => clk,
rst => internal_rst,
rx => rs232_rx,
out1 => input_rs232_rx(7 downto 0),
out1_stb => input_rs232_rx_stb,
out1_ack => input_rs232_rx_ack
);
input_rs232_rx(15 downto 8) <= (others => '0');
serial_output_inst_2 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 9600
)port map(
clk => clk,
rst => internal_rst,
tx => gps_rx,
in1 => output_gps_tx(7 downto 0),
in1_stb => output_gps_tx_stb,
in1_ack => output_gps_tx_ack
);
serial_input_inst_2 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 9600
) port map (
clk => clk,
rst => internal_rst,
rx => gps_tx,
out1 => input_gps_rx(7 downto 0),
out1_stb => input_gps_rx_stb,
out1_ack => input_gps_rx_ack
);
input_gps_rx(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(clk);
if output_leds_stb = '1' then
leds <= output_leds(7 downto 0);
end if;
end process;
output_leds_ack <= '1';
-- input buffering
--------------------------------------
clkin1_buf : ibufg
port map
(o => clkin1,
i => clk_in);
mmcme2_base_inst : mmcme2_base
generic map (
bandwidth => "optimized", -- jitter programming (optimized, high, low)
clkfbout_mult_f => 50.0, -- multiply value for all clkout (2.000-64.000).
clkfbout_phase => 0.0, -- phase offset in degrees of clkfb (-360.000-360.000).
clkin1_period => 83.333, -- input clock period in ns to ps resolution (i.e. 33.333 is 30 mhz).
-- clkout0_divide - clkout6_divide: divide amount for each clkout (1-128)
clkout1_divide => 1,
clkout2_divide => 1,
clkout3_divide => 1,
clkout4_divide => 1,
clkout5_divide => 1,
clkout6_divide => 1,
clkout0_divide_f => 6.0, -- divide amount for clkout0 (1.000-128.000).
-- clkout0_duty_cycle - clkout6_duty_cycle: duty cycle for each clkout (0.01-0.99).
clkout0_duty_cycle => 0.5,
clkout1_duty_cycle => 0.5,
clkout2_duty_cycle => 0.5,
clkout3_duty_cycle => 0.5,
clkout4_duty_cycle => 0.5,
clkout5_duty_cycle => 0.5,
clkout6_duty_cycle => 0.5,
-- clkout0_phase - clkout6_phase: phase offset for each clkout (-360.000-360.000).
clkout0_phase => 0.0,
clkout1_phase => 0.0,
clkout2_phase => 0.0,
clkout3_phase => 0.0,
clkout4_phase => 0.0,
clkout5_phase => 0.0,
clkout6_phase => 0.0,
clkout4_cascade => false, -- cascade clkout4 counter with clkout6 (false, true)
divclk_divide => 1, -- master division value (1-106)
ref_jitter1 => 0.0, -- reference input jitter in ui (0.000-0.999).
startup_wait => false -- delays done until mmcm is locked (false, true)
)
port map (
clkout0 => clk100, -- 1-bit output: clkout0
clkout0b => open, -- 1-bit output: inverted clkout0
clkout1 => open, -- 1-bit output: clkout1
clkout1b => open, -- 1-bit output: inverted clkout1
clkout2 => open, -- 1-bit output: clkout2
clkout2b => open, -- 1-bit output: inverted clkout2
clkout3 => open, -- 1-bit output: clkout3
clkout3b => open, -- 1-bit output: inverted clkout3
clkout4 => open, -- 1-bit output: clkout4
clkout5 => open, -- 1-bit output: clkout5
clkout6 => open, -- 1-bit output: clkout6
-- feedback clocks: 1-bit (each) output: clock feedback ports
clkfbout => clkfbout, -- 1-bit output: feedback clock
clkfboutb => open, -- 1-bit output: inverted clkfbout
-- status ports: 1-bit (each) output: mmcm status ports
locked => locked_internal, -- 1-bit output: lock
-- clock inputs: 1-bit (each) input: clock input
clkin1 => clkin1, -- 1-bit input: clock
-- control ports: 1-bit (each) input: mmcm control ports
pwrdwn => '0', -- 1-bit input: power-down
rst => rst, -- 1-bit input: reset
-- feedback clocks: 1-bit (each) input: clock feedback ports
clkfbin => clkfb -- 1-bit input: feedback clock
);
process
begin
wait until rising_edge(clk);
not_locked <= not locked_internal;
internal_rst <= not_locked;
end process;
-- output buffering
-------------------------------------
bufg_inst2 : bufg
port map
(o => clkfb,
i => clkfbout);
bufg_inst3 : bufg
port map
(o => clk,
i => clk100);
end architecture rtl;
| mit | 3f921073e96d534987f6c5b3dfb0f597 | 0.519335 | 3.44286 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/462e/hdl/lib_fifo_v1_0_rfs.vhd | 1 | 206,202 | -- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_6 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_2_0;
use fifo_generator_v13_2_0.all;
--library lib_fifo_v1_0_9;
--use lib_fifo_v1_0_9.lib_fifo_pkg.all;
--use lib_fifo_v1_0_9.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
Library xpm;
use xpm.vcomponents.all;
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8
C_XPM_FIFO : integer := 0
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
function XPM_FIFO_GetMemType (inputmemtype : integer) return string is
Variable memtype1 : string(1 to 4) := "auto";
Variable memtype2 : string(1 to 5) := "block";
Variable memtype3 : string(1 to 11) := "distributed";
begin
----- "auto", "block", "distributed", or "ultra"
If (inputmemtype = 0) Then -- distributed Memory
return(memtype1);
elsif (inputmemtype = 1) then
return(memtype2);
elsif (inputmemtype = 2) then
return(memtype3);
End if;
end function XPM_FIFO_GetMemType;
-------------------------------------------------------------------------
function Get_READ_MODE (PRELOAD_REGS: integer; PRELOAD_LATENCY: integer) return string is
Variable READ_MODE_type1 : string(1 to 3) := "std";
Variable READ_MODE_type2 : string(1 to 4) := "fwft";
begin
if (PRELOAD_REGS = 0) and (PRELOAD_LATENCY = 1) then
return(READ_MODE_type1);
elsif (PRELOAD_REGS = 1) and (PRELOAD_LATENCY = 0) then
return(READ_MODE_type2);
end if;
end function Get_READ_MODE;
function Getlatency (PRELOAD_REGS: integer; PRELOAD_LATENCY: integer) return integer is
variable latency : integer := 1;
begin
if (PRELOAD_REGS = 0) and (PRELOAD_LATENCY = 1) then
latency := 1;
elsif (PRELOAD_REGS = 1) and (PRELOAD_LATENCY = 0) then
latency := 0;
end if;
return latency;
end function Getlatency;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
Constant C_EN_SAFETY_CKT_1 : integer := if_then_else(C_USE_BLOCKMEM = 1,C_EN_SAFETY_CKT,0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal Full_int : std_logic;
signal Almost_full_int : std_logic;
---------------------------------------------------
-----XPM FIFO FUNCTIONS & SIGNALS
signal Empty_i : std_logic;
signal Wr_err_i :std_logic;
signal Rd_err_i :std_logic;
constant READ_MODE :string := Get_READ_MODE(C_PRELOAD_REGS, C_PRELOAD_LATENCY);
constant FIFO_MEMORY_TYPE :string := XPM_FIFO_GetMemType(C_USE_BLOCKMEM);
constant RD_LATENCY : integer := Getlatency(C_PRELOAD_REGS, C_PRELOAD_LATENCY);
begin --(architecture implementation)
lib_fifo_instance : if C_XPM_FIFO = 0 generate
begin
full_gen: if (C_EN_SAFETY_CKT_1 = 1) generate
begin
Full <= Full_int or WR_RST_BUSY;
Almost_full <= Almost_full_int or WR_RST_BUSY;
end generate full_gen;
full_gen1: if (C_EN_SAFETY_CKT_1 = 0) generate
begin
Full <= Full_int;
Almost_full <= Almost_full_int;
end generate full_gen1;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_2_0.fifo_generator_v13_2_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full_int,
almost_full => Almost_full_int,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_2_0.fifo_generator_v13_2_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full_int, -- : OUT std_logic;
almost_full => Almost_full_int, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
end generate lib_fifo_instance;
-----------------------------------------------------------------------
-----XPM ASYNC FIFO INSTANCE
xpm_fifo_instance : if C_XPM_FIFO = 1 generate
begin
xpm_fifo_async_inst : xpm_fifo_async
generic map (
FIFO_MEMORY_TYPE => FIFO_MEMORY_TYPE, ---"auto", --string; "auto", "block", or "distributed";
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
RELATED_CLOCKS => 0, --positive integer; 0 or 1
FIFO_WRITE_DEPTH => C_FIFO_DEPTH, ----2048, --positive integer
WRITE_DATA_WIDTH => C_DATA_WIDTH, ----32, --positive integer
WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH, ---12, --positive integer
PROG_FULL_THRESH => 10, --positive integer
FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
READ_MODE => READ_MODE, ----"std", --string; "std" or "fwft";
FIFO_READ_LATENCY => RD_LATENCY, --positive integer;
READ_DATA_WIDTH => C_DATA_WIDTH, -----32, --positive integer
RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH, ---12, --positive integer
PROG_EMPTY_THRESH => 10, --positive integer
USE_ADV_FEATURES => "1F1F",
DOUT_RESET_VALUE => "0", --string
CDC_SYNC_STAGES => C_SYNCHRONIZER_STAGE, --2, --positive integer
WAKEUP_TIME => 0 --positive integer; 0 or 2;
)
port map (
sleep => '0',
rst => Ainit,
wr_clk => Wr_clk,
wr_ack => Wr_ack,
wr_en => Wr_en,
din => Din,
full => Full_int,
almost_full => Almost_full,
overflow => Wr_err_i,
wr_rst_busy => wr_rst_busy,
rd_clk => Rd_clk,
rd_en => Rd_en,
dout => Dout,
empty => Empty_i,
almost_empty => Almost_empty,
underflow => Rd_err_i,
data_valid => Rd_ack,
rd_rst_busy => open, ------rd_rst_busy,
prog_full => open, ------prog_full,
wr_data_count => Wr_count,
prog_empty => open, ------prog_empty,
rd_data_count => Rd_count,
injectsbiterr => '0',
injectdbiterr => '0',
sbiterr => open,
dbiterr => open
);
Empty <= Empty_i;
Full <= Full_int or wr_rst_busy;
Wr_err <= Wr_err_i when (C_HAS_WR_ERR = 1) else '0';
Rd_err <= Rd_err_i when (C_HAS_RD_ERR = 1) else '0';
STD_MODE : if READ_MODE = "std" generate
begin
--process (rd_Clk)
--begin
--if (rd_Clk'event and rd_Clk = '1') then
-- Rd_ack <= Rd_en;
--end if;
--end process;
end generate STD_MODE;
FWFT_MODE : if READ_MODE = "fwft" generate
begin
--Rd_ack <= not Empty_i;
end generate FWFT_MODE;
end generate xpm_fifo_instance;
end implementation;
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_2_0
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_2_0;
use fifo_generator_v13_2_0.all;
Library xpm;
use xpm.vcomponents.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2; -- Valid values are 0 to 8
C_XPM_FIFO : integer range 0 to 1 := 0
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
function GetMemType (inputmemtype : integer) return string is
Variable memtype1 : string(1 to 4) := "auto";
Variable memtype2 : string(1 to 5) := "block";
Variable memtype3 : string(1 to 11) := "distributed";
Variable memtype4 : string(1 to 5) := "ultra";
begin
----- "auto", "block", "distributed", or "ultra"
If (inputmemtype = 0) Then -- distributed Memory
return(memtype1);
elsif (inputmemtype = 1) then
return(memtype2);
elsif (inputmemtype = 2) then
return(memtype3);
elsif (inputmemtype = 3) then
return(memtype4);
End if;
end function GetMemType;
-------------------------------------------------------------------------
function Get_READ_MODE (PRELOAD_REGS: integer; PRELOAD_LATENCY: integer) return string is
Variable READ_MODE_type1 : string(1 to 3) := "std";
Variable READ_MODE_type2 : string(1 to 4) := "fwft";
begin
if (PRELOAD_REGS = 0) and (PRELOAD_LATENCY = 1) then
return(READ_MODE_type1);
elsif (PRELOAD_REGS = 1) and (PRELOAD_LATENCY = 0) then
return(READ_MODE_type2);
end if;
end function Get_READ_MODE;
function Getlatency (PRELOAD_REGS: integer; PRELOAD_LATENCY: integer) return integer is
variable latency : integer := 1;
begin
if (PRELOAD_REGS = 0) and (PRELOAD_LATENCY = 1) then
latency := 1;
elsif (PRELOAD_REGS = 1) and (PRELOAD_LATENCY = 0) then
latency := 0;
end if;
return latency;
end function Getlatency;
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
signal Wr_err_i :std_logic;
signal Rd_err_i :std_logic;
Constant xpm_fifo_or_lib_fifo_sel : integer := 1 ;
constant READ_MODE :string := Get_READ_MODE(C_PRELOAD_REGS, C_PRELOAD_LATENCY);
constant FIFO_MEMORY_TYPE :string := GetMemType(C_MEMORY_TYPE);
constant RD_LATENCY : integer := Getlatency(C_PRELOAD_REGS, C_PRELOAD_LATENCY);
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal empty_i : std_logic;
begin --(architecture implementation)
-----Xpm_fifo instance
xpm_fifo_instance : if C_XPM_FIFO = 1 generate
begin
xpm_fifo_sync_inst : xpm_fifo_sync
generic map (
FIFO_MEMORY_TYPE => FIFO_MEMORY_TYPE, ----"auto", --string; "auto", "block", "distributed", or "ultra" ;
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
FIFO_WRITE_DEPTH => MAX_DEPTH, --C_WRITE_DEPTH, --2048, --positive integer
WRITE_DATA_WIDTH => C_WRITE_DATA_WIDTH, --32, --positive integer
WR_DATA_COUNT_WIDTH => FGEN_CNT_WIDTH, --ADJ_FGEN_CNT_WIDTH,----C_DCOUNT_WIDTH, --positive integer
PROG_FULL_THRESH => 10, --positive integer
FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
READ_MODE => READ_MODE, --"std", --string; "std" or "fwft";
FIFO_READ_LATENCY => RD_LATENCY, --positive integer;
READ_DATA_WIDTH => C_READ_DATA_WIDTH, -- 32, --positive integer
RD_DATA_COUNT_WIDTH => 4 , --positive integer
USE_ADV_FEATURES => "1F1F",
PROG_EMPTY_THRESH => 10, --positive integer
DOUT_RESET_VALUE => "0", --string
WAKEUP_TIME => 0 --positive integer; 0 or 2;
)
port map (
rst => Sinit,
wr_clk => Clk,
wr_en => Wr_en,
wr_ack => Wr_ack,
din => Din,
full => sig_Full,
almost_full => Almost_full,
overflow => Wr_err_i,
rd_en => Rd_en,
dout => Dout,
empty => Empty_i,
almost_empty => open,
data_valid => Rd_ack,
underflow => Rd_err_i,
wr_data_count => sig_full_fg_datacnt, --sig_prim_fg_datacnt,---Data_count,
wr_rst_busy => open,
rd_rst_busy => open,
prog_full => open,
prog_empty => open,
rd_data_count => open,
sleep => '0',
injectsbiterr => '0',
injectdbiterr => '0',
sbiterr => open,
dbiterr => open
);
Empty <= empty_i;
Full <= sig_full;
Wr_err <= Wr_err_i when (C_HAS_WR_ERR = 1) else '0';
Rd_err <= Rd_err_i when (C_HAS_RD_ERR = 1) else '0';
Data_count <= sig_full_fg_datacnt;
STD_MODE : if READ_MODE = "std" generate
begin
--process (Clk)
--begin
--if (Clk'event and Clk = '1') then
-- Rd_ack <= Rd_en;
--end if;
--end process;
end generate STD_MODE;
FWFT_MODE : if READ_MODE = "fwft" generate
begin
--Rd_ack <= not Empty_i;
end generate FWFT_MODE;
end generate xpm_fifo_instance;
legacy_fifo_instance : if C_XPM_FIFO = 0 generate
begin
---lib_fifo_instance : if xpm_fifo_or_lib_fifo_sel = 0 generate
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq" and FAMILY_TO_USE /= "spartan7") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq" or FAMILY_TO_USE = "spartan7") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_2_0.fifo_generator_v13_2_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end generate legacy_fifo_instance;
end implementation;
| mit | a5fc1bad16694c5e078e126ca4cb0ba8 | 0.416562 | 3.888036 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd | 1 | 3,142 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library techmap;
use techmap.allclkgen.all;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
------------------------------------------------------------------
-- Altera Cyclone ep1c20 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_ep1c20board is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal s_clk : std_logic;
signal intclk : std_ulogic;
begin
gen : if (tech = inferred)
generate
intclk <= clkin;
sdclk <= not intclk when SDINVCLK = 1 else intclk;
clk <= intclk; clkn <= not intclk;
cgo.clklock <= '1'; cgo.pcilock <= '1';
end generate;
alt : if (tech /= inferred) generate
pll1 : altera_pll
generic map (clk_mul, clk_div, freq)
port map ( inclk0 => clkin, e0 => clkout, c0 => open,
locked => open);
pll2 : altera_pll
generic map (clk_mul, clk_div, freq)
port map ( inclk0 => cgi.pllref, e0 => sdclk, c0 => s_clk,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_ep1c20board" & ": EP1C20 board sdram/pci clock generator, version " & tost(VERSION),
"clkgen_ep1c20board" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 3da604f05ba49591bca0147461de32a5 | 0.570974 | 3.977215 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/a79f7727e74fe6ae/zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl | 1 | 374,878 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:36 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[1:0][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:2][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[5:4][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:22][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[25:24][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:26][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[29:28][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:30][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:6][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[9:8][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:10][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[13:12][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:14][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[17:16][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:18][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[21:20][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[10].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(21 downto 20),
dinb(1 downto 0) => dinb(21 downto 20),
douta(1 downto 0) => douta(21 downto 20),
doutb(1 downto 0) => doutb(21 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[11].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(23 downto 22),
dinb(1 downto 0) => dinb(23 downto 22),
douta(1 downto 0) => douta(23 downto 22),
doutb(1 downto 0) => doutb(23 downto 22),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[12].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(25 downto 24),
dinb(1 downto 0) => dinb(25 downto 24),
douta(1 downto 0) => douta(25 downto 24),
doutb(1 downto 0) => doutb(25 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[13].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(27 downto 26),
dinb(1 downto 0) => dinb(27 downto 26),
douta(1 downto 0) => douta(27 downto 26),
doutb(1 downto 0) => doutb(27 downto 26),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[14].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(29 downto 28),
dinb(1 downto 0) => dinb(29 downto 28),
douta(1 downto 0) => douta(29 downto 28),
doutb(1 downto 0) => doutb(29 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[15].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(31 downto 30),
dinb(1 downto 0) => dinb(31 downto 30),
douta(1 downto 0) => douta(31 downto 30),
doutb(1 downto 0) => doutb(31 downto 30),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
dinb(1 downto 0) => dinb(3 downto 2),
douta(1 downto 0) => douta(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(5 downto 4),
dinb(1 downto 0) => dinb(5 downto 4),
douta(1 downto 0) => douta(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(7 downto 6),
dinb(1 downto 0) => dinb(7 downto 6),
douta(1 downto 0) => douta(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(9 downto 8),
dinb(1 downto 0) => dinb(9 downto 8),
douta(1 downto 0) => douta(9 downto 8),
doutb(1 downto 0) => doutb(9 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(11 downto 10),
dinb(1 downto 0) => dinb(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
doutb(1 downto 0) => doutb(11 downto 10),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(13 downto 12),
dinb(1 downto 0) => dinb(13 downto 12),
douta(1 downto 0) => douta(13 downto 12),
doutb(1 downto 0) => doutb(13 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(15 downto 14),
dinb(1 downto 0) => dinb(15 downto 14),
douta(1 downto 0) => douta(15 downto 14),
doutb(1 downto 0) => doutb(15 downto 14),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[8].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(17 downto 16),
dinb(1 downto 0) => dinb(17 downto 16),
douta(1 downto 0) => douta(17 downto 16),
doutb(1 downto 0) => doutb(17 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[9].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(19 downto 18),
dinb(1 downto 0) => dinb(19 downto 18),
douta(1 downto 0) => douta(19 downto 18),
doutb(1 downto 0) => doutb(19 downto 18),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
port map (
addra(13 downto 0) => addra(15 downto 2),
addrb(13 downto 0) => addrb(15 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
| mit | 594f87e75693e0bfc18368097eb3fe07 | 0.743202 | 4.708162 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-cpci-xc4v/leon3mp.vhd | 1 | 34,682 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_logic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI+CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(6), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 or CFG_PCI /= 0 generate
grpci2x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_PCI = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn,
clkm,
pciclk,
pci_dirq,
pcii,
pcio,
apbi,
apbo(4),
ahbsi,
ahbso(4),
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open,
open,
open,
open);
end generate;
grpci1x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) = 0 and CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 13, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(13));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(8)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 1, oepol => OEPOL,
noreset => 0, drivereset => 0, int => 10) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio, pci_int);
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i, paddr => 10+i, pirq => 5+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1, memtech => memtech,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN, netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3FT GR-CPCI-XC4V Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | f2b4b66b9caf22d00025eb31a2202118 | 0.562136 | 3.403199 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/8d6f9c45e1ea3378/zqynq_lab_1_design_auto_pc_3_sim_netlist.vhdl | 1 | 30,171 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:13:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_3,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 58fa47db24cd6e305031f45d0a1242ff | 0.645487 | 2.90945 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/grgprbank.vhd | 1 | 3,664 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgprbank
-- File: grgprbank.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: General purpose register bank
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0)
);
end;
architecture rtl of grgprbank is
constant nregsp2: integer := 2**log2(nregs);
subtype regtype is std_logic_vector(regbits-1 downto 0);
type regbank is array(nregsp2-1 downto 0) of regtype;
type grgprbank_regs is record
regs: regbank;
end record;
signal r,nr: grgprbank_regs;
constant pconfig: apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GPREGBANK, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
comb: process(r,rst,apbi)
variable v: grgprbank_regs;
variable o: apb_slv_out_type;
begin
-- Init vars
v := r;
o := apb_none;
o.pindex := pindex;
o.pconfig := pconfig;
-- APB Interface
if nregs > 1 then
o.prdata(regbits-1 downto 0) := r.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))));
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
v.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2)))) := apbi.pwdata(regbits-1 downto 0);
end if;
else
o.prdata(regbits-1 downto 0) := r.regs(0);
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
v.regs(0) := apbi.pwdata(regbits-1 downto 0);
end if;
end if;
-- Reset
if rst='0' then
v.regs := (others => std_logic_vector(to_unsigned(rstval,regbits)));
end if;
-- clear unused part of reg bank so it can be pruned
if nregs < nregsp2 then
for x in nregsp2-1 downto nregs loop
v.regs(x) := (others => '0');
end loop;
end if;
-- Drive outputs
nr <= v;
apbo <= o;
for x in nregs-1 downto 0 loop
rego(x*regbits+regbits-1 downto x*regbits) <= r.regs(x);
end loop;
end process;
regs: process(clk)
begin
if rising_edge(clk) then r <= nr; end if;
end process;
end;
| gpl-2.0 | 81f09366d5f761cb7fc02dbe5c177a7c | 0.603439 | 3.609852 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/comp/ethcomp.vhd | 1 | 20,118 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ethcomp is
component grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbitc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(8 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(8 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(8 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(8 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
gbit : out std_ulogic;
speed : out std_ulogic);
end component;
component greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end component;
end package;
| gpl-2.0 | 769cf4ef59bc022d2fb623982acd5227 | 0.491301 | 3.877795 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml605/testbench.vhd | 1 | 12,349 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
use work.ml605.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_tdqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_logic;
signal egtx_clk : std_logic;
signal gmiiclk_p : std_logic := '1';
signal gmiiclk_n : std_logic := '0';
-- Output signals for LEDs
signal led : std_logic_vector(6 downto 0);
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal clk_33 : std_ulogic := '0';
signal brdyn : std_ulogic;
---------------------pcie----------------------------------------------
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
---------------------pcie end---------------------------------------------
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
gmiiclk_p <= not gmiiclk_p after 4 ns;
gmiiclk_n <= not gmiiclk_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rst <= '1', '0' after 200 us;
rstn1 <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL)
port map (
reset => rst,
errorn => error,
clk_ref_p => clk200p,
clk_ref_n => clk200n,
-- PROM
address => address(24 downto 1),
data => data(15 downto 0),
romsn => romsn,
oen => oen,
writen => writen,
-- DDR3
ddr3_dq => ddr3_dq,
ddr3_dm => ddr3_dm,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
gmiiclk_p => gmiiclk_p,
gmiiclk_n => gmiiclk_n,
egtx_clk => egtx_clk,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
emdint => emdint,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- Output signals for LEDs
iic_scl_main => iic_scl_main,
iic_sda_main => iic_sda_main,
dvi_iic_scl => iic_scl_dvi,
dvi_iic_sda => iic_sda_dvi,
tft_lcd_data => tft_lcd_data,
tft_lcd_clk_p => tft_lcd_clk_p,
tft_lcd_clk_n => tft_lcd_clk_n,
tft_lcd_hsync => tft_lcd_hsync,
tft_lcd_vsync => tft_lcd_vsync,
tft_lcd_de => tft_lcd_de,
tft_lcd_reset_b => tft_lcd_reset_b,
clk_33 => clk_33,
sysace_mpa => sysace_mpa,
sysace_mpce => sysace_mpce,
sysace_mpirq => sysace_mpirq,
sysace_mpoe => sysace_mpoe,
sysace_mpwe => sysace_mpwe,
sysace_d => sysace_d,
pci_exp_txp=> cor_pci_exp_txp,
pci_exp_txn=> cor_pci_exp_txn,
pci_exp_rxp=> cor_pci_exp_rxp,
pci_exp_rxn=> cor_pci_exp_rxn,
sys_clk_p=> ep_sys_clk_p,
sys_clk_n=> ep_sys_clk_n,
sys_reset_n=> cor_sys_reset_n,
led => led
);
u1 : ddr3ram
generic map (
width => 64,
abits => 13,
colbits => 10,
rowbits => 13,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 32)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
address(0) <= '0';
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 7)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, egtx_clk);
end generate;
-- spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
-- end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | b2963b898b76ec1289e1d3781690374e | 0.551381 | 3.220078 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/b9c82e235214f825/zynq_design_1_auto_pc_0_sim_netlist.vhdl | 1 | 533,310 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:15 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | a9d2a030828c0a9cfd81b966f535f9dd | 0.532034 | 2.542986 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 206,825 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Wed Oct 18 15:15:22 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : ip_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "ip_design_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 1 downto 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_1.FCLK_CLK_1_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1 downto 0) => FCLK_CLK_unbuffered(1 downto 0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\buffer_fclk_clk_1.FCLK_CLK_1_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(1),
O => FCLK_CLK1
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_processing_system7_0_0 is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_processing_system7_0_0 : entity is "ip_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of ip_design_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of ip_design_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
end ip_design_processing_system7_0_0;
architecture STRUCTURE of ip_design_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "ip_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK";
attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of I2C0_SCL_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of I2C0_SCL_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of I2C0_SCL_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of I2C0_SDA_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of I2C0_SDA_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of I2C0_SDA_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => FCLK_CLK1,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => I2C0_SCL_I,
I2C0_SCL_O => I2C0_SCL_O,
I2C0_SCL_T => I2C0_SCL_T,
I2C0_SDA_I => I2C0_SDA_I,
I2C0_SDA_O => I2C0_SDA_O,
I2C0_SDA_T => I2C0_SDA_T,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 42bf1b80395e2e13e1110cdbc071d9cf | 0.639468 | 2.76323 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddrintpkg.vhd | 1 | 17,614 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
| gpl-2.0 | 33b38cdca090ce7f640092159a4c3f6b | 0.530487 | 3.610166 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | VHDL_funcs_and_procs/VHDL_func_and_procs.vhd | 1 | 1,453 | -- Based on tutorial here:
-- https://www.youtube.com/watch?v=j2lAPIjpF1w&t=309s
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library sevseg_package;
use sevseg_package.my.all;
ENTITY SEVSEG is
PORT(
SW: IN STD_LOGIC_VECTOR(9 downto 0);
HEX0: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX1: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX2: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX3: OUT STD_LOGIC_VECTOR(6 downto 0);
KEY: in STD_LOGIC_VECTOR(3 downto 0);
CLOCK_50: IN STD_LOGIC
);
END SEVSEG;
ARCHITECTURE MAIN of SEVSEG IS
SIGNAL NUMBER: INTEGER RANGE 0 to 9999:=0;
SIGNAL PRESCALER: INTEGER RANGE 0 to 50000000:=0;
SIGNAL SEG0, SEG1, SEG2, SEG3: INTEGER range 0 to 9:=0;
BEGIN
-- Call package procedure to assign values to each 7seg display.
HEX_DEC(NUMBER, SEG0, SEG1, SEG2, SEG3);
-- Call function to update each hex display.
HEX0<=INT_TO7SEG(SEG0);
HEX1<=INT_TO7SEG(SEG1);
HEX2<=INT_TO7SEG(SEG2);
HEX3<=INT_TO7SEG(SEG3);
-- Define clock-driven process:
PROCESS(CLOCK_50)
BEGIN
IF(CLOCK_50'EVENT and CLOCK_50='1') THEN
IF(PRESCALER<100000*to_integer(unsigned(SW))) THEN
PRESCALER<=PRESCALER+1;
ELSE
PRESCALER<=0;
end if;
IF(PRESCALER=0)THEN
IF(KEY(0)='1')THEN
IF(NUMBER<9999)THEN
NUMBER<=NUMBER+1;
ELSE
NUMBER<=9999;
END IF;
ELSE
IF(NUMBER>0) THEN
NUMBER<=NUMBER-1;
ELSE
NUMBER<=0;
END IF;
END IF;
-- Does lack of else here cause a latch situation?
END IF;
END IF;
END PROCESS;
END MAIN; | mit | 632ec0ea66280abf38706f023bc7152c | 0.70819 | 2.705773 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/bscanregs.vhd | 1 | 2,767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregs
-- File: bscanregs.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, single-ended IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregs is
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end;
architecture hier of bscanregs is
signal itdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable=0 generate
sigo <= sigi;
itdi <= (others => '0');
tdo <= '0';
end generate;
engen: if enable /= 0 generate
g0: for x in 0 to nsigs-1 generate
irgen: if ((dirmask / (2**x)) mod 2)=0 generate
ireg: scanregi
generic map (tech)
port map (sigi(x),sigo(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdi,bsdrive,bshighz);
end generate;
orgen: if ((dirmask / (2**x)) mod 2)/=0 generate
oreg: scanrego
generic map (tech)
port map (sigo(x),sigi(x),sigi(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdo,bsdrive);
end generate;
end generate;
itdi(0) <= tdi;
tdo <= itdi(nsigs);
end generate;
end;
| gpl-2.0 | 93f838f7b9d6cf5f62f23b33a8abead1 | 0.594868 | 3.75441 | false | false | false | false |
davidhorrocks/1541UltimateII | fpga/6502/vhdl_source/alu.vhd | 2 | 5,098 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic;
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : std_logic_vector(7 downto 0) := X"FF";
signal oper4 : std_logic_vector(3 downto 0);
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
with oper4 select data_out_i <=
data_a or data_b when "1000",
data_a and data_b when "1001",
data_a xor data_b when "1010",
sum_result when "1011" | "1110" | "1111",
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
sum: process(data_a, data_b, c_in, operation, d_in)
variable b : std_logic_vector(7 downto 0);
variable sum_l : std_logic_vector(4 downto 0);
variable sum_h : std_logic_vector(4 downto 0);
variable sum_h_nocarry : std_logic_vector(4 downto 0);
begin
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := not data_b;
else
b := data_b;
end if;
-- sum_l(4) = carry of lower end, carry in is masked to '1' for CMP
sum_l := ('0' & data_a(3 downto 0)) + ('0' & b(3 downto 0)) + (c_in or not operation(0));
sum_h_nocarry := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4));
sum_h := sum_h_nocarry + ("0000" & sum_l(4));
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= sum_h(4);
sum_v <= (data_a(7) xor sum_h(3)) and (data_a(7) xor data_b(7) xor (not operation(2)));
-- fix up in decimal mode (not for CMP!)
if d_in='1' and support_bcd then
if operation(2)='0' then -- ADC
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_l := sum_l + 6;
sum_h := sum_h_nocarry + "00001";
else
sum_h := sum_h_nocarry;
end if;
sum_n <= sum_h(3);
sum_v <= (sum_h(3) xor data_a(7)) and not (data_a(7) xor data_b(7));
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_h := sum_h + 6;
sum_c <= '1';
else
sum_c <= '0';
end if;
elsif operation(0)='1' then -- SBC
-- flags are not adjusted in subtract mode
sum_l := ('0' & data_a(3 downto 0)) + ('1' & b(3 downto 0)) + (c_in);
if sum_l(4) = '1' then
sum_l := sum_l - 6;
sum_h := ('0' & data_a(7 downto 4)) + ('1' & b(7 downto 4));
else
sum_h := ('0' & data_a(7 downto 4)) + ('1' & b(7 downto 4)) + "00001";
end if;
if sum_h(4) = '1' then
sum_h := sum_h - 6;
end if;
end if;
end if;
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
oper4 <= enable & operation;
with oper4 select c_out <=
sum_c when "1011" | "1111" | "1110",
c_in when others;
with oper4 select z_out <=
sum_z when "1011" | "1111" | "1110",
zero when "1000" | "1001" | "1010" | "1101",
z_in when others;
with oper4 select n_out <=
sum_n when "1011" | "1111",
data_out_i(7) when "1000" | "1001" | "1010" | "1101" | "1110",
n_in when others;
with oper4 select v_out <=
sum_v when "1011" | "1111",
v_in when others;
data_out <= data_out_i;
end gideon; | gpl-3.0 | 961f14474bb48dc072031876dcae9683 | 0.431346 | 3.351742 | false | false | false | false |
kloboves/sicxe | vhdl/top_module.vhd | 1 | 11,486 | library ieee;
use ieee.std_logic_1164.all;
entity top_module is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
run_toggle_i : in std_logic;
-- Micron CellularRAM connections
micron_chip_enable_o : out std_logic;
micron_output_enable_o : out std_logic;
micron_write_enable_o : out std_logic;
micron_address_o : out std_logic_vector(23 downto 1);
micron_data_bus : inout std_logic_vector(7 downto 0);
micron_address_valid_o : out std_logic;
micron_clock_o : out std_logic;
micron_upper_byte_o : out std_logic;
micron_lower_byte_o : out std_logic;
micron_cre_o : out std_logic;
-- Intel Flash connections
intel_chip_enable_o : out std_logic;
-- Serial interface
serial_i : in std_logic;
serial_o : out std_logic;
-- PS2
ps2_kbd_clock_i : in std_logic;
ps2_kbd_data_i : in std_logic;
-- VGA
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
vga_red_o : out std_logic_vector(2 downto 0);
vga_green_o : out std_logic_vector(2 downto 0);
vga_blue_o : out std_logic_vector(1 downto 0);
-- 7 segment display
seg7_cathode_o : out std_logic_vector(7 downto 0);
seg7_anode_o : out std_logic_vector(3 downto 0);
-- other
leds_o : out std_logic_vector(7 downto 0);
switches_i : in std_logic_vector(7 downto 0);
buttons_i : in std_logic_vector(1 downto 0)
);
end top_module;
architecture behavioral of top_module is
component memory_controller
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- device 1
dev1_read_i : in std_logic;
dev1_write_i : in std_logic;
dev1_address_i : in std_logic_vector(19 downto 0);
dev1_data_in_o : out std_logic_vector(7 downto 0);
dev1_data_out_i : in std_logic_vector(7 downto 0);
dev1_done_o : out std_logic;
-- device 2
dev2_read_i : in std_logic;
dev2_write_i : in std_logic;
dev2_address_i : in std_logic_vector(19 downto 0);
dev2_data_in_o : out std_logic_vector(7 downto 0);
dev2_data_out_i : in std_logic_vector(7 downto 0);
dev2_done_o : out std_logic;
-- Micron CellularRAM connections
micron_chip_enable_o : out std_logic;
micron_output_enable_o : out std_logic;
micron_write_enable_o : out std_logic;
micron_address_o : out std_logic_vector(23 downto 1);
micron_data_bus : inout std_logic_vector(7 downto 0);
micron_address_valid_o : out std_logic;
micron_clock_o : out std_logic;
micron_upper_byte_o : out std_logic;
micron_lower_byte_o : out std_logic;
micron_cre_o : out std_logic
);
end component;
component computer_interface
Port (
clock_i : in std_logic;
reset_i : in std_logic;
serial_i : in std_logic;
serial_o : out std_logic;
control_signals_o : out std_logic_vector(3 downto 0);
memory_read_o : out std_logic;
memory_write_o : out std_logic;
memory_address_o : out std_logic_vector(19 downto 0);
memory_data_in_i : in std_logic_vector(7 downto 0);
memory_data_out_o : out std_logic_vector(7 downto 0);
memory_done_i : in std_logic
);
end component;
component sicxe_core
Port (
clock_i : in std_logic;
reset_i : in std_logic;
enable_i : in std_logic;
error_o : out std_logic;
-- memory
memory_read_o : out std_logic;
memory_write_o : out std_logic;
memory_address_o : out std_logic_vector(19 downto 0);
memory_data_in_i : in std_logic_vector(7 downto 0);
memory_data_out_o : out std_logic_vector(7 downto 0);
memory_done_i : in std_logic;
-- device ports
port_id_o : out std_logic_vector(7 downto 0);
port_in_i : in std_logic_vector(7 downto 0);
port_out_o : out std_logic_vector(7 downto 0);
port_read_strobe_o : out std_logic;
port_write_strobe_o : out std_logic;
-- interrupt
interrupt_i : in std_logic;
interrupt_acknowledge_o : out std_logic;
interrupt_enabled_o : out std_logic
);
end component;
component device_subsystem
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- device port
port_id_i : in std_logic_vector(7 downto 0);
port_in_o : out std_logic_vector(7 downto 0);
port_out_i : in std_logic_vector(7 downto 0);
port_read_strobe_i : in std_logic;
port_write_strobe_i : in std_logic;
-- special
error_i : in std_logic;
stop_i : in std_logic;
event_o : out std_logic;
-- PS2
ps2_kbd_clock_i : in std_logic;
ps2_kbd_data_i : in std_logic;
-- VGA
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
vga_red_o : out std_logic_vector(2 downto 0);
vga_green_o : out std_logic_vector(2 downto 0);
vga_blue_o : out std_logic_vector(1 downto 0);
-- 7 segment display
seg7_cathode_o : out std_logic_vector(7 downto 0);
seg7_anode_o : out std_logic_vector(3 downto 0);
-- other
leds_o : out std_logic_vector(7 downto 0);
switches_i : in std_logic_vector(7 downto 0);
buttons_i : in std_logic_vector(1 downto 0)
);
end component;
component run_control
Port (
clock_i : in std_logic;
reset_i : in std_logic;
start_i : in std_logic;
stop_i : in std_logic;
toggle_i : in std_logic;
enable_o : out std_logic
);
end component;
component interrupt_control
Port (
clock_i : in std_logic;
reset_i : in std_logic;
enable_i : in std_logic;
event_i : in std_logic;
acknowledge_i : in std_logic;
interrupt_o : out std_logic
);
end component;
component debouncer
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end component;
-- computer interface
signal computer_mem_read : std_logic;
signal computer_mem_write : std_logic;
signal computer_mem_address : std_logic_vector(19 downto 0);
signal computer_mem_data_in : std_logic_vector(7 downto 0);
signal computer_mem_data_out : std_logic_vector(7 downto 0);
signal computer_mem_done : std_logic;
signal computer_control_signals : std_logic_vector(3 downto 0);
-- SIC/XE cpu
signal cpu_reset : std_logic;
signal cpu_enable : std_logic;
signal cpu_error : std_logic;
signal cpu_mem_read : std_logic;
signal cpu_mem_write : std_logic;
signal cpu_mem_address : std_logic_vector(19 downto 0);
signal cpu_mem_data_in : std_logic_vector(7 downto 0);
signal cpu_mem_data_out : std_logic_vector(7 downto 0);
signal cpu_mem_done : std_logic;
signal cpu_port_id : std_logic_vector(7 downto 0);
signal cpu_port_in : std_logic_vector(7 downto 0);
signal cpu_port_out : std_logic_vector(7 downto 0);
signal cpu_port_read_strobe : std_logic;
signal cpu_port_write_strobe : std_logic;
signal cpu_interrupt : std_logic;
signal cpu_interrupt_acknowledge : std_logic;
signal cpu_interrupt_enabled : std_logic;
-- devices
signal seg7_stop : std_logic;
signal device_event : std_logic;
-- run control
signal run_toggle : std_logic;
-- interrupt event
signal event : std_logic;
begin
intel_chip_enable_o <= '1'; -- disable chip
seg7_stop <= not cpu_enable;
cpu_reset <= reset_i or computer_control_signals(0);
event <= device_event or computer_control_signals(3);
memory_cmpt : memory_controller
port map (
clock_i => clock_i,
reset_i => reset_i,
-- device 1
dev1_read_i => computer_mem_read,
dev1_write_i => computer_mem_write,
dev1_address_i => computer_mem_address,
dev1_data_in_o => computer_mem_data_in,
dev1_data_out_i => computer_mem_data_out,
dev1_done_o => computer_mem_done,
-- device 2
dev2_read_i => cpu_mem_read,
dev2_write_i => cpu_mem_write,
dev2_address_i => cpu_mem_address,
dev2_data_in_o => cpu_mem_data_in,
dev2_data_out_i => cpu_mem_data_out,
dev2_done_o => cpu_mem_done,
-- micron ram
micron_chip_enable_o => micron_chip_enable_o,
micron_output_enable_o => micron_output_enable_o,
micron_write_enable_o => micron_write_enable_o,
micron_address_o => micron_address_o,
micron_data_bus => micron_data_bus,
micron_address_valid_o => micron_address_valid_o,
micron_clock_o => micron_clock_o,
micron_upper_byte_o => micron_upper_byte_o,
micron_lower_byte_o => micron_lower_byte_o,
micron_cre_o => micron_cre_o
);
computer_cmpt : computer_interface
port map (
clock_i => clock_i,
reset_i => reset_i,
serial_i => serial_i,
serial_o => serial_o,
control_signals_o => computer_control_signals,
memory_read_o => computer_mem_read,
memory_write_o => computer_mem_write,
memory_address_o => computer_mem_address,
memory_data_in_i => computer_mem_data_in,
memory_data_out_o => computer_mem_data_out,
memory_done_i => computer_mem_done
);
sicxe_cmpt : sicxe_core
port map (
clock_i => clock_i,
reset_i => cpu_reset,
enable_i => cpu_enable,
error_o => cpu_error,
memory_read_o => cpu_mem_read,
memory_write_o => cpu_mem_write,
memory_address_o => cpu_mem_address,
memory_data_in_i => cpu_mem_data_in,
memory_data_out_o => cpu_mem_data_out,
memory_done_i => cpu_mem_done,
port_id_o => cpu_port_id,
port_in_i => cpu_port_in,
port_out_o => cpu_port_out,
port_read_strobe_o => cpu_port_read_strobe,
port_write_strobe_o => cpu_port_write_strobe,
interrupt_i => cpu_interrupt,
interrupt_acknowledge_o => cpu_interrupt_acknowledge,
interrupt_enabled_o => cpu_interrupt_enabled
);
device_cmpt : device_subsystem
port map (
clock_i => clock_i,
reset_i => reset_i,
port_id_i => cpu_port_id,
port_in_o => cpu_port_in,
port_out_i => cpu_port_out,
port_read_strobe_i => cpu_port_read_strobe,
port_write_strobe_i => cpu_port_write_strobe,
error_i => cpu_error,
stop_i => seg7_stop,
event_o => device_event,
ps2_kbd_clock_i => ps2_kbd_clock_i,
ps2_kbd_data_i => ps2_kbd_data_i,
vga_hsync_o => vga_hsync_o,
vga_vsync_o => vga_vsync_o,
vga_red_o => vga_red_o,
vga_green_o => vga_green_o,
vga_blue_o => vga_blue_o,
seg7_cathode_o => seg7_cathode_o,
seg7_anode_o => seg7_anode_o,
leds_o => leds_o,
switches_i => switches_i,
buttons_i => buttons_i
);
run_ctrl_cmpt : run_control
port map (
clock_i => clock_i,
reset_i => reset_i,
start_i => computer_control_signals(1),
stop_i => computer_control_signals(2),
toggle_i => run_toggle,
enable_o => cpu_enable
);
interrupt_ctrl_cmpt : interrupt_control
port map (
clock_i => clock_i,
reset_i => reset_i,
enable_i => cpu_interrupt_enabled,
event_i => event,
acknowledge_i => cpu_interrupt_acknowledge,
interrupt_o => cpu_interrupt
);
toggle_debouncer_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => run_toggle_i,
output_o => open,
change_on_o => run_toggle,
change_off_o => open
);
end behavioral;
| mit | d248619e58d454ceb1ed944bf437bce0 | 0.611179 | 3.142544 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/SREGn.vhd | 1 | 906 | library ieee;
use ieee.std_logic_1164.all;
entity SREGn is
generic (n : integer := 4);
port(
Sin : in std_logic;
SE : in std_logic;
CLK : in std_logic;
RST : in std_logic;
Pout : inout std_logic_vector(n-1 downto 0)
);
end SREGn;
architecture behavior of SREGn is
signal reg : std_logic_vector(n-1 downto 0);
signal si : std_logic;
begin
main : process(Sin, SE , CLK, RST)
begin
if rising_edge(CLK) then
if SE='1' then
reg(n-1 downto 1) <= reg(n-2 downto 0);
reg(0) <= Sin;
end if;
end if;
end process;
Pout <= reg;
end behavior;
architecture structual of SREGn is
component DETAR
port(D, E, C, CLR : in std_logic; Q: out std_logic);
end component DETAR;
begin
FST: DETAR port map (Sin, SE, CLK, RST, Pout(0));
G_1 : for I in 1 to N-1 generate
DETAR_I :
DETAR port map
(Pout(I-1), SE, CLK, RST, Pout(I));
end generate;
end architecture structual;
| mit | e7c45b63a2b4fcec2f9c6eb815070ea6 | 0.645695 | 2.618497 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/f7abcf1d6f5a92f5/ip_design_nco_0_0_sim_netlist.vhdl | 1 | 93,230 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:26 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_sim_netlist.vhdl
-- Design : ip_design_nco_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is
port (
reset : out STD_LOGIC;
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\temp_V_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
ap_clk : in STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
temp_V_reg : in STD_LOGIC_VECTOR ( 15 downto 0 );
ap_rst_n : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is
signal ar_hs : STD_LOGIC;
signal int_sine_sample_V_ap_vld : STD_LOGIC;
signal int_sine_sample_V_ap_vld_i_1_n_0 : STD_LOGIC;
signal int_sine_sample_V_ap_vld_i_2_n_0 : STD_LOGIC;
signal \int_step_size_V[15]_i_3_n_0\ : STD_LOGIC;
signal \or\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_0_in : STD_LOGIC;
signal q0_reg_0_i_10_n_0 : STD_LOGIC;
signal q0_reg_0_i_11_n_0 : STD_LOGIC;
signal q0_reg_0_i_12_n_0 : STD_LOGIC;
signal q0_reg_0_i_12_n_1 : STD_LOGIC;
signal q0_reg_0_i_12_n_2 : STD_LOGIC;
signal q0_reg_0_i_12_n_3 : STD_LOGIC;
signal q0_reg_0_i_13_n_0 : STD_LOGIC;
signal q0_reg_0_i_14_n_0 : STD_LOGIC;
signal q0_reg_0_i_15_n_0 : STD_LOGIC;
signal q0_reg_0_i_16_n_0 : STD_LOGIC;
signal q0_reg_0_i_17_n_0 : STD_LOGIC;
signal q0_reg_0_i_18_n_0 : STD_LOGIC;
signal q0_reg_0_i_19_n_0 : STD_LOGIC;
signal q0_reg_0_i_1_n_1 : STD_LOGIC;
signal q0_reg_0_i_1_n_2 : STD_LOGIC;
signal q0_reg_0_i_1_n_3 : STD_LOGIC;
signal q0_reg_0_i_20_n_0 : STD_LOGIC;
signal q0_reg_0_i_2_n_0 : STD_LOGIC;
signal q0_reg_0_i_2_n_1 : STD_LOGIC;
signal q0_reg_0_i_2_n_2 : STD_LOGIC;
signal q0_reg_0_i_2_n_3 : STD_LOGIC;
signal q0_reg_0_i_3_n_0 : STD_LOGIC;
signal q0_reg_0_i_3_n_1 : STD_LOGIC;
signal q0_reg_0_i_3_n_2 : STD_LOGIC;
signal q0_reg_0_i_3_n_3 : STD_LOGIC;
signal q0_reg_0_i_4_n_0 : STD_LOGIC;
signal q0_reg_0_i_5_n_0 : STD_LOGIC;
signal q0_reg_0_i_6_n_0 : STD_LOGIC;
signal q0_reg_0_i_7_n_0 : STD_LOGIC;
signal q0_reg_0_i_8_n_0 : STD_LOGIC;
signal q0_reg_0_i_9_n_0 : STD_LOGIC;
signal \rdata_data[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata_data[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[15]_i_3_n_0\ : STD_LOGIC;
signal \rdata_data[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata_data[9]_i_1_n_0\ : STD_LOGIC;
signal \^reset\ : STD_LOGIC;
signal rstate : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \rstate[0]_i_1_n_0\ : STD_LOGIC;
signal \rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal step_size_V : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \temp_V[0]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[0]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[12]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[4]_i_5_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_2_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_3_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_4_n_0\ : STD_LOGIC;
signal \temp_V[8]_i_5_n_0\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \temp_V_reg[8]_i_1_n_3\ : STD_LOGIC;
signal waddr0 : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
signal wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \wstate[1]_i_1_n_0\ : STD_LOGIC;
signal NLW_q0_reg_0_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_q0_reg_0_i_12_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \int_step_size_V[0]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_step_size_V[10]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_step_size_V[11]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_step_size_V[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_step_size_V[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_step_size_V[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_step_size_V[15]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_step_size_V[15]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_step_size_V[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \int_step_size_V[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_step_size_V[3]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_step_size_V[4]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_step_size_V[5]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_step_size_V[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_step_size_V[7]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_step_size_V[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_step_size_V[9]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \rdata_data[10]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rdata_data[11]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rdata_data[12]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rdata_data[13]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rdata_data[14]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rdata_data[15]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rdata_data[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rdata_data[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rdata_data[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rdata_data[5]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rdata_data[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rdata_data[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rdata_data[8]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rdata_data[9]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rstate[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_AXILiteS_ARREADY_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_AXILiteS_AWREADY_INST_0 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of s_axi_AXILiteS_BVALID_INST_0 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of s_axi_AXILiteS_RVALID_INST_0 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_AXILiteS_WREADY_INST_0 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wstate[1]_i_1\ : label is "soft_lutpair2";
begin
reset <= \^reset\;
s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^reset\
);
int_sine_sample_V_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFBFFFFAAAAAAAA"
)
port map (
I0 => Q(0),
I1 => s_axi_AXILiteS_ARADDR(2),
I2 => s_axi_AXILiteS_ARADDR(3),
I3 => int_sine_sample_V_ap_vld_i_2_n_0,
I4 => ar_hs,
I5 => int_sine_sample_V_ap_vld,
O => int_sine_sample_V_ap_vld_i_1_n_0
);
int_sine_sample_V_ap_vld_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => s_axi_AXILiteS_ARADDR(1),
I1 => s_axi_AXILiteS_ARADDR(4),
I2 => s_axi_AXILiteS_ARADDR(0),
O => int_sine_sample_V_ap_vld_i_2_n_0
);
int_sine_sample_V_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_sine_sample_V_ap_vld_i_1_n_0,
Q => int_sine_sample_V_ap_vld,
R => \^reset\
);
\int_step_size_V[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(0),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(0),
O => \or\(0)
);
\int_step_size_V[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(10),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(10),
O => \or\(10)
);
\int_step_size_V[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(11),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(11),
O => \or\(11)
);
\int_step_size_V[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(12),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(12),
O => \or\(12)
);
\int_step_size_V[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(13),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(13),
O => \or\(13)
);
\int_step_size_V[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(14),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(14),
O => \or\(14)
);
\int_step_size_V[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[2]\,
I2 => \waddr_reg_n_0_[1]\,
I3 => \int_step_size_V[15]_i_3_n_0\,
O => p_0_in
);
\int_step_size_V[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(15),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(15),
O => \or\(15)
);
\int_step_size_V[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \waddr_reg_n_0_[4]\,
I1 => \waddr_reg_n_0_[3]\,
I2 => s_axi_AXILiteS_WVALID,
I3 => wstate(0),
I4 => wstate(1),
O => \int_step_size_V[15]_i_3_n_0\
);
\int_step_size_V[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(1),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(1),
O => \or\(1)
);
\int_step_size_V[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(2),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(2),
O => \or\(2)
);
\int_step_size_V[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(3),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(3),
O => \or\(3)
);
\int_step_size_V[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(4),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(4),
O => \or\(4)
);
\int_step_size_V[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(5),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(5),
O => \or\(5)
);
\int_step_size_V[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(6),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(6),
O => \or\(6)
);
\int_step_size_V[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(7),
I1 => s_axi_AXILiteS_WSTRB(0),
I2 => step_size_V(7),
O => \or\(7)
);
\int_step_size_V[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(8),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(8),
O => \or\(8)
);
\int_step_size_V[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_AXILiteS_WDATA(9),
I1 => s_axi_AXILiteS_WSTRB(1),
I2 => step_size_V(9),
O => \or\(9)
);
\int_step_size_V_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(0),
Q => step_size_V(0),
R => '0'
);
\int_step_size_V_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(10),
Q => step_size_V(10),
R => '0'
);
\int_step_size_V_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(11),
Q => step_size_V(11),
R => '0'
);
\int_step_size_V_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(12),
Q => step_size_V(12),
R => '0'
);
\int_step_size_V_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(13),
Q => step_size_V(13),
R => '0'
);
\int_step_size_V_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(14),
Q => step_size_V(14),
R => '0'
);
\int_step_size_V_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(15),
Q => step_size_V(15),
R => '0'
);
\int_step_size_V_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(1),
Q => step_size_V(1),
R => '0'
);
\int_step_size_V_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(2),
Q => step_size_V(2),
R => '0'
);
\int_step_size_V_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(3),
Q => step_size_V(3),
R => '0'
);
\int_step_size_V_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(4),
Q => step_size_V(4),
R => '0'
);
\int_step_size_V_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(5),
Q => step_size_V(5),
R => '0'
);
\int_step_size_V_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(6),
Q => step_size_V(6),
R => '0'
);
\int_step_size_V_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(7),
Q => step_size_V(7),
R => '0'
);
\int_step_size_V_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(8),
Q => step_size_V(8),
R => '0'
);
\int_step_size_V_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => p_0_in,
D => \or\(9),
Q => step_size_V(9),
R => '0'
);
q0_reg_0_i_1: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_2_n_0,
CO(3) => NLW_q0_reg_0_i_1_CO_UNCONNECTED(3),
CO(2) => q0_reg_0_i_1_n_1,
CO(1) => q0_reg_0_i_1_n_2,
CO(0) => q0_reg_0_i_1_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => temp_V_reg(14 downto 12),
O(3 downto 0) => sel(11 downto 8),
S(3) => q0_reg_0_i_4_n_0,
S(2) => q0_reg_0_i_5_n_0,
S(1) => q0_reg_0_i_6_n_0,
S(0) => q0_reg_0_i_7_n_0
);
q0_reg_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(9),
I1 => step_size_V(9),
O => q0_reg_0_i_10_n_0
);
q0_reg_0_i_11: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(8),
I1 => step_size_V(8),
O => q0_reg_0_i_11_n_0
);
q0_reg_0_i_12: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => q0_reg_0_i_12_n_0,
CO(2) => q0_reg_0_i_12_n_1,
CO(1) => q0_reg_0_i_12_n_2,
CO(0) => q0_reg_0_i_12_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(3 downto 0),
O(3 downto 0) => NLW_q0_reg_0_i_12_O_UNCONNECTED(3 downto 0),
S(3) => q0_reg_0_i_17_n_0,
S(2) => q0_reg_0_i_18_n_0,
S(1) => q0_reg_0_i_19_n_0,
S(0) => q0_reg_0_i_20_n_0
);
q0_reg_0_i_13: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(7),
I1 => step_size_V(7),
O => q0_reg_0_i_13_n_0
);
q0_reg_0_i_14: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(6),
I1 => step_size_V(6),
O => q0_reg_0_i_14_n_0
);
q0_reg_0_i_15: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(5),
I1 => step_size_V(5),
O => q0_reg_0_i_15_n_0
);
q0_reg_0_i_16: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(4),
I1 => step_size_V(4),
O => q0_reg_0_i_16_n_0
);
q0_reg_0_i_17: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(3),
I1 => step_size_V(3),
O => q0_reg_0_i_17_n_0
);
q0_reg_0_i_18: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(2),
I1 => step_size_V(2),
O => q0_reg_0_i_18_n_0
);
q0_reg_0_i_19: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(1),
I1 => step_size_V(1),
O => q0_reg_0_i_19_n_0
);
q0_reg_0_i_2: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_3_n_0,
CO(3) => q0_reg_0_i_2_n_0,
CO(2) => q0_reg_0_i_2_n_1,
CO(1) => q0_reg_0_i_2_n_2,
CO(0) => q0_reg_0_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(11 downto 8),
O(3 downto 0) => sel(7 downto 4),
S(3) => q0_reg_0_i_8_n_0,
S(2) => q0_reg_0_i_9_n_0,
S(1) => q0_reg_0_i_10_n_0,
S(0) => q0_reg_0_i_11_n_0
);
q0_reg_0_i_20: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(0),
I1 => step_size_V(0),
O => q0_reg_0_i_20_n_0
);
q0_reg_0_i_3: unisim.vcomponents.CARRY4
port map (
CI => q0_reg_0_i_12_n_0,
CO(3) => q0_reg_0_i_3_n_0,
CO(2) => q0_reg_0_i_3_n_1,
CO(1) => q0_reg_0_i_3_n_2,
CO(0) => q0_reg_0_i_3_n_3,
CYINIT => '0',
DI(3 downto 0) => temp_V_reg(7 downto 4),
O(3 downto 0) => sel(3 downto 0),
S(3) => q0_reg_0_i_13_n_0,
S(2) => q0_reg_0_i_14_n_0,
S(1) => q0_reg_0_i_15_n_0,
S(0) => q0_reg_0_i_16_n_0
);
q0_reg_0_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(15),
I1 => step_size_V(15),
O => q0_reg_0_i_4_n_0
);
q0_reg_0_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(14),
I1 => step_size_V(14),
O => q0_reg_0_i_5_n_0
);
q0_reg_0_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(13),
I1 => step_size_V(13),
O => q0_reg_0_i_6_n_0
);
q0_reg_0_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(12),
I1 => step_size_V(12),
O => q0_reg_0_i_7_n_0
);
q0_reg_0_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(11),
I1 => step_size_V(11),
O => q0_reg_0_i_8_n_0
);
q0_reg_0_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(10),
I1 => step_size_V(10),
O => q0_reg_0_i_9_n_0
);
\rdata_data[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => \rdata_data[0]_i_2_n_0\,
I1 => s_axi_AXILiteS_ARADDR(0),
I2 => s_axi_AXILiteS_ARADDR(4),
I3 => s_axi_AXILiteS_ARADDR(1),
I4 => ar_hs,
I5 => \^s_axi_axilites_rdata\(0),
O => \rdata_data[0]_i_1_n_0\
);
\rdata_data[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => step_size_V(0),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => int_sine_sample_V_ap_vld,
I3 => s_axi_AXILiteS_ARADDR(2),
I4 => \out\(0),
O => \rdata_data[0]_i_2_n_0\
);
\rdata_data[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(10),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(10),
O => \rdata_data[10]_i_1_n_0\
);
\rdata_data[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(11),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(11),
O => \rdata_data[11]_i_1_n_0\
);
\rdata_data[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(12),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(12),
O => \rdata_data[12]_i_1_n_0\
);
\rdata_data[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(13),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(13),
O => \rdata_data[13]_i_1_n_0\
);
\rdata_data[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(14),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(14),
O => \rdata_data[14]_i_1_n_0\
);
\rdata_data[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0000"
)
port map (
I0 => s_axi_AXILiteS_ARADDR(1),
I1 => s_axi_AXILiteS_ARADDR(4),
I2 => s_axi_AXILiteS_ARADDR(0),
I3 => s_axi_AXILiteS_ARADDR(2),
I4 => ar_hs,
O => \rdata_data[15]_i_1_n_0\
);
\rdata_data[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => s_axi_AXILiteS_ARVALID,
I1 => rstate(2),
I2 => rstate(0),
O => ar_hs
);
\rdata_data[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(15),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(15),
O => \rdata_data[15]_i_3_n_0\
);
\rdata_data[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(1),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(1),
O => \rdata_data[1]_i_1_n_0\
);
\rdata_data[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(2),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(2),
O => \rdata_data[2]_i_1_n_0\
);
\rdata_data[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(3),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(3),
O => \rdata_data[3]_i_1_n_0\
);
\rdata_data[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(4),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(4),
O => \rdata_data[4]_i_1_n_0\
);
\rdata_data[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(5),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(5),
O => \rdata_data[5]_i_1_n_0\
);
\rdata_data[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(6),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(6),
O => \rdata_data[6]_i_1_n_0\
);
\rdata_data[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(7),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(7),
O => \rdata_data[7]_i_1_n_0\
);
\rdata_data[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(8),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(8),
O => \rdata_data[8]_i_1_n_0\
);
\rdata_data[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => step_size_V(9),
I1 => s_axi_AXILiteS_ARADDR(3),
I2 => \out\(9),
O => \rdata_data[9]_i_1_n_0\
);
\rdata_data_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata_data[0]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(0),
R => '0'
);
\rdata_data_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[10]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(10),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[11]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(11),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[12]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(12),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[13]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(13),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[14]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(14),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[15]_i_3_n_0\,
Q => \^s_axi_axilites_rdata\(15),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[1]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(1),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[2]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(2),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[3]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(3),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[4]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(4),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[5]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(5),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[6]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(6),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[7]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(7),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[8]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(8),
R => \rdata_data[15]_i_1_n_0\
);
\rdata_data_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata_data[9]_i_1_n_0\,
Q => \^s_axi_axilites_rdata\(9),
R => \rdata_data[15]_i_1_n_0\
);
\rstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F5CF"
)
port map (
I0 => s_axi_AXILiteS_ARVALID,
I1 => s_axi_AXILiteS_RREADY,
I2 => rstate(2),
I3 => rstate(0),
O => \rstate[0]_i_1_n_0\
);
\rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2604"
)
port map (
I0 => rstate(0),
I1 => rstate(2),
I2 => s_axi_AXILiteS_RREADY,
I3 => s_axi_AXILiteS_ARVALID,
O => \rstate[2]_i_1_n_0\
);
\rstate_reg[0]\: unisim.vcomponents.FDSE
port map (
C => ap_clk,
CE => '1',
D => \rstate[0]_i_1_n_0\,
Q => rstate(0),
S => \^reset\
);
\rstate_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rstate[2]_i_1_n_0\,
Q => rstate(2),
R => \^reset\
);
s_axi_AXILiteS_ARREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rstate(0),
I1 => rstate(2),
O => s_axi_AXILiteS_ARREADY
);
s_axi_AXILiteS_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => wstate(1),
I1 => wstate(0),
O => s_axi_AXILiteS_AWREADY
);
s_axi_AXILiteS_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wstate(1),
I1 => wstate(0),
O => s_axi_AXILiteS_BVALID
);
s_axi_AXILiteS_RVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rstate(2),
I1 => rstate(0),
O => s_axi_AXILiteS_RVALID
);
s_axi_AXILiteS_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wstate(0),
I1 => wstate(1),
O => s_axi_AXILiteS_WREADY
);
\temp_V[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(3),
I1 => temp_V_reg(3),
O => \temp_V[0]_i_2_n_0\
);
\temp_V[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(2),
I1 => temp_V_reg(2),
O => \temp_V[0]_i_3_n_0\
);
\temp_V[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(1),
I1 => temp_V_reg(1),
O => \temp_V[0]_i_4_n_0\
);
\temp_V[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(0),
I1 => temp_V_reg(0),
O => \temp_V[0]_i_5_n_0\
);
\temp_V[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => temp_V_reg(15),
I1 => step_size_V(15),
O => \temp_V[12]_i_2_n_0\
);
\temp_V[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(14),
I1 => temp_V_reg(14),
O => \temp_V[12]_i_3_n_0\
);
\temp_V[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(13),
I1 => temp_V_reg(13),
O => \temp_V[12]_i_4_n_0\
);
\temp_V[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(12),
I1 => temp_V_reg(12),
O => \temp_V[12]_i_5_n_0\
);
\temp_V[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(7),
I1 => temp_V_reg(7),
O => \temp_V[4]_i_2_n_0\
);
\temp_V[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(6),
I1 => temp_V_reg(6),
O => \temp_V[4]_i_3_n_0\
);
\temp_V[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(5),
I1 => temp_V_reg(5),
O => \temp_V[4]_i_4_n_0\
);
\temp_V[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(4),
I1 => temp_V_reg(4),
O => \temp_V[4]_i_5_n_0\
);
\temp_V[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(11),
I1 => temp_V_reg(11),
O => \temp_V[8]_i_2_n_0\
);
\temp_V[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(10),
I1 => temp_V_reg(10),
O => \temp_V[8]_i_3_n_0\
);
\temp_V[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(9),
I1 => temp_V_reg(9),
O => \temp_V[8]_i_4_n_0\
);
\temp_V[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => step_size_V(8),
I1 => temp_V_reg(8),
O => \temp_V[8]_i_5_n_0\
);
\temp_V_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \temp_V_reg[0]_i_1_n_0\,
CO(2) => \temp_V_reg[0]_i_1_n_1\,
CO(1) => \temp_V_reg[0]_i_1_n_2\,
CO(0) => \temp_V_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(3 downto 0),
O(3 downto 0) => O(3 downto 0),
S(3) => \temp_V[0]_i_2_n_0\,
S(2) => \temp_V[0]_i_3_n_0\,
S(1) => \temp_V[0]_i_4_n_0\,
S(0) => \temp_V[0]_i_5_n_0\
);
\temp_V_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[8]_i_1_n_0\,
CO(3) => \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \temp_V_reg[12]_i_1_n_1\,
CO(1) => \temp_V_reg[12]_i_1_n_2\,
CO(0) => \temp_V_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => step_size_V(14 downto 12),
O(3 downto 0) => \temp_V_reg[15]\(3 downto 0),
S(3) => \temp_V[12]_i_2_n_0\,
S(2) => \temp_V[12]_i_3_n_0\,
S(1) => \temp_V[12]_i_4_n_0\,
S(0) => \temp_V[12]_i_5_n_0\
);
\temp_V_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[0]_i_1_n_0\,
CO(3) => \temp_V_reg[4]_i_1_n_0\,
CO(2) => \temp_V_reg[4]_i_1_n_1\,
CO(1) => \temp_V_reg[4]_i_1_n_2\,
CO(0) => \temp_V_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(7 downto 4),
O(3 downto 0) => \temp_V_reg[7]\(3 downto 0),
S(3) => \temp_V[4]_i_2_n_0\,
S(2) => \temp_V[4]_i_3_n_0\,
S(1) => \temp_V[4]_i_4_n_0\,
S(0) => \temp_V[4]_i_5_n_0\
);
\temp_V_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \temp_V_reg[4]_i_1_n_0\,
CO(3) => \temp_V_reg[8]_i_1_n_0\,
CO(2) => \temp_V_reg[8]_i_1_n_1\,
CO(1) => \temp_V_reg[8]_i_1_n_2\,
CO(0) => \temp_V_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => step_size_V(11 downto 8),
O(3 downto 0) => \temp_V_reg[11]\(3 downto 0),
S(3) => \temp_V[8]_i_2_n_0\,
S(2) => \temp_V[8]_i_3_n_0\,
S(1) => \temp_V[8]_i_4_n_0\,
S(0) => \temp_V[8]_i_5_n_0\
);
\waddr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_AXILiteS_AWVALID,
I1 => wstate(0),
I2 => wstate(1),
O => waddr0
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr0,
D => s_axi_AXILiteS_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr0,
D => s_axi_AXILiteS_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr0,
D => s_axi_AXILiteS_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr0,
D => s_axi_AXILiteS_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr0,
D => s_axi_AXILiteS_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
\wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => s_axi_AXILiteS_AWVALID,
I1 => wstate(0),
I2 => s_axi_AXILiteS_WVALID,
I3 => wstate(1),
O => \wstate[0]_i_1_n_0\
);
\wstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5202"
)
port map (
I0 => wstate(1),
I1 => s_axi_AXILiteS_BREADY,
I2 => wstate(0),
I3 => s_axi_AXILiteS_WVALID,
O => \wstate[1]_i_1_n_0\
);
\wstate_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \wstate[0]_i_1_n_0\,
Q => wstate(0),
R => \^reset\
);
\wstate_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \wstate[1]_i_1_n_0\,
Q => wstate(1),
R => \^reset\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
sel : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is
signal NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_0_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 8 );
signal NLW_q0_reg_0_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_q0_reg_0_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_q0_reg_0_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_0_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_q0_reg_0_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_q0_reg_1_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 7 );
signal NLW_q0_reg_1_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_q0_reg_1_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_1_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_q0_reg_1_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_q0_reg_1_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_0 : label is "p1_d8";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of q0_reg_0 : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of q0_reg_0 : label is 65536;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of q0_reg_0 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of q0_reg_0 : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of q0_reg_0 : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of q0_reg_0 : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of q0_reg_0 : label is 8;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_1 : label is "p0_d7";
attribute METHODOLOGY_DRC_VIOS of q0_reg_1 : label is "";
attribute RTL_RAM_BITS of q0_reg_1 : label is 65536;
attribute RTL_RAM_NAME of q0_reg_1 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0";
attribute bram_addr_begin of q0_reg_1 : label is 0;
attribute bram_addr_end of q0_reg_1 : label is 4095;
attribute bram_slice_begin of q0_reg_1 : label is 9;
attribute bram_slice_end of q0_reg_1 : label is 15;
begin
q0_reg_0: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"07FF001FFC00FFE003FF001FF800FFC007FE007FF003FF003FF801FF801FF800",
INITP_01 => X"E0007FFE0007FFC001FFF0007FFC003FFC003FFC003FFC007FF800FFF001FFC0",
INITP_02 => X"E000000FFFFFE000007FFFF800007FFFE00007FFFC0001FFFE0001FFFC0007FF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000001FFFFFFFFF00000001FFFFFF",
INITP_04 => X"FFFFFF00000001FFFFFFFFF000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INITP_05 => X"FFC0007FFF0000FFFF00007FFFC0000FFFFC00003FFFFC00000FFFFFE000000F",
INITP_06 => X"07FF001FFE003FFC007FF8007FF8007FF8007FFC001FFF0007FFC000FFFC000F",
INITP_07 => X"003FF003FF003FF801FF801FFC00FFC007FE003FF001FF800FFE007FF001FFC0",
INITP_08 => X"F800FFE003FF001FFC00FFE007FF003FF801FF800FFC00FFC007FE007FE007FE",
INITP_09 => X"1FFF8001FFF8003FFE000FFF8003FFC003FFC003FFC003FF8007FF000FFE003F",
INITP_0A => X"1FFFFFF000001FFFFF800007FFFF80001FFFF80003FFFE0001FFFE0003FFF800",
INITP_0B => X"00000000000000000000000000001FFFFFFFFFFFE000000000FFFFFFFE000000",
INITP_0C => X"000000FFFFFFFE000000000FFFFFFFFFFFF00000000000000000000000000000",
INITP_0D => X"003FFF8000FFFF0000FFFF80003FFFF00003FFFFC00003FFFFF000001FFFFFF0",
INITP_0E => X"F800FFE001FFC003FF8007FF8007FF8007FF8003FFE000FFF8003FFF0003FFF0",
INITP_0F => X"FFC00FFC00FFC007FE007FE003FF003FF801FFC00FFE007FF001FF800FFE003F",
INIT_00 => X"0AF1D8BFA68D745B41280FF6DDC4AB92785F462D14FBE2C9AF967D644B321900",
INIT_01 => X"2C13FAE1C8AF967D644B321900E7CEB59C836A51371E05ECD3BAA1886F563D23",
INIT_02 => X"4B321900E7CEB59C846B52392007EED5BCA38A71583F260DF4DBC2A990775E45",
INIT_03 => X"634B321901E8CFB69E856C543B2209F1D8BFA68D755C432A11F9E0C7AE957C64",
INIT_04 => X"745C432B12FAE2C9B19880674F361E05EDD4BCA38B7259412810F7DEC6AD957C",
INIT_05 => X"7B634B331B03EBD3BBA28A725A422A11F9E1C9B09880684F371F06EED6BDA58C",
INIT_06 => X"776048301901E9D1BAA28A725A432B13FBE3CBB39B836C543C240CF4DCC4AC94",
INIT_07 => X"664F382009F2DAC3AC947D664E371F08F1D9C2AA937B644C341D05EED6BEA78F",
INIT_08 => X"462F1802EBD4BDA68F79624B341D06EFD8C1AA937C654E372008F1DAC3AC957D",
INIT_09 => X"15FEE8D2BCA68F79634C362009F3DCC6AF99836C553F2812FBE5CEB7A18A735D",
INIT_0A => X"D1BBA6907B654F39240EF8E2CDB7A18B755F49341E08F2DCC6B099836D57412B",
INIT_0B => X"79644F3A2510FBE6D1BCA7927D67523D2812FDE8D2BDA8927D68523D2712FCE7",
INIT_0C => X"0BF7E3CFBAA6927D6954402C1703EEDAC5B09C87735E4934200BF6E1CDB8A38E",
INIT_0D => X"86725F4B382411FDEAD6C2AF9B87735F4C382410FCE8D4C0AC9884705C48341F",
INIT_0E => X"E8D5C2B09D8A7765523F2C1906F3E0CDBAA794816E5A4734210EFAE7D4C0AD99",
INIT_0F => X"2F1D0BF9E8D6C4B2A08E7C6A574533210FFCEAD8C6B3A18E7C6A574532200DFA",
INIT_10 => X"5A4938281605F4E3D2C1B09F8D7C6B5A4837251403F1E0CEBCAB998876645241",
INIT_11 => X"69594938281808F8E8D8C7B7A796867665554434231302F1E1D0BFAF9E8D7C6B",
INIT_12 => X"58493A2B1C0DFEEEDFD0C1B1A293837464554536261607F7E7D8C8B8A8988879",
INIT_13 => X"281A0CFEF0E2D4C6B7A99B8C7E706153443627190AFBEDDECFC1B2A394857667",
INIT_14 => X"D8CBBEB1A496897C6F6254473A2C1F1204F7E9DCCEC0B3A597897C6E60524436",
INIT_15 => X"65594D4135291D1105F9EDE0D4C8BBAFA3968A7D7164574B3E3125180BFEF1E5",
INIT_16 => X"D0C5BAAFA4998E83786D62574C41352A1F1308FDF1E6DACFC3B7ACA094897D71",
INIT_17 => X"170D03FAF0E6DCD2C8BEB4AAA0968C82786D63594F443A2F251A1005FBF0E5DA",
INIT_18 => X"39312820170E06FDF4EBE2DAD1C8BFB6ADA39A91887F756C635950473D342A20",
INIT_19 => X"372F282119120A02FBF3ECE4DCD4CCC5BDB5ADA59D958C847C746C635B534A42",
INIT_1A => X"0E0802FCF5EFE9E2DCD6CFC9C2BBB5AEA7A19A938C857E777069625B544D453E",
INIT_1B => X"C0BBB6B1ACA7A19C97928C87827C77716C66615B55504A443E38332D27211B14",
INIT_1C => X"4A47433F3B37332F2B27231F1B17130E0A0601FDF8F4EFEBE6E1DDD8D3CECAC5",
INIT_1D => X"AEACA9A6A4A19E9C999693908D8A8784817E7B7874716E6A6764605D5955524E",
INIT_1E => X"EBE9E8E7E5E4E2E1DFDEDCDAD8D7D5D3D1CFCDCBC9C7C5C3C1BFBCBAB8B5B3B1",
INIT_1F => X"FFFFFFFFFFFFFFFEFEFEFDFDFCFCFBFBFAF9F9F8F7F6F5F4F3F2F1F0EFEEEDEC",
INIT_20 => X"EDEEEFF0F1F2F3F4F5F6F7F8F9F9FAFBFBFCFCFDFDFEFEFEFFFFFFFFFFFFFF00",
INIT_21 => X"B3B5B8BABCBFC1C3C5C7C9CBCDCFD1D3D5D7D8DADCDEDFE1E2E4E5E7E8E9EBEC",
INIT_22 => X"5255595D6064676A6E7174787B7E8184878A8D909396999C9EA1A4A6A9ACAEB1",
INIT_23 => X"CACED3D8DDE1E6EBEFF4F8FD01060A0E13171B1F23272B2F33373B3F43474A4E",
INIT_24 => X"1B21272D33383E444A50555B61666C71777C82878C92979CA1A7ACB1B6BBC0C5",
INIT_25 => X"454D545B626970777E858C939AA1A7AEB5BBC2C9CFD6DCE2E9EFF5FC02080E14",
INIT_26 => X"4A535B636C747C848C959DA5ADB5BDC5CCD4DCE4ECF3FB020A121921282F373E",
INIT_27 => X"2A343D475059636C757F88919AA3ADB6BFC8D1DAE2EBF4FD060E172028313942",
INIT_28 => X"E5F0FB05101A252F3A444F59636D78828C96A0AAB4BEC8D2DCE6F0FA030D1720",
INIT_29 => X"7D8994A0ACB7C3CFDAE6F1FD08131F2A35414C57626D78838E99A4AFBAC5D0DA",
INIT_2A => X"F1FE0B1825313E4B5764717D8A96A3AFBBC8D4E0EDF905111D2935414D596571",
INIT_2B => X"4452606E7C8997A5B3C0CEDCE9F704121F2C3A4754626F7C8996A4B1BECBD8E5",
INIT_2C => X"768594A3B2C1CFDEEDFB0A192736445361707E8C9BA9B7C6D4E2F0FE0C1A2836",
INIT_2D => X"8898A8B8C8D8E7F707162636455564748393A2B1C1D0DFEEFE0D1C2B3A495867",
INIT_2E => X"7C8D9EAFBFD0E1F102132334445565768696A7B7C7D8E8F80818283849596979",
INIT_2F => X"5264768899ABBCCEE0F103142537485A6B7C8D9FB0C1D2E3F405162838495A6B",
INIT_30 => X"0D203245576A7C8EA1B3C6D8EAFC0F213345576A7C8EA0B2C4D6E8F90B1D2F41",
INIT_31 => X"ADC0D4E7FA0E2134475A6E8194A7BACDE0F306192C3F5265778A9DB0C2D5E8FA",
INIT_32 => X"34485C708498ACC0D4E8FC1024384C5F73879BAFC2D6EAFD1124384B5F728699",
INIT_33 => X"A3B8CDE1F60B2034495E73879CB0C5DAEE03172C4054697D92A6BACFE3F70B1F",
INIT_34 => X"FC12273D52687D92A8BDD2E8FD12283D52677D92A7BCD1E6FB10253A4F64798E",
INIT_35 => X"41576D8399B0C6DCF2081E34495F758BA1B7CDE2F80E24394F657B90A6BBD1E7",
INIT_36 => X"738AA1B7CEE5FB12283F556C8399AFC6DCF30920364C63798FA6BCD2E8FE152B",
INIT_37 => X"95ACC3DAF10820374E657C93AAC1D8EF061D344B62798FA6BDD4EB02182F465D",
INIT_38 => X"A7BED6EE051D344C647B93AAC2D9F1081F374E667D94ACC3DAF20920384F667D",
INIT_39 => X"ACC4DCF40C243C546C839BB3CBE3FB132B435A728AA2BAD1E90119304860778F",
INIT_3A => X"A5BDD6EE061F374F688098B0C9E1F9112A425A728AA2BBD3EB031B334B637B94",
INIT_3B => X"95ADC6DEF710284159728BA3BCD4ED051E364F678098B1C9E2FA122B435C748C",
INIT_3C => X"7C95AEC7E0F9112A435C758DA6BFD8F109223B546C859EB6CFE80119324B637C",
INIT_3D => X"5E7790A9C2DBF40D263F58718AA3BCD5EE072039526B849CB5CEE70019324B64",
INIT_3E => X"3D566F88A1BAD3EC051E37516A839CB5CEE70019324B647D96AFC8E1FA132C45",
INIT_3F => X"19324B647D96AFC9E2FB142D465F7892ABC4DDF60F28415B748DA6BFD8F10A23",
INIT_40 => X"F50E274059728BA4BED7F009223B546D87A0B9D2EB041D365069829BB4CDE600",
INIT_41 => X"D3EC051E375069829BB4CDE6FF18314A637C95AEC8E1FA132C455E7790A9C2DC",
INIT_42 => X"B4CDE6FF18314A637B94ADC6DFF8112A435C758EA7C0D9F20B243D566F88A1BA",
INIT_43 => X"9CB4CDE6FE173049617A93ABC4DDF60E274059728AA3BCD5EE061F38516A839B",
INIT_44 => X"8BA3BCD4ED051D364E677F98B0C9E1FA122B435C748DA6BED7EF082139526A83",
INIT_45 => X"849CB4CCE4FC142C445D758DA5BDD5EE061E364F677F97B0C8E0F91129425A73",
INIT_46 => X"889FB7CFE6FE162E455D758DA5BCD4EC041C344C647C93ABC3DBF30B233B536B",
INIT_47 => X"99B0C7DFF60D253C536B8299B1C8E0F70E263D556C849BB3CBE2FA1129415870",
INIT_48 => X"B9D0E7FD142B425970869DB4CBE2F910273E556C839AB1C8DFF70E253C536A82",
INIT_49 => X"EA01172D435970869CB3C9DFF60C233950667C93AAC0D7ED041A31485E758CA2",
INIT_4A => X"2E44596F849AB0C6DBF1071D32485E748AA0B6CBE1F70D23394F667C92A8BED4",
INIT_4B => X"869BB0C5DAEF04192E43586D8298ADC2D7ED02172D42576D8297ADC2D8ED0318",
INIT_4C => X"F4081C3045596D8296ABBFD3E8FC11253A4F63788CA1B6CBDFF4091E32475C71",
INIT_4D => X"798DA0B4C7DBEE0215293D5064788CA0B3C7DBEF03172B3F53677B8FA3B7CBE0",
INIT_4E => X"172A3D4F6275889AADC0D3E6F90C1F3245586B7E91A5B8CBDEF105182B3F5266",
INIT_4F => X"D0E2F40617293B4D5F718395A8BACCDEF0031527394C5E718395A8BACDDFF205",
INIT_50 => X"A5B6C7D7E9FA0B1C2D3E4F60728394A5B7C8DAEBFC0E1F3143546677899BADBE",
INIT_51 => X"96A6B6C7D7E7F70717273848586979899AAABBCBDCECFD0E1E2F405061728394",
INIT_52 => X"A7B6C5D4E3F20111202F3E4E5D6C7C8B9BAABAC9D9E9F8081827374757677786",
INIT_53 => X"D7E5F3010F1D2B3948566473818F9EACBBC9D8E6F5041221303E4D5C6B7A8998",
INIT_54 => X"2734414E5B697683909DABB8C5D3E0EDFB081623313F4C5A687683919FADBBC9",
INIT_55 => X"9AA6B2BECAD6E2EEFA06121F2B3744505C6975828E9BA8B4C1CEDAE7F4010E1A",
INIT_56 => X"2F3A45505B66717C87929DA8B3BECAD5E0ECF7020E1925303C48535F6B76828E",
INIT_57 => X"E8F2FC050F19232D37414B555F69737D87929CA6B0BBC5D0DAE5EFFA040F1A25",
INIT_58 => X"C6CED7DFE8F1F9020B141D252E374049525C656E77808A939CA6AFB8C2CBD5DF",
INIT_59 => X"C8D0D7DEE6EDF5FD040C131B232B333A424A525A626A737B838B939CA4ACB5BD",
INIT_5A => X"F1F7FD030A10161D232930363D444A51585E656C737A81888F969DA4ABB2BAC1",
INIT_5B => X"3F44494E53585E63686D73787D83888E93999EA4AAAFB5BBC1C7CCD2D8DEE4EB",
INIT_5C => X"B5B8BCC0C4C8CCD0D4D8DCE0E4E8ECF1F5F9FE02070B1014191E22272C31353A",
INIT_5D => X"515356595B5E616366696C6F7275787B7E8184878B8E9195989B9FA2A6AAADB1",
INIT_5E => X"141617181A1B1D1E2021232527282A2C2E30323436383A3C3E404345474A4C4E",
INIT_5F => X"000000000000000101010202030304040506060708090A0B0C0D0E0F10111213",
INIT_60 => X"1211100F0E0D0C0B0A0908070606050404030302020101010000000000000000",
INIT_61 => X"4C4A474543403E3C3A38363432302E2C2A2827252321201E1D1B1A1817161413",
INIT_62 => X"ADAAA6A29F9B9895918E8B8784817E7B7875726F6C696663615E5B595653514E",
INIT_63 => X"35312C27221E1914100B0702FEF9F5F1ECE8E4E0DCD8D4D0CCC8C4C0BCB8B5B1",
INIT_64 => X"E4DED8D2CCC7C1BBB5AFAAA49E99938E88837D78736D68635E58534E49443F3A",
INIT_65 => X"BAB2ABA49D968F88817A736C655E58514A443D363029231D16100A03FDF7F1EB",
INIT_66 => X"B5ACA49C938B837B736A625A524A423A332B231B130C04FDF5EDE6DED7D0C8C1",
INIT_67 => X"D5CBC2B8AFA69C938A80776E655C524940372E251D140B02F9F1E8DFD7CEC6BD",
INIT_68 => X"1A0F04FAEFE5DAD0C5BBB0A69C92877D73695F554B41372D23190F05FCF2E8DF",
INIT_69 => X"82766B5F53483C3025190E02F7ECE0D5CABEB3A89D92877C71665B50453A2F25",
INIT_6A => X"0E01F4E7DACEC1B4A89B8E8275695C5044372B1F1206FAEEE2D6CABEB2A69A8E",
INIT_6B => X"BBAD9F918376685A4C3F31231608FBEDE0D3C5B8AB9D908376695B4E4134271A",
INIT_6C => X"897A6B5C4D3E30211204F5E6D8C9BBAC9E8F8173645648392B1D0F01F3E5D7C9",
INIT_6D => X"7767574737271808F8E9D9C9BAAA9B8B7C6C5D4E3E2F201101F2E3D4C5B6A798",
INIT_6E => X"83726150402F1E0EFDECDCCBBBAA9A897969584838271707F7E7D7C7B6A69686",
INIT_6F => X"AD9B8977665443311F0EFCEBDAC8B7A5948372604F3E2D1C0BFAE9D7C7B6A594",
INIT_70 => X"F2DFCDBAA89583715E4C39271503F0DECCBAA89583715F4D3B291706F4E2D0BE",
INIT_71 => X"523F2B1805F1DECBB8A5917E6B5845321F0CF9E6D3C0AD9A8875624F3D2A1705",
INIT_72 => X"CBB7A38F7B67533F2B1703EFDBC7B3A08C7864503D291502EEDBC7B4A08D7966",
INIT_73 => X"5C47321E09F4DFCBB6A18C78634F3A2511FCE8D3BFAB96826D5945301C08F4E0",
INIT_74 => X"03EDD8C2AD97826D57422D1702EDD7C2AD98826D58432E1904EFDAC5B09B8671",
INIT_75 => X"BEA8927C664F39230DF7E1CBB6A08A745E48321D07F1DBC6B09A846F59442E18",
INIT_76 => X"8C755E48311A04EDD7C0AA937C665039230CF6DFC9B39C867059432D1701EAD4",
INIT_77 => X"6A533C250EF7DFC8B19A836C553E2710F9E2CBB49D867059422B14FDE7D0B9A2",
INIT_78 => X"58412911FAE2CBB39B846C553D260EF7E0C8B199826B533C250DF6DFC7B09982",
INIT_79 => X"533B230BF3DBC3AB937C644C341C04ECD4BCA58D755D452E16FEE6CFB79F8870",
INIT_7A => X"5A422911F9E0C8B0977F674F361E06EED5BDA58D755D442C14FCE4CCB49C846B",
INIT_7B => X"6A52392108EFD7BEA68D745C432B12FAE1C9B0987F674E361D05EDD4BCA38B73",
INIT_7C => X"836A51381F06EED5BCA38A725940270EF6DDC4AB937A61493017FEE6CDB49C83",
INIT_7D => X"A1886F563D240BF2D9C0A78E755C432A11F8DFC6AD947B634A3118FFE6CDB49B",
INIT_7E => X"C2A990775E452C13FAE1C8AE957C634A3118FFE6CDB49B826950371E05ECD3BA",
INIT_7F => X"E6CDB49B826950361D04EBD2B9A0876D543B2209F0D7BEA48B725940270EF5DC",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => sel(11 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(15 downto 0) => B"1111111111111111",
CASCADEINA => '1',
CASCADEINB => '0',
CASCADEOUTA => NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => ap_clk,
CLKBWRCLK => '0',
DBITERR => NLW_q0_reg_0_DBITERR_UNCONNECTED,
DIADI(31 downto 0) => B"00000000000000000000000011111111",
DIBDI(31 downto 0) => B"11111111111111111111111111111111",
DIPADIP(3 downto 0) => B"0001",
DIPBDIP(3 downto 0) => B"1111",
DOADO(31 downto 8) => NLW_q0_reg_0_DOADO_UNCONNECTED(31 downto 8),
DOADO(7 downto 0) => \out\(7 downto 0),
DOBDO(31 downto 0) => NLW_q0_reg_0_DOBDO_UNCONNECTED(31 downto 0),
DOPADOP(3 downto 1) => NLW_q0_reg_0_DOPADOP_UNCONNECTED(3 downto 1),
DOPADOP(0) => \out\(8),
DOPBDOP(3 downto 0) => NLW_q0_reg_0_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_q0_reg_0_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => Q(0),
ENBWREN => '0',
INJECTDBITERR => NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_q0_reg_0_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => Q(1),
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => SR(0),
RSTREGB => '0',
SBITERR => NLW_q0_reg_0_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
q0_reg_1: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0101010101010101010101000000000000000000000000000000000000000000",
INIT_01 => X"0303020202020202020202020202020202020202020202010101010101010101",
INIT_02 => X"0404040404040404040404040404030303030303030303030303030303030303",
INIT_03 => X"0606060606050505050505050505050505050505050505050504040404040404",
INIT_04 => X"0707070707070707070707070707070706060606060606060606060606060606",
INIT_05 => X"0909090909090808080808080808080808080808080808080808080707070707",
INIT_06 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09090909090909090909090909090909",
INIT_07 => X"0C0C0C0C0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A",
INIT_08 => X"0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C",
INIT_09 => X"0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D",
INIT_0A => X"101010101010101010100F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"1111111111111111111111111111111111111010101010101010101010101010",
INIT_0C => X"1312121212121212121212121212121212121212121212121212111111111111",
INIT_0D => X"1414141414141413131313131313131313131313131313131313131313131313",
INIT_0E => X"1515151515151515151515151514141414141414141414141414141414141414",
INIT_0F => X"1616161616161616161616161616161616151515151515151515151515151515",
INIT_10 => X"1717171717171717171717171717171717171717171616161616161616161616",
INIT_11 => X"1818181818181818181818181818181818181818181818171717171717171717",
INIT_12 => X"1919191919191919191919191919191919191919191919181818181818181818",
INIT_13 => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1919191919191919191919",
INIT_14 => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A",
INIT_15 => X"1C1C1C1C1C1C1C1C1C1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B",
INIT_16 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C",
INIT_17 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1C1C1C1C",
INIT_18 => X"1E1E1E1E1E1E1E1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D",
INIT_19 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_1A => X"1F1F1F1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_1B => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1C => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1D => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1E => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_1F => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_20 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F20",
INIT_21 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_22 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_23 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_24 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F",
INIT_25 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F",
INIT_26 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E",
INIT_27 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1E1E1E1E1E1E1E1E",
INIT_28 => X"1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D",
INIT_29 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C",
INIT_2A => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C1C1C1C1C1C1C",
INIT_2B => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B",
INIT_2C => X"191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A",
INIT_2D => X"1818181818181818191919191919191919191919191919191919191919191919",
INIT_2E => X"1717171717171717181818181818181818181818181818181818181818181818",
INIT_2F => X"1616161616161616161617171717171717171717171717171717171717171717",
INIT_30 => X"1515151515151515151515151515161616161616161616161616161616161616",
INIT_31 => X"1414141414141414141414141414141414141515151515151515151515151515",
INIT_32 => X"1313131313131313131313131313131313131313131313131414141414141414",
INIT_33 => X"1111111111121212121212121212121212121212121212121212121212121313",
INIT_34 => X"1010101010101010101010101011111111111111111111111111111111111111",
INIT_35 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1010101010101010101010",
INIT_36 => X"0D0D0D0D0D0D0D0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F",
INIT_37 => X"0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D",
INIT_38 => X"0A0A0A0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C",
INIT_39 => X"0909090909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
INIT_3A => X"0707070708080808080808080808080808080808080808080809090909090909",
INIT_3B => X"0606060606060606060606060606060707070707070707070707070707070707",
INIT_3C => X"0404040404040505050505050505050505050505050505050505060606060606",
INIT_3D => X"0303030303030303030303030303030303040404040404040404040404040404",
INIT_3E => X"0101010101010101020202020202020202020202020202020202020202030303",
INIT_3F => X"0000000000000000000000000000000000000000010101010101010101010101",
INIT_40 => X"7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F00",
INIT_41 => X"7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E7E7E7E7E7E",
INIT_42 => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C",
INIT_43 => X"79797979797A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B",
INIT_44 => X"7878787878787878787878787878787879797979797979797979797979797979",
INIT_45 => X"7676767676767777777777777777777777777777777777777777777878787878",
INIT_46 => X"7575757575757575757575757575757576767676767676767676767676767676",
INIT_47 => X"7373737373747474747474747474747474747474747474747474747575757575",
INIT_48 => X"7272727272727272727272727272727373737373737373737373737373737373",
INIT_49 => X"7071717171717171717171717171717171717171717171717272727272727272",
INIT_4A => X"6F6F6F6F6F6F6F6F6F6F70707070707070707070707070707070707070707070",
INIT_4B => X"6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F",
INIT_4C => X"6C6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E",
INIT_4D => X"6B6B6B6B6B6B6B6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C",
INIT_4E => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B",
INIT_4F => X"69696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A6A6A",
INIT_50 => X"6868686868686868686868686868686868686868686969696969696969696969",
INIT_51 => X"6767676767676767676767676767676767676767676767686868686868686868",
INIT_52 => X"6666666666666666666666666666666666666666666666676767676767676767",
INIT_53 => X"6565656565656565656565656565656565656565656666666666666666666666",
INIT_54 => X"6464646464646464646464646464646464656565656565656565656565656565",
INIT_55 => X"6363636363636363636464646464646464646464646464646464646464646464",
INIT_56 => X"6363636363636363636363636363636363636363636363636363636363636363",
INIT_57 => X"6262626262626262626262626262626262626262626262626262626263636363",
INIT_58 => X"6161616161616162626262626262626262626262626262626262626262626262",
INIT_59 => X"6161616161616161616161616161616161616161616161616161616161616161",
INIT_5A => X"6060606161616161616161616161616161616161616161616161616161616161",
INIT_5B => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5C => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5D => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5E => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_5F => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_60 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_61 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_62 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_63 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_64 => X"6060606060606060606060606060606060606060606060606060606060606060",
INIT_65 => X"6161616161616161616161616161616161616161616161616161616160606060",
INIT_66 => X"6161616161616161616161616161616161616161616161616161616161616161",
INIT_67 => X"6262626262626262626262626262626262626262626262626161616161616161",
INIT_68 => X"6363636262626262626262626262626262626262626262626262626262626262",
INIT_69 => X"6363636363636363636363636363636363636363636363636363636363636363",
INIT_6A => X"6464646464646464646464646464646464646464646463636363636363636363",
INIT_6B => X"6565656565656565656565656565646464646464646464646464646464646464",
INIT_6C => X"6666666666666666666665656565656565656565656565656565656565656565",
INIT_6D => X"6767676767676767666666666666666666666666666666666666666666666666",
INIT_6E => X"6868686868686868676767676767676767676767676767676767676767676767",
INIT_6F => X"6969696969696969696968686868686868686868686868686868686868686868",
INIT_70 => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6A696969696969696969696969696969696969",
INIT_71 => X"6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6A6A6A6A6A6A6A6A6A6A6A6A6A6A",
INIT_72 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6B6B6B6B6B6B6B6B",
INIT_73 => X"6E6E6E6E6E6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6C6C",
INIT_74 => X"6F6F6F6F6F6F6F6F6F6F6F6F6F6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E",
INIT_75 => X"7070707070707070707070707070707070707070706F6F6F6F6F6F6F6F6F6F6F",
INIT_76 => X"7272727272727271717171717171717171717171717171717171717171717070",
INIT_77 => X"7373737373737373737373737373737372727272727272727272727272727272",
INIT_78 => X"7575757574747474747474747474747474747474747474747474737373737373",
INIT_79 => X"7676767676767676767676767676767575757575757575757575757575757575",
INIT_7A => X"7878787877777777777777777777777777777777777777777776767676767676",
INIT_7B => X"7979797979797979797979797979797878787878787878787878787878787878",
INIT_7C => X"7B7B7B7B7B7B7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A797979797979",
INIT_7D => X"7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B",
INIT_7E => X"7E7E7E7E7E7E7E7E7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7C7C7C",
INIT_7F => X"7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7E7E7E7E7E7E7E7E7E7E7E7E",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => sel(11 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(15 downto 0) => B"1111111111111111",
CASCADEINA => '1',
CASCADEINB => '0',
CASCADEOUTA => NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => ap_clk,
CLKBWRCLK => '0',
DBITERR => NLW_q0_reg_1_DBITERR_UNCONNECTED,
DIADI(31 downto 0) => B"00000000000000000000000001111111",
DIBDI(31 downto 0) => B"11111111111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"1111",
DOADO(31 downto 7) => NLW_q0_reg_1_DOADO_UNCONNECTED(31 downto 7),
DOADO(6 downto 0) => \out\(15 downto 9),
DOBDO(31 downto 0) => NLW_q0_reg_1_DOBDO_UNCONNECTED(31 downto 0),
DOPADOP(3 downto 0) => NLW_q0_reg_1_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_q0_reg_1_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_q0_reg_1_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => Q(0),
ENBWREN => '0',
INJECTDBITERR => NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_q0_reg_1_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => Q(1),
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => SR(0),
RSTREGB => '0',
SBITERR => NLW_q0_reg_1_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
sel : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is
begin
nco_sine_lut_V_rom_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom
port map (
Q(1 downto 0) => Q(1 downto 0),
SR(0) => SR(0),
ap_clk => ap_clk,
\out\(15 downto 0) => \out\(15 downto 0),
sel(11 downto 0) => sel(11 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is
port (
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer;
attribute C_S_AXI_AXILITES_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 6;
attribute C_S_AXI_AXILITES_DATA_WIDTH : integer;
attribute C_S_AXI_AXILITES_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 32;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is
signal \<const0>\ : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 to 1 );
signal ce0 : STD_LOGIC;
signal int_sine_sample_V : STD_LOGIC_VECTOR ( 15 downto 0 );
signal nco_AXILiteS_s_axi_U_n_10 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_11 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_12 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_13 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_14 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_15 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_16 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_17 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_18 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_3 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_4 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_5 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_6 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_7 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_8 : STD_LOGIC;
signal nco_AXILiteS_s_axi_U_n_9 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sel : STD_LOGIC_VECTOR ( 11 downto 0 );
signal sine_sample_V_ap_vld : STD_LOGIC;
signal temp_V_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
begin
s_axi_AXILiteS_BRESP(1) <= \<const0>\;
s_axi_AXILiteS_BRESP(0) <= \<const0>\;
s_axi_AXILiteS_RDATA(31) <= \<const0>\;
s_axi_AXILiteS_RDATA(30) <= \<const0>\;
s_axi_AXILiteS_RDATA(29) <= \<const0>\;
s_axi_AXILiteS_RDATA(28) <= \<const0>\;
s_axi_AXILiteS_RDATA(27) <= \<const0>\;
s_axi_AXILiteS_RDATA(26) <= \<const0>\;
s_axi_AXILiteS_RDATA(25) <= \<const0>\;
s_axi_AXILiteS_RDATA(24) <= \<const0>\;
s_axi_AXILiteS_RDATA(23) <= \<const0>\;
s_axi_AXILiteS_RDATA(22) <= \<const0>\;
s_axi_AXILiteS_RDATA(21) <= \<const0>\;
s_axi_AXILiteS_RDATA(20) <= \<const0>\;
s_axi_AXILiteS_RDATA(19) <= \<const0>\;
s_axi_AXILiteS_RDATA(18) <= \<const0>\;
s_axi_AXILiteS_RDATA(17) <= \<const0>\;
s_axi_AXILiteS_RDATA(16) <= \<const0>\;
s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0);
s_axi_AXILiteS_RRESP(1) <= \<const0>\;
s_axi_AXILiteS_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\ap_CS_fsm[1]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sine_sample_V_ap_vld,
O => ap_NS_fsm(1)
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => sine_sample_V_ap_vld,
Q => ce0,
S => reset
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => sine_sample_V_ap_vld,
R => reset
);
nco_AXILiteS_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi
port map (
O(3) => nco_AXILiteS_s_axi_U_n_3,
O(2) => nco_AXILiteS_s_axi_U_n_4,
O(1) => nco_AXILiteS_s_axi_U_n_5,
O(0) => nco_AXILiteS_s_axi_U_n_6,
Q(0) => sine_sample_V_ap_vld,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\out\(15 downto 0) => int_sine_sample_V(15 downto 0),
reset => reset,
s_axi_AXILiteS_ARADDR(4 downto 0) => s_axi_AXILiteS_ARADDR(4 downto 0),
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_AWADDR(4 downto 0) => s_axi_AXILiteS_AWADDR(4 downto 0),
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_RDATA(15 downto 0) => \^s_axi_axilites_rdata\(15 downto 0),
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_WDATA(15 downto 0) => s_axi_AXILiteS_WDATA(15 downto 0),
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WSTRB(1 downto 0) => s_axi_AXILiteS_WSTRB(1 downto 0),
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID,
sel(11 downto 0) => sel(11 downto 0),
temp_V_reg(15 downto 0) => temp_V_reg(15 downto 0),
\temp_V_reg[11]\(3) => nco_AXILiteS_s_axi_U_n_11,
\temp_V_reg[11]\(2) => nco_AXILiteS_s_axi_U_n_12,
\temp_V_reg[11]\(1) => nco_AXILiteS_s_axi_U_n_13,
\temp_V_reg[11]\(0) => nco_AXILiteS_s_axi_U_n_14,
\temp_V_reg[15]\(3) => nco_AXILiteS_s_axi_U_n_15,
\temp_V_reg[15]\(2) => nco_AXILiteS_s_axi_U_n_16,
\temp_V_reg[15]\(1) => nco_AXILiteS_s_axi_U_n_17,
\temp_V_reg[15]\(0) => nco_AXILiteS_s_axi_U_n_18,
\temp_V_reg[7]\(3) => nco_AXILiteS_s_axi_U_n_7,
\temp_V_reg[7]\(2) => nco_AXILiteS_s_axi_U_n_8,
\temp_V_reg[7]\(1) => nco_AXILiteS_s_axi_U_n_9,
\temp_V_reg[7]\(0) => nco_AXILiteS_s_axi_U_n_10
);
sine_lut_V_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V
port map (
Q(1) => sine_sample_V_ap_vld,
Q(0) => ce0,
SR(0) => reset,
ap_clk => ap_clk,
\out\(15 downto 0) => int_sine_sample_V(15 downto 0),
sel(11 downto 0) => sel(11 downto 0)
);
\temp_V_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_6,
Q => temp_V_reg(0),
R => '0'
);
\temp_V_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_12,
Q => temp_V_reg(10),
R => '0'
);
\temp_V_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_11,
Q => temp_V_reg(11),
R => '0'
);
\temp_V_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_18,
Q => temp_V_reg(12),
R => '0'
);
\temp_V_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_17,
Q => temp_V_reg(13),
R => '0'
);
\temp_V_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_16,
Q => temp_V_reg(14),
R => '0'
);
\temp_V_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_15,
Q => temp_V_reg(15),
R => '0'
);
\temp_V_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_5,
Q => temp_V_reg(1),
R => '0'
);
\temp_V_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_4,
Q => temp_V_reg(2),
R => '0'
);
\temp_V_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_3,
Q => temp_V_reg(3),
R => '0'
);
\temp_V_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_10,
Q => temp_V_reg(4),
R => '0'
);
\temp_V_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_9,
Q => temp_V_reg(5),
R => '0'
);
\temp_V_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_8,
Q => temp_V_reg(6),
R => '0'
);
\temp_V_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_7,
Q => temp_V_reg(7),
R => '0'
);
\temp_V_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_14,
Q => temp_V_reg(8),
R => '0'
);
\temp_V_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ce0,
D => nco_AXILiteS_s_axi_U_n_13,
Q => temp_V_reg(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_nco_0_0,nco,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "nco,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer;
attribute C_S_AXI_AXILITES_ADDR_WIDTH of U0 : label is 6;
attribute C_S_AXI_AXILITES_DATA_WIDTH : integer;
attribute C_S_AXI_AXILITES_DATA_WIDTH of U0 : label is 32;
attribute x_interface_info : string;
attribute x_interface_info of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_AXILiteS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute x_interface_parameter of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute x_interface_info of s_axi_AXILiteS_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY";
attribute x_interface_info of s_axi_AXILiteS_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID";
attribute x_interface_info of s_axi_AXILiteS_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY";
attribute x_interface_info of s_axi_AXILiteS_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID";
attribute x_interface_info of s_axi_AXILiteS_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY";
attribute x_interface_info of s_axi_AXILiteS_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID";
attribute x_interface_info of s_axi_AXILiteS_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY";
attribute x_interface_info of s_axi_AXILiteS_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID";
attribute x_interface_info of s_axi_AXILiteS_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY";
attribute x_interface_info of s_axi_AXILiteS_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID";
attribute x_interface_info of s_axi_AXILiteS_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR";
attribute x_interface_info of s_axi_AXILiteS_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR";
attribute x_interface_parameter of s_axi_AXILiteS_AWADDR : signal is "XIL_INTERFACENAME s_axi_AXILiteS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_AXILiteS_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP";
attribute x_interface_info of s_axi_AXILiteS_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA";
attribute x_interface_info of s_axi_AXILiteS_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP";
attribute x_interface_info of s_axi_AXILiteS_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA";
attribute x_interface_info of s_axi_AXILiteS_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
s_axi_AXILiteS_ARADDR(5 downto 0) => s_axi_AXILiteS_ARADDR(5 downto 0),
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_AWADDR(5 downto 0) => s_axi_AXILiteS_AWADDR(5 downto 0),
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP(1 downto 0) => s_axi_AXILiteS_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => s_axi_AXILiteS_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RRESP(1 downto 0) => s_axi_AXILiteS_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => s_axi_AXILiteS_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => s_axi_AXILiteS_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID
);
end STRUCTURE;
| mit | 951360bda6ad61fa539dad762f0c91bb | 0.630065 | 2.526011 | false | false | false | false |
Piasy/THCO-MIPS-CPU | src/MUX_4.vhd | 2 | 1,594 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:32:35 11/22/2013
-- Design Name:
-- Module Name: MUX_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_4 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (1 downto 0) := "00";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_4;
architecture Behavioral of MUX_4 is
begin
process (SRC_1, SRC_2, SRC_3, SRC_4, SELEC)
begin
case SELEC is
when "00" =>
OUTPUT <= SRC_1;
when "01" =>
OUTPUT <= SRC_2;
when "10" =>
OUTPUT <= SRC_3;
when "11" =>
OUTPUT <= SRC_4;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
| apache-2.0 | ce065db1487d1fb0c5d911d03a8076b8 | 0.558971 | 3.465217 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 330,319 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:41 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 5bc70d0cf4a28242208a6d6f7bb05a9d | 0.545279 | 2.566402 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/pps.vhd | 1 | 746 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pps is
port(
clk : in std_logic;
pps : in std_logic;
pps_count : out std_logic_vector(31 downto 0);
pps_count_stb : out std_logic;
pps_count_ack : in std_logic);
end entity pps;
architecture rtl of pps is
signal count : std_logic_vector(31 downto 0);
signal pps_d, pps_d1, pps_d2 : std_logic;
begin
process
begin
wait until rising_edge(clk);
pps_d <= pps;
pps_d1 <= pps_d;
pps_d2 <= pps_d1;
if pps_d1 = '1' and pps_d2 = '0' then
count <= (others => '0');
pps_count <= count;
else
count <= std_logic_vector(unsigned(count) + 1);
end if;
end process;
pps_count_stb <= '1';
end rtl;
| mit | 72b70ac3eea5edfd214234273ded0e49 | 0.600536 | 2.902724 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430_fpga.vhd | 1 | 17,339 | ------------------------------------------------------------------------------
-- Copyright (C) 2011 Authors
--
-- This source file may be used and distributed without restriction provided
-- that this copyright statement is not removed from the file and that any
-- derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
-- License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this source; if not, write to the Free Software Foundation,
-- Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
------------------------------------------------------------------------------
--
-- *File Name: fpgaMSP430_fpga.v
--
-- *Module Description:
-- fpgaMSP430 FPGA Top-level for the DE0 Nano Soc
--
-- *Author(s):
-- - Olivier Girard, [email protected]
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use work.fmsp430_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
use work.fpga_package.all;
entity fmsp430_fpga is
port (
-- USER CLOCKS
FPGA_CLK : in std_logic;
PIN_RESET_N : in std_logic;
-- USER INTERFACE (FPGA)
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(3 downto 0);
LED : out std_logic_vector(7 downto 0);
PIN_INCLK : in std_logic;
PIN_TACLK : in std_logic;
-- TIMER INTERFACE (FPGA)
PIN_CCIXA : in std_logic_vector(2 downto 0);
PIN_CCIXB : in std_logic_vector(2 downto 0);
PIN_TAOUT : out std_logic_vector(2 downto 0);
-- I2C DEBUG INTERFACE
PIN_SCL : inout std_logic;
PIN_SDA : inout std_logic
);
end entity fmsp430_fpga;
architecture RTL of fmsp430_fpga is
constant INST_NR : integer := 0; -- Current fmsp instance number (for multicore systems)
constant TOTAL_NR : integer := 0; -- Total number of fmsp instances-1 (for multicore systems)
constant PMEM_SIZE : integer := 16384; -- Program Memory Size
constant DMEM_SIZE : integer := 16384; -- Data Memory Size
constant PER_SIZE : integer := 16384; -- Peripheral Memory Size
constant MULTIPLIER : boolean := true; -- Include/Exclude Hardware Multiplier
constant USER_VERSION : integer := 0; -- Custom user version number
constant DEBUG_EN : boolean := true; -- Include/Exclude Serial Debug interface
constant WATCHDOG : boolean := true; -- Include/Exclude Watchdog timer
constant CPUOFF_EN : boolean := false; -- Wakeup condition from DMA interface
constant DMA_IF_EN : boolean := true; -- Include/Exclude DMA interface support
constant NMI_EN : boolean := true; -- Include/Exclude Non-Maskable-Interrupt support
constant IRQ_NR : integer := 16; -- Number of IRQs
constant SYNC_NMI_EN : boolean := true; --
constant SYNC_CPU_EN : boolean := true; --
constant SYNC_DBG_EN : boolean := true; --
constant SYNC_DBG_UART_RXD : boolean := true; -- Synchronize RXD inputs
constant DBG_I2C_BROADCAST_EN : boolean := true; -- Enable the I2C broadcast address
constant DBG_RST_BRK_EN : boolean := true; -- CPU break on PUC reset
constant DBG_HWBRK_0_EN : boolean := false; -- Include hardware breakpoints unit
constant DBG_HWBRK_1_EN : boolean := false; -- Include hardware breakpoints unit
constant DBG_HWBRK_2_EN : boolean := false; -- Include hardware breakpoints unit
constant DBG_HWBRK_3_EN : boolean := false; -- Include hardware breakpoints unit
constant DBG_HWBRK_RANGE : boolean := false; -- Enable/Disable the hardware breakpoint RANGE mode
constant DBG_UART : boolean := false; -- Enable UART (8N1) debug interface
constant DBG_UART_AUTO_SYNC : boolean := true; -- Debug UART interface auto data synchronization
constant DBG_UART_BAUD : integer := 9600; -- Debug UART interface data rate
constant DBG_DCO_FREQ : integer := 20000000; -- Debug mclk frequency
constant DBG_I2C : boolean := true; -- Enable I2C debug interface
--=============================================================================
-- 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
--=============================================================================
-- mclk Program memory bus
signal pmem_addr : std_logic_vector(f_log2(pMEM_SIZE)-2 downto 0);
signal pmem_dout : std_logic_vector(15 downto 0);
signal pmem_din : std_logic_vector(15 downto 0);
signal pmem_cen : std_logic;
signal pmem_wen : std_logic_vector(1 downto 0);
-- mclk Data memory bus
signal dmem_addr : std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0);
signal dmem_dout : std_logic_vector(15 downto 0);
signal dmem_din : std_logic_vector(15 downto 0);
signal dmem_cen : std_logic;
signal dmem_wen : std_logic_vector(1 downto 0);
-- mclk Peripheral memory bus
signal per_addr : std_logic_vector(13 downto 0);
signal per_dout : std_logic_vector(15 downto 0);
signal per_din : std_logic_vector(15 downto 0);
signal per_en : std_logic;
signal per_we : std_logic_vector(1 downto 0);
-- fpgaMSP430 IRQs
signal nmi : std_logic;
signal irq_bus : std_logic_vector(IRQ_NR-3 downto 0);
signal irq_acc : std_logic_vector(IRQ_NR-3 downto 0);
-- fpgaMSP430 debug interface
signal dbg_freeze : std_logic;
signal dbg_i2c_addr : std_logic_vector(6 downto 0);
signal dbg_i2c_broadcast : std_logic_vector(6 downto 0);
signal dbg_i2c_scl : std_logic;
signal dbg_i2c_sda_in : std_logic;
signal dbg_i2c_sda_out : std_logic;
signal dbg_uart_txd : std_logic;
signal dbg_uart_rxd : std_logic;
-- fpgaMSP430 clocks and resets
signal mclk : std_logic;
signal lfxt_clk : std_logic;
signal aclk_en : std_logic;
signal smclk_en : std_logic;
signal reset_n : std_logic;
signal puc_rst : std_logic;
signal mrst : std_logic;
-- LED / KEY / SW
signal irq_key : std_logic;
signal irq_sw : std_logic;
signal per_dout_led_key_sw : std_logic_vector(15 downto 0);
-- Timer A
signal irq_ta0 : std_logic;
signal irq_ta1 : std_logic;
signal per_dout_tA : std_logic_vector(15 downto 0);
signal reset_in_n : std_logic;
signal reset_dly_chain : std_logic_vector(7 downto 0);
signal lfxt_clk_cnt : unsigned(8 downto 0);
signal ta_outx : std_logic_vector(2 downto 0);
signal ta_outx_en : std_logic_vector(2 downto 0);
begin
--=============================================================================
-- 2) CLOCK AND RESET GENERATION
--=============================================================================
mclk <= FPGA_CLK;
reset_in_n <= PIN_RESET_N;
-- Release system reset a few clock cyles after the FPGA power-on-reset
RESET_DELAY : process (mclk,reset_in_n)
begin
if (reset_in_n = '0') then
reset_dly_chain <= x"00";
elsif rising_edge(mclk) then
reset_dly_chain <= '1' & reset_dly_chain(7 downto 1);
end if;
end process RESET_DELAY;
reset_n <= reset_dly_chain(0);
-- Generate a slow reference clock LFXT_CLK (10us period)
LFXT_CLK_COUNTER : process (mclk,reset_n)
begin
if (reset_n = '0') then
lfxt_clk_cnt <= "000000000";
elsif rising_edge(mclk) then
lfxt_clk_cnt <= lfxt_clk_cnt + 1;
end if;
end process LFXT_CLK_COUNTER;
lfxt_clk <= lfxt_clk_cnt(8);
--=============================================================================
-- 3) fpgaMSP430
--=============================================================================
fmsp430_0 : fmsp430
generic map(
INST_NR => INST_NR,
TOTAL_NR => TOTAL_NR,
PMEM_SIZE => PMEM_SIZE,
DMEM_SIZE => DMEM_SIZE,
PER_SIZE => PER_SIZE,
MULTIPLIER => MULTIPLIER,
USER_VERSION => USER_VERSION,
DEBUG_EN => DEBUG_EN,
WATCHDOG => WATCHDOG,
DMA_IF_EN => DMA_IF_EN,
NMI_EN => NMI_EN,
IRQ_NR => IRQ_NR,
SYNC_NMI_EN => SYNC_NMI_EN,
SYNC_CPU_EN => SYNC_CPU_EN,
SYNC_DBG_EN => SYNC_DBG_EN,
SYNC_DBG_UART_RXD => SYNC_DBG_UART_RXD, -- Synchronize RXD inputs
DBG_UART => DBG_UART, -- Enable UART (8N1) debug interface
DBG_I2C => DBG_I2C, -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN => DBG_I2C_BROADCAST_EN, -- Enable the I2C broadcast address
DBG_RST_BRK_EN => DBG_RST_BRK_EN, -- CPU break on PUC reset
DBG_HWBRK_0_EN => DBG_HWBRK_0_EN, -- Include hardware breakpoints unit
DBG_HWBRK_1_EN => DBG_HWBRK_1_EN, -- Include hardware breakpoints unit
DBG_HWBRK_2_EN => DBG_HWBRK_2_EN, -- Include hardware breakpoints unit
DBG_HWBRK_3_EN => DBG_HWBRK_3_EN, -- Include hardware breakpoints unit
DBG_HWBRK_RANGE => DBG_HWBRK_RANGE, -- Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC => DBG_UART_AUTO_SYNC, -- Debug UART interface auto data synchronization
DBG_UART_BAUD => DBG_UART_BAUD, -- Debug UART interface data rate
DBG_DCO_FREQ => DBG_DCO_FREQ -- Debug mclk frequency
)
port map(
mclk => mclk, -- Main system clock
-- INPUTs
lfxt_clk => lfxt_clk, -- Low frequency oscillator (typ 32kHz)
reset_n => reset_n, -- Reset Pin (low active, asynchronous and non-glitchy)
cpu_en => '1', -- Enable CPU code execution (asynchronous and non-glitchy)
nmi => nmi, -- Non-maskable interrupt (asynchronous)
-- Debug interface
dbg_en => '1', -- Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_sda_out => dbg_i2c_sda_out, -- Debug interface: I2C SDA OUT
dbg_i2c_addr => dbg_i2c_addr, -- Debug interface: I2C Address
dbg_i2c_broadcast => dbg_i2c_broadcast, -- Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl => dbg_i2c_scl, -- Debug interface: I2C SCL
dbg_i2c_sda_in => dbg_i2c_sda_in, -- Debug interface: I2C SDA IN
dbg_uart_rxd => dbg_uart_rxd, -- Debug interface: UART RXD (asynchronous)
dbg_uart_txd => dbg_uart_txd, -- Debug interface: UART TXD
-- DMA access
dma_addr => "000000000000000", -- Direct Memory Access address
dma_dout => open, -- Direct Memory Access data output
dma_din => x"0000", -- Direct Memory Access data input
dma_we => "00", -- Direct Memory Access write byte enable (high active)
dma_en => '0', -- Direct Memory Access enable (high active)
dma_priority => '0', -- Direct Memory Access priority (0:low / 1:high)
dma_ready => open, -- Direct Memory Access is complete
dma_resp => open, -- Direct Memory Access response (0:Okay / 1:Error)
-- Data memory
dmem_addr => dmem_addr, -- Data Memory address
dmem_dout => dmem_dout, -- Data Memory data output
dmem_din => dmem_din, -- Data Memory data input
dmem_wen => dmem_wen, -- Data Memory write enable (low active)
dmem_cen => dmem_cen, -- Data Memory chip enable (low active)
-- Program memory
pmem_addr => pmem_addr, -- Program Memory address
pmem_dout => pmem_dout, -- Program Memory data output
pmem_din => pmem_din, -- Program Memory data input (optional)
pmem_wen => pmem_wen, -- Program Memory write enable (low active) (optional)
pmem_cen => pmem_cen, -- Program Memory chip enable (low active)
-- Peripheral interface
per_irq => irq_bus, -- Maskable interrupts
per_irq_acc => irq_acc, -- Interrupt request accepted (one-hot signal)
per_rst => puc_rst, -- Main system reset
per_freeze => dbg_freeze, -- Freeze peripherals
per_aclk_en => aclk_en, -- FPGA ONLY: ACLK enable
per_smclk_en => smclk_en, -- FPGA ONLY: SMCLK enable
-- Peripheral memory
per_addr => per_addr, -- Peripheral address
per_dout => per_dout, -- Peripheral data output
per_din => per_din, -- Peripheral data input
per_we => per_we, -- Peripheral write enable (high active)
per_en => per_en -- Peripheral enable (high active)
);
--=============================================================================
-- 4) fpgaMSP430 PERIPHERALS
--=============================================================================
-------------------------------
-- LED / KEY / SW interface
-------------------------------
de0_nano_soc_led_key_sw_0 : fmsp_de0_nano_soc_led_key_sw
port map(
-- INPUTs
mclk => mclk, -- Main system clock
puc_rst => puc_rst, -- Main system reset
key => KEY, -- key/button inputs
sw => SW, -- switches inputs
per_addr => per_addr, -- Peripheral address
per_din => per_din, -- Peripheral data input
per_en => per_en, -- Peripheral enable (high active)
per_we => per_we, -- Peripheral write enable (high active)
-- OUTPUTs
irq_key => irq_key, -- Key/Button interrupt
irq_sw => irq_sw, -- Switch interrupt
led => LED, -- LED output control
per_dout => per_dout_led_key_sw -- Peripheral data output
);
-------------------------------
-- Timer A
-------------------------------
timerA_0 : fmsp_timerA
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- INPUTs
aclk_en => aclk_en, -- ACLK enable (from CPU)
smclk_en => smclk_en, -- SMCLK enable (from CPU)
dbg_freeze => dbg_freeze, -- Freeze Timer A counter
inclk => PIN_INCLK, -- INCLK external timer clock (SLOW)
taclk => PIN_TACLK, -- TACLK external timer clock (SLOW)
irq_ta0_acc => irq_acc(9), -- Interrupt request TACCR0 accepted
per_addr => per_addr, -- Peripheral address
per_din => per_din, -- Peripheral data input
per_en => per_en, -- Peripheral enable (high active)
per_we => per_we, -- Peripheral write enable (high active)
ta_cci0a => PIN_CCIXA(0), -- Timer A capture 0 input A
ta_cci0b => PIN_CCIXB(0), -- Timer A capture 0 input B
ta_cci1a => PIN_CCIXA(1), -- Timer A capture 1 input A
ta_cci1b => PIN_CCIXB(1), -- Timer A capture 1 input B
ta_cci2a => PIN_CCIXA(2), -- Timer A capture 2 input A
ta_cci2b => PIN_CCIXB(2), -- Timer A capture 2 input B
-- OUTPUTs
irq_ta0 => irq_ta0, -- Timer A interrupt: TACCR0
irq_ta1 => irq_ta1, -- Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout => per_dout_tA, -- Peripheral data output
ta_out0 => ta_outx(0), -- Timer A output 0
ta_out0_en => ta_outx_en(0), -- Timer A output 0 enable
ta_out1 => ta_outx(1), -- Timer A output 1
ta_out1_en => ta_outx_en(1), -- Timer A output 1 enable
ta_out2 => ta_outx(2), -- Timer A output 2
ta_out2_en => ta_outx_en(2) -- Timer A output 2 enable
);
PIN_TAOUT(0) <= 'Z' when (ta_outx_en(0) = '0') else ta_outx(0);
PIN_TAOUT(1) <= 'Z' when (ta_outx_en(1) = '0') else ta_outx(1);
PIN_TAOUT(2) <= 'Z' when (ta_outx_en(2) = '0') else ta_outx(2);
-------------------------------
-- Combine peripheral
-- data buses
-------------------------------
per_dout <= per_dout_led_key_sw
or per_dout_tA;
-------------------------------
-- Assign interrupts
-------------------------------
nmi <= '0';
irq_bus <= '0' -- Vector 13 (0xFFFA)
& '0' -- Vector 12 (0xFFF8)
& '0' -- Vector 11 (0xFFF6)
& '0' -- Vector 10 (0xFFF4) - Watchdog -
& irq_ta0 -- Vector 9 (0xFFF2)
& irq_ta1 -- Vector 8 (0xFFF0)
& '0' -- Vector 7 (0xFFEE)
& '0' -- Vector 6 (0xFFEC)
& '0' -- Vector 5 (0xFFEA)
& '0' -- Vector 4 (0xFFE8)
& irq_key -- Vector 3 (0xFFE6)
& irq_sw -- Vector 2 (0xFFE4)
& '0' -- Vector 1 (0xFFE2)
& '0'; -- Vector 0 (0xFFE0)
--=============================================================================
-- 5) PROGRAM AND DATA MEMORIES
--=============================================================================
pmem_0 : ram_16x8k
port map(
address => pmem_addr,
byteena => not(pmem_wen),
clken => not(pmem_cen),
clock => mclk,
data => pmem_din,
wren => not(pmem_wen(0) and pmem_wen(1)),
q => pmem_dout
);
dmem_0 : ram_16x8k
port map(
address => dmem_addr,
byteena => not(dmem_wen),
clken => not(dmem_cen),
clock => mclk,
data => dmem_din,
wren => not(dmem_wen(0) and dmem_wen(1)),
q => dmem_dout
);
--=============================================================================
-- 6) DEBUG INTERFACE
--=============================================================================
dbg_i2c_addr <= STD_LOGIC_VECTOR(TO_UNSIGNED(50,7));
dbg_i2c_broadcast <= STD_LOGIC_VECTOR(TO_UNSIGNED(49,7));
dbg_i2c_scl <= PIN_SCL;
PIN_SDA <= 'Z' when (dbg_i2c_sda_out = '1') else '0';
dbg_i2c_sda_in <= PIN_SDA;
dbg_uart_rxd <= '0';
-- io_buf_sda_0 : io_buf
-- port map(
-- datain => '0',
-- oe => not(dbg_i2c_sda_out),
-- dataout => dbg_i2c_sda_in,
-- dataio => ARDUINO_IO(14)
-- );
end RTL; -- fpgaMSP430_fpga
| bsd-3-clause | dbaae5f1aae5bfb3402385a60321aa7a | 0.588442 | 2.84853 | false | false | false | false |
dsaves/dsaves-hdl | primitives/latch.vhd | 1 | 1,918 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
entity LATCH is
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end entity;
architecture HI_EN of LATCH is
signal o2 : std_logic;
begin
--assign output
o <= o2;
--LATCH logic
process(clk, i)
begin
if(clk='1') then
o2 <= i;
else
o2 <= o2;
end if;
end process;
end architecture;
architecture LO_EN of LATCH is
signal o2 : std_logic;
begin
--assign output
o <= o2;
--LATCH logic
process(clk, i)
begin
if(clk='0') then
o2 <= i;
else
o2 <= o2;
end if;
end process;
end architecture;
| mit | 3e42d9d685e4a75a36c34ce95895e52a | 0.642336 | 3.954639 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml50x/leon3mp.vhd | 1 | 39,642 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
use work.pcie.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
clk_33 : in std_ulogic; -- 33 MHz
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(12 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
iic_scl_video : inout std_logic;
iic_sda_video : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(15 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_PCIEXP;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of clk_33_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clk_33_pad : clkpad generic map (tech => padtech)
port map (clk_33, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
-- D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => CFG_BOARD_SELECTION,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
txd2 <= '0'; -- Second UART is unused
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr_ad(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr_ba(1 downto 0), ddr2_ras_n => ddr_rasb,
ddr2_cas_n => ddr_casb, ddr2_we_n => ddr_web,
ddr2_cs_n => ddr_csb(CS_NUM-1 downto 0), ddr2_odt => ddr_odt(0 downto 0),
ddr2_cke => ddr_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr_dqsp(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr_dqsn(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr_clk((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr_clkb((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
led(5) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; led(5) <= '0'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_d, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(
memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_video, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_video, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
gpioi.din(12 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hslvndx => 6,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 10,
paddr => 10,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE)
);
end generate;
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
dapbndx => 13, dapbaddr => 13,dapbirq => 13, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 6, apbndx => 10, apbaddr => 10, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(13),
dahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(6)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 6, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 10, paddr => 10,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10)
);
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(CFG_BOARD_SELECTION),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | bbfc2b0bae8ceba377421fd2c700706f | 0.564528 | 3.345034 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-clock-gate/clkgate.vhd | 1 | 2,475 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgate is
generic (tech : integer := 0; ncpu : integer := 1; dsuen : integer := 1);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0)
);
end;
architecture rtl of clkgate is
signal npwd, xpwd, ypwd : std_logic_vector(ncpu-1 downto 0);
signal vrst, wrst : std_logic_vector(ncpu-1 downto 0);
signal clken: std_logic_vector(ncpu-1 downto 0);
signal xrst, vcc : std_ulogic;
begin
vcc <= '1';
cand : for i in 0 to ncpu-1 generate
clken(i) <= not npwd(i);
clkand0 : clkand generic map (tech) port map (clkin, clken(i), clkcpu(i));
end generate;
cand0 : clkand generic map (tech) port map (clkin, vcc, clkahb);
vrst <= (others => rst);
r1 : if dsuen = 1 generate
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= pwd and vrst;
end if;
end process;
end generate;
r2 : if dsuen = 0 generate
reg : process(clkin)
begin
if rising_edge(clkin) then
xrst <= rst;
xpwd <= pwd and wrst;
end if;
end process;
wrst <= (others => xrst);
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= xpwd;
end if;
end process;
end generate;
end;
| gpl-2.0 | 36a2688804eaaaf3cbe4f3c141905c2e | 0.613737 | 3.72741 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/grlfpw_net.vhd | 1 | 37,764 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
strtxii : if (tech = altera) or (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| gpl-2.0 | 6af35c469a0c0951e50a184723c38200 | 0.639524 | 2.594394 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/virage/memory_virage.vhd | 1 | 16,150 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
| gpl-2.0 | 929402102709a71f346ff01a8c43633a | 0.621238 | 2.915162 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/ahbtrace_mb.vhd | 1 | 2,696 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
ntrace => 1)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv);
end;
| gpl-2.0 | ff0e90ed2e05e70e3af89706b1f17394 | 0.582344 | 3.930029 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/grfpwxsh.vhd | 1 | 9,680 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwxsh is
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic_vector(2 downto 0);
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas,
id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2
);
end;
| gpl-2.0 | 1adb394a5ce0cc5fa83da4d2e9bfc8b8 | 0.481198 | 3.522562 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_1/sim/zynq_design_1_rst_ps7_0_100M_1.vhd | 2 | 5,881 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_11;
USE proc_sys_reset_v5_0_11.proc_sys_reset;
ENTITY zynq_design_1_rst_ps7_0_100M_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zynq_design_1_rst_ps7_0_100M_1;
ARCHITECTURE zynq_design_1_rst_ps7_0_100M_1_arch OF zynq_design_1_rst_ps7_0_100M_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zynq_design_1_rst_ps7_0_100M_1_arch;
| mit | d7b88c9b92aa80cebd6b3ac48e711e87 | 0.706172 | 3.534255 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/38a92fb39758d0fa/led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35,714 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:41 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : led_controller_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 57e188d27252d25e770ca6f3fdf8cb2a | 0.590077 | 2.913764 | false | false | false | false |
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